Micro electro mechanical system piezoresistive chip, manufacturing method, pressure monitoring method and system
By employing a rigid central island and annular thin-walled composite diaphragm structure in a MEMS pressure chip, combined with stress concentration design and multilayer metal interconnects, the contradiction between sensitivity and range in MEMS pressure chip monitoring of internal pressure in lithium-ion batteries is resolved, achieving high sensitivity, large range, and corrosion resistance, thereby improving the reliability of battery safety monitoring.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-03
AI Technical Summary
Existing MEMS pressure chips struggle to balance high sensitivity, large range, corrosion resistance, and low stress sensitivity in monitoring the internal pressure of lithium-ion batteries, and are also susceptible to packaging and temperature variations.
The chip employs a rigid central island and annular thin-walled composite diaphragm structure, combined with a stress concentration structure and multi-layer metal interconnect design. The varistor strips are arranged within a high stress gradient zone to form a Wheatstone bridge, enhancing chip sensitivity and corrosion resistance.
It achieves a sensitivity improvement of more than 2 times that of traditional designs, can withstand pressures of more than 300 kPa without damage, and has high reliability and stability in electrolyte environments.
Smart Images
Figure CN121783393A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of pressure monitoring technology for microelectromechanical systems (MEMS), and particularly relates to MEMS piezoresistive chips, manufacturing methods, pressure monitoring methods, and systems. Background Technology
[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.
[0003] An abnormally high internal pressure in a battery is usually a direct signal of malfunction or danger. The main causes of this increase include gas-generating side reactions, material phase changes and expansion, and thermal runaway. Therefore, real-time and accurate monitoring of the internal pressure of lithium-ion batteries is one of the most direct and effective means of early warning of thermal runaway and ensuring battery safety. However, the internal environment of a battery is extremely harsh: the pressure ranges from negative pressure to hundreds of kilopascals, it contains highly corrosive organic electrolytes, and it operates at high temperatures for extended periods. This places stringent requirements on the core of the built-in pressure sensor—the microelectromechanical system (MEMS) piezoresistive chip.
[0004] Existing traditional general-purpose MEMS pressure chips cannot meet this requirement: 1. Conflict between sensitivity and measurement range: To detect trace gas production in the early stages of battery life, a flexible diaphragm is required, demanding high sensitivity; however, to withstand potential high pressure in the later stages, a large measurement range is required, necessitating a rigid diaphragm. Traditional diaphragms with uniform thickness are difficult to achieve both.
[0005] 2. Insufficient reliability: The electrolyte inside the battery can easily penetrate the passivation layer of the chip, corroding the metal interconnects and varistor strips on its surface, leading to device failure.
[0006] 3. Stress sensitivity: Stress introduced by packaging and temperature changes can significantly affect the chip output accuracy, and traditional designs have poor anti-interference capabilities. Summary of the Invention
[0007] To overcome the shortcomings of the prior art, the present invention provides a microelectromechanical system piezoresistive chip, manufacturing method, pressure monitoring method and system for monitoring internal pressure of batteries. It has the characteristics of corrosion resistance and achieves high sensitivity, large range, high reliability and low stress sensitivity.
[0008] To achieve the above objectives, one or more embodiments of the present invention provide the following technical solutions: The first aspect discloses a microelectromechanical system (MEMS) piezoresistive chip, including: A silicon substrate, one side of which is provided with a composite film; The composite membrane consists of a rigid central island and an annular thin-walled region surrounding the rigid central island, wherein the rigid central island and the annular thin-walled region have different thicknesses. A stress concentration structure is provided on the annular thin-walled region; A varistor strip is fabricated at the stress concentration structure of the annular thin-walled region; Metal interconnects are connected to the varistor strip.
[0009] As a further technical solution, the stress concentration structure is one or more combinations of annular bosses, lattice protrusions, or grooves.
[0010] As a further technical solution, the metal interconnect is a multi-layer composite structure, consisting of an adhesion layer, a barrier layer, and a solderable corrosion-resistant layer from bottom to top.
[0011] As a further technical solution, the adhesion layer is titanium or a titanium-tungsten alloy; the barrier layer is platinum or nickel; and the weldable and corrosion-resistant layer is gold.
[0012] As a further technical solution, the chip surface is covered with a silicon nitride passivation layer, and the passivation layer has windows in the pad area.
[0013] As a further technical solution, the thickness of the annular thin-walled region is less than the thickness of the rigid central island.
[0014] Secondly, a method for manufacturing a microelectromechanical system (MEMS) piezoresistive chip is disclosed, including: A varistor strip is formed on the front side of a silicon substrate with a specific crystal orientation by ion implantation; A composite film is formed on the back side of a silicon substrate by anisotropic wet etching. The composite film includes a rigid central island and an annular thin-walled region. A ring-shaped stress concentration protrusion is formed in the annular thin-walled region by dry etching; P-type varistor strips are formed in the stress concentration boss area by ion implantation and annealing processes and connected to form a Wheatstone bridge. Fabricate multilayer metal interconnects that connect to the varistor strip; A silicon nitride passivation layer is deposited on the entire chip surface and the pad openings are photolithographically formed.
[0015] As a further technical solution, when fabricating the multilayer metal interconnects connected to the varistor strip, an electron beam evaporation process is used to sequentially deposit Ti / Pt / Au multilayer metal thin films, and photolithography is used to form the metal interconnects and pads.
[0016] As a further technical solution, the silicon nitride passivation layer has a thickness of approximately 1 μm.
[0017] Thirdly, a method for monitoring the internal pressure of a battery using a microelectromechanical system (MEMS) piezoresistive chip is disclosed, including: The battery receives external pressure; The piezoresistive chip of the microelectromechanical system is deformed under pressure, and the stress concentration boss deforms and squeezes the piezoresistive strip. The resistance change of the varistor strip is transmitted to the main controller through the metal interconnects; The main controller compares the received resistance change value of the varistor strip with a set threshold. If the change value is greater than the set threshold, an alarm is triggered.
[0018] Fourthly, a battery internal pressure monitoring system based on a microelectromechanical system (MEMS) piezoresistive chip is disclosed, comprising: a MEMS piezoresistive chip and a main controller, wherein the MEMS piezoresistive chip is connected to the main controller via a metal interconnect.
[0019] The above one or more technical solutions have the following beneficial effects: Based on a microelectromechanical system (MEMS) piezoresistive chip, this design employs a rigid central island and annular thin-walled composite diaphragm structure. The rigid central island, located in the rigid, thick-walled region at the geometric center of the diaphragm, withstands high pressure and prevents diaphragm rupture under overload. The annular thin-walled region is a flexible, ring-shaped area surrounding the rigid central island, with a thickness much smaller than the supporting areas at the island and diaphragm edges. This region is prone to significant deformation under external pressure. Within this annular thin-walled region, near the edge of the rigid central island, a series of micron-scale protrusions or depressions, such as annular bosses or dot arrays, are formed using microfabrication techniques. This creates a high-stress gradient band in the region. Piezoresistive strips (formed through ion implantation) are precisely positioned within this high-stress gradient band and connected to form a Wheatstone bridge. This design allows the piezoresistor to generate greater strain under the same pressure, significantly improving the chip's sensitivity by more than double that of traditional designs. Simultaneously, the presence of the rigid central island ensures the chip can withstand pressures exceeding 300 kPa without damage, perfectly resolving the conflict between sensitivity and large range.
[0020] The aforementioned microelectromechanical system piezoresistive chip is used for monitoring the internal pressure of the battery. By changing the resistance of the piezoresistor under pressure, the chip's output information is altered, thereby issuing an alarm to the outside world and enabling timely countermeasures.
[0021] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0022] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.
[0023] Figure 1 This is a top view of the chip of the present invention; Figure 2 yes Figure 1Cross-sectional view along line AA; Figure 3 This is a partial 3D schematic diagram of the composite membrane structure of the present invention, illustrating the stress concentration design; Figure 4 This is a flowchart illustrating the battery internal pressure monitoring implemented by the chip; Figure 5 This is a schematic diagram of the chip's three-dimensional structure; In the figure, 101-silicon substrate; 102-composite film; 102a-rigid central island; 102b-annular thin-walled region; 102c-stress concentration boss; 103-varistor strip; 104-metal interconnect; 104a-adhesion layer; 104b-barrier layer; 104c-solderable corrosion-resistant layer; 105-silicon nitride passivation layer; 106-pad opening. Detailed Implementation
[0024] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.
[0025] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations of the present invention.
[0026] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.
[0027] Example 1 See appendix Figure 1-3 As shown, this embodiment discloses a microelectromechanical system piezoresistive chip, including: A silicon substrate, one side of which is provided with a composite film; The composite membrane consists of a rigid central island and an annular thin-walled region surrounding the rigid central island, wherein the rigid central island and the annular thin-walled region have different thicknesses; the thickness of the annular thin-walled region is less than the thickness of the rigid central island.
[0028] A stress concentration structure is provided on the annular thin-walled region; A varistor strip is fabricated at the stress concentration structure of the annular thin-walled region; Metal interconnects are connected to the varistor strip.
[0029] In practical use, the chip can be packaged first, and then the packaged chip can be soldered to the battery electrode.
[0030] In this embodiment, the substrate, the annular thin-walled region, and the rigid central island, which serve as the chip body, are a single structure made of silicon with an overall thickness of approximately 80-100 micrometers. The annular thin-walled region has a thickness of 20-30 micrometers. The rigid central island is a raised structure with a circular cross-section. The annular thin-walled region is divided into two parts: one part is a stress concentration structure, which is uneven, and the other part is a conventional flat film. The stress concentration structure is one or more combinations of annular bosses, dot matrix protrusions, or grooves.
[0031] See appendix again Figure 2 As shown, the rigid central island is a rigid, thick-walled region located at the geometric center of the diaphragm, designed to withstand high pressure and prevent the diaphragm from rupturing under overload. The annular thin-walled region is a flexible, ring-shaped region surrounding the rigid central island, with a thickness much smaller than that of the central island and the supporting regions at the diaphragm edges. This region is prone to significant deformation under external pressure.
[0032] In this embodiment, the stress concentration structure is a stress concentration boss. In the annular thin-walled region, near the edge of the rigid central island, a series of micron-scale protrusions or depressions, such as annular bosses or lattice arrays, are formed by micromachining processes, thereby forming a high stress gradient zone in the region.
[0033] The varistor strips, formed by ion implantation, are precisely arranged within this high-stress gradient zone and connected to form a Wheatstone bridge. This design allows the varistor to generate greater strain under the same pressure, thereby significantly improving the chip's sensitivity by more than twice that of traditional designs. Simultaneously, the presence of a rigid central island ensures that the chip can withstand pressures exceeding 300 kPa without damage, perfectly resolving the conflict between sensitivity and large range.
[0034] See appendix again Figure 1 As shown, the metal interconnects on the chip surface have a multi-layered composite structure, consisting of an adhesion layer, a barrier layer, and a solderable corrosion-resistant layer from bottom to top. The adhesion layer is made of titanium or a titanium-tungsten alloy; the barrier layer is made of platinum or nickel; and the solderable corrosion-resistant layer is made of gold.
[0035] More specifically, the metal interconnects and pads on the chip surface employ a multi-layered composite corrosion-resistant metal structure. The pads are located on the chip surface, see... Figure 2 As shown, leads are soldered to external circuits via solder pads to enable signal conduction. From bottom to top, the layers include: Adhesion layer: composed of titanium (Ti) or titanium-tungsten alloy (TiW), providing good adhesion to the silicon substrate or silicon dioxide insulating layer. Barrier layer: composed of platinum (Pt) or nickel (Ni), whose dense crystal structure effectively blocks the penetration and diffusion of electrolyte ions. Solderable and corrosion-resistant layer: composed of gold (Au), providing excellent conductivity, solderability, and superior chemical inertness, resisting electrolyte corrosion.
[0036] In one embodiment, the chip surface is covered with a silicon nitride passivation layer, which has windows in the pad area. The chip surface includes varistor strips and metal interconnects, with contact windows only in the pad area. Bonding areas are packaged based on these contact windows, providing connections to the external environment. This silicon nitride layer provides the chip with superior insulation and chemical barrier properties.
[0037] The chip surface is the entire front surface of the chip, including a rigid central island, an annular thin-walled region, and a pad area. The annular thin-walled region includes stress concentration structures and conventional flat film structures. Figure 2 (Left) is the structure described above.
[0038] In this embodiment, the composite diaphragm of rigid island-thin-walled ring and stress concentration design successfully unifies the two contradictory performance indicators of high sensitivity and large range, enabling the detection of micro-pressure changes of <0.5kPa and a range of >300kPa.
[0039] In this embodiment, the combination of a "Ti / Pt / Au" or "TiW / Ni / Au" multilayer metallization system with a silicon nitride passivation layer forms a robust defense against electrolyte corrosion, greatly extending the chip's working life inside the battery.
[0040] In this implementation example, by optimizing the design and placing the varistor in the optimal strain zone, the sensitivity to packaging stress is reduced, and the stability and accuracy of the output are improved.
[0041] In this implementation example, the design is specific to the extreme environments in which lithium-ion batteries are monitored, providing an indispensable core sensing element for the next generation of high-safety batteries.
[0042] In this embodiment, the chip employs a rigid central island and annular thin-walled composite diaphragm structure, with stress concentration protrusions in the thin-walled region on which the varistor is placed, perfectly resolving the conflict between high sensitivity and large range. Its metal interconnects utilize a multilayer corrosion-resistant structure of "Ti / Pt / Au" or "TiW / Ni / Au," with a silicon nitride passivation layer covering the surface, significantly improving long-term reliability in battery electrolyte environments. This chip provides a high-performance, highly reliable core sensing element for battery safety early warning.
[0043] Example 2 The purpose of this embodiment is to provide a method for manufacturing a piezoresistive chip for a microelectromechanical system (MEMS), including: A varistor strip is formed on the front side of a silicon substrate with a specific crystal orientation by ion implantation; A composite film is formed on the front side of a silicon substrate by anisotropic wet etching. The composite film includes a rigid central island and an annular thin-walled region. A ring-shaped stress concentration protrusion is formed in the annular thin-walled region by dry etching; P-type varistor strips are formed in the stress concentration boss area by ion implantation and annealing processes and connected to form a Wheatstone bridge. First, a layer of silicon nitride is deposited on the chip surface to protect the surface circuitry. Then, windows are etched onto the silicon nitride surface. An adhesion layer, a barrier layer, and a solderable corrosion-resistant layer are then placed in the windowed area to form the entire chip window. See details... Figure 2 .
[0044] In one implementation example, when fabricating the multilayer metal interconnects connected to the varistor strip, an electron beam evaporation process is used to sequentially deposit Ti / Pt / Au multilayer metal thin films, and photolithography is used to form the metal interconnects and pads.
[0045] The MEMS piezoresistive chip of this embodiment is fabricated on a crystal-oriented silicon substrate (101). A composite film (102) is formed on its back side by anisotropic wet etching. The rigid island (102a) at the center of the film is relatively thick, while the surrounding annular thin-walled region (102b) is thinned to tens of micrometers. On this annular region, an annular stress concentration protrusion (102c) is formed by dry etching.
[0046] P-type varistor strips (103) are formed in the stress concentration boss (102c) region by ion implantation and annealing processes and connected to form a Wheatstone bridge. Subsequently, Ti / Pt / Au multilayer metal thin films are deposited sequentially by electron beam evaporation, and metal interconnects (104) and pads are formed by photolithography. The metal interconnects (104) are multilayer composite structures, including an adhesion layer (104a), a barrier layer (104b), and a solderable corrosion-resistant layer (104c) from bottom to top. Finally, a silicon nitride passivation layer (105) with a thickness of about 1 μm is deposited on the entire chip surface by PECVD process, and the pad openings (106) are opened by photolithography.
[0047] Example 3 The purpose of this embodiment is to provide a method for monitoring the internal pressure of a battery using a microelectromechanical system (MEMS) piezoresistive chip, including: When the battery receives external pressure, the internal pressure increases, causing the flexible composite membrane of the chip to deform. When a piezoresistive chip in a microelectromechanical system is subjected to pressure and deformation, the stress concentration bosses formed by the high stress gradient band deform and compress the piezoresistive strip, causing a change in the resistance value of the piezoresistive strip. The resistance change of the varistor strip is transmitted to the main controller through the metal interconnects; The main controller compares the received resistance change value of the varistor strip with a set threshold. If the change value is greater than the set threshold, an alarm is triggered.
[0048] Example 4 The purpose of this embodiment is to provide a battery internal pressure monitoring system based on a microelectromechanical system (MEMS) piezoresistive chip, including: a MEMS piezoresistive chip and a main controller, wherein the MEMS piezoresistive chip is connected to the main controller via a metal interconnect.
[0049] Those skilled in the art will understand that the modules or steps of the present invention described above can be implemented using general-purpose computer devices. Optionally, they can be implemented using computer-executable program code, thereby allowing them to be stored in a storage device for execution by a computer device, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. The present invention is not limited to any particular combination of hardware and software.
[0050] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.
Claims
1. A microelectromechanical system (MEMS) piezoresistive chip, characterized in that it includes: A silicon substrate, one side of which is provided with a composite film; The composite membrane consists of a rigid central island and an annular thin-walled region surrounding the rigid central island, wherein the rigid central island and the annular thin-walled region have different thicknesses. A stress concentration structure is provided on the annular thin-walled region; A varistor strip is fabricated at the stress concentration structure of the annular thin-walled region; Metal interconnects are connected to the varistor strip.
2. The piezoresistive chip for microelectromechanical systems as described in claim 1, characterized in that, The stress concentration structure is one or more combinations of annular bosses, lattice protrusions, or grooves.
3. The piezoresistive chip for microelectromechanical systems as described in claim 1, characterized in that, The metal interconnect has a multi-layer composite structure, consisting of an adhesion layer, a barrier layer, and a solderable corrosion-resistant layer from bottom to top.
4. The piezoresistive chip for microelectromechanical systems as described in claim 1, characterized in that, The adhesion layer is made of titanium or a titanium-tungsten alloy; the barrier layer is made of platinum or nickel; and the weldable and corrosion-resistant layer is made of gold.
5. The piezoresistive chip for microelectromechanical systems as described in claim 1, characterized in that, The chip surface is covered with a silicon nitride passivation layer, and the passivation layer has windows in the pad area.
6. The piezoresistive chip for microelectromechanical systems as described in claim 1, characterized in that, The thickness of the annular thin-walled region is less than the thickness of the rigid central island.
7. A method for manufacturing a piezoresistive chip for microelectromechanical systems, characterized in that, include: A varistor strip is formed on the front side of a silicon substrate with a specific crystal orientation by ion implantation; A composite film is formed on the back side of a silicon substrate by anisotropic wet etching. The composite film includes a rigid central island and an annular thin-walled region. A ring-shaped stress concentration protrusion is formed in the annular thin-walled region by dry etching; P-type varistor strips are formed in the stress concentration boss area by ion implantation and annealing processes and connected to form a Wheatstone bridge. Fabricate multilayer metal interconnects that connect to the varistor strip; A silicon nitride passivation layer is deposited on the entire chip surface and the pad openings are photolithographically formed.
8. The method for manufacturing a microelectromechanical system piezoresistive chip as described in claim 7, characterized in that, When fabricating the multilayer metal interconnects connected to the varistor strip, an electron beam evaporation process is used to sequentially deposit Ti / Pt / Au multilayer metal thin films, and photolithography is used to form the metal interconnects and pads.
9. A method for monitoring the internal pressure of a battery using a piezoresistive chip in a microelectromechanical system (MEMS), characterized in that, include: The battery receives external pressure; The piezoresistive chip of the microelectromechanical system is deformed under pressure, and the stress concentration boss deforms and squeezes the piezoresistive strip. The resistance change of the varistor strip is transmitted to the main controller through the metal interconnects; The main controller compares the received resistance change value of the varistor strip with a set threshold. If the change value is greater than the set threshold, an alarm is triggered.
10. A battery internal pressure monitoring system using a microelectromechanical system (MEMS) piezoresistive chip, characterized in that, include: The microelectromechanical system piezoresistive chip and main controller according to any one of claims 1-6, wherein the microelectromechanical system piezoresistive chip is connected to the main controller through a metal interconnect; the main controller compares the received resistance change value of the piezoresistive strip with a set threshold, and if it is greater than the set threshold, an alarm is triggered.