A method for anti-single event upset processing for avionics

Abstract

The application provides an anti-single event upset processing method for avionics, which comprises the following steps: step one, defining and initializing a configurable hierarchical check data structure; step two, entering a loop task and obtaining to-be-written data; step three, writing the to-be-written data and a correction detection mode into the data structure; and step four, when the data needs to be read, reading to-be-read data from the data structure in groups. Compared with a traditional triple modular redundancy scheme, the application reduces storage occupation by more than 60%, solves the problem of high cost of directly using Hamming code for real-time correction and detection of memory data in an aviation device, and reduces resource consumption of encoding and decoding while having correction and detection capability, thereby meeting high requirements of the aviation device on real-time performance and resource efficiency.

Description

Technical Field

[0001] This invention relates to the technical field of reliability of aerospace electronic equipment, airborne control systems, etc., and in particular to a method for preventing single-event upsets in avionics equipment. Background Technology

[0002] Single-Event Upsets (SEUs) are common faults in electronic devices in irradiated environments, causing unexpected bit flips in memory cells and triggering system errors. Traditional SEU mitigation methods mainly rely on hardware redundancy (such as triple modulo redundancy) or hardware ECC (error-correcting codes), but these methods are typically costly and inflexible. In aerospace equipment, due to long-term exposure to high-energy cosmic rays, the probability of SEUs and even multiple bit flips increases significantly, placing higher demands on software error correction capabilities. Such scenarios usually require a combination of multi-layered redundancy and complex verification algorithms (such as RS codes), but such solutions incur enormous overhead in terms of computational resources and storage space, making them difficult to apply directly in resource-constrained embedded systems.

[0003] In the aviation field, although the atmosphere's shielding effect on cosmic rays reduces the probability of single-event upsets, the extremely high safety requirements of airborne equipment (such as flight control systems) necessitate stringent requirements for data reliability. Furthermore, avionics typically utilize chip models with long service lives and high reliability, but relatively outdated performance. These chips often lack hardware ECC verification or triple-mode redundancy and must operate within limited computing time and storage resources.

[0004] Existing software solutions (such as triple modulo redundancy or complex error-correcting codes) face the following problems in such scenarios:

[0005] (1) Excessive resource consumption

[0006] Triple redundancy requires 200% redundant storage space, and the majority voting mechanism consumes additional computation time.

[0007] (2) High algorithm complexity

[0008] Complex verification algorithms such as RS codes require high computing power and are difficult to run in real time on low-performance chips in civilian aircraft.

[0009] (3) Low recovery efficiency

[0010] Traditional backup mechanisms rely on periodic full verification, which is difficult to meet the real-time requirements of aviation equipment.

[0011] For example, patent application CN201110387908.9 discloses a method for reading program memory data in segments via DMA and dynamically generating fault-tolerant parameters. Although this reduces CPU resource consumption, it relies on a hardware DMA module and redundant storage leads to high memory consumption. Patent application CN201510993615.3 discloses a method for reinforcing critical logic through redundant coding and tri-mode redundancy design, which is suitable for high-radiation environments in aerospace. However, the fixed redundancy strategy leads to resource waste and cannot be dynamically adjusted according to the criticality of the data. Patent CN202010586774.2 discloses a method for selectively enabling ECC verification based on the configured data frame address, flexibly adapting to different storage areas. The method only targets FPGA configuration data and does not cover real-time memory data protection. It also relies on a hardware ECC module, which older chips cannot support. Patent application CN201910340318.7 combines CPU, FPGA, and triple redundancy to implement a closed-loop multi-level storage system, offering high reliability, but also high system complexity, requiring additional hardware support, and its cost and power consumption are difficult to meet the requirements of aerospace equipment. Patent application CN202010666387.X, based on the Zynq-7000 dual-core architecture, implements on-chip memory protection through software EDAC and interrupt write-back, offering good real-time performance, but with high computational overhead, making it difficult for low-performance chips to handle, and it does not address the vulnerability of the checksum itself (SEU). Patent CN201610580590.9 provides a method for effectively detecting and recovering mission stack data errors in a space radiation environment. Through an improved (71,63) Hamming code and a real-time updated checksum control block, it achieves low-performance overhead and high-efficiency error detection and recovery, but requires the chip processor to support the deployment of a real-time operating system like μC / OS-II.

[0012] Hamming codes, as a classic error-correcting code, possess the ability to "correct one bit error and detect two bits error," and their error correction and detection capabilities can meet the requirements of aviation equipment. However, the application of traditional Hamming codes has significant limitations:

[0013] (1) Increased complexity of storage structure

[0014] Hamming codes require the parity bit to be directly inserted into the data bits (e.g., storing data bits and parity bits together), which changes the data storage structure. In scenarios with frequent memory reads and writes, this design increases the complexity of data access and addressing overhead.

[0015] (2) Encoding and decoding resource overhead is large

[0016] Each time data is written, the parity bit needs to be recalculated and inserted into the data stream. When reading, the parity bit and data bit need to be separated for decoding, which adds extra calculation time and memory access count.

[0017] Real-time limitations

[0018] For critical data that changes in real time in memory (such as the real-time status of sensors), the encoding and decoding operations of traditional Hamming codes may become a performance bottleneck, making it difficult to meet the hard real-time requirements of aviation equipment for low latency.

[0019] Therefore, there is a need to provide a single-event upset (SED) protection method for avionics equipment to address the high cost of using Hamming codes directly for real-time error correction and detection of memory data in avionics equipment. This method should be able to reduce the resource overhead of encoding and decoding while retaining error correction and detection capabilities, thus meeting the high requirements of avionics equipment for real-time performance and resource efficiency. Summary of the Invention

[0020] To address the problems in the prior art, this invention provides a single-event upset (SED) protection method for avionics equipment. This method solves the problem of high costs associated with using Hamming codes directly for real-time error correction and detection of memory data in avionics equipment. It enables the method to reduce the resource overhead of encoding and decoding while retaining error correction and detection capabilities, thus meeting the high requirements of avionics equipment for real-time performance and resource efficiency.

[0021] To achieve the above objectives, the present invention provides the following technical solution: a method for preventing single-event upsets in avionics equipment, comprising the following steps:

[0022] Step 1: Define and initialize the configurable hierarchical verification data structure;

[0023] Step 2: Enter the loop task and obtain the data to be written;

[0024] Step 3: Write the data to be written and the error correction mode into the data structure;

[0025] Step 4: When data needs to be read, read the data to be read in groups from the data structure.

[0026] In a preferred embodiment, the data structure includes an array with multiple members, a multi-bit primary checksum, and a secondary error correction code; the array is used to store data and perform reverse monitoring of the primary checksum; each check bit of the primary checksum corresponds to the even parity value of a member of the array.

[0027] In a preferred embodiment, the secondary error correction code includes a recovery code based on the Hamming code check algorithm, a secondary check code, and a correction mode code; the recovery code is used to monitor the array; and the secondary check code is used to perform even parity check on the recovery code and the primary check code.

[0028] In a preferred embodiment, the secondary check code employs triple redundancy; the error correction mode code includes a check enable flag and an error correction enable flag, and both the check enable flag and the error correction enable flag employ triple redundancy.

[0029] The preferred technical solution, the specific process of step two is as follows:

[0030] Enter the task loop, obtain the data to be written from external input through driver calls, and write each piece of data to be written into a local variable.

[0031] In a preferred embodiment, the externally input data to be written originates from a sensor.

[0032] The preferred technical solution, the specific process of step three is as follows:

[0033] Step 3: 1. Obtain the parameters of the data to be written through the driver;

[0034] Step 32: Write the data to be written;

[0035] Step 33: Determine the error correction mode;

[0036] Steps 3 and 4: Determine the range of data members that need to be updated;

[0037] Step 35: Update the Level 1 verification code;

[0038] Step 36: Update the recovery code;

[0039] Step 37: Update the secondary verification code;

[0040] Step 38: Update the error correction mode code.

[0041] In a preferred technical solution, the error correction mode includes an error correction mode, a verification mode, and a normal mode; the parameters of the data to be written obtained in step three include the source address of the data to be written, the target address of the data to be written, the number of members of the data to be written, and the error correction mode of the data to be written.

[0042] The preferred technical solution, the specific process of step three is as follows:

[0043] Step 3: 1. Obtain the source address, destination address, number of members, and error correction / detection mode of the data to be written through the driver.

[0044] Step 32: Copy the source address of the data to be written to the target address of the data to be written, and complete the writing of the data;

[0045] Step 33: When the data to be written is in the normal mode, no data verification is required, proceed directly to Step 4; when the data to be written is in the verification mode, only data verification is performed, execute Steps 34 and 35 in sequence, skip Steps 36 and 37, proceed directly to Step 38, and then proceed to Step 4; when the data to be written is in the error correction mode, both data verification and error correction are required, execute Steps 34, 35, 36, 37, and 38 in sequence, and then proceed to Step 4.

[0046] Steps 3 and 4: Based on the target address of the data to be written and the length of the data to be written, locate the index of the data member whose checksum needs to be updated, and update the corresponding data member according to the data member index;

[0047] Step 35: Calculate the even parity value for each updated data member and update the corresponding bit of the first-level checksum;

[0048] Step 36: Based on the Hamming code calculation method, calculate the Hamming code for all array members and store it in the recovery code area of ​​the data structure;

[0049] Step 37: Calculate the even parity value for the recovery code and the first-level check code as a whole, and update it to a second-level check code with three times the redundancy;

[0050] Step 38: Update the triple-redundant correction mode code based on the correction mode obtained in Step 31.

[0051] The preferred technical solution, the specific process of step four is as follows:

[0052] Step 41: Obtain the parameters of the data to be read; the parameters of the data to be read include the array address of the data to be read, the data member sequence number of the data to be read, and the error correction mode code of the data to be read.

[0053] Step 42: Determine the verification mode of the data to be read; if a verification enable flag is obtained, enter the verification mode and execute Step 43; otherwise, proceed to Step 40.

[0054] Step 43: Calculate the even parity value of the current data member and compare it with the parity bit stored in the first-level check code; if the even parity value of the current data member is equal to the parity bit stored in the corresponding first-level check code, the verification passes and proceeds to step 40; otherwise, the verification fails and proceeds to step 44.

[0055] Step 44: Determine the error correction mode of the data to be read; if an error correction enable flag is obtained, enter the error correction mode and proceed to Step 46; otherwise, proceed to Step 49.

[0056] Steps 4 and 5: Perform secondary verification on the data to be read and judge the result; obtain the secondary verification code, calculate the even parity value of the recovery code and the primary verification code, and compare it with the secondary verification code. If the even parity value of the primary verification code is equal to the secondary verification code, the verification passes and the error correction step 4 and 6 is executed; otherwise, the verification fails and the error correction step 4 and 7 is executed.

[0057] Step 46: Correct the erroneous data members; Calculate the recovery code of the current data area according to the method in Step 36, and perform bitwise XOR with the recovery code in the secondary error correction code to obtain the recovery code comparison result matrix. Calculate the data position column index to be corrected based on the result matrix, and flip the corresponding bit data member in the data according to the data position column index to complete the correction of the erroneous bit.

[0058] Step 47: Confirm whether there are multiple bit flips; calculate the recovery code of the current data area according to the method in Step 36. If the recovery code is equal to the recovery code in the second-level error correction code, it proves that the data bits are not wrong but the first-level check code is wrong. Execute step 48 for error correction; otherwise, execute step 49.

[0059] Step 48: Correct the erroneous Level 1 checksum; flip the Level 1 checksum corresponding to the read data member to complete the error correction;

[0060] Step 49: Return the error and report it; return the error code and report the error.

[0061] Step 40: Return to read data; return the corrected data or the original data to the caller.

[0062] Compared with existing technologies, the beneficial effects of the single-event upset resistance method for avionics of this invention are:

[0063] 1. This invention employs a configurable hierarchical parity data structure. The array of the data structure stores data and supports reverse monitoring of the primary parity code and recovery code. Each parity bit of the primary parity code corresponds to an even parity value of the array member of the data, enabling fast error detection. The recovery code of the secondary error correction code is a K-bit recovery code based on improved Hamming codes, covering all data bits and supporting single-bit error correction. The secondary parity code of the secondary error correction code uses triple modulo redundancy even parity values ​​to protect the integrity of the primary parity code and the recovery code itself. The error correction mode code of the secondary error correction code has a 6-bit triple modulo redundancy code, allowing for dynamic configuration of the parity and error correction modes.

[0064] 2. The dynamic fault-tolerance mechanism of this invention includes three error correction modes. These include: Normal mode 00b (no verification required): direct data reading and writing with no additional overhead; Verification mode 01b (verification only): detecting and reporting errors without performing error correction, resulting in lower overhead; and Error correction mode 11b (verification and correction): automatically correcting errors after detection, supporting single-bit repair. This invention employs a layered verification logic: Level 1 verification can quickly locate data errors; Level 2 verification can verify the reliability of the recovery code and Level 1 verification code; recovery code error correction can achieve data repair through separate Hamming codes.

[0065] 3. This invention combines even parity check with Hamming code: even parity check detects errors with low overhead, while Hamming code accurately locates single-bit errors; this invention uses a triple-modulus redundancy code, using redundancy only for the mode identifier bit and the secondary check code, avoiding redundancy across the entire data; this invention uses dynamic calculation of Hamming code, dynamically determining the number of check bits based on the data length, reducing the overhead of calculating Hamming code across the entire data.

[0066] 4. When applied to airborne equipment, this invention can significantly improve resource efficiency and reduce storage overhead. Compared to a typical triple redundancy scheme, storage usage is reduced by more than 60%. Simultaneously, the application of multi-level error protection modes can address different levels of error prevention requirements and dynamically configure the error correction mode based on data importance, balancing resource overhead and data reliability. Furthermore, although the improved Hamming check sacrifices the error prevention capability of the recovery code itself and the detection capability of multiple bit flips, for avionics equipment where the probability of single-event flips is low and most cases involve single-bit flips, the flexibility and low overhead gained from sacrificing this capability still have high application value.

[0067] 5. This invention solves the problem of how to design a highly reliable, highly flexible, and low-overhead software anti-SEU scheme in resource-constrained airborne equipment embedded systems. This allows designers to flexibly select different levels of error correction and detection strategies based on the criticality of the data, and minimize the storage and time overhead caused by introducing error correction and detection logic.

[0068] 6. This invention can solve the problem that the cost of using Hamming codes directly for real-time error correction and detection of memory data in aviation equipment is too high, so that it can reduce the resource overhead of encoding and decoding while retaining the error correction and detection capabilities, thus meeting the high requirements of aviation equipment for real-time performance and resource efficiency. Attached Figure Description

[0069] Figure 1 This is a schematic diagram illustrating the composition of the configurable hierarchical verification data structure of the present invention.

[0070] Figure 2 This is a flowchart illustrating a single-event upset (SED) protection method for avionics equipment according to the present invention. Detailed Implementation

[0071] The relevant terms used in this invention are explained as follows:

[0072] CPU: Central Processing Unit;

[0073] DMA: Direct Memory Access;

[0074] ECC: Error Correcting Code;

[0075] RS: Reed-Solomon codes;

[0076] SEU: Single-Event Upset.

[0077] Reference Figures 1 to 2 The present invention provides a further description of a single-event upset (SED) protection method for avionics equipment.

[0078] Example 1

[0079] like Figure 1 As shown: The configurable hierarchical verification data structure in the single-event upset (SED) protection method for avionics equipment of this invention mainly includes three parts: The first part is an array D[N] with N members, each member having a length of W bits, whose main function is to store data and implement reverse monitoring of the primary check code; the second part is an N-bit primary check code, where each check bit corresponds to the even parity value of a member of array D[N]; the third part is a secondary error correction code, which includes three parts: a K-bit recovery code based on the Hamming code check algorithm, used to monitor array D[N]; a 3-bit secondary check code, used to perform even parity on the K-bit recovery code and the primary check code, using triple redundancy; and a 6-bit error correction mode code, including a check enable flag and an error correction enable flag, both of which use triple redundancy. The constraint relationships between the parameters are as follows:

[0080] 2K ≥ W×N + 1

[0081] W≥N

[0082] W∈{16, 32, 64}

[0083] Figure 2As shown, the data read / write process of this invention is as follows. The main process is a background task that executes in a loop. Before the task execution, a data structure is defined, and the array D[N] of the data structure members is used to store the data to be read / written, and its default values ​​are initialized. After entering the task, the values ​​of each array member of the data to be written are obtained (usually obtained from external inputs such as sensors through driver calls). After the data acquisition is completed, the data writing module is called to write data and the correction mode into the array D[N] of the data structure members, and at the same time, the first-level check code and the second-level error correction code are updated as needed according to the corresponding correction mode. After the data writing is completed, each array member of the array D[N] of the data structure members is read according to the task requirements, and the data is verified and corrected as needed according to the correction mode, and the read data is processed. Finally, the data writing and reading process is executed cyclically according to the task cycle. The detailed steps are as follows:

[0084] S0. System Startup

[0085] The system starts running and enters the initialization process.

[0086] S1. Define and initialize the data structure.

[0087] according to Figure 1 The data structure shown defines a data structure whose first member is an array D[N], the number of bits of the data type in the array is W, and the number of array members N≤W; its second member is a level 1 check code F[0:W-1]; its third member is a level 2 error correction code S[0:W-1]; D[N], level 1 check code F[0:W-1], and level 2 error correction code S[0:W-1] are initialized to all 0.

[0088] S2. Enter the loop task and obtain the data to be written.

[0089] Upon entering the task loop, external inputs from sensors and other sources are obtained through driver calls, and the acquired data is written into a local variable temp[N]. Furthermore, the user needs to determine a correction mode based on the criticality of this data (00b no verification required / 01b verification only / 11b verification and error correction).

[0090] S3. Write data to D[N]

[0091] Call the data writing module to write data and error correction mode to the data structure.

[0092] S31. Obtain write parameters

[0093] Read the source address SA, the destination address DA, the number of data members to be written L, and the error correction and detection mode M.

[0094] S32. Write data

[0095] Copy (L×W / 4) bytes from source address SA to DA to complete the process of writing data to D[N].

[0096] S33. Determine the correction mode

[0097] When M = 00b, the data does not need to be verified and proceeds directly to step S4; when M = 01b, the data is only verified, and steps S34, S35, and S38 are executed sequentially before proceeding to step S4; when M = 11b, the error correction mode is entered, and the data needs to be verified and corrected, and steps S34, S35, S36, S37, and S38 are executed sequentially before proceeding to step S4.

[0098] S34. Determine the range of array members that need to be updated.

[0099] Based on the target address DA and the data length L, the indexes of the data members whose check codes need to be updated are i, i+1, …, i+L-1.

[0100] S35. Update the Level 1 checksum

[0101] For each updated data member D[i] to D[i+L-1], calculate the even parity value and update the corresponding bit of the first-level parity code.

[0102] S36. Update recovery code

[0103] Based on the optimized Hamming code calculation method, the Hamming codes of all array members D[0] to D[N-1] are calculated and stored in the structure recovery code area. The detailed calculation process is as follows:

[0104] 1) Calculate the number of bits K in the recovery code:

[0105]

[0106] In the above formula, ceil[] is rounded up, W is the number of bits in each array member, and N is the number of array members;

[0107] 2) Calculate recovery code S

[0108] Each bit in the recovery code S is an even parity value of a set of data at a specific position in the W×N data. Based on the K value calculated in step 1), the value of each bit in the recovery code S is calculated. The coverage relationship between each bit of the codeword in S and the W×N data is as follows:

[0109] S[0] covers the 1st, 3rd, 5th...W×N-1st bit;

[0110] S[1] covers the 2nd, 3rd, 6th, 7th..., 2nd 1 ×(2j - 1) ~ 22 ×j- 1、…… positions, where j is a positive integer and satisfies 2 2 ×j - 1≤W×N;

[0111] S[2] covers the 4th, 5th, 6th, 7th, 12th, 13th..., 2nd 2 ×(2j - 1) ~ 2 3 ×j - 1, ..., where j is a positive integer and satisfies 2 3 ×j - 1≤W×N;

[0112] ...

[0113] S[K-1] covers the 2nd K-1 ×(2j - 1) ~ W×N bits, where i is a positive integer and satisfies 2 K-1 ×(2j- 1) ≤W×N;

[0114] The recovery code S[0:K-1] is calculated from this.

[0115] S37. Update the secondary checksum

[0116] Calculate even parity values ​​for the recovery code and the first-level check code as a whole, and update them to a three-fold redundant second-level check code S[W-9:W-7] to prevent the first-level check code from becoming invalid due to SEU.

[0117] S38. Update the correction mode code

[0118] Based on the error correction mode M obtained from S31, update the triple-redundant error correction mode code S[W-6:W-1]. Specifically, if M is 00b, representing the normal mode, then S[W-6:W-1] is all set to 0; if M is 01b, representing the verification mode, then the error correction enable flag S[W-3:W-1] is all set to 0, and the verification enable flag S[W-6:W-4] is all set to 1; if M is 11b, representing the error correction mode, then S[W-6:W-1] is all set to 1.

[0119] S4. Read data D[i]

[0120] When data D[i] needs to be read, the data reading process begins.

[0121] S41. Obtain the parameters to be read

[0122] Read the array address Ra and the sequence number i of the data member to be accessed, and obtain the detection mode code S[W-6:W-1].

[0123] S42. Verification Mode Determination

[0124] Obtain the verification enable flag S[W-6:W-4]. If the value is 111b, 110b, 101b, or 011b, it means the verification enable flag is set (111b means the bit has not been flipped, 110b, 101b, or 011b means a bit has been flipped, the same below). Update S[W-6:W-4] to 111b and enter the verification mode, proceeding to step S43. Otherwise, it means the verification enable flag is not set (000b means the bit has not been flipped, 100b, 010b, or 001b means a bit has been flipped, the same below). Update S[W-6:W-4] to 000b and proceed to step S410.

[0125] S43. Perform level one verification and determine the result.

[0126] Calculate the even parity value P_i of the current data member D[i] and compare it with the parity bit F[i] stored in the first-level check code.

[0127] If P_i = F[i], the verification passes and proceeds to step S410; otherwise, the verification fails and proceeds to step S44.

[0128] S44. Error Correction Mode Determination

[0129] Obtain S[W-3:W-1]. If the value is 111b, 110b, 101b, or 011b, update S[W-3:W-1] to 111b and enter error correction mode, then proceed to step S46; otherwise, update S[W-3:W-1] to 000b and proceed to step S49.

[0130] S45. Perform secondary verification and result judgment.

[0131] Obtain S[W-9:W-7]. If the value is 111b, 110b, 101b, or 011b, update S[W-9:W-7] to 111b and P2 to 1; otherwise, update S[W-9:W-7] to 000b and P2 to 0. Calculate the even parity value PP of the recovery code and the first-level check code, and compare it with the second-level check code P2. If PP = P2, the verification passes, proving that the reason for the first-level verification failure is an error in D[i], and execute the error correction step S46; otherwise, the verification fails, and execute the error correction step S47.

[0132] S46. Correcting faulty data members

[0133] Calculate the recovery code H[0:K-1] of the current data area according to the method in step S37, and perform a bitwise XOR with S[0:K-1] to obtain R[0:K-1]. Calculate the index of the data column to be corrected according to the following formula:

[0134]

[0135] Flip the index-th bit data in D[i] to correct the error bit.

[0136] S47. Confirm whether there is a multi-bit flip.

[0137] Calculate the recovery code H[0:K-1] of the current data area according to the method in step S37. If H[0:K-1]=S[0:K-1], it proves that there is no error in the data bits but there is an error in the first-level check code. Then execute the error correction step S48. Otherwise, it proves that both the data area and the first-level check code (or recovery code) have been flipped. Then execute step S49.

[0138] S48. Correction of error-level checksum

[0139] Perform a bit flip on F[i] to complete the error correction.

[0140] S49. Return the error and report it.

[0141] Return error code 01b and report the error.

[0142] S410. Return to read data

[0143] Return the corrected data or the original data D[i] to the caller.

[0144] S5. Data Processing

[0145] The read D[i] is processed according to the user's requirements.

[0146] According to user requirements, other array members are read and processed in a loop cycle. The process ends after all the required data has been read and processed, and returns to the loop start point. The process of batch writing, reading and processing data is repeated in a loop.

[0147] This invention discloses a single-event upset (SED) protection method for airborne equipment, belonging to the field of embedded systems and high-reliability software technology. Addressing the problems of high resource overhead and insufficient real-time performance of existing hardware redundancy schemes and traditional Hamming codes in avionics, this invention employs a configurable hierarchical parity data structure and a dynamic fault-tolerance mechanism. Layered protection is achieved through a data array, a primary parity code (even parity), and a secondary error-correcting code (including improved Hamming code recovery code, secondary parity code, and a tri-modal redundancy correction mode code). It supports dynamic switching between three correction modes (no parity required / parity only / parity with correction), flexibly configured according to the criticality of the data. Even parity is used for rapid error detection, combined with dynamically optimized Hamming codes for precise single-bit error localization, and the tri-modal redundancy mode code reduces redundancy overhead. Compared to traditional tri-modal redundancy schemes, storage usage is reduced by more than 60%, while simultaneously meeting the stringent requirements of avionics equipment for real-time performance, resource efficiency, and high reliability. It is suitable for real-time fault-tolerant protection of critical memory such as sensor data.

[0148] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. It should be noted that any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for preventing single-event upsets in avionics equipment, characterized in that: It includes the following steps: Step 1: Define and initialize the configurable hierarchical verification data structure; Step 2: Enter the loop task and obtain the data to be written; Step 3: Write the data to be written and the error correction mode into the data structure; The error correction and detection modes include error correction mode, verification mode, and normal mode; the parameters of the data to be written include the source address of the data to be written, the destination address of the data to be written, the number of members of the data to be written, and the error correction and detection mode of the data to be written; the specific process of step three is as follows: Step 3:

1. Obtain the source address, destination address, number of members, and error correction / detection mode of the data to be written through the driver. Step 32: Copy the source address of the data to be written to the target address of the data to be written, and complete the writing of the data; Step 33: When the data to be written is in the normal mode, no data verification is required, proceed directly to Step 4; when the data to be written is in the verification mode, only data verification is performed, execute Steps 34 and 35 in sequence, skip Steps 36 and 37, proceed directly to Step 38, and then proceed to Step 4; when the data to be written is in the error correction mode, both data verification and error correction are required, execute Steps 34, 35, 36, 37, and 38 in sequence, and then proceed to Step 4. Steps 3 and 4: Based on the target address of the data to be written and the length of the data to be written, locate the index of the data member whose checksum needs to be updated, and update the corresponding data member according to the data member index; Step 35: Calculate the even parity value for each updated data member and update the corresponding bit of the first-level checksum; Step 36: Based on the optimized Hamming code calculation method, calculate the Hamming code for all array members and store it in the recovery code area of ​​the data structure; Step 37: Calculate the even parity value for the recovery code and the first-level check code as a whole, and update it to a second-level check code with three times the redundancy; Step 38: Update the triple-redundant correction mode code based on the correction mode obtained in Step 31. Step 4: When data needs to be read, read the data to be read in groups from the data structure; The data structure includes an array with multiple members, a multi-bit primary checksum, and a secondary error correction code. The array stores data and performs reverse monitoring of the primary checksum. Each check bit of the primary checksum corresponds to an even parity value of a member of the array. The secondary error correction code includes a recovery code based on the Hamming code check algorithm, a secondary checksum, and a correction mode code. The recovery code monitors the array. The secondary checksum performs even parity checks on the recovery code and the primary checksum. The secondary checksum uses triple redundancy. The correction mode code includes a checksum enable flag and an error correction enable flag, both of which use triple redundancy.

2. The method for resisting single-event upsets in avionics according to claim 1, characterized in that: The specific process of step two is as follows: Enter the task loop, obtain the data to be written from external input through driver calls, and write each piece of data to be written into a local variable.

3. The method for preventing single-event upsets in avionics according to claim 2, characterized in that: The external input data to be written comes from the sensor.

4. The method for resisting single-event upsets in avionics according to claim 3, characterized in that: The specific process of step four is as follows: Step 41: Obtain the parameters of the data to be read; the parameters of the data to be read include the array address of the data to be read, the data member sequence number of the data to be read, and the error correction mode code of the data to be read. Step 42: Determine the verification mode of the data to be read; if a verification enable flag is obtained, enter the verification mode and proceed to Step 43. Otherwise, proceed to step forty; Step 43: Calculate the even parity value of the current data member and compare it with the parity bit stored in the first-level check code; if the even parity value of the current data member is equal to the parity bit stored in the corresponding first-level check code, the verification passes and proceed to step 40. Otherwise, the verification fails, proceed to step four. Step 44: Determine the error correction mode of the data to be read; if an error correction enable flag is obtained, enter the error correction mode and proceed to step 46. Otherwise, proceed to step 49; Steps 4 and 5: Perform secondary verification on the data to be read and judge the result; obtain the secondary verification code, calculate the even parity value of the recovery code and the primary verification code, and compare it with the secondary verification code. If the even parity value of the primary verification code is equal to the secondary verification code, the verification passes and the error correction step 4 and 6 is executed; otherwise, the verification fails and the error correction step 4 and 7 is executed. Step 46: Correct the erroneous data members; Calculate the recovery code of the current data area according to the method in Step 36, and perform bitwise XOR with the recovery code in the secondary error correction code to obtain the recovery code comparison result matrix. Calculate the data position column index to be corrected based on the result matrix, and flip the corresponding bit data member in the data according to the data position column index to complete the correction of the erroneous bit. Step 47: Confirm whether there are multiple bit flips; Calculate the recovery code of the current data area according to the method in Step 36. If the recovery code is equal to the recovery code in the second-level error correction code, it proves that the data bits are not wrong but the first-level check code is wrong. Then execute the error correction step 48. Otherwise, proceed to step 49; Step 48: Correct the erroneous Level 1 checksum; flip the Level 1 checksum corresponding to the read data member to complete the error correction; Step 49: Return the error and report it; Return the error code and report the error; Step 40: Return to read data; return the corrected data or the original data to the caller.

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