An integrated wired network adapter and its implementation method

Abstract

This application relates to the field of network communication equipment technology, and in particular to an integrated wired network adapter and its implementation method. The adapter includes: a core PCB board, an M.2 interface etched on one end of the core PCB board, a power management unit onboard to the core PCB board, a protocol conversion chip, a network controller, and an SFP+ interface soldered to the core PCB board. The M.2 interface, power management unit, protocol conversion chip, network controller, and SFP+ interface are electrically connected through internal wiring of the core PCB board and are integrated into a single physical entity through a permanent connection. This application helps to achieve integrated structure and enables compact devices without PCIe slots to expand to high-speed wired networks.

Description

Technical Field

[0001] This application relates to the field of network communication equipment technology, and in particular to an integrated wired network adapter and its implementation method. Background Technology

[0002] Most wired network adapters on the market currently adopt a split design, requiring separate mechanical connectors, external adapter cables, and independent power supply modules to achieve signal connection and power supply to the host. This design has several technical drawbacks: In the split design, mechanical connectors and adapter cable joints are high-risk points for failure, and long-term use or slight vibration can easily lead to poor contact and signal interruption; the external power supply module is greatly affected by voltage fluctuations, and different devices have different power supply specifications, which can easily lead to problems such as power supply incompatibility and voltage instability, thus affecting the stability of network transmission; traditional high-speed Ethernet cards rely on physical PCIe slots to achieve protocol communication, and cannot be adapted to compact devices without PCIe slots. This forces these devices to rely on wireless LANs, making it difficult to meet the high-speed network requirements of scenarios such as large file transfers, high-definition video streaming, and low-latency office work.

[0003] Therefore, in view of the above-mentioned shortcomings of existing technologies, there is an urgent need for an integrated wired network adapter that can fundamentally solve the pain point of high-speed wired network expansion for compact devices through integrated structure. Summary of the Invention

[0004] Therefore, it is necessary to address the aforementioned technical issues by providing an integrated wired network adapter and its implementation method that enables the expansion of high-speed wired networks into compact devices without PCIe slots.

[0005] In a first aspect, this application provides an integrated wired network adapter, comprising: a core PCB board, an M.2 interface etched on one end of the core PCB board, a power management unit onboard the core PCB board, a protocol conversion chip, a network controller, and an SFP+ interface soldered and fixed to the core PCB board;

[0006] The M.2 interface, the power management unit, the protocol conversion chip, the network controller, and the SFP+ interface are electrically connected through internal wiring on the core PCB board and are integrated into a single physical entity through a permanent connection.

[0007] In one embodiment, the input terminal of the power management unit is connected to the power pin of the M.2 interface, and the output terminal is electrically connected to the power pin of the protocol conversion chip, the network controller, and the SFP+ interface, respectively, for obtaining native power from the host and performing voltage regulation and voltage division processing to provide stable operating power for the SFP+ optical module.

[0008] In one embodiment, the protocol conversion chip is used to read the extended dedicated adapter protocol data carried by the M.2 interface and convert the extended dedicated adapter protocol data into standard PCIe protocol data to drive the network controller to work.

[0009] In one embodiment, the input terminal of the network controller receives PCIe protocol data output by the protocol conversion chip, and the output terminal is electrically connected to the SFP+ interface through the internal wiring of the core PCB board. This is used to realize bidirectional conversion, data verification, and high-speed transmission and reception of PCIe protocol data and 10 Gigabit high-speed electrical signals. The 10 Gigabit high-speed electrical signals are adapted to the signal transmission format of the SFP+ optical module.

[0010] In one embodiment, the SFP+ interface is used for physical connection with an SFP+ optical module to achieve stable transmission of 10 Gigabit-level high-speed electrical signals.

[0011] In one embodiment, a temperature monitoring module is integrated on the core PCB board, and the temperature monitoring module is electrically connected to the power management unit to exchange data;

[0012] When the temperature monitoring module detects that the operating temperature of the core PCB board exceeds the preset temperature threshold, the power management unit triggers the power regulation mechanism to reduce the output power.

[0013] Secondly, this application provides a method for implementing an integrated wired network adapter, the method comprising:

[0014] The M.2 interface, power management unit, protocol conversion chip, network controller, and SFP+ interface are integrated into the core PCB board via a permanent connection.

[0015] The host's native power is obtained through the M.2 interface, and the power management unit supplies power to the various functional components of the core PCB board and the SFP+ optical module.

[0016] The M.2 interface reads the extended dedicated adaptation protocol data generated by the host, which is then converted into PCIe protocol data adapted for 10 Gigabit transmission by the protocol conversion chip.

[0017] The network controller is driven to encode the PCIe protocol data into a 10 Gigabit high-speed electrical signal and send it to the SFP+ interface through the internal wiring of the core PCB board.

[0018] The SFP+ interface converts high-speed electrical signals into optical signals through the SFP+ optical module and transmits them to external network devices to complete data transmission.

[0019] In one embodiment, the method for implementing the integrated wired network adapter further includes:

[0020] The SFP+ interface receives 10 Gigabit high-speed electrical signals transmitted by the SFP+ optical module, which are obtained by converting optical signals transmitted from the external network through the SFP+ optical module.

[0021] High-speed electrical signals are transmitted to the network controller via the SFP+ interface and the internal wiring of the core PCB board.

[0022] The network controller decodes and verifies the high-speed electrical signal, converts it into PCIe protocol data, and transmits the PCIe protocol data to the protocol conversion chip.

[0023] The protocol conversion chip converts the PCIe protocol data into extended dedicated adapter protocol data, which is then transmitted to the host via the M.2 interface to complete data reception.

[0024] In one embodiment, when the protocol conversion chip converts the PCIe protocol data into the extended dedicated adapter protocol data, it employs a data caching mechanism to temporarily store the data to be converted, thereby avoiding data transmission congestion.

[0025] In one embodiment, the network controller uses the CRC32 check algorithm to verify the high-speed electrical signal, and the verification covers the frame header, frame data and frame trailer of the data packet. When an error is found during the verification, a retransmission request is triggered.

[0026] In summary, this application includes the following beneficial technical effects:

[0027] By integrating the M.2 interface, power management unit, protocol conversion chip, network controller, and SFP+ interface into a single core PCB board via a permanent connection, the system eliminates potential points of failure such as mechanical connectors, adapter cables, and interface connectors found in traditional separate designs. This avoids contact problems and signal interruptions caused by multiple adapters. The entire system is a single physical entity, allowing users to simply insert the M.2 interface into the host's M.2 slot without needing additional adapter cables or external power supplies, greatly simplifying the adaptation process. The protocol conversion chip enables the conversion between extended dedicated adapter protocol data and PCIe protocols, bypassing the dependence on physical PCIe slots and allowing compact devices without PCIe slots to expand to high-speed wired networks. Attached Figure Description

[0028] Figure 1 This is a structural block diagram of an integrated wired network adapter in one embodiment;

[0029] Figure 2This is a structural block diagram of an integrated wired network adapter in another embodiment;

[0030] Figure 3 This is a flowchart illustrating the implementation method of an integrated wired network adapter in one embodiment. Detailed Implementation

[0031] This invention provides an integrated wired network adapter and its implementation method.

[0032] The embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the accompanying drawings and embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0033] In the description of the embodiments disclosed in this invention, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0034] For ease of understanding, the specific process of the embodiments of the present invention is described below. Please refer to [link / reference]. Figure 1 One embodiment of the integrated wired network adapter in this invention includes: a core PCB board, an M.2 interface etched on one end of the core PCB board, a power management unit onboard to the core PCB board, a protocol conversion chip, a network controller, and an SFP+ interface soldered to the core PCB board; the M.2 interface, power management unit, protocol conversion chip, network controller, and RJ45 interface are electrically connected through internal wiring of the core PCB board and are integrated into one unit through a permanent connection method to form a single physical entity.

[0035] Specifically, the core PCB board, serving as the hardware foundation of the entire adapter, adopts the M.2 interface standard design. Its physical dimensions can flexibly adapt to the M.2 slot installation space of different host devices, and the board thickness is controlled between 1.2mm and 1.6mm, ensuring both mechanical strength and meeting the internal space constraints of compact devices. The core PCB board has pre-set chip pads, interface soldering positions, and internal wiring channels to achieve electrical conduction and physical fixation of various components. The M.2 interface, power management unit, protocol conversion chip, network controller, and SFP+ interface are core functional components. They do not exist independently or are spliced ​​together by cables. Instead, they are deeply integrated with the core PCB board through permanent connections, forming an inseparable whole. This structural design eliminates the failure points caused by mechanical connectors and adapter cables in traditional designs from the root, while significantly reducing the size of the adapter and perfectly meeting the installation requirements of compact devices. The permanent connection method specifically includes surface mount technology (SMT) and soldering process. The core chip is precisely soldered to the pre-set pads on the PCB board through SMT process, and the SFP+ interface is firmly fixed through soldering. The electrical connections of all components are completed through copper wire routing inside the PCB board, without any external redundant parts.

[0036] In one embodiment, the input of the power management unit is connected to the power pin of the M.2 interface, and the output is electrically connected to the power pin of the protocol conversion chip, the network controller, and the SFP+ interface, respectively, to obtain native power from the host and perform voltage regulation and division to provide stable operating power for the SFP+ optical module.

[0037] Specifically, the power management unit (PMU), as the core of the power supply system, uses an integrated power management chip. Its input end precisely connects to the power pins of the M.2 interface through internal PCB wiring, ensuring direct access to native power from the host. This design fully utilizes the host's native power supply capabilities, eliminating the need for an additional independent power supply module, simplifying the structure and improving power supply compatibility. The output end, through independent wiring channels on the core PCB, reliably connects to the power pins of the protocol conversion chip, the network controller, and the SFP+ interface. The core function of the PMU is to optimize the native power supply: on one hand, it suppresses voltage fluctuations through a voltage regulator circuit, ensuring the stability of the output power supply and preventing chip damage or performance fluctuations due to voltage instability; on the other hand, it converts the host's native power supply into the operating voltage of the protocol conversion chip, network controller, and SFP+ optical module through a voltage divider circuit, achieving precise power matching. Simultaneously, the PMU also integrates overvoltage protection, overcurrent protection, and electrostatic discharge (ESD) protection modules. When the input voltage exceeds the safe range or the output current is abnormal, it can automatically disconnect the power supply link, effectively protecting the adapter's core components and the host interface from damage, further enhancing the reliability of the power supply system.

[0038] In this embodiment, the power management unit directly obtains native power from the host, without the need for additional external power adapters or power cables, thus achieving integrated power supply. This completely eliminates the traditional external power supply mode of adapters and avoids compatibility issues caused by external power supplies.

[0039] In one embodiment, the protocol conversion chip is used to read the extended dedicated adapter protocol data carried by the M.2 interface and convert the extended dedicated adapter protocol data into standard PCIe protocol data to drive the network controller to work.

[0040] Specifically, the protocol conversion chip acts as a "protocol translator," connecting to the communication pins of the M.2 interface via internal PCB wiring. It specifically interfaces with the communication pins in the M.2 interface used for transmitting protocol data, ensuring accurate capture of signals transmitted by the host through this interface. When the adapter is inserted into the host's M.2 slot via the M.2 interface, the host generates expansion-specific adaptation protocol data based on high-speed network expansion needs, which is then transmitted to the adapter's M.2 interface. The protocol conversion chip reads this expansion-specific adaptation protocol data in real time. This protocol data is a communication command specific to the host and adapter, not the native protocol data of the M.2 interface, and cannot be directly recognized by the network controller of the PCIe architecture. This protocol data is dedicated interactive data designed for high-speed wired network expansion scenarios using the M.2 interface. Through standardized encoding and a dedicated transmission channel, it achieves accurate communication between the host and adapter, ultimately bypassing the dependence on the physical PCIe slot and ensuring the successful implementation of high-speed wired network expansion functionality in compact devices. To achieve protocol compatibility and functional compatibility, the protocol conversion chip incorporates pre-defined protocol mapping and conversion logic. This allows it to accurately convert the read extended-specific adapter protocol data into standard PCI protocol data that the network controller can directly recognize, according to standard rules. During the conversion process, the chip strictly ensures data integrity and accuracy, preventing data loss, distortion, or timing errors caused by protocol conversion, ensuring that the converted PCIe protocol data fully meets the network controller's operational requirements. After conversion, the chip transmits the standard PCIe protocol data to the onboard network controller via internal PCB routing, providing the controller with compatible drive signals to initiate high-speed data processing functions. This enables the conversion, verification, and transmission / reception of PCIe protocol data with high-speed electrical signals.

[0041] In this embodiment, a protocol conversion chip is used to achieve bidirectional conversion between extended dedicated adapter protocol data and standard PCIe protocol, bypassing the traditional Ethernet card's rigid requirement for physical PCIe slots. This allows compact devices without PCIe slots to expand high-speed wired networks, solving the core pain point that devices without PCIe slots cannot adapt to PCIe architecture network controllers.

[0042] In one embodiment, the input end of the network controller receives PCIe protocol data output by the protocol conversion chip, and the output end is electrically connected to the SFP+ interface through the internal wiring of the core PCB board. This is used to realize bidirectional conversion between PCIe protocol data and 10 Gigabit high-speed electrical signals, data verification, and high-speed transmission and reception. The 10 Gigabit high-speed electrical signals are adapted to the signal transmission mode of the SFP+ optical module.

[0043] Specifically, in the data transmission direction, after receiving the PCIe protocol data output from the protocol conversion chip, the network controller converts it into a 10 Gigabit high-speed electrical signal through its built-in encoding module. The format of this high-speed electrical signal strictly matches the signal transmission requirements of the SFP+ optical module, ensuring that the optical module can accurately receive and perform subsequent photoelectric conversion. On the other hand, it can receive the 10 Gigabit high-speed electrical signal transmitted through the SFP+ interface and converted by the SFP+ optical module, decode it back into PCIe protocol data, and feed it back to the protocol conversion chip, achieving bidirectional and accurate conversion between PCIe protocol data and 10 Gigabit high-speed electrical signals. To further ensure data integrity, the network controller has a built-in CRC32 check module, covering the frame header, frame data, and frame trailer of the data packet. When data errors, missing data, or tampering are detected, a retransmission request is automatically triggered. Furthermore, the network adapter is electrically connected to the SFP+ interface through internal PCB wiring, eliminating the need for any external adapter circuits, minimizing signal loss and interference, and ensuring signal integrity during high-speed transmission.

[0044] In one embodiment, the SFP+ interface is used for physical connection with an SFP+ optical module to achieve stable transmission of 10 Gigabit-level high-speed electrical signals.

[0045] Specifically, the SFP+ interface, as the core physical component for the integrated wired network adapter to interface with the SFP+ optical module, is firmly fixed to the core PCB board through a soldering process. It can achieve precise physical adaptation and reliable electrical connection with the SFP+ optical module. The core function of this interface is, on the one hand, to transmit the 10 Gigabit high-speed electrical signal adapted to the optical module's signal transmission format to the optical module without loss, providing a stable signal input for subsequent photoelectric conversion; on the other hand, it receives the 10 Gigabit high-speed electrical signal converted from the external optical signal by the SFP+ optical module and transmits it accurately to the network controller.

[0046] In one embodiment, a temperature monitoring module is integrated on the core PCB board. The temperature monitoring module is electrically connected to the power management unit and exchanges data with it. When the temperature monitoring module detects that the operating temperature of the core PCB board exceeds a preset temperature threshold, the power management unit triggers a power regulation mechanism to reduce the output power.

[0047] Specifically, such as Figure 2As shown, the temperature monitoring module integrated on the core PCB establishes a stable electrical connection with the power management unit and achieves real-time data exchange. The temperature detection module uses a high-precision sensor, which can accurately collect the real-time operating temperature of the core PCB. Its detection range covers the installation areas of core heat-generating components such as the power management unit, protocol conversion chip, and network controller, ensuring the comprehensiveness and accuracy of temperature data. When the temperature monitoring module detects that the operating temperature of the core PCB exceeds the preset temperature threshold, it will immediately send a temperature over-limit signal to the power management unit. After receiving the signal, the power management unit automatically triggers the power regulation mechanism, reducing the power supply by lowering the output voltage or limiting the output current, thereby reducing the heat generation of the core components.

[0048] In this embodiment, the temperature monitoring module can effectively prevent the adapter from running at high speed for a long time, or the temperature from rising continuously due to excessively high ambient temperature or poor ventilation. This prevents the core chip from experiencing performance degradation and reduced transmission rate due to high temperature, and further eliminates safety hazards such as component burnout and short circuits caused by high temperature, significantly improving the working stability and service life of the adapter.

[0049] In one embodiment, such as Figure 3 As shown, an implementation method for an integrated wired network adapter is provided, including:

[0050] The S100 integrates the M.2 interface, power management unit, protocol conversion chip, network controller, and SFP+ interface onto the core PCB board via a permanent connection.

[0051] The S200 obtains the host's native power through the M.2 interface and supplies power to the various functional components on the core PCB board and the SFP+ optical module through the power management unit;

[0052] The S300 reads the extended dedicated adapter protocol data generated by the host through the M.2 interface, and converts it into PCIe protocol data adapted for 10 Gigabit transmission via a protocol conversion chip;

[0053] The S400 drives the network controller to encode PCIe protocol data into 10 Gigabit high-speed electrical signals, which are then sent to the SFP+ interface through the internal wiring of the core PCB board.

[0054] The S500's SFP+ interface converts high-speed electrical signals into optical signals via SFP+ optical modules and transmits them to external network devices to complete data transmission.

[0055] Specifically, the core components are integrated through a permanent connection, precisely mounting the M.2 interface, power management unit, protocol conversion chip, network controller, and SFP+ interface onto the core PCB board. All components are electrically connected through internal wiring on the PCB board, ultimately forming an inseparable single physical entity, laying the hardware foundation for subsequent functionalities. Then, after the adapter is inserted into the host's M.2 slot via the M.2 interface, the power supply link is automatically activated. Specifically, the power pins of the M.2 interface are connected to the host's power output, obtaining native power. This power is transmitted to the onboard power management unit, where it is regulated and divided to convert into a stable operating voltage suitable for the protocol conversion chip, network controller, and SFP+ optical module, providing continuous and reliable power support for all core components without the need for additional external power supply equipment. In the communication protocol adaptation phase, the host generates dedicated adaptation protocol data based on expansion requirements. This protocol data is transmitted from the host to the adapter's M.2 interface. The adapter then sends this data to the protocol conversion chip via internal wiring on the core PCB board. The protocol conversion chip accurately converts the dedicated adaptation protocol data into standard PCIe protocol data recognizable by the network controller according to preset mapping rules. This bypasses the dependence of traditional high-speed Ethernet cards on physical PCIe slots, achieving compatibility between PCIe slotless devices and PCIe architecture network controllers. The converted PCIe protocol data is then transmitted to the network controller. The network controller initiates its encoding function, converting the PCIe protocol data into 10 Gigabit Ethernet high-speed electrical signals. These signals are then transmitted to the SFP+ interface via internal wiring on the core PCB board, eliminating the need for external adapter cables and reducing signal loss. Finally, the SFP+ interface converts the high-speed electrical signals into optical signals via an SFP+ optical module and transmits them to external network devices, completing the data transmission.

[0056] In one embodiment, the method for implementing the integrated wired network adapter further includes:

[0057] The system receives 10 Gigabit high-speed electrical signals transmitted from SFP+ optical modules via the SFP+ interface. These signals are obtained by converting optical signals transmitted from external networks using the SFP+ optical modules. The high-speed electrical signals are then transmitted to the network controller via internal wiring on the core PCB board through the SFP+ interface. The network controller decodes and verifies the high-speed electrical signals, converts them into PCIe protocol data, and transmits the PCIe protocol data to the protocol conversion chip. The protocol conversion chip converts the PCIe protocol data into extended dedicated adapter protocol data, which is then transmitted to the host via the M.2 interface, completing the data reception.

[0058] Specifically, in the data reception stage, the SFP+ optical module first converts the optical signal transmitted from the external network into a 10 Gigabit-level high-speed electrical signal and transmits it to the SFP+ interface of the adapter. Subsequently, the high-speed electrical signal is transmitted to the network controller through the internal wiring of the core PCB board, avoiding signal loss caused by external conversion. After receiving the signal, the network controller first uses the decoding module to restore the high-speed electrical signal into digital data, and then uses the CRC32 verification module to perform integrity verification on the data to ensure that the received data is error-free. After the verification is passed, the data is converted into PCIe protocol data and transmitted to the protocol conversion chip. After receiving the PCIe protocol data, the protocol conversion chip converts the PCIe protocol data in reverse into extended dedicated adapter protocol data that the host can recognize, and finally transmits it to the host through the M.2 interface, completing the entire data reception process and ensuring that the host can accurately obtain external network data and realize bidirectional communication with the external network.

[0059] In one embodiment, when the protocol conversion chip converts PCIe protocol data into extended dedicated adapter protocol data, it employs a data caching mechanism to temporarily store the data to be converted, thereby avoiding data transmission congestion.

[0060] Specifically, in high-speed network transmission scenarios, external network data may flood in. If the protocol conversion chip directly converts all data in real time, insufficient conversion rate may lead to data accumulation, resulting in transmission congestion or data loss. This invention achieves temporary storage of data to be converted by incorporating a buffer unit within the protocol conversion chip. When a large amount of PCIe protocol data is transmitted to the protocol conversion chip, the chip first stores the data in the buffer unit and then converts it sequentially according to the "first-in, first-out" principle, ensuring an orderly and efficient conversion process.

[0061] In one embodiment, the network controller uses the CRC32 check algorithm to verify the high-speed electrical signal, and the verification covers the frame header, frame data and frame trailer of the data packet. When an error is found during the verification, a retransmission request is triggered.

[0062] Specifically, the CRC32 checksum algorithm is a core technology for ensuring the accuracy of data transmission. It features high accuracy and fast processing speed, and is widely used in high-speed data transmission scenarios. During data reception, the network controller performs a comprehensive check on the data packets obtained after decoding the high-speed electrical signals. The check covers the frame header (containing address and control information), the frame data body (core transmission content), and the frame trailer (checksum and end marker), ensuring that every part of the data packet is accurately checked without omissions. When the checksum algorithm detects errors, missing data, or tampering in the data packet, the network controller immediately sends a retransmission request to the external network device. The number of retransmissions does not exceed three, with a retransmission interval of 2ms, ensuring that the correct data packet can be quickly obtained. This checksum-retransmission mechanism provides fault tolerance for data transmission, effectively compensating for potential signal interference and attenuation issues during network cable transmission, controlling the error rate of data transmission, and ensuring that all data received by the host is complete and accurate, providing reliable assurance for subsequent data processing and applications.

[0063] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. An integrated wired network adapter, characterized in that, include: The core PCB board, the M.2 interface etched on one end of the core PCB board, the power management unit, the protocol conversion chip, the network controller, and the SFP+ interface soldered and fixed to the core PCB board are all included. The M.2 interface, the power management unit, the protocol conversion chip, the network controller, and the SFP+ interface are electrically connected through internal wiring on the core PCB board and are integrated into a single physical entity through a permanent connection. The protocol conversion chip is used to read the extended dedicated adapter protocol data carried by the M.2 interface, and convert the extended dedicated adapter protocol data into standard PCIe protocol data to drive the network controller to work.

2. The integrated wired network adapter according to claim 1, characterized in that, The input terminal of the power management unit is connected to the power pin of the M.2 interface, and the output terminal is electrically connected to the power pin of the protocol conversion chip, the network controller, and the SFP+ interface, respectively. It is used to obtain native power from the host and perform voltage regulation and voltage division to provide stable operating power for the SFP+ optical module.

3. The integrated wired network adapter according to claim 1, characterized in that, The network controller receives PCIe protocol data output by the protocol conversion chip at its input end, and its output end is electrically connected to the SFP+ interface through the internal wiring of the core PCB board. This is used to realize bidirectional conversion, data verification, and high-speed transmission and reception of PCIe protocol data and 10 Gigabit high-speed electrical signals. The 10 Gigabit high-speed electrical signals are adapted to the signal transmission format of the SFP+ optical module.

4. The integrated wired network adapter according to claim 1, characterized in that, The SFP+ interface is used for physical connection with the SFP+ optical module to achieve stable transmission of 10 Gigabit-level high-speed electrical signals.

5. An integrated wired network adapter according to claim 1, characterized in that, The core PCB board integrates a temperature monitoring module, which is electrically connected to the power management unit and enables data exchange. When the temperature monitoring module detects that the operating temperature of the core PCB board exceeds the preset temperature threshold, the power management unit triggers the power regulation mechanism to reduce the output power.

6. A method for implementing an integrated wired network adapter, characterized in that, include: The M.2 interface, power management unit, protocol conversion chip, network controller, and SFP+ interface are integrated into the core PCB board via a permanent connection. The host's native power is obtained through the M.2 interface, and the power management unit supplies power to the various functional components of the core PCB board and the SFP+ optical module. The M.2 interface reads the extended dedicated adaptation protocol data generated by the host, which is then converted into PCIe protocol data adapted for 10 Gigabit transmission by the protocol conversion chip. The network controller is driven to encode the PCIe protocol data into a 10 Gigabit high-speed electrical signal and send it to the SFP+ interface through the internal wiring of the core PCB board. The SFP+ interface converts high-speed electrical signals into optical signals through the SFP+ optical module and transmits them to external network devices to complete data transmission.

7. The method for implementing an integrated wired network adapter according to claim 6, characterized in that, Also includes: The SFP+ interface receives 10 Gigabit high-speed electrical signals transmitted by the SFP+ optical module, which are obtained by converting optical signals transmitted from the external network through the SFP+ optical module. High-speed electrical signals are transmitted to the network controller via the SFP+ interface and the internal wiring of the core PCB board. The network controller decodes and verifies the high-speed electrical signal, converts it into PCIe protocol data, and transmits the PCIe protocol data to the protocol conversion chip. The protocol conversion chip converts the PCIe protocol data into extended dedicated adapter protocol data, which is then transmitted to the host via the M.2 interface to complete data reception.

8. The method for implementing an integrated wired network adapter according to claim 7, characterized in that, When the protocol conversion chip converts the PCIe protocol data into the extended dedicated adapter protocol data, it adopts a data caching mechanism to temporarily store the data to be converted and avoid data transmission congestion.

9. The method for implementing an integrated wired network adapter according to claim 7, characterized in that, The network controller uses the CRC32 check algorithm to verify the high-speed electrical signal, and the verification covers the frame header, frame data and frame trailer of the data packet. When an error is found during the verification, a retransmission request is triggered.

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