High-precision semiconductor chip surface defect detection method and system

Abstract

The invention discloses a high-precision semiconductor chip surface defect detection method and system. The method comprises the following steps: collecting chip surface data; multi-level image features are extracted through data; dynamically calculating and updating the gray threshold graph to obtain a two-dimensional defect suspected area; a chip surface three-dimensional shape model is generated through the three-dimensional point cloud data; carrying out fusion matching on the two-dimensional image features and the three-dimensional morphology features, and judging defect types and spatial positions; according to the defect judgment result, the comprehensive detection report information is matched with production line process parameters, and when the occurrence frequency of the defect exceeds a preset threshold value, a process parameter adjustment suggestion is generated. According to the high-precision semiconductor chip surface defect detection method and system, two-dimensional image and three-dimensional point cloud data are acquired at the same time, and multi-level image feature extraction and three-dimensional morphology reconstruction are combined, so that collaborative analysis of two-dimensional texture and three-dimensional morphology of surface defects is realized; and the accuracy and the reliability of defect identification, especially morphology defects, are obviously improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a high-precision method and system for detecting surface defects in semiconductor chips. Background Technology

[0002] As integrated circuit manufacturing processes continue to evolve towards nanometer nodes, chip failures often originate from minute defects. Currently, detecting such defects relies on large auxiliary equipment such as scanning electron microscopes (SEM), focused ion beam microscopes (FIB), or transmission electron microscopes (TEM) for scanning imaging to locate the defects. However, as device sizes continue to shrink, obtaining high-magnification images of ultra-small defects becomes increasingly difficult, posing a serious challenge to both detection efficiency and imaging quality.

[0003] In wafer fabrication, scratches and other damage layers are often present on the surface after chemical mechanical polishing. These scratches are fine, deep, randomly located, and irregularly shaped, severely affecting the quality of subsequent epitaxial growth and device performance. Due to the tiny size of semiconductors, scratches are difficult to detect with the naked eye; furthermore, the rough surface after polishing further reduces the difference between shallow scratches and the surrounding environment, significantly increasing the difficulty of detection. Currently, surface scratch detection in the production process still largely relies on manual or traditional visual recognition, which is not only costly and prone to fatigue-induced missed detections, but also has limited ability to identify inconspicuous scratches based on conventional edge detection algorithms, making it difficult to adapt to the current high-speed production environment. Existing detection methods have significant limitations in addressing these issues. Detection processes relying on large equipment are inefficient and cannot meet the real-time monitoring needs of production lines; traditional two-dimensional vision-based methods struggle to obtain three-dimensional geometric information such as scratch depth and curvature, and image segmentation algorithms with fixed thresholds are easily affected by fluctuations in ambient lighting, failing to stably reflect the intrinsic properties of the material. Crucially, existing measurement methods lack the ability to directly measure the core physical characteristic of the surface's three-dimensional morphology.

[0004] To address the aforementioned problems, this invention proposes a high-precision method and system for detecting surface defects in semiconductor chips. Summary of the Invention

[0005] In view of the problems existing in the above-mentioned methods for detecting surface defects in semiconductor chips, the present invention is proposed.

[0006] Therefore, the purpose of this invention is to provide a high-precision semiconductor chip surface defect detection method and system, which aims to achieve high-precision and robust online detection and quantitative determination of abnormal material physical properties caused by semiconductor chip surface defects by integrating three-dimensional vision and multi-scale intelligent analysis.

[0007] To address the aforementioned technical problems, this invention provides a high-precision method for detecting surface defects in semiconductor chips, comprising the following steps: Two-dimensional image data and three-dimensional point cloud data of the surface of the chip under test are collected.

[0008] The two-dimensional image data is preprocessed to extract multi-level image features containing macroscopic contours and microscopic textures.

[0009] Based on the local grayscale statistics of the two-dimensional image data, the grayscale threshold map used for defect segmentation is dynamically calculated and updated.

[0010] The grayscale threshold image is used to perform binarization segmentation on the multi-level image features to obtain a two-dimensional suspected defect region.

[0011] The three-dimensional point cloud data is registered and reconstructed to generate a three-dimensional topographic model of the chip surface.

[0012] The image features of the suspected two-dimensional defect area are fused and matched with the morphological features of the three-dimensional morphological model to determine the defect category and spatial location.

[0013] Based on the defect determination results, a comprehensive inspection report is generated, including the defect type, location, and size.

[0014] The defect statistics in the comprehensive inspection report are correlated and matched with the production line process parameter records. When the frequency of defect occurrence exceeds the preset process alarm threshold, corresponding process parameter adjustment suggestions are generated.

[0015] As a preferred embodiment of the high-precision semiconductor chip surface defect detection method of the present invention, the process of extracting the multi-level image features includes: The preprocessed image is input into a multi-scale feature extraction network, which outputs a first-scale feature map and a second-scale feature map respectively. The feature saliency of each pixel in the first-scale feature map is calculated. If the feature saliency is higher than a first saliency threshold, the pixel region is marked as a macroscopic candidate region. The texture complexity of each pixel in the second-scale feature map is calculated. If the texture complexity is lower than a texture smoothing threshold, the pixel region is marked as a microscopic candidate region. The macroscopic candidate regions and microscopic candidate regions are merged to generate the multi-level image features.

[0016] As a preferred embodiment of the high-precision semiconductor chip surface defect detection method of the present invention, the process of dynamically calculating and updating the grayscale threshold image includes: The image is divided into multiple overlapping local windows; within each window, the gray-level mean and gray-level standard deviation are calculated; based on the threshold of the previous window, the gray-level mean and gray-level standard deviation of the current window, the update threshold of the current window is calculated using a filtering algorithm; if the deviation between the update threshold of the current window and the global average threshold exceeds the dynamic range threshold, the threshold after limiting the amplitude is used as the output; all windows are traversed to generate the continuously changing gray-level threshold map.

[0017] As a preferred embodiment of the high-precision semiconductor chip surface defect detection method of the present invention, the process of generating a three-dimensional morphological model of the chip surface includes: Receive 3D point cloud datasets from multiple viewpoints; register adjacent point cloud datasets; if the registration error exceeds the registration tolerance threshold, re-acquire point clouds from that viewpoint; stitch all registered point clouds together to form a complete point cloud; reconstruct the surface of the complete point cloud to generate a triangular mesh model; if the curvature change of the surface of the model exceeds the curvature smoothing threshold, perform smoothing filtering on the region.

[0018] As a preferred embodiment of the high-precision semiconductor chip surface defect detection method of the present invention, the process of fusion matching to determine defects includes: A feature fusion network comprising a two-dimensional image branch and a three-dimensional morphology branch is constructed. The multi-level image features are input into the two-dimensional image branch, and a two-dimensional defect feature vector is output. The three-dimensional morphology model is input into the three-dimensional morphology branch, and a three-dimensional defect feature vector is output. The two-dimensional defect feature vector and the three-dimensional defect feature vector are weighted and fused. If the classification confidence of the fused feature vector is higher than the defect judgment threshold, it is judged as a real defect, and the defect category and location coordinates are output.

[0019] As a preferred embodiment of the high-precision semiconductor chip surface defect detection method of the present invention, it further includes deploying a rapid screening step on the production line side: A simplified version of the feature fusion network is run in the edge computing device. The simplified version of the feature fusion network only includes a two-dimensional image branch. If the defect confidence score output by the simplified version of the feature fusion network is lower than the fast pass threshold, the chip is determined to be defect-free and the detection ends. If the defect confidence score is higher than the fast pass threshold, the complete two-dimensional image and three-dimensional point cloud data of the corresponding chip are uploaded to the cloud server to perform full-process detection.

[0020] As a preferred embodiment of the high-precision semiconductor chip surface defect detection method of the present invention, the process of generating corresponding process parameter adjustment suggestions includes: Establish a database linking defect types with process parameters; count the number of each type of defect in the current batch of chips; if the number of any type of defect exceeds the batch defect threshold, trigger process traceability; search the database for the process parameter with the highest correlation to the defect type; and generate the adjustment direction and suggested adjustment amount for the process parameter based on historical optimization records.

[0021] A high-precision semiconductor chip surface defect detection system, used in the aforementioned high-precision semiconductor chip surface defect detection method, includes: The image acquisition module is used to acquire two-dimensional images and three-dimensional point cloud data of the chip surface.

[0022] The computational processing module is used to perform multi-level image feature extraction, grayscale threshold calculation, three-dimensional shape reconstruction, feature fusion matching, and defect determination.

[0023] The report generation module is used to generate and output a comprehensive test report.

[0024] The process feedback module is used to generate and output suggestions for adjusting process parameters.

[0025] In a preferred embodiment of the high-precision semiconductor chip surface defect detection method of the present invention, the computational processing module adopts a hierarchical computational architecture, including: Edge computing units, deployed on the production line side, are used to perform rapid screening steps; The deep computing unit, deployed in the cloud, is used to perform the entire inspection process. The edge computing unit and the deep computing unit interact with each other through data compression and encrypted transmission.

[0026] As a preferred embodiment of the high-precision semiconductor chip surface defect detection method of the present invention, it further includes: The environmental monitoring module is used to collect and monitor environmental temperature, humidity, and vibration data in real time.

[0027] The adaptive compensation module is used to dynamically adjust the acquisition parameters of the image acquisition module and the judgment threshold of the calculation and processing module based on the data from the environmental monitoring module. If the environmental data exceeds the stable operating range, the system self-calibration process is triggered.

[0028] The beneficial effects of this invention are as follows: The high-precision semiconductor chip surface defect detection method and system proposed in this invention achieves high-precision and robust detection of semiconductor chip surface defects and process closed-loop optimization through multi-dimensional data fusion and intelligent analysis. By simultaneously acquiring two-dimensional images and three-dimensional point cloud data, and combining multi-level image feature extraction and three-dimensional morphology reconstruction, collaborative analysis of the two-dimensional texture and three-dimensional morphology of surface defects is achieved, significantly improving the accuracy and reliability of defect identification, especially morphology-related defects. By deploying edge computing units for rapid screening, triggering full-process deep detection in the cloud only for suspected defect samples, the amount of data transmission and cloud computing load are greatly reduced, significantly improving production line detection throughput and real-time response while ensuring detection accuracy. By establishing a database linking defect types and process parameters, and automatically triggering process traceability and parameter adjustment suggestions based on defect occurrence frequency, the detection results are directly fed back to the manufacturing process, forming a "detection-analysis-optimization" closed loop, which helps to suppress defect generation from the source and continuously improve production yield and process stability. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic diagram of the rapid screening process of the present invention is shown; Figure 2 The present invention is shown Figure 1 A flowchart illustrating the entire testing process; Figure 3 A schematic diagram of the overall system flow of the present invention is shown. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0032] The terminology used in this invention is that which is currently widely used in the art in consideration of the function of the invention; however, these terms may vary according to the intent of those skilled in the art, precedent, or new technology in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of the invention. Therefore, the terms used in this specification should not be construed as simple names, but rather based on their meanings and the overall description of the invention.

[0033] Reference Figure 1, Figure 2 A high-precision method for detecting surface defects in semiconductor chips is provided, which includes the following steps: Two-dimensional image data and three-dimensional point cloud data of the chip surface under test are acquired. A high-resolution area scan camera (e.g., 50 megapixels) paired with a programmable ring light source is used to acquire RGB images of the chip surface within a constant temperature and humidity chamber. Simultaneously, a multi-axis structured light scanner (e.g., a blue light scanner) projects coded light stripes from three different angles to acquire three-dimensional point cloud data of the chip surface. The images and point cloud data are synchronously transmitted to the collaborative computing module via gigabit Ethernet.

[0034] Two-dimensional image data is preprocessed to extract multi-level image features containing both macroscopic contours and microscopic textures. Preprocessing of the original image information includes grayscale conversion, Gaussian filtering for noise reduction, and histogram equalization to enhance contrast. The extracted features include edge contours based on sub-pixel edge operators (macroscopic features) and local texture patterns based on local binary pattern operators (microscopic features).

[0035] Based on local grayscale statistics of two-dimensional image data, a grayscale threshold map for defect segmentation is dynamically calculated and updated. The dynamic grayscale threshold map calculates the local mean and variance through a sliding window, and combines it with the threshold update of the previous window to form an adaptive threshold surface.

[0036] By using grayscale thresholding to perform binarization segmentation on multi-level image features, two-dimensional suspected defect regions are obtained. These two-dimensional suspected defect regions are obtained through thresholding segmentation and morphological opening operations.

[0037] The 3D point cloud data is registered and reconstructed to generate a 3D topographic model of the chip surface. Multi-view stitching is performed using an iterative nearest-point registration operator, and then a Poisson surface reconstruction operator is used to generate a triangular mesh surface model.

[0038] The image features of suspected 2D defect areas are fused and matched with the morphological features of a 3D topography model to determine the defect category and spatial location. In the feature fusion stage, a trained lightweight convolutional neural network (CNN) is used to concatenate the 2D features and 3D height map features through channels, and then a fully connected layer is used to classify and output the defect category (such as scratches, stains, and bumps) and 3D coordinates.

[0039] Based on the defect determination results, a comprehensive inspection report is generated, including the defect type, location, and size.

[0040] The system correlates and matches defect statistics from the comprehensive inspection report with production line process parameters. When the frequency of a defect exceeds a preset process alarm threshold, corresponding process parameter adjustment suggestions are generated. The system also correlates defect information from the comprehensive inspection report with a pre-stored process parameter database to generate process optimization feedback instructions. A defect-process parameter correlation matrix is ​​established, and a mutual information algorithm is used to analyze the correlation between parameters and defects. When a certain type of defect occurs more than 5 times in 100 consecutive chips, an alarm is automatically triggered, and adjustments to relevant process parameter settings are recommended.

[0041] Furthermore, the process of extracting multi-level image features includes: inputting the preprocessed image into a multi-scale feature extraction network, which outputs a first-scale feature map and a second-scale feature map respectively; calculating the feature saliency of each pixel in the first-scale feature map, and if the feature saliency is higher than a first saliency threshold, then the pixel region is marked as a macroscopic candidate region; calculating the texture complexity of each pixel in the second-scale feature map, and if the texture complexity is lower than a texture smoothing threshold, then the pixel region is marked as a microscopic candidate region; merging the macroscopic candidate regions and the microscopic candidate regions to generate multi-level image features.

[0042] The multi-scale feature extraction network employs a dual-branch structure: branch one downsamples to the original... Figure 1 For the first branch, the edge response map is extracted as the first-scale feature map, while the second branch maintains the original image size and extracts the local binary pattern histogram as the second-scale feature map. Feature saliency is calculated by the ratio of the gradient magnitude of each pixel in the edge map to the average gradient of its neighborhood. If this ratio is greater than 2.0, it is considered a macroscopic candidate region. Texture complexity is calculated by the number of local binary patterns within the local region. If the number of patterns is less than 8 (i.e., the texture is relatively simple), it is considered a microscopic candidate region. Finally, the two types of candidate regions are merged using a pixel-level logical "OR" operation, and the merged result is filled with holes to form a continuous multi-layered feature mask.

[0043] Furthermore, the process of dynamically calculating and updating the grayscale threshold image includes: dividing the image into multiple overlapping local windows; calculating the grayscale mean and standard deviation within each window; calculating the updated threshold for the current window using a filtering algorithm based on the threshold of the previous window and the grayscale mean and standard deviation of the current window; if the deviation between the updated threshold of the current window and the global average threshold exceeds the dynamic range threshold, then using the threshold after limiting the amplitude as the output; and traversing all windows to generate a continuously changing grayscale threshold image.

[0044] The dynamic threshold calculation traverses the entire grayscale image using a 64×64 pixel sliding window. Within each window, the grayscale mean μ and standard deviation σ are calculated. An improved update strategy is employed, with its observation equation being a user-defined formula: , where z kμ is the observation threshold for the k-th window. k σ is the mean gray level of the window. k Let T be the standard deviation of the window's grayscale, and α be a texture adjustment factor (usually set to 0.2-0.5, adaptively determined based on the overall image contrast). This formula incorporates the squared ratio of the standard deviation to the mean as a texture fluctuation term into the observed value, making the threshold more sensitive in areas with complex textures. If the threshold T calculated for a certain window... k With global mean threshold T g If the absolute difference is greater than 30 (grayscale level), then for T k Apply soft limiting: Finally, a smooth grayscale threshold image is generated through bilinear interpolation.

[0045] Furthermore, the process of generating a three-dimensional topography model of the chip surface includes: receiving three-dimensional point cloud datasets from multiple perspectives; registering adjacent point cloud datasets, and if the registration error is greater than the registration tolerance threshold, re-acquiring point clouds from that perspective; stitching all registered point clouds together to form a complete point cloud; reconstructing the surface of the complete point cloud to generate a triangular mesh model, and if the curvature change of the surface of the model exceeds the curvature smoothing threshold, then performing smoothing filtering on the region.

[0046] During the 3D reconstruction process, a 6-axis robotic arm carrying a line laser scanner acquires point clouds from five fixed angles. Registration employs an iterative nearest-point algorithm, with a maximum of 50 iterations and a registration tolerance threshold of 0.1 mm. If the median residual after a registration exceeds 0.1 mm, the robotic arm is controlled to rescan that angle. The stitched point cloud is then downsampled using a voxel grid (0.01 mm grid size) and a Poisson surface is used to reconstruct a triangular mesh. The curvature of each vertex in the generated mesh is calculated; if the average curvature of the three vertices of a triangular facet exceeds 0.5 mm... -1 Then, Laplacian smoothing filtering is applied to the patch and its neighboring patches, iterating 3 times.

[0047] Furthermore, the process of fusion matching to determine defects includes: constructing a feature fusion network containing a two-dimensional image branch and a three-dimensional shape branch; inputting multi-level image features into the two-dimensional image branch and outputting a two-dimensional defect feature vector; inputting the three-dimensional shape model into the three-dimensional shape branch and outputting a three-dimensional defect feature vector; performing weighted fusion of the two-dimensional defect feature vector and the three-dimensional defect feature vector; if the classification confidence of the fused feature vector is higher than the defect determination threshold, it is determined to be a real defect, and the defect category and location coordinates are output.

[0048] The feature fusion network employs a dual-input, single-output structure. The 2D branch is a 4-layer convolutional network, taking a 256×256 grayscale feature map as input and outputting a feature vector for the 2D branch. The 3D branch voxels the triangular mesh model (0.02mm resolution), inputs it into a 3D convolutional neural network, and outputs a feature vector for the 3D branch. The fusion module concatenates the two vectors into a new vector, which is then mapped to the number of defect categories (e.g., 8 categories) through a fully connected layer. A defect determination threshold of 0.85 is set; if the output value of a certain category exceeds this threshold, it is determined to be a defect of that category. The location of the defect in the image and the 3D model is then jointly output through the deconvolutional layer of the 2D branch and the coordinate regression layer of the 3D branch.

[0049] Furthermore, it also includes deploying a rapid screening step on the production line side: running a simplified version of the feature fusion network in an edge computing device, which only contains a two-dimensional image branch; if the defect confidence score output by the simplified feature fusion network is lower than the fast pass threshold, the chip is determined to be defect-free and the detection ends; if the defect confidence score is higher than the fast pass threshold, the complete two-dimensional image and three-dimensional point cloud data of the corresponding chip are uploaded to the cloud server for full-process detection.

[0050] The rapid screening step is deployed on the production line's industrial control computer. The simplified network retains only the first two convolutional layers and one global average pooling layer of the two-dimensional branch from the above method, outputting a feature vector followed by a binary classification fully connected layer (defect / no defect). The pass threshold in the rapid screening stage is not fixed but dynamically adjusted based on the detection results of the most recent batch of chips. When the number of defects increases recently, the system automatically lowers the pass threshold to make the screening standard more stringent and prevent missed defects. When the production line stabilizes, the threshold gradually rises again to avoid excessive interception. For example, the pass threshold is set to 0.7. If the output value is below 0.7, the chip directly flows to the next process, and "passed" is recorded in the local log. If it is above 0.7, the chip ID, original image, and original point cloud data are packaged and uploaded to the cloud server queue for deep analysis. This design allows 95% of normal chips to be screened within 50ms, with only 5% of suspected chips triggering full inspection, greatly reducing data transmission and cloud load.

[0051] Furthermore, the process of generating corresponding process parameter adjustment suggestions includes: establishing a database linking defect types with process parameter items; counting the number of various defects in the current batch of chips, and triggering process traceability if the number of any type of defect exceeds the batch defect threshold; searching the database for the process parameter item with the highest correlation to the defect type; and generating the adjustment direction and suggested adjustment amount for the process parameter item based on historical optimization records.

[0052] The process feedback module has a built-in relational matrix database. Rows represent defect types (e.g., D1: scratches, D2: oxidation), and columns represent process parameters (e.g., P1: etching time, P2: nitrogen flow rate). Matrix element values ​​are mutual information values ​​calculated based on historical data. After each batch (e.g., 300 pieces) is inspected, the system calculates the frequency of each type of defect. If the frequency of a defect exceeds a preset threshold (e.g., scratches > 2%), the system selects the top 3 process parameters with the highest mutual information values ​​for that defect from the matrix. Next, it queries the "Optimization Case Library," which stores key-value pairs. The key is "defect type + parameter combination," and the value is a historical adjustment record (e.g., "increase deionized water rinsing time by 10%"). The system automatically generates a suggestion in the format: "A high scratch incidence rate (2.5%) was detected. It is recommended to prioritize adjusting the etching time (currently 120s, recommended to reduce to 115s), based on: 3 similar historical cases, after which the average incidence rate decreased to 1.2%." A high-precision semiconductor chip surface defect detection system, referring to Figure 3 The high-precision semiconductor chip surface defect detection method described above includes: an image acquisition module for acquiring two-dimensional images and three-dimensional point cloud data of the chip surface; a calculation and processing module for performing multi-level image feature extraction, grayscale threshold map calculation, three-dimensional morphology reconstruction, feature fusion matching, and defect judgment; a report generation module for generating and outputting a comprehensive inspection report; and a process feedback module for generating and outputting process parameter adjustment suggestions.

[0053] The system hardware is integrated into a closed inspection cabinet. The image acquisition module includes a monochrome area array camera, a blue laser line scanner, and a programmable RGBW ring light source. The computing and processing module adopts a distributed architecture: the industrial control computer is responsible for acquisition control and real-time 2D processing, while the workstation is responsible for 3D reconstruction and fusion analysis. The report generation module writes the results to the database and simultaneously generates reports and sends messages to the system. The process feedback module runs as an independent service, reading real-time process parameters and pushing adjustment suggestions to the process control console.

[0054] Furthermore, edge computing units are deployed on the production line side to perform rapid screening steps; deep computing units are deployed in the cloud to perform full-process testing steps; edge computing units and deep computing units interact with each other through data compression and encrypted transmission.

[0055] The edge computing unit utilizes ruggedized industrial computers to deploy rapid screening models and image preprocessing pipelines. The deep computing unit is a cloud-based virtual machine cluster. Every 100 chips processed by the edge unit, a heartbeat packet and batch data are sent to the cloud. Upon receiving the data, the cloud returns an acknowledgment and a model update instruction, such as a monthly incremental model update.

[0056] Furthermore, it also includes: an environmental monitoring module for real-time acquisition of temperature, humidity, and vibration data of the detection environment; and an adaptive compensation module for dynamically adjusting the acquisition parameters of the image acquisition module and the judgment threshold of the calculation and processing module based on the data from the environmental monitoring module. If the environmental data exceeds the stable operating range, the system self-calibration process is triggered.

[0057] The environmental monitoring module is integrated inside the testing cabinet and includes a high-precision temperature and humidity sensor and a triaxial vibration sensor. The software portion of the adaptive compensation module reads the sensor data in real time. If the environmental conditions exceed the limit for more than 30 seconds, the system automatically pauses testing, starts the thermoelectric cooler and dehumidifier inside the cabinet, and executes a self-calibration process using a set of standard whiteboard images to recalibrate the camera parameters and lighting model until the environment stabilizes, at which point testing automatically resumes.

[0058] This invention employs a high-resolution area array camera and a multi-axis structured light scanner in synergy to ensure the synchronization and high fidelity of 2D images and 3D point cloud data. Through multi-view point cloud registration and high-precision surface reconstruction, the generated triangular mesh model accurately reflects the microscopic morphology of the chip surface, providing a reliable data foundation for the stereoscopic localization and quantitative analysis of defects. A multi-scale feature extraction network captures macroscopic contour and microscopic texture features respectively, and adaptive binarization segmentation is performed using dynamically calculated grayscale threshold maps. This effectively distinguishes between real defects and complex background textures, improving the accuracy of defect-suspected area extraction and reducing false negatives and false positives. Local statistics and filtering update strategies are introduced in the dynamic threshold calculation, and an environmental monitoring module compensates for interference factors such as temperature, humidity, and vibration in real time, enabling the system to maintain stable detection performance in non-ideal industrial environments and reducing the stringent requirements of external conditions. The constructed 2D and 3D feature fusion network, through weighted fusion of feature vectors from both modalities, comprehensively utilizes texture and morphology information, significantly improving the confidence and spatial localization accuracy of defect classification (such as scratches, stains, and protrusions). Deploying a lightweight, rapid screening model on the production line can complete the screening of most defect-free chips within milliseconds, uploading only suspicious samples to the cloud for full analysis. This strategy effectively balances detection speed and depth, making it suitable for real-time quality monitoring on high-speed production lines. By constructing a defect-process parameter correlation matrix and analyzing key parameters based on mutual information, the system can automatically identify process steps leading to frequent defects and generate specific adjustment suggestions by referencing historical optimization cases. This function elevates quality inspection from "post-event detection" to "process prevention," facilitating intelligent manufacturing and continuous process improvement. This invention not only provides a high-precision chip surface defect detection solution but also achieves automation, intelligence, and closed-loop optimization of the detection process through systematic design, possessing significant practical value for improving the quality control level and production efficiency of semiconductor manufacturing.

[0059] It is important to note that the constructions and arrangements of this application shown in several different exemplary embodiments are merely illustrative. Although only a few embodiments are described in detail in this disclosure, those who consult this disclosure will readily understand that many modifications are possible (e.g., changes in the size, dimensions, structure, shape, and proportions of various elements, as well as parameter values ​​(e.g., temperature, pressure, etc.), mounting arrangements, use of materials, color, orientation, etc.) without substantially departing from the novel teachings and advantages of the subject matter described in this application). For example, an element shown as integrally formed may be composed of multiple parts or elements, the position of elements may be inverted or otherwise altered, and the nature or number or position of discrete elements may be changed or altered. Therefore, all such modifications are intended to be included within the scope of the invention. The order or sequence of any process or method steps may be changed or rearranged according to alternative embodiments. In the claims, any "device plus function" clause is intended to cover the structure described herein that performs the function, and not only structurally equivalent but also equivalent in structure. Other substitutions, modifications, alterations, and omissions may be made in the design, operation, and arrangement of the exemplary embodiments without departing from the scope of the invention. Therefore, the invention is not limited to the specific embodiments, but extends to various modifications that still fall within the scope of the appended claims. Furthermore, for the purpose of providing a concise description of exemplary embodiments, not all features of actual embodiments (i.e., those features not relevant to the currently considered best mode for carrying out the invention, or those features not relevant to implementing the invention) may be omitted.

[0060] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A high-precision method for detecting surface defects in semiconductor chips, characterized in that, Includes the following steps: Acquire two-dimensional image data and three-dimensional point cloud data of the surface of the chip under test; The two-dimensional image data is preprocessed to extract multi-level image features containing macroscopic contours and microscopic textures; Based on the local grayscale statistics of the two-dimensional image data, the grayscale threshold map used for defect segmentation is dynamically calculated and updated. The grayscale threshold image is used to perform binarization segmentation on the multi-level image features to obtain a two-dimensional suspected defect region; The three-dimensional point cloud data is registered and reconstructed to generate a three-dimensional topography model of the chip surface; The image features of the suspected two-dimensional defect area are fused and matched with the morphological features of the three-dimensional morphological model to determine the defect category and spatial location. Based on the defect determination results, a comprehensive inspection report is generated, including the defect type, location, and size. The defect statistics in the comprehensive inspection report are correlated and matched with the production line process parameter records. When the frequency of defect occurrence exceeds the preset process alarm threshold, corresponding process parameter adjustment suggestions are generated.

2. The high-precision semiconductor chip surface defect detection method according to claim 1, characterized in that, The process of extracting the multi-level image features includes: The preprocessed image is input into a multi-scale feature extraction network, which outputs a first-scale feature map and a second-scale feature map respectively. The feature saliency of each pixel in the first-scale feature map is calculated. If the feature saliency is higher than a first saliency threshold, the pixel region is marked as a macroscopic candidate region. The texture complexity of each pixel in the second-scale feature map is calculated. If the texture complexity is lower than a texture smoothing threshold, the pixel region is marked as a microscopic candidate region. The macroscopic candidate regions and microscopic candidate regions are merged to generate the multi-level image features.

3. The high-precision semiconductor chip surface defect detection method according to claim 2, characterized in that, The process of dynamically calculating and updating the grayscale threshold image includes: The image is divided into multiple overlapping local windows; within each window, the gray-level mean and gray-level standard deviation are calculated; based on the threshold of the previous window, the gray-level mean and gray-level standard deviation of the current window, the update threshold of the current window is calculated using a filtering algorithm; if the deviation between the update threshold of the current window and the global average threshold exceeds the dynamic range threshold, the threshold after limiting the amplitude is used as the output; all windows are traversed to generate the continuously changing gray-level threshold map.

4. The high-precision semiconductor chip surface defect detection method according to claim 3, characterized in that, The process of generating a three-dimensional morphological model of the chip surface includes: Receive 3D point cloud datasets from multiple viewpoints; register adjacent point cloud datasets; if the registration error exceeds the registration tolerance threshold, re-acquire point clouds from that viewpoint; stitch all registered point clouds together to form a complete point cloud; reconstruct the surface of the complete point cloud to generate a triangular mesh model; if the curvature change of the surface of the model exceeds the curvature smoothing threshold, perform smoothing filtering on the region.

5. The high-precision semiconductor chip surface defect detection method according to claim 1, characterized in that, The process of determining defects in the fusion matching includes: A feature fusion network comprising a two-dimensional image branch and a three-dimensional morphology branch is constructed. The multi-level image features are input into the two-dimensional image branch, and a two-dimensional defect feature vector is output. The three-dimensional morphology model is input into the three-dimensional morphology branch, and a three-dimensional defect feature vector is output. The two-dimensional defect feature vector and the three-dimensional defect feature vector are weighted and fused. If the classification confidence of the fused feature vector is higher than the defect judgment threshold, it is judged as a real defect, and the defect category and location coordinates are output.

6. The high-precision semiconductor chip surface defect detection method according to claim 5, characterized in that, This also includes deploying rapid screening steps on the production line side: A simplified version of the feature fusion network is run in the edge computing device. The simplified version of the feature fusion network only includes a two-dimensional image branch. If the defect confidence score output by the simplified version of the feature fusion network is lower than the fast pass threshold, the chip is determined to be defect-free and the detection ends. If the defect confidence score is higher than the fast pass threshold, the complete two-dimensional image and three-dimensional point cloud data of the corresponding chip are uploaded to the cloud server to perform full-process detection.

7. The high-precision semiconductor chip surface defect detection method according to claim 1, characterized in that, The process of generating corresponding process parameter adjustment suggestions includes: Establish a database linking defect types with process parameters; count the number of each type of defect in the current batch of chips; if the number of any type of defect exceeds the batch defect threshold, trigger process traceability; search the database for the process parameter with the highest correlation to the defect type; and generate the adjustment direction and suggested adjustment amount for the process parameter based on historical optimization records.

8. A high-precision semiconductor chip surface defect detection system, used to implement the high-precision semiconductor chip surface defect detection method according to any one of claims 1-7, characterized in that, include: The image acquisition module is used to acquire two-dimensional images and three-dimensional point cloud data of the chip surface; The computational processing module is used to perform multi-level image feature extraction, grayscale threshold calculation, three-dimensional shape reconstruction, feature fusion matching, and defect determination. The report generation module is used to generate and output a comprehensive test report. The process feedback module is used to generate and output suggestions for adjusting process parameters.

9. The high-precision semiconductor chip surface defect detection system according to claim 8, characterized in that, The computing processing module adopts a hierarchical computing architecture, including: Edge computing units, deployed on the production line side, are used to perform rapid screening steps; The deep computing unit, deployed in the cloud, is used to perform the entire inspection process. The edge computing unit and the deep computing unit interact with each other through data compression and encrypted transmission.

10. The high-precision semiconductor chip surface defect detection system according to claim 8, characterized in that, Also includes: The environmental monitoring module is used to collect and monitor temperature, humidity, and vibration data of the environment in real time. The adaptive compensation module is used to dynamically adjust the acquisition parameters of the image acquisition module and the judgment threshold of the calculation and processing module based on the data from the environmental monitoring module. If the environmental data exceeds the stable operating range, the system self-calibration process is triggered.

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