Frequency multiplier and wireless communication chip

Abstract

The invention discloses a frequency multiplier and a wireless communication chip, and relates to the field of wireless communication, and the frequency multiplier comprises a phase generation module which is used for generating a plurality of delay signals with a preset phase relation according to an original clock signal, the delay signals comprise a main delay signal and an interpolation delay signal, phases of the main delay signals and the interpolation delay signals are interphase, and the main delay signals and the interpolation delay signals are in one-to-one correspondence; and the signal synthesis module is used for synthesizing the plurality of main delay signals and the plurality of interpolation delay signals to generate a target frequency multiplication signal, and the frequency of the target frequency multiplication signal is N times of the frequency of the original clock signal. According to the invention, high frequency multiplication can be realized, meanwhile, periodic offset and additional noise which are possibly caused by duty ratio correction loop interference are avoided, and the time sequence precision and the spectrum purity of output signals are improved. In addition, a duty ratio correction circuit and a calibration process thereof are omitted, so that the chip area is saved, the power consumption is reduced, and the overall efficiency of the system is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of wireless communication, in particular to a frequency multiplier and a wireless communication chip. BACKGROUND

[0002] In a wireless communication chip, the quality of the reference clock signal generated by the crystal oscillator directly affects the radio frequency performance. In order to balance low cost and high performance, a low-frequency crystal oscillator combined with a frequency multiplier is often used to obtain a high-frequency clock. Related technologies usually use multiple delay lines for frequency multiplication and duty cycle correction. However, during the correction process, the delay control used to adjust the duty cycle will interfere with the calibrated frequency multiplication period, resulting in period shift and additional noise of the output signal, which limits its performance in low-noise and high-precision applications.

[0003] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. SUMMARY

[0004] The purpose of the present application is to provide a frequency multiplier and a wireless communication chip, which can achieve high frequency multiplication while avoiding period shift and additional noise caused by duty cycle correction loop interference, improving the timing accuracy and spectral purity of the output signal. In addition, since the duty cycle correction circuit and its calibration process are omitted, the chip area is saved, the power consumption is reduced, and the overall system efficiency is improved.

[0005] To solve the above technical problems, the present application provides a frequency multiplier, comprising: a phase generation module, configured to generate a plurality of delay signals with a preset phase relationship according to an original clock signal, the delay signals comprising a main delay signal and an interpolation delay signal, the phases of the main delay signal and the interpolation delay signal being different, and the main delay signal and the interpolation delay signal corresponding one by one; a signal synthesis module, configured to synthesize a plurality of the main delay signals and a plurality of corresponding interpolation delay signals to generate a target frequency multiplication signal, the frequency of the target frequency multiplication signal being N times the frequency of the original clock signal, N being an integer greater than or equal to 2.

[0006] Optionally, the phase generation module comprises: M cascaded delay lines, the i-th delay line receiving a delay signal to be delayed, which is the main delay signal output by the i-1-th delay line, i being an integer greater than or equal to 2 and less than or equal to M; wherein the value of M is related to N; the i-1-th delay line is configured to delay the delay signal to be delayed received by the input node thereof and output the main delay signal of the i-1-th delay line; wherein the main delay signal comprises the main delay signal of the i-1-th delay line; Intermediate nodes of the M delay lines output interpolation delay signals of the M delay lines; wherein the interpolation delay signals comprise interpolation delay signals of the M delay lines.

[0007] Optionally, the signal synthesis module comprises: A plurality of first processing units, the plurality of first processing units are connected in one-to-one correspondence with the plurality of delay lines; The first processing unit is configured to perform first logical operation on the interpolation delay signal and the corresponding main delay signal to obtain a first logic signal corresponding to each delay line.

[0008] Optionally, the first processing unit comprises an exclusive or unit; The first processing unit is specifically configured to perform exclusive or operation on the interpolation delay signal and the corresponding main delay signal to obtain the first logic signal.

[0009] Optionally, the signal synthesis module further comprises: A plurality of second processing units connected in one-to-one correspondence with the plurality of first processing units, configured to generate a second logic signal according to the first logic signal output by each first processing unit and a corresponding cancellation signal; wherein the main delay signal comprises the corresponding cancellation signal.

[0010] Optionally, the second processing unit comprises an and gate; The second processing unit is specifically configured to perform and operation on the first logic signal and the corresponding cancellation signal to generate the second logic signal.

[0011] Optionally, the signal synthesis module further comprises a third processing unit; The third processing unit is connected with the plurality of second processing units, configured to generate the target frequency multiplication signal according to the second logic signal.

[0012] Optionally, the third processing unit comprises an or gate; The third processing unit is specifically configured to perform or operation on the second logic signal to generate the target frequency multiplication signal.

[0013] Optionally, the frequency multiplier further comprises a calibration module, the calibration module is configured to adjust delay amounts of the plurality of delay lines according to the main delay signal output by a last delay line and the to-be-delayed signal received by a first delay line, so that a target clock edge of the main delay signal output by the last delay line is aligned in time with a target clock edge of the to-be-delayed signal received by the first delay line.

[0014] The application further provides a wireless communication chip, comprising a crystal oscillator and a frequency multiplier as described in any one of the preceding embodiments connected to the crystal oscillator.

[0015] Since the application generates multiple delay signals with preset phase relationships through the phase generation module, and the signal synthesis module synthesizes signals based on the phase relationship between the main delay signal and the interpolation delay signal, a target frequency multiplication signal with a frequency of N times the original clock signal is directly generated. This synthesis mechanism only relies on the preset phase arrangement and synthesis logic at the signal level, without introducing the duty cycle correction link commonly used in traditional frequency multiplication schemes. Therefore, while achieving high frequency multiplication, the application avoids the period deviation and additional noise that may be caused by the duty cycle correction loop interference, effectively improving the timing accuracy and spectral purity of the output signal. In addition, since the duty cycle correction circuit and its calibration process are omitted, the scheme can also save chip area, reduce power consumption, and improve the overall efficiency of the system. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0017] Figure 1 Structure diagram of the first frequency multiplier provided by the present application; Figure 2 Structure diagram of the second frequency multiplier provided by the present application; Figure 3a Structure diagram of the third frequency multiplier provided by the present application; Figure 3b Structure diagram of the fourth frequency multiplier provided by the present application; Figure 4 Waveform diagram of a quadrupler working mode provided by the present application; Figure 5 Waveform diagram of another quadrupler working mode provided by the present application; Figure 6 Structure diagram of the fifth frequency multiplier provided by the present application. DETAILED DESCRIPTION

[0018] The core of the present application is to provide a frequency multiplier and a wireless communication chip, which can realize high frequency multiplication while avoiding the period shift and additional noise caused by the duty cycle correction loop interference, thereby improving the timing accuracy and spectral purity of the output signal. In addition, since the duty cycle correction circuit and its calibration process are omitted, the chip area is saved, the power consumption is reduced, and the overall system efficiency is improved.

[0019] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0020] Please refer to Figure 1 The present application provides a frequency multiplier, comprising: A phase generation module 1 is configured to generate a plurality of delay signals with preset phase relationship according to an original clock signal, wherein the delay signals include main delay signals and interpolation delay signals, the phases of the main delay signals and the interpolation delay signals are different, and the main delay signals and the interpolation delay signals are one-to-one corresponding. A signal synthesis module 2 is configured to synthesize a plurality of main delay signals and a plurality of corresponding interpolation delay signals to generate a target frequency multiplication signal, wherein the frequency of the target frequency multiplication signal is N times of the frequency of the original clock signal, and N is an integer greater than or equal to 2.

[0021] In the present embodiment, the input end of the phase generation module 1 is connected with a crystal oscillator, receives the original clock signal generated by the crystal oscillator, and generates a plurality of delay signals based on the original clock signal, wherein the plurality of delay signals have preset phase relationship, the preset phase relationship includes that the phases of the plurality of delay signals are uniformly distributed within one complete period of the original clock signal, and the phase difference between adjacent delay signals is constant. The delay signals include main delay signals and interpolation delay signals corresponding to the main delay signals one-to-one. If the plurality of delay signals are arranged in order from small to large in phase, the main delay signals and the interpolation delay signals are arranged alternately in the sequence.

[0022] Specifically, if N times frequency multiplication is needed, 2N delay signals need to be generated, which are uniformly distributed in one complete cycle of the original clock signal. For example, if four times frequency multiplication (N=4) is needed, four main delay signals and four interpolation delay signals need to be generated, and the phases can be 0, 45°, 90°, 135°, 180°, 225°, 270°, and 315°, respectively. Among them, 0, 90°, 180°, and 270° are main delay signals, and 45°, 45°, 225°, and 315° are interpolation delay signals, which are one-to-one corresponding and phase intervals. It should be noted that in order to realize the output of four times frequency multiplication signal, four main delay signals and four interpolation delay signals need to be generated, and the phases can also be 45°, 90°, 135°, 180°, 225°, 270°, 315°, and 360°, respectively. Among them, 90°, 180°, 270°, and 360° are main delay signals, and 45°, 135°, 225°, and 315° are interpolation delay signals.

[0023] Among them, the phase generation module 1 can be realized by a delay-locked loop or a multi-stage delay line, which can be selected according to actual engineering needs, and the present embodiment does not limit it.

[0024] The signal synthesis module 2 is used to synthesize the above-mentioned multiple main delay signals and corresponding interpolation delay signals, and finally generates a target frequency multiplication signal, and the frequency of the target frequency multiplication signal is N times the frequency of the original clock signal. The synthesis process is based on the edge combination or logic operation of each signal. For example, an XOR gate or an edge combination circuit can be used to logically synthesize each main delay signal and its corresponding interpolation delay signal, and each combination can produce a frequency-doubled sub-signal. By logically ORing all N pairs of sub-signals, the target frequency multiplication signal with a frequency of N times the original clock signal can be obtained, and its duty cycle is determined and kept stable by the phase layout, so there is no need to introduce the duty cycle correction link commonly used in traditional frequency multiplication schemes.

[0025] The present embodiment generates uniformly distributed delay signals through the phase generation module 1, and then performs edge synthesis through the signal synthesis module 2, thereby realizing efficient and stable frequency multiplication function without relying on high-frequency oscillation source.

[0026] This application generates multiple delayed signals with preset phase relationships through phase generation module 1, and signal synthesis module 2 synthesizes the signal based on the phase relationship between the main delayed signal and the interpolated delayed signal, directly generating a target frequency multiplier signal with a frequency N times that of the original clock signal. This synthesis mechanism relies solely on preset phase arrangement and synthesis logic at the signal level, eliminating the need for duty cycle correction circuits common in traditional frequency multiplication schemes. Therefore, this application achieves high frequency multiplication while avoiding period offset and additional noise that may be caused by duty cycle correction loop interference, effectively improving the timing accuracy and spectral purity of the output signal. Furthermore, by eliminating the duty cycle correction circuit and its calibration process, this solution also saves chip area, reduces power consumption, and improves overall system efficiency.

[0027] Please refer to Figure 2 This frequency multiplier is based on the above embodiment: In one exemplary embodiment, the phase generation module 1 includes: There are M cascaded delay lines. The signal to be delayed received by the i-th delay line is the main delayed signal output by the (i-1)-th delay line, where i is an integer greater than or equal to 2 and less than or equal to M; where the value of M is related to N. The (i-1)th delay line is used to delay the signal to be delayed received by its input node and output the main delay signal of the (i-1)th delay line; wherein, the main delay signal includes the main delay signal of the (i-1)th delay line; The intermediate nodes of M delay lines output interpolated delay signals for the M delay lines; wherein, the interpolated delay signals include the interpolated delay signals of the M delay lines.

[0028] In this embodiment, the phase generation module 1 includes M delay lines, which are cascaded sequentially to form a delay chain. Among the M delay lines, the (i-1)th delay line (where i is an integer greater than or equal to 2 and less than or equal to M, and M is the total number of delay lines) is used to delay the signal to be delayed received by its input node and outputs the main delayed signal of the (i-1)th delay line. For the ith delay line, the signal to be delayed received is the main delayed signal output by the (i-1)th delay line. For the first delay line, its input node serves as the input terminal of the phase generation module 1, receiving the buffered original clock signal. That is, the signal to be delayed received by the input node of the first delay line is the first main delayed signal in the main delayed signal, meaning the delayed signal includes the signal to be delayed received by the input point of the first delay line. For the last delay line, it delays the signal to be delayed received by its input node and outputs the main delayed signal through its output node.

[0029] Accordingly, the main delay signal for each delay line can be either the main delay signal output by the output node of that delay line, or the main delay signal output by the preceding delay line and connected to its input node. For the first delay line, since there is no preceding delay line, the buffered original clock signal connected to it serves as the main delay signal connected to its input node. During subsequent synthesis processing, when selecting the corresponding main delay signal for each delay line, either the main delay signal connected to its input node or the main delay signal output by its output node can be selected for all lines.

[0030] Simultaneously, the intermediate node of each delay line outputs a corresponding interpolated delay signal. Specifically, each delay line can be considered a basic delay unit, whose total delay time (from the input node to the output node) is pre-calibrated to a preset value Td. Its intermediate node is led out from a specific position on the delay path, configured such that the delay time from the input node to the intermediate node is Td / 2. Therefore, for the same delay line, its output interpolated delay signal is located in phase between the input signal to be delayed and the output main delay signal, thus achieving an alternating phase layout between the main delay signal and the interpolated delay signal.

[0031] It is understandable that the total number of delay lines M is related to the target frequency multiplication factor N. To achieve N times the frequency multiplication factor, 2N uniform phase delay signals need to be generated. Since each delay line can generate a corresponding main delay signal and an interpolated delay signal based on the received signal to be delayed, the total number of delay lines M can be equal to the frequency multiplication factor N.

[0032] In this embodiment, the entire delay chain requires only a unified control mechanism (e.g., through a DLL loop) to calibrate the total delay of all delay units. The delay (Td / 2) of all intermediate nodes is automatically calibrated proportionally, avoiding the extreme complexity of calibrating each phase individually and reducing the design difficulty, power consumption, and area overhead of the control circuit. The interpolated delay signal is directly derived from the intermediate node of the existing delay unit, eliminating the need to design a separate, complete delay path. This signal multiplexing method efficiently acquires all 2N required phase signals without increasing additional power consumption and area, maximizing hardware efficiency.

[0033] In one exemplary embodiment, the signal synthesis module 2 includes: Multiple first processing units are connected one-to-one with multiple delay lines; The first processing unit is used to perform a first logic operation on the interpolated delay signal and the corresponding main delay signal to obtain the first logic signal corresponding to each delay line.

[0034] In this embodiment, the signal synthesis module 2 includes multiple first processing units, and the multiple first processing units and multiple delay lines are connected one-to-one. Taking one first processing unit as an example, the following description will be provided.

[0035] In the first embodiment: the two input terminals of the first processing unit are respectively connected to the input node and the intermediate node of the corresponding delay line, so that the first processing unit performs a first logic operation on the main delay signal input to the input node of the delay line and the interpolated delay signal output by the intermediate node of the delay line to generate a first logic signal. The signal to be delayed transmitted to the delay line is the main delay signal. The first logic signal represents the phase difference between the signal to be delayed and the corresponding interpolated delay signal of the delay line, that is, it represents the phase difference between the corresponding main delay signal and the interpolated delay signal. Specifically, it is a periodic pulse signal. The rising edge and falling edge of the pulse are triggered by the edges of the two input signals, so that the width of the pulse precisely corresponds to the time length represented by the fixed phase difference. In the second embodiment: the two input terminals of the first processing unit are respectively connected to the intermediate node and the output node of the corresponding delay line, so that the first processing unit performs a first logic operation on the delayed signal output by the output node of the delay line and the interpolated delayed signal output by the intermediate node of the delay line to generate a first logic signal, wherein the delayed signal output by the output node of the delay line is a main delay signal, and the first logic signal represents the phase difference between the main delay signal and the corresponding interpolated delayed signal.

[0036] In this embodiment, the fixed phase difference relationship is converted into a pulse signal with a defined time width by the first processing unit, which facilitates subsequent processing.

[0037] In one exemplary embodiment, the first processing unit includes an XOR unit; The first processing unit is specifically used to perform an XOR operation on the interpolated delay signal and the corresponding main delay signal to obtain the first logic signal.

[0038] In this embodiment, the first processing unit is implemented by at least an XOR unit, and correspondingly, the first logical operation is an XOR operation. It can be understood that XOR logic outputs a high level when the two input signal levels are different. Because there is a fixed and precise preset phase difference between the main delay signal and the interpolated delay signal, the main delay signal and the interpolated delay signal will have two state windows in each cycle, with a duration equal to the phase difference but opposite level states. Therefore, the XOR operation can convert this fixed phase relationship into a periodic pulse signal with a corresponding fixed pulse width, i.e., the first logical signal. The rising and falling edges of this pulse signal are precisely triggered by the edges of the two input signals.

[0039] For example, refer to Figure 3a andFigure 3b As shown, taking a quadruple clock as an example, the system includes four cascaded delay lines: DL1, DL2, DL3, and DL4. The original clock signal is CK_IN, which is buffered to obtain signal A. Signal A serves as the first main delay signal, i.e., the signal to be delayed received by DL1. α is the interpolated delay signal of DL1. B is the main delay signal output by DL1, i.e., the signal to be delayed received by DL2. β is the interpolated delay signal of DL2. C is the main delay signal output by DL2, i.e., the signal to be delayed received by DL3. θ is the interpolated delay signal of DL3. D is the main delay signal output by DL3, i.e., the signal to be delayed received by DL4. E is the interpolation delay signal of DL4, and E is the main delay signal output by DL4. Signal E serves as the second main delay signal. Figure 3a In each case, the main delay signal (signal A, signal B, signal C, signal D) connected to the input node of the delay line is used as the main delay signal corresponding to that delay line. Figure 3b In this context, the main delay signals (signal B, signal C, signal D, signal E) output by the output node of the delay line are used as the main delay signals corresponding to that delay line.

[0040] After XOR operation by the first processing unit, and Figure 3a The waveforms of the corresponding first logic signals are referenced. Figure 4 As shown.

[0041] In one exemplary embodiment, the signal synthesis module 2 further includes: Multiple second processing units are connected one-to-one with multiple first processing units, and are used to generate second logic signals based on the first logic signals output by each first processing unit and the corresponding cancellation signals; wherein, the main delay signal includes the corresponding cancellation signal.

[0042] In this embodiment, a plurality of second processing units are further included. The first input terminals of the plurality of second processing units are connected one-to-one with the output terminals of the plurality of first processing units, and the second input terminals of the plurality of second processing units are used to receive their respective cancellation signals. Each first processing unit is used to receive a first logic signal output by its corresponding first processing unit and a corresponding cancellation signal, and generates a second logic signal based on the two. In the second logic signal, only the valid pulses triggered by the target clock edge in the first logic signal are retained, while invalid pulses triggered by non-target clock edges are suppressed.

[0043] It can be understood that the first logic signal (e.g., generated by an XOR operation) essentially converts the phase difference between two input signals into pulses. Since the input signals are periodic clock signals, this phase difference occurs twice within each input clock cycle, generated by the difference between the rising and falling edges of the pair of signals. Therefore, the first logic signal contains two pulses within each original clock cycle, one triggered by the rising edge of the corresponding signal to be delayed, and the other triggered by the falling edge of the corresponding signal to be delayed.

[0044] However, during the calibration process of the front-end phase generation module 1, precise phase alignment and locking are performed only for one edge of the original clock signal (e.g., the rising edge) to ensure that the rising edges of all delayed signals are evenly distributed on the time axis. At this time, the timing of the pulses triggered by these rising edges (referred to as the first pulse) is calibrated and accurate. Conversely, the timing of the pulses triggered by the falling edge (referred to as the second pulse) is determined solely by the natural delay of the circuit and is not calibrated, which may introduce significant timing jitter and uncertainty.

[0045] To address this issue, this embodiment introduces a cancellation signal. This cancellation signal is configured to eliminate pulse signals in the first logic signal triggered by non-target clock edges of the corresponding delay signal. Specifically, it is configured such that, within a certain time period on the time axis, the level of the cancellation signal is the same as the level of pulses in the first logic signal triggered by target clock edges (e.g., rising edges), but opposite to the level of pulses triggered by non-target edges (e.g., falling edges). By performing a specific logical combination of the first logic signal and this cancellation signal in the second processing unit, the second pulse triggered by an uncalibrated falling edge can be selectively suppressed or even eliminated, while the first pulse triggered by a calibrated rising edge is fully preserved. This results in a pure second logic signal whose timing is entirely determined by the calibrated edge. By introducing the second processing unit and the selective pulse suppression mechanism of the cancellation signal, this embodiment further improves the timing accuracy and purity of the target frequency multiplication signal. The second logic signal processed by the second processing unit is as follows: Figure 5 As shown. This embodiment effectively eliminates the uncalibrated edge jitter caused by the single-edge calibration regime, ensuring that the second logic signal ultimately participating in the synthesis has consistent timing characteristics.

[0046] In one exemplary embodiment, the second processing unit includes an AND gate; The second processing unit is specifically used to perform an AND operation on the first logic signal and the corresponding cancellation signal to generate the second logic signal.

[0047] In this embodiment, the second processing unit is implemented by at least an AND gate. The first input of the AND gate receives a first logic signal, and the second input receives a corresponding delay signal (or other clock signal with the required phase) that can serve as the cancellation signal. Through the AND operation, only the pulse portion of the first logic signal that overlaps with the high-level period of the cancellation signal is retained in the second logic signal, while the remaining pulse portion is suppressed.

[0048] Specifically, the effective edge (e.g., rising edge) of the selected cancellation signal needs to be synchronized with the target edge (e.g., rising edge) calibrated by the phase generation module 1, and the width of its high-level pulse needs to at least cover the effective pulse (first pulse) triggered by the target edge. Therefore, in this embodiment, a calibrated delay signal is multiplexed as a cancellation signal, avoiding the power consumption, chip area, and design complexity caused by additional calibration circuitry. Since the invalid pulse (second pulse) triggered by the uncalibrated edge (e.g., falling edge) is out of sync with the high-level period of the cancellation signal on the time axis, the cancellation signal is in a low-level state when the invalid pulse appears during the AND operation, causing the AND gate output to be pulled low, thereby achieving the shielding or cancellation of the invalid pulse. At the same time, the effective pulse triggered by the calibrated target edge has an occurrence time that completely coincides with the high-level period of the cancellation signal, so it can pass through the AND gate without loss and be retained in the second logic signal.

[0049] As an optional embodiment, the main delay signal includes a corresponding cancellation signal, as shown in the reference. Figure 3a To avoid glitches, D can be used as the cancellation signal for DL1, A as the cancellation signal for DL2, B as the cancellation signal for DL3, and C as the cancellation signal for DL4, as per [reference needed]. Figure 3b A can be used as the cancellation signal corresponding to DL1, B as the cancellation signal corresponding to DL2, C as the cancellation signal corresponding to DL3, and D as the cancellation signal corresponding to DL4.

[0050] In one exemplary embodiment, the signal synthesis module 2 further includes a third processing unit; The third processing unit is connected to multiple second processing units and is used to generate a target frequency multiplication signal based on the second logic signal.

[0051] In this embodiment, the signal synthesis unit further includes a third processing unit that receives the outputs of all the second processing units. It can be understood that the second logic signal output by each second processing unit, relative to the delay signal received by the corresponding delay line, is a frequency multiplier signal with a fixed pulse width and precise timing. This frequency multiplier signal is generated by a pair of clock signals with a fixed phase difference (the delay signal and the interpolated delay signal), and through signal elimination filtering, only the pulse triggered by the calibration edge (such as a rising edge) is retained in each cycle. Therefore, to achieve N-fold frequency multiplication, a total of N second logic signals are generated, corresponding to N uniformly distributed phase intervals within the original clock cycle. Since these N second logic signals originate from the uniformly phase-distributed delay lines, their high-level pulses appear sequentially and at equal intervals on the time axis, without overlapping. The width (high-level time) of the high-level pulse in each frequency multiplier signal is fixed, and the interval (low-level time) between each frequency multiplier signal is also fixed. The third processing unit superimposes the high-level pulses of these N frequency multiplier signals that appear sequentially in time. From the perspective of the target frequency multiplication signal's level state, when the first high-level pulse of the first frequency multiplication signal arrives, the target frequency multiplication signal's level state becomes high. When the first high-level pulse of the first frequency multiplication signal ends but the second high-level pulse of the first frequency multiplication signal has not yet arrived, and before the first high-level pulse of the second frequency multiplication signal arrives, the target frequency multiplication signal's level state is low. When the first high-level pulse of the second frequency multiplication signal arrives, the target frequency multiplication signal's level state becomes high. When the first high-level pulse of the second frequency multiplication signal ends but the first high-level pulse of the third frequency multiplication signal has not yet arrived, the target frequency multiplication signal's level state is low. However, when the first high-level pulse of the third frequency multiplication signal arrives, the target frequency multiplication signal's waveform becomes high again... and so on. Ultimately, the waveform of the target frequency multiplication signal presented at the output of the third processing unit is a continuous square wave signal. Since its alternating high and low levels are strictly determined by N uniformly distributed pulses, the period of this square wave is equal to the original clock period divided by N, thus achieving N-fold frequency multiplication.

[0052] In one exemplary embodiment, the third processing unit includes an OR gate; The third processing unit is specifically used to perform an OR operation on the second logic signal to generate the target frequency multiplication signal.

[0053] In this embodiment, the third processing unit is implemented using a multi-input OR gate. Each input of the OR gate is connected to the output of a second processing unit to receive the corresponding second logic signal, and the output of the OR gate outputs the final target frequency multiplication signal.

[0054] An OR gate performs a logical OR operation on all N input second logic signals. According to the logic characteristics of an OR gate, the output is high as long as any one of its inputs is high; the output is low only when all inputs are low. As mentioned earlier, these N second logic signals are frequency multipliers of high-level pulses that occur sequentially and at equal intervals. Therefore, when the first high-level pulse of the first frequency multiplier arrives, the OR gate output goes high; after this high-level pulse ends, before the next high-level pulse arrives, all inputs are low, and the OR gate output goes low; then the second high-level pulse arrives (i.e., the first high-level pulse of the second frequency multiplier), and the output goes high again… This process repeats cyclically. From a waveform perspective, these discrete pulses are seamlessly connected by the OR gate on the time axis, forming a continuous, periodic square wave. Using only a single standard digital logic gate, the hardware overhead is minimal, it is easy to integrate, and it is fast.

[0055] It should be noted that, Figure 3b In this process, the first processing unit performs an XOR operation on the main delay signal output by the output node of the delay line and the interpolation delay signal output by the intermediate node of the delay line to obtain the first logic signal corresponding to each delay line. Then, the second processing unit performs an AND operation on the first logic signal output by each first processing unit and the corresponding cancellation signal to generate a second logic signal. Then, the third processing unit performs an OR operation on each second logic signal to obtain the target frequency multiplier signal. The frequency of the target frequency multiplier signal is N times the frequency of the original clock signal (N is 4 in this embodiment). The initial phase of the target frequency multiplier signal is delayed by T / 2N compared to the initial phase of the original clock signal. Subsequently, the target frequency multiplier signal can be restored to synchronize the initial phase of the target frequency multiplier signal with the initial phase of the original clock signal.

[0056] In one exemplary embodiment, reference is made to Figure 6 The frequency multiplier also includes a calibration module 3, which is used to adjust the delay amount of each delay line according to the main delay signal output by the last delay line and the signal to be delayed received by the first delay line, so that the target clock edge of the main delay signal output by the last delay line is aligned in time with the target clock edge of the signal to be delayed received by the first delay line.

[0057] In this embodiment, the frequency multiplier also includes a calibration module 3. The two input terminals of the calibration module 3 are connected to the input node of the first delay line (receiving the reference signal, i.e., the buffered original clock or the signal to be delayed) and the output node of the last delay line (receiving the feedback signal, i.e., the final main delay signal), respectively. When the calibration module 3 is activated, it compares the target clock edges of the two input signals. If the target clock edge of the feedback signal leads the target clock edge of the reference signal, the delay of each delay line is increased; if the target clock edge of the feedback signal lags the target clock edge of the reference signal, the delay of each delay line is decreased. After several cycles of dynamic adjustment, it finally enters a locked state. In this state, the target clock edge of the main delay signal output by the last delay line is precisely aligned with the target delay edge of the reference signal input by the first delay line, making the phase of the delayed signal accurate and uniformly distributed, thereby directly generating a frequency multiplier signal with a duty cycle close to 50%.

[0058] Embodiments of the present invention also provide a wireless communication chip, including a crystal oscillator and a frequency multiplier connected to the crystal oscillator as described in any of the embodiments above.

[0059] For a description of the wireless communication chip provided by this invention, please refer to the above embodiments; further details of this invention will not be repeated here.

[0060] The wireless communication chip provided by this invention has the same beneficial effects as the frequency multiplier described above.

[0061] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0062] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A frequency multiplier, characterized in that, include: A phase generation module is used to generate multiple delayed signals with a preset phase relationship based on the original clock signal. The delayed signals include a main delayed signal and an interpolated delayed signal. The main delayed signal and the interpolated delayed signal have alternating phases, and the main delayed signal and the interpolated delayed signal correspond one-to-one. The signal synthesis module is used to synthesize multiple main delay signals and corresponding multiple interpolation delay signals to generate a target frequency multiplication signal, wherein the frequency of the target frequency multiplication signal is N times the frequency of the original clock signal, and N is an integer greater than or equal to 2.

2. The frequency multiplier according to claim 1, characterized in that, The phase generation module includes: There are M cascaded delay lines, where the signal to be delayed received by the i-th delay line is the main delayed signal output by the (i-1)-th delay line, and i is an integer greater than or equal to 2 and less than or equal to M; where the value of M is related to N. The (i-1)th delay line is used to delay the signal to be delayed received by its own input node and output the main delay signal of the (i-1)th delay line; wherein, the main delay signal includes the main delay signal of the (i-1)th delay line; The intermediate nodes of the M delay lines output interpolated delay signals for the M delay lines; wherein the interpolated delay signals include the interpolated delay signals of the M delay lines.

3. The frequency multiplier according to claim 2, characterized in that, The signal synthesis module includes: Multiple first processing units are connected one-to-one with the multiple delay lines; The first processing unit is configured to perform a first logical operation on the interpolated delay signal and the corresponding main delay signal to obtain a first logical signal corresponding to each delay line.

4. The frequency multiplier according to claim 3, characterized in that, The first processing unit includes an XOR unit; The first processing unit is specifically used to perform an XOR operation on the interpolated delay signal and the corresponding main delay signal to obtain the first logic signal.

5. The frequency multiplier according to claim 3, characterized in that, The signal synthesis module further includes: Multiple second processing units are connected one-to-one with multiple first processing units, and are used to generate a second logic signal based on the first logic signal output by each first processing unit and the corresponding cancellation signal; wherein, the main delay signal includes the corresponding cancellation signal.

6. The frequency multiplier according to claim 5, characterized in that, The second processing unit includes an AND gate; The second processing unit is specifically used to perform an AND operation on the first logic signal and the corresponding cancellation signal to generate the second logic signal.

7. The frequency multiplier according to claim 5, characterized in that, The signal synthesis module further includes a third processing unit; The third processing unit is connected to multiple second processing units and is used to generate the target frequency multiplication signal based on the second logic signal.

8. The frequency multiplier according to claim 7, characterized in that, The third processing unit includes an OR gate; The third processing unit is specifically used to perform an OR operation on the second logic signal to generate the target frequency multiplication signal.

9. The frequency multiplier according to any one of claims 2-8, characterized in that, The frequency multiplier also includes a calibration module, which is used to adjust the delay amount of each delay line according to the main delay signal output by the last delay line and the signal to be delayed received by the first delay line, so that the target clock edge of the main delay signal output by the last delay line is aligned in time with the target clock edge of the signal to be delayed received by the first delay line.

10. A wireless communication chip, characterized in that, It includes a crystal oscillator and a frequency multiplier as described in any one of claims 1-9, connected to the crystal oscillator.

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