Semiconductor device and preparation method thereof
By forming a continuous concave-convex structure in a semiconductor device and utilizing etching path self-alignment technology, the via alignment problem caused by photolithography deviation was solved, achieving precise alignment between the upper via and the lower metal line, improving the fabrication yield, reducing interconnect resistance, and decreasing the power consumption of the semiconductor device.
Patent Information
- Application Number
- CN202610031137.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-09
- Publication Date
- 2026-04-07
AI Technical Summary
In the prior art, through-holes caused by photolithography alignment deviations cannot be accurately aligned with the underlying metal lines, resulting in circuit connection failure or short circuits, and increasing signal delay and chip power consumption.
By forming a continuous uneven structure on the substrate, through-holes are formed using etching path self-alignment technology, avoiding reliance on photolithography precision, ensuring precise alignment between the through-holes and metal interconnects, and guiding the etching path through the groove structure to achieve self-aligned etching of through-holes.
It improves the fabrication yield and reliability of semiconductor devices, reduces the resistance of interconnects, and reduces the power consumption of semiconductor devices.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor device and a preparation method thereof. BACKGROUND
[0002] In advanced semiconductor manufacturing, back-end-of-line (BEOL) is responsible for fabricating metal lines on top of transistors and connecting them into complete circuits. As chip manufacturing continues to upgrade, the number of metal lines increases, forming a three-dimensional interconnection structure, which improves the impact of interconnection on chip performance.
[0003] Currently, the levels where the upper and lower metal lines are located need to be connected vertically through vias. The commonly used interconnection line process needs to rely on multiple photolithography to define the positions of the vias and metal lines. However, there is a slight deviation in the photolithography alignment. In a structure with a large number of layers, the accumulation of the deviation can cause the via of the upper level to fail to accurately align with the target metal line of the lower level, which can cause circuit connection failure or short circuit.
[0004] In order to prevent this problem, the current practice is usually to deliberately make the size of the via small. In this way, even if there is a slight deviation in the alignment, the via can still fall on the correct metal line, avoiding short circuit. However, the smaller via leads to a larger resistance value of the interconnection line, which in turn leads to an increase in signal delay in transmission and an increase in chip power consumption. SUMMARY
[0005] The purpose of the present application is to provide a semiconductor device and a preparation method thereof, which can realize accurate alignment of the upper via and the lower metal line, while reducing the resistance of the interconnection line and reducing the power consumption of the semiconductor device.
[0006] Embodiments of the present application are implemented as follows: In one aspect of the present application, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate, the substrate comprising a substrate, a first dielectric layer on the substrate, and a first metal interconnect line in the first dielectric layer and penetrating through the first dielectric layer, a top surface of the first metal interconnect line being higher than a top surface of the first dielectric layer; forming a first etching stop layer and a sacrificial layer covering the first etching stop layer, the first etching stop layer covering the top surface of the first metal interconnect line and the top surface of the first dielectric layer; forming a second dielectric layer covering the sacrificial layer, the second dielectric layer exposing the sacrificial layer on the top surface of the first metal interconnect line, a top surface of the exposed sacrificial layer being flush with a top surface of the second dielectric layer; removing the exposed sacrificial layer until the first etching stop layer is exposed, forming a groove on the top surface of the first metal interconnect line; forming a second etching stop layer and a third dielectric layer on a surface of the second etching stop layer, the second etching stop layer covering the exposed surface of the first etching stop layer and the top surface of the second dielectric layer; etching the third dielectric layer, the second etching stop layer and the first etching stop layer in sequence until the top of the first metal interconnect line is exposed, forming a via; and forming a metal in the via to form a second metal interconnect line electrically connected to the first metal interconnect line.
[0007] Optionally, the first etching stop layer also covers sidewalls of the protruding first metal interconnect line; the sacrificial layer conformally covers the first etching stop layer; the second dielectric layer also exposes the sacrificial layer on the top surface of the first etching stop layer on the sidewalls of the first metal interconnect line, and the top surface of the sacrificial layer on the sidewalls of the first etching stop layer.
[0008] Optionally, the providing the substrate comprises: providing a substrate; forming a first dielectric layer covering a surface of the substrate; forming a via structure penetrating through the first dielectric layer; filling the via structure with an interconnect metal to form the first metal interconnect line; and removing a portion of the thickness of the first dielectric layer so that the top surface of the first metal interconnect line is higher than the top surface of the first dielectric layer.
[0009] Optionally, the removing a portion of the thickness of the first dielectric layer is by dry etching. After the removing a portion of the thickness of the first dielectric layer by dry etching, the method further comprises: cleaning the surface of the first metal interconnect line with a chemical reagent to remove an oxide layer on the surface of the first metal interconnect line, the chemical reagent comprising at least one of formic acid, acetic acid and hydrochloric acid, or a mixed solution of at least one of them and a metal complexing agent.
[0010] Optionally, the forming the second dielectric layer comprises: forming an initial second dielectric layer on the sacrificial layer; and planarizing the initial second dielectric layer until the sacrificial layer on the top surface of the first metal interconnect line is exposed.
[0011] Optionally, after the forming the via, the method further comprises: cleaning the via and drying.
[0012] Optionally, forming the metal in the via hole comprises: annealing the top surface of the first metal interconnection line; and electroplating copper to form a copper interconnection structure in the via hole.
[0013] Optionally, the first etching stop layer is any one of a silicon carbon nitride layer, a silicon nitride layer, a silicon oxide layer, or an aluminum nitride layer; and the second etching stop layer is any one of a silicon carbon nitride layer, an aluminum nitride layer, a silicon oxide layer, or a silicon nitride layer.
[0014] Optionally, the sacrificial layer is an aluminum oxide layer.
[0015] In another aspect of the present application, a semiconductor device is provided, which is prepared by the method for preparing a semiconductor device.
[0016] The beneficial effects of the present application include: The application provides a semiconductor device manufacturing method, comprising: providing a substrate, the substrate comprising a substrate, a first dielectric layer on the substrate, and a first metal interconnection line in the first dielectric layer and penetrating through the first dielectric layer, the top surface of the first metal interconnection line being higher than the top surface of the first dielectric layer, forming a first surface, and making the first surface form a continuous concave-convex structure; forming a first etching stop layer and a sacrificial layer covering the first etching stop layer; forming a second dielectric layer covering the sacrificial layer, the second dielectric layer exposing the sacrificial layer on the top surface of the first metal interconnection line, and the top surface of the exposed sacrificial layer being flush with the top surface of the second dielectric layer; removing the exposed sacrificial layer until the first etching stop layer is exposed, and forming a groove on the top surface of the first metal interconnection line; forming a second etching stop layer and a third dielectric layer on the surface of the second etching stop layer, the second etching stop layer covering the exposed surface of the first etching stop layer and the top surface of the second dielectric layer; etching the third dielectric layer, the second etching stop layer and the first etching stop layer in sequence until the top of the first metal interconnection line is exposed, in the process, the etching path of the via is guided by the groove structure formed by the concave-convex surface and the high etching selectivity of the second etching stop layer and the dielectric material, and the etching path of the via avoids the second etching stop layer on the convex part and advances towards the area where the groove area is located, and finally the top of the first metal interconnection line is accurately exposed; and forming a metal in the via to form a second metal interconnection line electrically connected with the first metal interconnection line. Compared with the traditional process which defines the position of the via and the metal interconnection line by relying on multiple photoetchings, the application does not rely on the photoetching accuracy, but uses the groove structure formed by the prepared concave-convex surface as a physical guide to realize self-alignment of the etching path of the via, and fundamentally eliminates the mispositioning of the via caused by photoetching deviation, improves the manufacturing yield and reliability of the semiconductor device; and in order to reduce the possibility of mispositioning of the via, the traditional process is forced to reduce the size of the via, resulting in a sharp increase in the contact resistance and bulk resistance of the metal in the via; and since the etching path of the via can realize self-alignment, the application can set a larger size of the via, can reduce the resistance of the interconnection line, and can reduce the power consumption of the semiconductor device. The semiconductor device manufacturing method can realize accurate alignment of the upper via and the lower metal line, can reduce the resistance of the interconnection line, and can reduce the power consumption of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS
[0017] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.
[0018] Figure 1 One of the flowcharts of the semiconductor device manufacturing method provided by the embodiments of the application; Figure 2 This is a second schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figure 3 This is the third schematic flowchart illustrating the method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 4 Fourth schematic flowchart of the method for fabricating a semiconductor device provided in an embodiment of the present invention; Figure 5 One of the schematic diagrams illustrating the fabrication of a semiconductor device provided in an embodiment of the present invention; Figure 6 This is a second schematic diagram illustrating the fabrication of a semiconductor device provided in an embodiment of the present invention; Figure 7 The third schematic diagram illustrating the fabrication of the semiconductor device provided in this embodiment of the invention; Figure 8 The fourth schematic diagram illustrating the fabrication of a semiconductor device provided in an embodiment of the present invention; Figure 9 Fifth schematic diagram illustrating the fabrication of a semiconductor device provided in an embodiment of the present invention; Figure 10 Sixth schematic diagram of the fabrication of a semiconductor device provided in an embodiment of the present invention; Figure 11 The seventh schematic diagram illustrating the fabrication of a semiconductor device provided in an embodiment of the present invention; Figure 12 Eighth schematic diagram of the fabrication of a semiconductor device provided in an embodiment of the present invention; Figure 13 This is the ninth schematic diagram illustrating the fabrication of a semiconductor device provided in an embodiment of the present invention.
[0019] Icons: 110 - First metal interconnect; 120 - First dielectric layer; 130 - First etch stop layer; 140 - Sacrificial layer; 150 - Second dielectric layer; 160 - Second etch stop layer; 170 - Third dielectric layer; 180 - Through-hole; 190 - Second metal interconnect; 200 - Semiconductor device; A - Groove. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0023] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0024] Furthermore, terms such as "horizontal" and "vertical" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0025] In one aspect, the present invention provides a method for fabricating a semiconductor device 200, such as... Figure 1 As shown, it may include the following steps: Step S100: Provide a substrate, the substrate including a substrate, a first dielectric layer 120 located on the substrate, and a first metal interconnect 110 located within and penetrating the first dielectric layer 120, the top surface of the first metal interconnect 110 protruding from the top surface of the first dielectric layer 120.
[0026] Specifically, the substrate may include a substrate on which a first dielectric layer 120 is formed, and the first dielectric layer 120 is provided with at least one through groove in the vertical direction for accommodating the first metal interconnect 110.
[0027] Preferably, the first dielectric layer 120 is typically a low dielectric constant material to reduce parasitic capacitance.
[0028] In this embodiment, as Figure 6As shown, a plurality of through slots are spaced apart on the first dielectric layer 120 to accommodate a plurality of spaced-apart first metal interconnects 110. The top surface of the first metal interconnect 110 protrudes from the top surface of the first dielectric layer 120, such that the top surface of the first dielectric layer and the top surface of the second metal interconnect 190 form a first surface with a continuous concave-convex structure.
[0029] In this embodiment, the top surfaces of the plurality of first metal interconnects 110 are flush.
[0030] In actual production, such as Figure 2 As shown, a preferred embodiment of obtaining this substrate is as follows: Step S110: Provide a substrate. Optionally, the substrate is a silicon substrate or a substrate on which active devices such as transistors have been formed.
[0031] Step S120: Forming a first dielectric layer 120 covering the surface of the substrate. Preferably, the first dielectric layer 120 is a low dielectric constant dielectric material deposited on the surface of the substrate by a chemical vapor deposition process.
[0032] Step S130: Form a through-hole structure penetrating the first dielectric layer 120. Specifically, the pattern can be formed by photolithography, and the through-hole structure can be fabricated by dry etching process.
[0033] Step S140: Fill the through-hole structure with interconnect metal to form the first metal interconnect 110, such as... Figure 5 As shown. Preferably, the top surface of the first dielectric layer 120 can be made flush with the top surface of the first metal interconnect 110 by means of a chemical mechanical polishing process.
[0034] Step S150: Remove a portion of the thickness of the first dielectric layer 120, causing the top surface of the first metal interconnect 110 to protrude beyond the top surface of the first dielectric layer 120, thereby forming a first surface with a continuous uneven structure between the top surface of the first dielectric layer 120 and the top surface of the first metal interconnect 110, such as... Figure 6 As shown.
[0035] Optionally, a portion of the thickness of the first dielectric layer 120 can be removed by dry etching. Since the etching process has a selectivity ratio for dielectric and metal materials, the first metal interconnect 110 is not etched, thereby naturally causing its top surface to protrude relative to the top surface of the etched and recessed first dielectric layer 120, precisely forming the first surface of the desired convex-continuous uneven structure.
[0036] In this embodiment, the etching removal amount of the first dielectric layer 120 can be determined based on the thickness of the first etch stop layer and the sacrificial layer to be formed subsequently. Specifically, the etching removal amount can be greater than the thickness of the first etch stop layer and the sacrificial layer.
[0037] In this dry etching step, the oxygen-containing plasma used may oxidize the surface of the exposed first metal interconnect 110. Optionally, after removing a portion of the thickness of the first dielectric layer 120 by dry etching, the surface of the first metal interconnect 110 may be cleaned with chemical reagents to remove the oxide layer on the surface of the first metal interconnect 110.
[0038] Specifically, the chemical reagent may contain at least one of formic acid, acetic acid, and hydrochloric acid at low concentrations, or a mixed solution of at least one of these and a metal complexing agent; in addition to the above-mentioned acid solutions, the chemical solvent may also be other organic acid solvents, such as propionic acid, oxalic acid, etc. The mass fraction of the chemical reagent may be 0.1% to 5%.
[0039] Preferably, the chemical reagent is at least one of formic acid, acetic acid, and hydrochloric acid, and is a mixed solution of a metal complexing agent. The metal complexing agent can be selected from at least one of ammonia, citric acid, and tartaric acid. The metal complexing agent can form a stable and soluble complex with the metal ions dissolved during the cleaning process, preventing the metal ions from redepositing on the wafer surface and causing contamination, and also inhibiting over-corrosion of the first metal interconnect 110. For example, if the first metal interconnect 110 is made of copper, the chemical reagent can be a low-concentration mixed solution of formic acid and ammonia, which effectively removes copper oxide while protecting the underlying copper substrate from corrosion.
[0040] After successfully fabricating a base wafer with a first surface having a continuous uneven structure, the fabrication method further includes step S200, forming a first etch stop layer 130 and a sacrificial layer 140 covering the first etch stop layer 130, wherein the first etch stop layer 130 covers the top surface of the first metal interconnect 110 and the top surface of the first dielectric layer 120.
[0041] like Figure 8 As shown, since the first surface has a continuous uneven structure, the structure of the first etch stop layer 130 and the sacrificial layer 140 formed on the first surface is consistent with the first surface, that is, the first etch stop layer 130 conformally covers the first surface, and the sacrificial layer 140 conformally covers the first etch stop layer 130.
[0042] Specifically, such as Figure 7 As shown, the first etch stop layer 130 covers the top surface of the first metal interconnect 110 and its sidewalls protruding from the first dielectric layer 120, and also covers the top surface of the first dielectric layer 120. The subsequently formed sacrificial layer 140 also conformally covers the first etch stop layer 130, thereby completely replicating the underlying unevenness.
[0043] Preferably, both the first etch stop layer 130 and the sacrificial layer 140 are prepared by chemical vapor deposition.
[0044] In this embodiment, the first etch stop layer 130 serves as a protective layer and stop layer for subsequent processes.
[0045] In one specific embodiment of this application, the first etch stop layer 130 can be any one of a silicon carbonitride layer, a silicon nitride layer, a silicon oxide layer, or an aluminum nitride layer.
[0046] The material of the sacrificial layer 140 needs to have a high selectivity in etching rate with the first etch stop layer 130 and the subsequent dielectric layer to ensure that the etching process of the subsequent via 180 can be precisely terminated at the surface of the first etch stop layer 130. In one specific embodiment of this application, the sacrificial layer 140 is an alumina layer. The alumina layer can achieve conformal coverage through chemical vapor deposition and can be removed with high selectivity by subsequent wet reagents, with minimal damage to the surrounding materials.
[0047] In this embodiment, after sequentially forming the first etch stop layer 130 and the sacrificial layer 140, the fabrication method may further include step S300: forming a second dielectric layer 150 covering the sacrificial layer 140. The second dielectric layer 150 exposes the sacrificial layer 140 on the top surface of the first metal interconnect 110, and the top surface of the exposed sacrificial layer 140 is flush with the top surface of the second dielectric layer 150. Figure 8 As shown.
[0048] Specifically, such as Figure 8 As shown, the surface of the sacrificial layer 140 has the same structure as the first surface, both being a continuous concave-convex structure. The second dielectric layer 150 is formed in the area on the sacrificial layer 140 that corresponds to the projection of the first dielectric layer 120, which is the recess of the sacrificial layer 140. The second dielectric layer 150 also exposes the sacrificial layer 140 on the top surface of the first etch stop layer 130 on the sidewall of the first metal interconnect 110, as well as the top surface of the sacrificial layer 140 on the sidewall of the first etch stop layer 130. The exposed top surface of the sacrificial layer 140 is flush with the top surface of the second dielectric layer 150. In other words, the top surface of the second dielectric layer 150 is flush with the top surface of the protrusion of the sacrificial layer 140.
[0049] In this embodiment, the second dielectric layer 150 can be a low dielectric constant material to reduce parasitic capacitance. Preferably, the second dielectric layer 150 is made of the same material as the first dielectric layer 120.
[0050] In actual production, such as Figure 3 As shown, a preferred embodiment of growing the second dielectric layer 150 is as follows: Step S310: Form an initial second dielectric layer on the sacrificial layer 140.
[0051] Step S320: The initial second dielectric layer is polished by chemical mechanical polishing or other methods to planarize the second dielectric layer 150 until the sacrificial layer 140 on the top surface of the first metal interconnect 110 is exposed.
[0052] like Figure 8 As shown, this means that the protrusion of the sacrificial layer 140 is exposed in the second dielectric layer 150, so that the top surface of the second dielectric layer 150 is flush with the top surface of the protrusion of the sacrificial layer 140.
[0053] Step S400: Remove the exposed sacrificial layer 140 until the first etch stop layer 130 is exposed, forming a groove A on the top surface of the first metal interconnect 110, as shown. Figure 9 As shown.
[0054] Specifically, in conjunction with reference Figure 8 and Figure 9 Since the top surface of the second dielectric layer 150 is flush with the top surface of the protrusion of the sacrificial layer 140, the recess of the sacrificial layer 140 is covered by the second dielectric layer 150, while the top surface of the protrusion of the sacrificial layer 140 is not covered by the second dielectric layer 150. The sacrificial layer 140 not covered by the second dielectric layer 150 is removed by etching or other methods. This process will simultaneously remove the sacrificial layer 140 on the top surface of the first etch stop layer 130 and the sacrificial layer 140 on the top surface of the sidewall of the first etch stop layer 130, until the top surface of the first etch stop layer 130 on the surface of the first metal interconnect 110 and the top surface of the first etch stop layer 130 on the sidewall of the first metal interconnect 110 are exposed.
[0055] In this embodiment, while removing the sacrificial layer 140 not covered by the second dielectric layer 150, a portion of the sacrificial layer 140 on the sidewall of the first etch stop layer 130 is also removed, so that the top surface of the sacrificial layer 140 on the sidewall of the first etch stop layer 130 is flush with the top surface of the first etch stop layer 130. Figure 9 As shown.
[0056] In this embodiment, since the second dielectric layer 150 is not removed, the top surface of the second dielectric layer 150 is higher than the top surface of the exposed first etch stop layer 130. At this time, the top surface of the second dielectric layer 150, the cross-section of part of the sacrificial layer 140, and the exposed top surface of the first etch stop layer 130 together form the second surface. The second surface has a continuous uneven structure, with the area containing the second dielectric layer 150 being the raised portion and the exposed first etch stop layer 130 being the recessed portion, thus forming groove A, as shown. Figure 9 As shown. The groove A has the exposed first etch stop layer 130 and part of the sacrificial layer 140 as its bottom, and the second dielectric layer 150 as its sidewalls; the first metal interconnect 110 is directly below the groove A.
[0057] Step S500: Forming a second etch stop layer 160 and a third dielectric layer 170 located on the surface of the second etch stop layer 160, wherein the second etch stop layer 160 covers the exposed surface of the first etch stop layer 130 and the top surface of the second dielectric layer 150, as shown. Figure 10 and Figure 11 As shown.
[0058] The surface of the second etch stop layer 160 has the same structure as the second surface, both being a continuous concave-convex structure.
[0059] In one specific embodiment of this application, the second etch stop layer 160 is any one of a silicon carbonitride layer, an aluminum nitride layer, a silicon oxide layer, or a silicon nitride layer.
[0060] like Figure 11 As shown, the surface of the third dielectric layer 170 can be planarized by chemical mechanical polishing to facilitate subsequent patterning. The third dielectric layer 170 can be a low dielectric constant material to reduce parasitic capacitance.
[0061] Preferably, the third dielectric layer 170, the second dielectric layer 150, and the first dielectric layer 120 are all made of the same material.
[0062] Step S600: Sequentially etch the third dielectric layer 170, the second etch stop layer 160, and the first etch stop layer 130 until the top of the first metal interconnect 110 is exposed to form a via 180. Figure 12 As shown.
[0063] Specifically, the location of the via 180 is defined on the third dielectric layer 170 using photolithography, followed by etching.
[0064] During the etching process, the third dielectric layer 170 is etched first. Since the second etch stop layer 160 has a continuous uneven structure, under high etch selectivity, compared to etching to the protrusions closer to the second etch stop layer 160, the etching path of the via 180 will autonomously move towards the groove A, which is farther from the second etch stop layer 160, and ultimately simultaneously etch through the first etch stop layer 130 and the second etch stop layer 160 at the bottom of the groove A, until the top of the first metal interconnect 110 is exposed. Figure 12 As shown.
[0065] In this embodiment, based on the opening of the via 180 defined on the surface of the third dielectric layer 170, the etching process is guided by a preset groove A structure to remove all material below the groove A, so that the via 180 connects to the top of the first metal interconnect 110, thereby achieving self-alignment between the via 180 and the first metal interconnect 110.
[0066] It should be noted that this application does not impose any restrictions on the specific inner diameter of the through hole 180. The specific inner diameter of the through hole 180 can be adjusted according to actual needs within the maximum designable size, as long as the end of the through hole 180 near the first metal interconnect 110 can be connected to the through groove where the first metal interconnect 110 is located.
[0067] Compared to traditional processes that rely on multiple photolithography steps to define the positions of vias 180 and metal interconnects, this application does not depend on photolithographic precision. Instead, it utilizes the groove A structure formed by the fabricated uneven surface as a physical guide, enabling the etching path of the vias 180 to achieve self-alignment. This fundamentally eliminates via misalignment caused by photolithographic deviations, improving the fabrication yield and reliability of the semiconductor device 200. Furthermore, traditional processes, in order to reduce the possibility of via misalignment, are forced to reduce the size of the vias 180, leading to a sharp increase in the contact resistance and bulk resistance of the metal within the vias 180. In contrast, because the etching path of the vias 180 in this application can achieve self-alignment, larger vias 180 can be set, reducing the resistance of the interconnects and decreasing the power consumption of the semiconductor device 200. The above-described method for fabricating the semiconductor device 200 enables precise alignment between the upper vias 180 and the lower metal lines, while simultaneously reducing the resistance of the interconnects and decreasing the power consumption of the semiconductor device 200.
[0068] Optionally, after forming the through hole 180, the method may further include: cleaning the through hole 180 and drying it.
[0069] Specifically, the residue generated during the etching process of the via 180 can be removed by diluted hydrofluoric acid, EKC590 reagent or NE111 reagent, so as to ensure the cleanliness of the inner wall of the via 180 and improve the reliability of the subsequent fabrication of the second metal interconnect 190.
[0070] The residues may include polymer residues generated by the reaction of etching gas with photoresist and dielectric layer materials, metal compound residues generated by etching stop layers containing metal elements during etching, and dielectric material residues from the etched dielectric layer.
[0071] In this embodiment, after etching the through hole 180, as Figure 4 As shown, the preparation method may further include step S700, forming metal within the through-hole 180 to form a second metal interconnect 190 electrically connected to the first metal interconnect 110, such as... Figure 13 As shown.
[0072] In one specific embodiment of this application, it includes step S710, annealing the top surface of the first metal interconnect; and step S720, electroplating copper to form a copper interconnect structure in the through hole 180.
[0073] Specifically, after through-hole etching and cleaning, the top surface of the first metal interconnect 110 may still have a natural oxide layer or trace contaminants. This annealing treatment effectively removes the oxide layer at the interface and purifies the metal surface, activating its surface chemical state to optimize the ohmic contact between it and the second metal interconnect 190 formed by subsequent electroplating, thereby significantly reducing the contact resistance between the two metal interconnect layers. After annealing, the through-hole 180 can be filled by copper electroplating to form the second metal interconnect 190. To optimize the electrical performance and reliability of the copper material, the copper interconnect structure can be annealed after electroplating to promote grain growth, reduce resistance, and improve electromigration resistance.
[0074] In another aspect, the present invention provides a semiconductor device 200, which is prepared by the above-described method for preparing semiconductor device 200. The specific details and beneficial effects of the method for preparing the semiconductor device have been described in detail above and will not be repeated here. This semiconductor device 200, through its preparation method, ensures precise alignment between the upper via 180 and the lower metal line, while simultaneously reducing the resistance of the interconnects and decreasing the power consumption of the semiconductor device 200.
[0075] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
[0076] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a substrate, a first dielectric layer on the substrate, and a first metal interconnect line located within and through the first dielectric layer, the top surface of the first metal interconnect line protruding from the top surface of the first dielectric layer. A first etch stop layer and a sacrificial layer covering the first etch stop layer are formed, wherein the first etch stop layer covers the top surface of the first metal interconnect and the top surface of the first dielectric layer; A second dielectric layer is formed to cover the sacrificial layer, the second dielectric layer exposing the sacrificial layer on the top surface of the first metal interconnect, and the top surface of the exposed sacrificial layer is flush with the top surface of the second dielectric layer; Remove the exposed sacrificial layer until the first etch stop layer is exposed, forming a groove on the top surface of the first metal interconnect; A second etch stop layer and a third dielectric layer are formed on the surface of the second etch stop layer, wherein the second etch stop layer covers the exposed surface of the first etch stop layer and the top surface of the second dielectric layer; The third dielectric layer, the second etch stop layer, and the first etch stop layer are etched sequentially until the top of the first metal interconnect is exposed to form a via. Metal is formed within the through-hole to form a second metal interconnect that is electrically connected to the first metal interconnect.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first etch stop layer also covers the sidewall of the protruding first metal interconnect; the sacrificial layer conformally covers the first etch stop layer; The second dielectric layer also exposes the sacrificial layer on the top surface of the first etch stop layer of the first metal interconnect sidewall, and the top surface of the sacrificial layer of the first etch stop layer sidewall.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The provided substrate includes: Provide substrate; A first dielectric layer is formed covering the surface of the substrate; Forming a through-hole structure that penetrates the first dielectric layer; The through-hole structure is filled with interconnecting metal to form the first metal interconnect line; Remove a portion of the thickness of the first dielectric layer so that the top surface of the first metal interconnect protrudes beyond the top surface of the first dielectric layer.
4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The first dielectric layer, of a certain thickness, is removed by dry etching; After removing a portion of the first dielectric layer by dry etching, the method further includes: The surface of the first metal interconnect is cleaned with a chemical reagent to remove the oxide layer on the surface of the first metal interconnect. The chemical reagent includes at least one of formic acid, acetic acid and hydrochloric acid, or a mixed solution of at least one of them and a metal complexing agent.
5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The second dielectric layer forming the layer covering the sacrificial layer includes: An initial second dielectric layer is formed on the sacrificial layer; The initial second dielectric layer is planarized until the sacrificial layer on the top surface of the first metal interconnect is exposed.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that, After forming the through hole, the method further includes: Clean the through hole and dry it.
7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of metal within the through hole includes: The top surface of the first metal interconnect is annealed. Copper plating is performed to form a copper interconnect structure within the through-holes.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first etch stop layer is any one of silicon carbonitride, silicon nitride, silicon oxide, or aluminum nitride; the second etch stop layer is any one of silicon carbonitride, aluminum nitride, silicon oxide, or silicon nitride.
9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The sacrificial layer is an aluminum oxide layer.
10. A semiconductor device, characterized in that, It is prepared by the method of any one of claims 1-9.