Production business data processing system for discrete manufacturing shop

Abstract

The application relates to the technical field of manufacturing data processing, and discloses a production business data processing system for a discrete manufacturing workshop, which comprises the following modules: an asynchronous data acquisition module which collects asynchronous event pulse sequences of discrete execution nodes; a mapping transformation module which establishes an addressing mapping relationship between an event source and a memory logic bit plane and generates an original differential bit map; a bit map filtering module which uses the self-reflection principle of exclusive or logic to pair up logical flip signals, filters out the jitter interference of signal edges to generate a net value differential bit plane; and a state synchronization processing module which implements in-situ flip update of a state global bit map through address offset addressing according to a bit identifier. Through the bit map differential synchronization mechanism, the application realizes asynchronous state update without transaction lock constraint, alleviates the calculation blockage caused by high-frequency pulse impact, and enhances the real-time performance and stability of system data throughput.

Description

Technical Field

[0001] This invention relates to a production business data processing system for discrete manufacturing workshops, belonging to the field of manufacturing data processing technology. Background Technology

[0002] Current production business data processing systems in discrete manufacturing workshops typically maintain global data consistency using centralized polling or full event broadcasting. They record business state changes at each workstation using relational databases and utilize global transaction lock mechanisms to ensure synchronization between logical nodes. In ultra-high frequency processing scenarios such as precision assembly lines that generate high-density pulse signals, the rebound of physical actuators or edge glitches in photoelectric signals can cause transient reversals in logical states. Since existing technologies generally rely on time-domain filters to suppress such physical noise and eliminate signal jitter by configuring timers or sliding sampling windows for each node, this approach generates a massive number of clock interrupt requests and memory context switching overhead when handling massive concurrent events, leading to the exhaustion of processor memory bandwidth.

[0003] Existing technologies for improving production efficiency focus on hardware structure improvements, while software control methods and data processing logic have shortcomings. For example, Chinese invention patent CN112183939B discloses an intelligent scheduling method in the field of vehicle manufacturing, which achieves automated generation of scheduling plans through deep integration of MES and APS systems. However, at the underlying data processing level, it is essentially a sequential execution logic based on a centralized management framework. Faced with the high-frequency asynchronous pulse impacts generated by discrete manufacturing scenarios, such solutions lack an algebraic hedging mechanism for underlying signal glitches, making it difficult to escape the locking of computing resources by transaction locks. When dealing with nonlinear concurrent events, there is a structural conflict between the system's real-time responsiveness and data stability, failing to meet sub-millisecond synchronization requirements. Because it attempts to use synchronization lock logic to encapsulate the essentially asynchronous discrete physical process, this mismatch in processing methods causes unpredictable computational delays when the system faces production fluctuations. Even with conventional methods such as increasing processor clock speed or network throughput, it is still impossible to solve the non-productive computational losses caused by maintaining time-domain variables, and the out-of-order data packets in asynchronous environments will cause the global state bitmap to deviate from the true physical state.

[0004] Therefore, how to select a technical means that can realize on-demand partial updates of business status, algebraic offsetting of physical jitter, and construction of a causal logic self-healing barrier has become the technical problem to be solved by this invention. Summary of the Invention

[0005] To address the problems mentioned in the background art, the technical solution of the present invention is as follows: A production business data processing system for discrete manufacturing workshops, comprising:

[0006] The asynchronous data acquisition module is used to acquire asynchronous event pulse sequence data streams that characterize the physical operating state transitions of each discrete execution node in the manufacturing workshop;

[0007] The mapping transformation module, connected to the asynchronous data acquisition module, is used to establish a one-to-one addressing mapping relationship between each independent event source in the asynchronous event pulse sequence and each offset bit in the memory logic bit plane within the system's preset memory address space, and to generate original differential bit map data representing the initial state transition attributes in the corresponding memory logic bit plane based on the level transition characteristics of each independent pulse signal in the asynchronous event pulse sequence.

[0008] The bitmap filtering module, whose input is connected to the mapping transformation module, is used to extract the preset transient state mask bit plane from the offset storage area, and perform bit-by-bit XOR logic operation on the original differential bitmap and the transient state mask bit plane. The reflexivity principle of XOR operation is used to offset the pairwise logic flip signals generated by the physical bounce of the execution node, so as to filter out the logic glitch interference triggered by the asynchronous event pulse sequence at the signal edge, and output the net value differential bit plane data representing the valid business change information.

[0009] The state synchronization processing module, whose input is connected to the bitmap filtering module, is used to perform in-situ flip update on the global bitmap of production business state stored in the system memory protection area based on the non-zero bit identifier in the net value difference bit plane and through memory address offset addressing operation. This converts the physical state jump of each discrete execution node into the potential logic switch of the corresponding logical bit address in the global bitmap of production business state in real time, realizing asynchronous differential synchronization between physical discrete events and production business logic state under the condition of no transaction lock constraints.

[0010] Preferably, it also includes a logic verification module; the logic verification module is used to load a causal constraint bit vector representing the logical evolution constraint on the synchronization path of the state synchronization processing module. The causal constraint bit vector is a mask vector pre-stored in the configuration storage area and corresponding to the process path topology; the logic verification module intercepts non-physical timing state transitions that do not meet the logical premises defined by the causal constraint bit vector by performing a bitwise AND operation on the net value difference bit plane, and temporarily stores the intercepted difference bit signals in the memory logic buffer until the logic verification module receives a subsequent pulse signal that meets the logical premises and triggers serialization completion.

[0011] Preferably, it also includes a hotspot reconstruction module; the hotspot reconstruction module is used to count the flip frequency of each offset bit in the global bitmap of production business status, and identify hotspot address regions in high-frequency jumping state according to the flip frequency; the hotspot reconstruction module adjusts the sampling weight of different offset bit regions of the state synchronization processing module according to the distribution density of hotspot address regions, and tilts the scanning cycle resources to hotspot address regions with flip frequency higher than the preset frequency threshold, so as to asymmetrically adapt the computing load of different logical nodes.

[0012] Preferably, it also includes a status monitoring module; the status monitoring module is used to lock the current logic node to be responded to using the active front bitmap generated by the mapping, and start incremental timing for the offset bits covered by the active front bitmap; when the value of the incremental timing exceeds the preset time threshold and the corresponding offset bit does not undergo logical flip, the status monitoring module outputs an abnormal status signal that indicates that the underlying execution node is running stagnates.

[0013] Preferably, when the hotspot reconstruction module adjusts the sampling weights of different offset bit regions by the state synchronization processing module, the target sampling frequency of the logic bit plane where the corresponding offset bit is located is determined using the following formula. : ,in, The preset base sampling frequency is given, and ΔC represents the number of bit flips of the corresponding offset bit within the statistical period, with a dimension of 1. The maximum number of bit flips in the global bitmap of production business status within the statistical period.

[0014] Preferably, after performing bitwise XOR logic operation, the bitmap filtering module is also used to extract the residual bits that have not been canceled in the original differential bitmap, and to determine the residual bits as valid business state change increments and send them to the state synchronization processing module for bit update processing.

[0015] Preferably, the memory logical bit plane adopts a sparse matrix storage structure, and the mapping transformation module only performs address addressing on the active offset bit triggered by the asynchronous event pulse sequence, so as to reduce the bus occupancy rate of the state synchronization processing module when updating the global bit map of production business state.

[0016] Preferably, the causal constraint bit vector is dynamically configured in the configuration storage area according to the preset process specifications. When the system receives an external process change instruction, the logic verification module rewrites the mask bits in the causal constraint bit vector to achieve adaptive switching of logic constraints for different production stages.

[0017] Preferably, the asynchronous data acquisition module is connected to a signal conditioning module, which is used to convert level signals of different physical ranges into a unified standard logic pulse signal, and generate the original differential bitmap data based on the transition edge of the standard logic pulse signal triggering the mapping transformation module.

[0018] Preferably, the system also includes a backup module, which is used to periodically read the global bitmap of production business status in the memory protection area at a period of not less than 100ms after the in-bit flip update is completed, and perform snapshot persistent storage.

[0019] Compared with the prior art, the beneficial effects of the present invention are:

[0020] 1. In the production business data processing of discrete manufacturing workshops, the logic decoupling of the business state synchronization complexity from the scale of processing nodes is achieved. Each physical workstation in the discrete manufacturing process is mapped to a unique offset bit in the global state bitmap, and local updates are performed using topological association masks. This ensures that the synchronization operation of the system state depends only on the differential signal that causes the jump, rather than the total number of workstations in the workshop. This bit-logic-based asymmetric processing method reduces the quadratic computational complexity commonly encountered by traditional relational databases when handling high-frequency concurrent events to a constant level. It effectively avoids cascading computation timeouts caused by global transaction lock contention and ensures that logical feedback in large-scale discrete processes always precedes physical actions.

[0021] 2. Achieve deep decoupling between physical signal stabilization and processor computing resources. By utilizing the reflexive property of bitwise XOR operation to construct a transient annihilation bit plane, the high-frequency jitter generated by the physical sensor during state switching is transformed into algebraic offset in the memory bitmap. This mechanism abandons the path dependence of conventional technologies on time-domain stabilization timers and sliding time windows. Pairs of invalid jitter pulses are self-cancelled in memory addressing operations before entering the core business flow, thereby eliminating the continuous occupation of processor memory bandwidth by massive clock interrupt contexts and achieving hardware-level signal cleaning with zero clock cycle overhead.

[0022] 3. Establish an asynchronous logic self-healing barrier that does not rely on global clock synchronization. By pre-setting causal constraint bit vectors on the bitmap synchronization path, the system can perform legality verification on the state differential signal according to the topological constraints of the process path. When network fluctuations or sensor bounces cause non-physical timing state jumps, the abnormal differential is actively intercepted by bitwise AND operation and temporarily stored in the logic buffer until the process logic premise is met and serialization completion is triggered. This mechanism eliminates logic distortion in the asynchronous environment from the bottom layer of the data structure, so that the system can maintain the true physical consistency of the global business state even without expensive high-precision clock synchronization. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the overall logical architecture and asynchronous data flow of the production business data processing system of the present invention.

[0024] Figure 2 This is a schematic diagram of the signal offsetting and debouncing principle of the bitmap filtering module of the present invention based on the reflexivity of XOR logic.

[0025] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0027] A production business data processing system for discrete manufacturing workshops includes:

[0028] The asynchronous data acquisition module is used to acquire asynchronous event pulse sequence data streams that characterize the physical operating state transitions of each discrete execution node in the manufacturing workshop;

[0029] The mapping transformation module, connected to the asynchronous data acquisition module, is used to establish a one-to-one addressing mapping relationship between each independent event source in the asynchronous event pulse sequence and each offset bit in the memory logic bit plane within the system's preset memory address space, and to generate original differential bit map data representing the initial state transition attributes in the corresponding memory logic bit plane based on the level transition characteristics of each independent pulse signal in the asynchronous event pulse sequence.

[0030] The bitmap filtering module, whose input is connected to the mapping transformation module, is used to extract the preset transient state mask bit plane from the offset storage area, and perform bit-by-bit XOR logic operation on the original differential bitmap and the transient state mask bit plane. The reflexivity principle of XOR operation is used to offset the pairwise logic flip signals generated by the physical bounce of the execution node, so as to filter out the logic glitch interference triggered by the asynchronous event pulse sequence at the signal edge, and output the net value differential bit plane data representing the valid business change information.

[0031] The state synchronization processing module, whose input is connected to the bitmap filtering module, is used to perform in-situ flip update on the global bitmap of production business state stored in the system memory protection area based on the non-zero bit identifier in the net value difference bit plane and through memory address offset addressing operation. This converts the physical state jump of each discrete execution node into the potential logic switch of the corresponding logical bit address in the global bitmap of production business state in real time, realizing asynchronous differential synchronization between physical discrete events and production business logic state under the condition of no transaction lock constraints.

[0032] Preferably, it also includes a logic verification module; the logic verification module is used to load a causal constraint bit vector representing the logical evolution constraint on the synchronization path of the state synchronization processing module. The causal constraint bit vector is a mask vector pre-stored in the configuration storage area and corresponding to the process path topology; the logic verification module intercepts non-physical timing state transitions that do not meet the logical premises defined by the causal constraint bit vector by performing a bitwise AND operation on the net value difference bit plane, and temporarily stores the intercepted difference bit signals in the memory logic buffer until the logic verification module receives a subsequent pulse signal that meets the logical premises and triggers serialization completion.

[0033] Preferably, it also includes a hotspot reconstruction module; the hotspot reconstruction module is used to count the flip frequency of each offset bit in the global bitmap of production business status, and identify hotspot address regions in high-frequency jumping state according to the flip frequency; the hotspot reconstruction module adjusts the sampling weight of different offset bit regions of the state synchronization processing module according to the distribution density of hotspot address regions, and tilts the scanning cycle resources to hotspot address regions with flip frequency higher than the preset frequency threshold, so as to asymmetrically adapt the computing load of different logical nodes.

[0034] Preferably, it also includes a status monitoring module; the status monitoring module is used to lock the current logic node to be responded to using the active front bitmap generated by the mapping, and start incremental timing for the offset bits covered by the active front bitmap; when the value of the incremental timing exceeds the preset time threshold and the corresponding offset bit does not undergo logical flip, the status monitoring module outputs an abnormal status signal that indicates that the underlying execution node is running stagnates.

[0035] Preferably, when the hotspot reconstruction module adjusts the sampling weights of different offset bit regions by the state synchronization processing module, the target sampling frequency of the logic bit plane where the corresponding offset bit is located is determined using the following formula. : ,in, The preset base sampling frequency is given, and ΔC represents the number of bit flips of the corresponding offset bit within the statistical period, with a dimension of 1. The maximum number of bit flips in the global bitmap of production business status within the statistical period.

[0036] Preferably, after performing bitwise XOR logic operation, the bitmap filtering module is also used to extract the residual bits that have not been canceled in the original differential bitmap, and to determine the residual bits as valid business state change increments and send them to the state synchronization processing module for bit update processing.

[0037] Preferably, the memory logical bit plane adopts a sparse matrix storage structure, and the mapping transformation module only performs address addressing on the active offset bit triggered by the asynchronous event pulse sequence, so as to reduce the bus occupancy rate of the state synchronization processing module when updating the global bit map of production business state.

[0038] Preferably, the causal constraint bit vector is dynamically configured in the configuration storage area according to the preset process specifications. When the system receives an external process change instruction, the logic verification module rewrites the mask bits in the causal constraint bit vector to achieve adaptive switching of logic constraints for different production stages.

[0039] Preferably, the asynchronous data acquisition module is connected to a signal conditioning module, which is used to convert level signals of different physical ranges into a unified standard logic pulse signal, and generate the original differential bitmap data based on the transition edge of the standard logic pulse signal triggering the mapping transformation module.

[0040] Preferably, the system also includes a backup module, which is used to periodically read the global bitmap of production business status in the memory protection area at a period of not less than 100ms after the in-bit flip update is completed, and perform snapshot persistent storage.

[0041] Example 1: In a continuously operating precision electronic discrete assembly line, 2000 photoelectric sensors deployed on-site generate 500,000 asynchronous event pulse sequences per second. These signals characterize the physical operating state transitions of each discrete execution node within the manufacturing workshop. Due to the physical rebound generated by the actuators during high-speed reciprocating motion, the pulse signals output by the sensors frequently trigger high-frequency logic glitches at the level transition edges. This physical instability causes conventional systems that rely on time-domain filters to suppress physical noise to generate a large number of clock interrupt requests and memory context switching overhead when handling massive concurrent events, exhausting the processor's memory bandwidth. When the production business data processing system operates under the aforementioned pulse impact conditions, the asynchronous data acquisition module captures the asynchronous event pulse sequences of each discrete execution node and maps and transforms them. Within the system's preset memory address space, the module establishes a one-to-one addressing mapping relationship between each independent event source and each offset bit in the memory logic bit plane. Based on the level transition characteristics of the pulse signal, it generates the original differential bitmap data in the memory logic bit plane. The bitmap filtering module is connected to the output of the mapping transformation module, extracts the preset transient state mask bit plane from the offset storage area, and performs a bit-by-bit XOR logic operation on the original differential bitmap and the transient state mask bit plane. It uses the reflexivity principle of XOR logic to offset the paired logic flip signals generated by the physical bounce of discrete execution nodes, so that the invalid jitter pulses appearing in pairs can directly cancel each other out in the memory addressing operation. Thus, without the need to introduce a time-domain anti-jitter timer or sliding time window, it filters out the logic glitch interference generated by the asynchronous event pulse sequence at the signal edge.

[0042] The state synchronization processing module, based on the non-zero bit identifiers in the net value difference quantile plane data output by the bitmap filtering module, performs in-situ flip updates on the global bitmap of production business status stored in the system memory protection area through memory address offset addressing operations. This transforms the physical state transitions of each discrete execution node into potential logic switching of the corresponding logical bit address in the global bitmap of production business status. During this process, the hotspot reconstruction module counts the flip frequency of each offset bit and identifies hotspot address regions in high-frequency transition states. The target sampling frequency of the logical bit plane where the corresponding offset bit is located is determined using the following formula. : ,in, For the target sampling frequency, The preset base sampling frequency is ΔC, where ΔC is the number of bit flip counts for the corresponding offset bit within the statistical period. The module calculates the maximum number of bit flips in the global bitmap of production business status within a statistical period. Based on the calculation results, it adjusts the sampling weights of different offset bit regions in the status synchronization processing module, tilting computing resources toward hotspot address regions with flip frequencies higher than a preset frequency threshold. This scheme achieves asynchronous differential synchronization of physical discrete events and production business logic status without transaction lock constraints through a bitmap-based differential synchronization mechanism. This bit logic-based processing method limits the processing complexity of high-frequency concurrent events to a constant level, ensuring that logical feedback under large-scale discrete processes always precedes physical actions.

[0043] Example 2: In a discrete electronic assembly test bench composed of 2000 photoelectric sensors, an asynchronous pulse stream with a frequency of 100kHz is generated using a high-precision digital signal generator, and a pulse width of 8.5 is superimposed. The high-frequency glitches in s are used to simulate the physical state transitions of discrete execution nodes in a real production environment and the interference caused by physical bounce, where the base sampling frequency is... The reference value is determined by the minimum pulse width of the monitored signal. Based on the Nyquist sampling theorem, 500kHz is selected as the basic reference value to ensure the integrity of signal capture. The control group uses a time-domain filtering and synchronous transaction lock architecture. The present invention's sample group uses an asynchronous event-driven bitmap-based differential synchronization mechanism, utilizing an asynchronous data acquisition module in conjunction with a mapping transformation module to perform bit-map conversion on the input signal. The mapping transformation module generates the original differential bitmap in the memory logic bit plane. Monitoring data shows that the total number of bit flips per second is [missing data]. The proportion of paired flipped bits belonging to physical bounce noise reached 35.2%. The bitmap filtering module extracted the transient state mask bit plane from the hedging storage area and performed a bit-by-bit XOR operation with the original differential bitmap; after the operation, the bit count value of non-zero bits in the output net value differential bit plane was reduced to This indicates that the mechanism eliminates more than 99.8% of paired logic jitter signals during the memory addressing phase by utilizing the reflexivity of XOR logic. In contrast, the control group, when dealing with noise impacts of the same intensity, suffers from 45,000 interrupt re-entry overheads per second due to its reliance on interrupt responses, resulting in the processor frequency being in a high-load saturation state of 92.5% before the business logic is triggered.

[0044] A problem intensity gradient system is established by adjusting 10% to 80% of the nodes to a high-frequency transition state. The hotspot reconstruction module monitors the flip frequency in the global bitmap of the production business status in real time and calculates the target sampling frequency for each offset bit. When the bit flip count ΔC of the corresponding offset bit is 8500 times and the maximum bit flip count in the system is... When the target sampling frequency is 12000 times, At the basic sampling frequency The dynamic boost from 500kHz to 854.1kHz is calculated using the following formula: ,in, For the target sampling frequency, The preset base sampling frequency is ΔC, where ΔC is the number of bit flip counts for the corresponding offset bit within the statistical period. The maximum number of bit flips in the global bitmap of production business status within the statistical period is used to count the total offset bits. At this time, the state synchronization time of the hot spot address area is reduced from 2.15ms in the fixed frequency mode to 0.88ms. When the proportion of high frequency nodes increases to more than 85% of the out-of-range range, the gain rate of sampling weight tends to level off because the memory bandwidth reaches the physical throughput limit of 95%. This phenomenon confirms the optimization boundary of the hot spot reconstruction mechanism in terms of computing resource allocation. The results show that the system using the scheme of this invention has an average response delay of around 1.15ms under the pulse impact condition. Compared with the response delay of 42.5ms in the control group, the bitmap differential update path effectively avoids the cascading blocking caused by synchronous transaction locks and reduces the computational complexity while maintaining data consistency.

[0045] Example 3: In a discrete manufacturing unit containing multi-level material sorting and parallel assembly processes, the system encounters an abnormal photoelectric pulse capture sequence due to electromagnetic interference in the field. Specifically, the assembly start pulse for station B has not yet arrived, while the completion pulse for station C arrives first due to network routing jitter. This non-physical timing state jump causes logical holes in the global bitmap of the production business state. The logic verification module loads a causal constraint bit vector on the synchronization path of the state synchronization processing module. Causal constraint bit vector This refers to the mask vector pre-stored in the configuration storage area and corresponding to the process path topology, and the causal constraint bit vector. Each logical bit in Offset bit in memory logical bit plane Establish a one-to-one mapping relationship; when the offset bit The physical action represented depends on the offset bit. When the preceding driving action of the representation is completed, the causal constraint bit vector The logic value at offset j is subject to real-time feedback of the current level state of offset i in the global bitmap of production business status.

[0046] The logic verification module receives the net value difference quantile plane output by the bitmap filtering module. By analyzing the net value difference quantile plane With the causal constraint bit vector pre-stored in the configuration storage area Perform a bitwise AND operation to determine the valid difference bitmap after verification. The calculation process is as follows: ,in, An effective differential bitmap consists of non-zero bits that have passed verification. For the input net value difference quantile plane, This represents the causal constraint bit vector under real-time business conditions; the logic verification module identifies the net value difference quantile plane. The bit vector constrained by causality Non-zero bits are masked, and the intercepted differential bit signals are temporarily stored in a memory logic buffer; the status monitoring module monitors the potential flipping of the corresponding predecessor logic bits in the global bitmap of production business status and synchronously updates the causal constraint bit vector. The shielding state; after receiving a subsequent pulse signal that meets the logical premise, the logic verification module retrieves the matching differential bit signal from the memory logic buffer and injects it into the input of the state synchronization processing module to realize the automatic completion of the state sequence. This mechanism uses bitmasks to process the logical dependency relationship of parallel multi-task bits, avoiding the conflict detection delay caused by the global business lock; when the system faces a 15% signal out-of-order condition, it maintains the consistency between the global bitmap of production business state and the physical field operation logic by loading logical constraints on the memory addressing path, ensuring that the business data flow in the large-scale discrete manufacturing scenario conforms to the preset physical evolution law.

[0047] Example 4: When the system is deployed in a new production process path scenario, the physical workstation timing logic of the manufacturing workshop is converted into address constraints of the memory logic bit plane through a topology discretization calibration process; the system parses the process description file containing the sequence of physical nodes and assigns a globally unique memory offset address to each discrete execution node. And based on the logical dependencies between process nodes, an initial causal constraint bit vector is constructed in the configuration storage area. If the initiation of physical action j depends on the completion of physical action i, then the corresponding offset bit in j... In a vector, The logic position pointed to by the offset bit is set to an active level, so that the logic verification module can verify the logic premise of the net value difference bit plane entering the synchronization path according to the bit mask during the operation phase, and transform the physical topology into digital logic constraints.

[0048] Before the production business data processing system is officially connected to the business flow, the transient state mask bit plane in the hedging storage area is initialized through the no-load monitoring calibration procedure to eliminate the background noise generated by the physical rebound of the actuator; the system starts high-speed pulse capture during the no-load operation phase of the manufacturing unit, and the asynchronous data acquisition module acquires the original pulse sequence of each discrete execution node within a continuous 500ms monitoring window, and counts each offset bit. The system calculates the non-service flip-over frequency per unit time and the signal stability coefficient, which is determined by the ratio of the monitoring window duration to the non-service flip-over frequency. When the signal stability coefficient of a node is lower than the system's preset stability threshold, the system sets the corresponding logical offset bit in the transient state mask bit plane. This causes the edge glitches generated by the node in the subsequent production process to be algebraically offset by the mask bit in the XOR operation of the bitmap filtering module, so that the update action of the global bitmap of the production business state only responds to the real physical state jump.

[0049] Example 5: In a flexible assembly workshop with 50 discrete workstations, the system faces a process path topology rearrangement caused by dynamic restructuring of the production process. The addition of new physical workstations leads to changes in the pre-defined causal constraint bit vectors. When discrepancies arise with the current physical dependencies, the system extracts the physical connection sequences of each discrete execution node within the manufacturing workshop through a topology scan calibration procedure. It then parses the process topology file describing the preceding and following relationships between workstations and converts the extracted process nodes into corresponding offset bits in the memory logical bit plane. For each workstation pair i and j with temporal dependencies, a test sequence containing valid state transitions is input in an offline environment. A bit logic tracker is used to record the bit level flip times of offset j under physical constraints. In a low-level state and When a flip signal is generated, the system determines that the state is a non-physical transition and sets the causal constraint bit vector accordingly. The mask position corresponding to the offset bit in the middle j is used to establish a physical logic constraint matrix based on the memory addressing offset, so as to realize the automatic conversion of the physical process path to the bit plane mask structure.

[0050] In the aforementioned deployment environment, to address the edge burr interference generated by mechanical vibrations of varying intensities on the sensor, the system determines the preset frequency threshold for the hotspot reconstruction module using an adaptive threshold calibration procedure. Within a 1000ms static sampling period after system initialization, the asynchronous data acquisition module captures random disturbance signals from the background environment, counts the number of bit flips for each offset bit within the sampling period, calculates the average value μ and standard deviation σ of the total offset bit flip count, and uses the following formula to determine the preset frequency threshold for the current deployment environment. : ,in, The system uses a preset frequency threshold, μ as the average number of bit flips within a statistical period, σ as the standard deviation of the number of bit flips, and k as a preset sensitivity adjustment coefficient. Based on the quantization index calculated by this formula, the system performs stability assessments on each offset bit. When the actual flip frequency exceeds... At that time, the hotspot reconstruction module triggers the asymmetric allocation logic of the sampling weight, so that the state synchronization processing module responds first to the memory area with high-frequency fluctuations. It uses the parameter calibration method based on statistical distribution to eliminate logical misjudgments caused by differences in environmental noise, and ensures that the update action of the global bitmap of production business status is consistent with the spatial distribution characteristics of production hotspots.

[0051] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A production business data processing system for discrete manufacturing workshops, characterized in that, include: The asynchronous data acquisition module is used to acquire asynchronous event pulse sequence data streams that characterize the physical operating state transitions of each discrete execution node in the manufacturing workshop; The mapping transformation module, connected to the asynchronous data acquisition module, is used to establish a one-to-one addressing mapping relationship between each independent event source in the asynchronous event pulse sequence and each offset bit in the memory logic bit plane within the system's preset memory address space, and to generate original differential bit map data representing the initial state transition attributes in the corresponding memory logic bit plane based on the level transition characteristics of each independent pulse signal in the asynchronous event pulse sequence. The bitmap filtering module, whose input is connected to the mapping transformation module, is used to extract the preset transient state mask bit plane from the offset storage area, and perform bit-by-bit XOR logic operation on the original differential bitmap and the transient state mask bit plane. The reflexivity principle of XOR operation is used to offset the pairwise logic flip signals generated by the physical bounce of the execution node, so as to filter out the logic glitch interference triggered by the asynchronous event pulse sequence at the signal edge, and output the net value differential bit plane data representing the valid business change information. The state synchronization processing module, whose input is connected to the bitmap filtering module, is used to perform in-situ flip update on the global bitmap of production business state stored in the system memory protection area based on the non-zero bit identifier in the net value difference bit plane and through memory address offset addressing operation. This converts the physical state jump of each discrete execution node into the potential logic switch of the corresponding logical bit address in the global bitmap of production business state in real time, realizing asynchronous differential synchronization between physical discrete events and production business logic state under the condition of no transaction lock constraints.

2. The production business data processing system for discrete manufacturing workshops according to claim 1, characterized in that, It also includes a logic verification module; the logic verification module is used to load the causal constraint bit vector representing the logical evolution constraint on the synchronization path of the state synchronization processing module. The causal constraint bit vector is a mask vector pre-stored in the configuration storage area and corresponding to the process path topology; the logic verification module intercepts non-physical timing state transitions that do not meet the logical premises defined by the causal constraint bit vector by performing a bitwise AND operation on the net value differential bit plane, and temporarily stores the intercepted differential bit signals in the memory logic buffer until the logic verification module receives the subsequent pulse signal that meets the logical premise and triggers serialization completion.

3. A production business data processing system for discrete manufacturing workshops according to claim 2, characterized in that, It also includes a hotspot reconstruction module; the hotspot reconstruction module is used to count the flip frequency of each offset bit in the global bitmap of production business status, and identify hotspot address regions in high-frequency jumping state based on the flip frequency; the hotspot reconstruction module adjusts the sampling weight of different offset bit regions of the status synchronization processing module according to the distribution density of hotspot address regions, and tilts the scanning cycle resources to hotspot address regions with flip frequency higher than the preset frequency threshold, so as to asymmetrically adapt the computing load of different logical nodes.

4. A production business data processing system for discrete manufacturing workshops according to claim 1, characterized in that, It also includes a status monitoring module; the status monitoring module is used to lock the currently responding logical node using the active front bitmap generated by the mapping, and start incremental timing for the offset bit covered by the active front bitmap; when the value of the incremental timing exceeds the preset time threshold and the corresponding offset bit does not undergo logical flip, the status monitoring module outputs an abnormal status signal that indicates that the underlying execution node is running stagnate.

5. A production business data processing system for discrete manufacturing workshops according to claim 3, characterized in that, When the hotspot reconstruction module adjusts the sampling weights of different offset bit regions by the state synchronization processing module, the target sampling frequency of the logic bit plane where the corresponding offset bit is located is determined using the following formula. : ,in, The preset base sampling frequency is given, and ΔC represents the number of bit flips of the corresponding offset bit within the statistical period, with a dimension of 1. The maximum number of bit flips in the global bitmap of production business status within the statistical period.

6. A production business data processing system for discrete manufacturing workshops according to claim 1, characterized in that, After performing bitwise XOR logic operations, the bitmap filtering module also extracts the residual bits that have not been canceled in the original differential bitmap, and determines the residual bits as valid business state change increments, which are then sent to the state synchronization processing module for bit update processing.

7. A production business data processing system for discrete manufacturing workshops according to claim 1, characterized in that, The memory logical bit plane adopts a sparse matrix storage structure. The mapping transformation module only performs address addressing on the active offset bit triggered by the asynchronous event pulse sequence, so as to reduce the bus occupancy rate of the state synchronization processing module when updating the global bit map of production business state.

8. A production business data processing system for discrete manufacturing workshops according to claim 2, characterized in that, The causal constraint bit vector is dynamically configured in the configuration storage area according to the preset process specifications. When the system receives an external process change instruction, the logic verification module adapts to the switching of logical constraints for different production stages by rewriting the mask bits in the causal constraint bit vector.

9. A production business data processing system for discrete manufacturing workshops according to claim 1, characterized in that, The asynchronous data acquisition module is connected to a signal conditioning module, which is used to convert level signals of different physical ranges into a unified standard logic pulse signal, and generate the original differential bitmap data based on the transition edge of the standard logic pulse signal to trigger the mapping transformation module.

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