Sensing amplification circuit, memory, electronic device, and data access method

Abstract

The invention relates to the field of integrated circuits, and discloses a sensing amplification circuit, a memory, electronic equipment and a data access method. The sensing amplification circuit comprises a cross coupling unit, a bias unit and an active load unit. The cross coupling unit is used for preliminarily amplifying a difference value between an input signal and a reference signal in a current sensing stage; and in the voltage sensing stage, the difference value between the input signal and the reference signal is further amplified. And the bias unit is used for conducting the first voltage source with the two output ends of the cross coupling unit in a current sensing stage. And the active load unit is used for connecting a second voltage source to the two input ends of the cross coupling unit. Wherein the active load unit has a first impedance in a current sensing stage, and has a second impedance in a voltage sensing stage; the first impedance is greater than the second impedance.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more specifically to a sensing amplifier circuit, a memory, an electronic device, and a data access method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that primarily works by using the charge within a storage cell to represent the stored data, that is, to represent whether a binary bit is 1 or 0.

[0003] The sense amplifier (SA) circuit is used to read and amplify the data stored in the memory cell. However, the performance of the sense amplifier circuit is limited by factors such as differences in transistor parameters, and there is still room for improvement. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a sensing amplifier circuit, a memory, an electronic device, and a data access method that can improve sensing speed and accuracy.

[0005] The technical solution of this disclosure embodiment is implemented as follows:

[0006] This disclosure provides a sensing amplification circuit for amplifying the signal difference between coupled bit lines during a sensing phase. The sensing phase includes at least a current sensing phase and a voltage sensing phase. The sensing amplification circuit includes a cross-coupling unit, a bias unit, and an active load unit. The two input terminals of the cross-coupling unit are respectively coupled to two corresponding bit lines for acquiring an input signal and a reference signal. The two output terminals of the cross-coupling unit are used to output a first sensing voltage and a second sensing voltage, wherein the first sensing voltage corresponds to the input signal, and the second sensing voltage corresponds to the reference signal. The bias unit is coupled between a first voltage source and the two output terminals of the cross-coupling unit. The first terminal of the bias unit is connected to the first voltage source, the second terminal of the bias unit is connected to the first output terminal of the cross-coupling unit, and the third terminal of the bias unit is connected to the second output terminal of the cross-coupling unit. The active load unit is coupled between a second voltage source and the two input terminals of the cross-coupling unit. The first terminal of the active load unit is connected to the second voltage source, and the active load unit is connected to the second input terminal of the cross-coupling unit. The second end of the load unit is connected to the first input terminal of the cross-coupled unit, and the third end of the active load unit is connected to the second input terminal of the cross-coupled unit. The bias unit is configured to conduct between the first voltage source and the two output terminals of the cross-coupled unit during the current sensing phase, and to disconnect between the first voltage source and the two output terminals of the cross-coupled unit during the voltage sensing phase. The active load unit is configured to connect the second voltage source to the two input terminals of the cross-coupled unit at least during the current sensing phase and the voltage sensing phase. The active load unit has a first impedance during the current sensing phase and a second impedance during the voltage sensing phase. The first impedance is greater than the second impedance. The cross-coupled unit is configured to initially amplify the difference between the input signal and the reference signal during the current sensing phase, at least under the action of the first voltage source and the second voltage source, and to further amplify the difference between the input signal and the reference signal during the voltage sensing phase, at least under the action of the second voltage source.

[0007] In some embodiments of this disclosure, the sensing amplification circuit further includes: an isolation unit; the isolation unit is coupled between two input terminals of the cross-coupling unit and the corresponding two bit lines; the isolation unit is configured to, during the equalization phase and the current sensing phase, turn on the cross-coupling unit and the corresponding two bit lines, and input the input signal and the reference signal to the cross-coupling unit; and, during the voltage sensing phase, disconnect the cross-coupling unit and the corresponding two bit lines.

[0008] In some embodiments of this disclosure, the sensing amplification circuit further includes: an equalization unit coupled between the two outputs of the cross-coupled unit, configured to bring the first sensing voltage and the second sensing voltage to equality during the equalization phase.

[0009] In some embodiments of this disclosure, the cross-coupling unit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; the source of the first transistor, the gate of the second transistor, the gate of the third transistor, and the source of the fourth transistor are connected together and connected to a first output terminal of the cross-coupling unit; the gate of the first transistor, the source of the second transistor, the source of the third transistor, and the gate of the fourth transistor are connected together and connected to a second output terminal of the cross-coupling unit; the drain of the first transistor is connected to a first input terminal of the cross-coupling unit; and the drain of the second transistor is connected to a second input terminal of the cross-coupling unit.

[0010] In some embodiments of this disclosure, the active load unit includes: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the fifth transistor and the seventh transistor are connected in parallel; the source of the fifth transistor and the source of the seventh transistor are both connected to a first input terminal of the cross-coupled unit; the drain of the fifth transistor and the drain of the seventh transistor are both connected to a second voltage source; the sixth transistor and the eighth transistor are connected in parallel; the source of the sixth transistor and the source of the eighth transistor are both connected to a second input terminal of the cross-coupled unit; the drain of the sixth transistor and the drain of the eighth transistor are both connected to the second voltage source; the gate of the seventh transistor and the gate of the eighth transistor both receive a first readout control signal.

[0011] In some embodiments of this disclosure, the impedance of the seventh transistor is less than that of the fifth transistor; and the impedance of the eighth transistor is less than that of the sixth transistor.

[0012] In some embodiments of this disclosure, the isolation unit includes a ninth transistor and a tenth transistor; the source of the ninth transistor receives the input signal, and the drain of the ninth transistor is connected to a first input terminal of the cross-coupling unit; the source of the tenth transistor receives the reference signal, and the drain of the tenth transistor is connected to a second input terminal of the cross-coupling unit; the gates of both the ninth and tenth transistors receive an inverted signal of a first readout control signal.

[0013] In some embodiments of this disclosure, the bias unit includes: an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; the source of the eleventh transistor is connected to the drain of the third transistor and the drain of the fourth transistor; the drain of the eleventh transistor is connected to a first voltage source; the gate of the eleventh transistor receives an inverted signal of a first readout control signal; the source of the twelfth transistor is connected to the drain of the thirteenth transistor and the drain of the fourteenth transistor; the drain of the twelfth transistor is connected to the first voltage source; the gate of the twelfth transistor receives an inverted signal of a second readout control signal; the source of the thirteenth transistor is connected to the source of the first transistor; the source of the fourteenth transistor is connected to the source of the second transistor; the gates of both the thirteenth and fourteenth transistors receive the first readout control signal.

[0014] In some embodiments of this disclosure, the equalization unit includes a fifteenth transistor and a sixteenth transistor; the source of the fifteenth transistor and the source of the sixteenth transistor are both connected to a first output terminal of the cross-coupling unit; the drain of the fifteenth transistor and the drain of the sixteenth transistor are both connected to a second output terminal of the cross-coupling unit; and the gate of the fifteenth transistor and the gate of the sixteenth transistor receive an equalization signal.

[0015] This disclosure also provides a memory comprising a plurality of sensing amplification circuits as described in the above embodiments. The memory includes multiple rows of word lines and multiple columns of bit lines, as well as storage cells coupled between the word lines and the bit lines; each sensing amplification circuit is coupled to two corresponding bit lines.

[0016] This disclosure also provides an electronic device, which includes the memory described in the above-described scheme.

[0017] This disclosure also provides a data access method applied to the sensing amplifier circuit described above; the data access method includes: in a current sensing stage, a cross-coupling unit acquires an input signal and a reference signal, and under the action of at least a first voltage source and a second voltage source, initially amplifies the difference between the input signal and the reference signal; wherein, in the current sensing stage, an active load unit has a first impedance; the active load unit is coupled between the second voltage source and the two input terminals of the cross-coupling unit; in a voltage sensing stage, the cross-coupling unit, under the action of at least the second voltage source, further amplifies the difference between the input signal and the reference signal, and outputs a first sensing voltage and a second sensing voltage; wherein, in the voltage sensing stage, the active load unit has a second impedance; the first impedance is greater than the second impedance.

[0018] In some embodiments of this disclosure, the data access method further includes: during the equalization phase and the current sensing phase, the isolation unit turns on the cross-coupling unit and the corresponding two bit lines, and inputs the input signal and the reference signal to the cross-coupling unit; during the voltage sensing phase, the isolation unit disconnects the cross-coupling unit and the corresponding two bit lines; during the equalization phase, the equalization unit equalizes the first sensed voltage and the second sensed voltage.

[0019] Understandably, during the current sensing phase, the bias unit connects the first voltage source to the two outputs of the cross-coupling unit, while the active load unit connects the second voltage source to the two inputs of the cross-coupling unit. Thus, the cross-coupling unit, under the influence of both the first and second voltage sources, initially amplifies the difference between the input and reference signals. During the voltage sensing phase, the bias unit disconnects the first voltage source from the two outputs of the cross-coupling unit, while the active load unit connects the second voltage source to the two inputs of the cross-coupling unit. Thus, the cross-coupling unit, under the influence of the second voltage source, further amplifies the difference between the input and reference signals. It's important to note that the impedance of the active load unit is not fixed during the operation of the sensing amplifier circuit; it can be adjusted as needed. This allows the active load unit to adjust its impedance as required during both the current and voltage sensing phases, thereby improving the performance of the sensing amplifier circuit and increasing the sensing rate and accuracy.

[0020] On the one hand, the active load unit can have a large first impedance during the current sensing stage; thus, compared with the first impedance of the active load unit, the impedance difference between the cross-coupling unit and the bias unit is too small to be ignored; thereby, the adverse effects caused by the mismatch of transistor pairs in the cross-coupling unit and the bias unit are reduced, ensuring the accuracy of sensing and avoiding data access errors.

[0021] On the other hand, the active load unit can have a smaller second impedance during the voltage sensing stage; this reduces the voltage division of the active load unit during the voltage sensing stage, thereby increasing the voltage division of the cross-coupling unit; thus, the amplification effect of the cross-coupling unit on the voltage difference is accelerated, and the sensing rate is improved. Attached Figure Description

[0022] Figure 1 Schematic diagram of the sensing amplifier circuit provided in the embodiments of this disclosure Figure 1 ;

[0023] Figure 2 Schematic diagram of the sensing amplifier circuit provided in the embodiments of this disclosure Figure 2 ;

[0024] Figure 3 Schematic diagram of the sensing amplifier circuit provided in the embodiments of this disclosure Figure 3 ;

[0025] Figure 4 Schematic diagram of the sensing amplifier circuit provided in the embodiments of this disclosure Figure 4 ;

[0026] Figure 5 Schematic diagram of the sensing amplifier circuit provided in the embodiments of this disclosure Figure 5 ;

[0027] Figure 6 Schematic diagram of the sensing amplifier circuit provided in the embodiments of this disclosure Figure 6 ;

[0028] Figure 7 The signal waveform diagram corresponding to the sensing amplifier circuit provided in the embodiments of this disclosure;

[0029] Figure 8 A schematic diagram of the memory structure provided in the embodiments of this disclosure;

[0030] Figure 9 This is a schematic diagram illustrating the implementation process of the data access method provided in the embodiments of this disclosure. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0032] In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for descriptive purposes only and is not intended to limit this disclosure.

[0034] Figure 1This is a schematic diagram of an optional structure of the sensing amplifier circuit provided in an embodiment of this disclosure. For example... Figure 1 As shown, the sensing amplifier circuit includes: a bias unit 10, a cross-coupling unit 20, and an active load unit 30.

[0035] The two input terminals of the cross-coupling unit 20 are respectively coupled to the two corresponding bit lines to acquire the input signal I. cell and reference signal I ref The two output terminals of the cross-coupling unit 20 are used to output the first sensed voltage V. SA Second sensing voltage V SAB The first sensing voltage V SA Corresponding input signal I cell The second sensing voltage V SAB Corresponding reference signal I ref .

[0036] Bias unit 10 is coupled to the first voltage source V DD Between the two output terminals of the cross-coupling unit 20; wherein, the first terminal of the bias unit 10 is connected to the first voltage source V. DD The second end of the bias unit 10 is connected to the first output end of the cross-coupled unit 20, and the third end of the bias unit 10 is connected to the second output end of the cross-coupled unit 20.

[0037] The active load unit 30 is coupled to the second voltage source V. SS Between the two input terminals of the cross-coupling unit 20; wherein, the first terminal of the active load unit 30 is connected to the second voltage source V. SS The second end of the active load unit 30 is connected to the first input end of the cross-coupled unit 20, and the third end of the active load unit 30 is connected to the second input end of the cross-coupled unit 20.

[0038] The bias unit 10 is configured to, in response to the readout control signal SAEN, during the current sensing phase, adjust the first voltage source V... DD The two output terminals of the cross-coupling unit 20 are connected to provide a bias voltage to the cross-coupling unit 20; and, during the voltage sensing phase, the first voltage source V is connected to the cross-coupling unit 20. DD Disconnected from the two outputs of the cross-coupled unit 20.

[0039] The active load unit 30 is configured to, in response to the readout control signal SAEN, at least during the current sensing phase and the voltage sensing phase, supply the second voltage source V SS The two input terminals of the cross-coupling unit 20 are connected; wherein, during the current sensing phase, the active load unit 30 has a first impedance; during the voltage sensing phase, the active load unit 30 has a second impedance; the first impedance is greater than the second impedance.

[0040] Cross-coupling unit 20 is configured to acquire input signal I cell and reference signal I ref During the current sensing phase, at least in the first voltage source V DD Second voltage source V SS Under the action of the input signal I cell and reference signal I ref The difference is initially amplified; and, during the voltage sensing phase, at least in the second voltage source V SS Under the action of the input signal I cell and reference signal I ref The difference is further amplified, thereby outputting the first sensing voltage V. SA Second sensing voltage V SAB .

[0041] It should be noted that the sensing amplifier circuit is used to amplify the signal difference between the coupled bit lines during the sensing phase; wherein, the sensing phase includes at least a current sensing phase and a voltage sensing phase.

[0042] refer to Figure 7 The sensing phase of the data access operation can be divided into three phases: equalization (EQ), current sensing, and voltage sensing. First, in the equalization phase, the voltages at the two output terminals of the cross-coupled unit 20 are brought to equality, that is, V... SA and V SAB There is no difference between them, thus avoiding the residual voltage on the two output terminals from affecting the sensing; among them, during the equalization phase, V SA and V SAB The voltage value is located between the first voltage source and the second voltage source, that is, V SA and V SAB The voltage value is less than the power supply terminal V DD And greater than the ground terminal V SS Furthermore, during the current sensing stage, the input signal I... cell and reference signal I ref The difference is initially amplified, thus, the first sensing voltage V SA Second sensing voltage V SAB A preliminary differential signal is formed, V SA and V SAB The difference between them begins to be amplified. Furthermore, during the voltage sensing phase, the cross-coupling unit 20 modulates the input signal I... cell and reference signal I ref The difference is further amplified, thereby increasing the first sensing voltage V. SA Second sensing voltage V SABFurther, a differential signal, V, is formed. SA and V SAB The difference between them is further amplified.

[0043] When the accessed data is "1", the input signal I cell Compared to the reference signal I ref If it is larger, then, during the voltage sensing phase, the first sensed voltage V SA Pulled up to near the power supply terminal V DD The second sensing voltage V SAB Pulled down to near ground terminal V SS Correspondingly, when the accessed data is "0", the input signal I... cell Compared to the reference signal I ref If it is smaller, then, in the voltage sensing stage, the first sensed voltage V SA Pulled down to near ground terminal V SS The second sensing voltage V SAB Pulled up to near the power supply terminal V DD .

[0044] In this embodiment of the disclosure, reference is made to Figure 1 The cross-coupling unit 20 is provided with cross-coupled transistor pairs (i.e., two corresponding transistors), thereby enabling the input signal I to be coupled. cell and reference signal I ref The difference is amplified. The bias unit 10 can then amplify the first voltage source V. DD The cross-coupling unit 20 is connected, and a bias voltage is provided to the cross-coupling unit 20 so that the transistor in the cross-coupling unit 20 operates in the amplification state.

[0045] It should also be noted that the reference Figure 1 During the current sensing and voltage sensing phases, the degree of matching between the transistor pairs in the cross-coupling unit 20 and the bias unit 10 directly affects the first sensed voltage V. SA Second sensing voltage V SAB If the transistor pairs in the cross-coupling unit 20 and the bias unit 10 are mismatched, that is, if there is a parameter difference between the two transistors, it will cause the first sensed voltage V to be lost. SA Second sensing voltage V SAB This could affect the output of an incorrect first sensing voltage V. SA Second sensing voltage V SAB This caused a data access error.

[0046] However, in actual manufacturing, it is difficult to manufacture two transistors with exactly the same parameters. In other words, there will always be some parameter differences between the two transistors in a transistor pair, and mismatch in the transistor pair will always exist to some extent.

[0047] In this embodiment of the disclosure, reference is made to Figure 1 The active load unit 30 serves as the load for the sensing amplifier circuit, reducing the impact of transistor pair mismatch. Specifically, the active load unit 30 can adjust its impedance in response to the readout control signal SAEN during both the current sensing and voltage sensing phases. In other words, the impedance of the active load unit 30 is not fixed during the operation of the sensing amplifier circuit, but can be adjusted as needed.

[0048] Understandably, during the current sensing phase, the bias unit 10 will bias the first voltage source V... DD The two output terminals of the cross-coupling unit 20 are connected, and at the same time, the active load unit 30 connects the second voltage source V. SS Connecting to the two input terminals of the cross-coupling unit 20, so that the cross-coupling unit 20 at least in the first voltage source V DD Second voltage source V SS Under the action of the input signal I cell and reference signal I ref The difference is initially amplified. During the voltage sensing stage, the bias unit 10 amplifies the first voltage source V. DD The two output terminals of the cross-coupling unit 20 are disconnected, and at the same time, the active load unit 30 connects the second voltage source V. SS Connecting to the two input terminals of the cross-coupling unit 20, thus, the cross-coupling unit 20 is at least connected to the second voltage source V. SS Under the action of the input signal I cell and reference signal I ref The difference is further amplified. In the current sensing stage and the voltage sensing stage, the active load unit 30 can adjust the impedance as needed, thereby improving the performance of the sensing amplifier circuit and increasing the sensing rate and accuracy.

[0049] On the one hand, the active load unit 30 can have a large first impedance during the current sensing stage; thus, compared with the first impedance of the active load unit 30, the impedance difference between the cross-coupling unit 20 and the bias unit 10 is too small to be ignored; thereby, the adverse effects caused by the mismatch of transistor pairs in the cross-coupling unit 20 and the bias unit 10 are reduced, ensuring the accuracy of sensing and avoiding data access errors.

[0050] On the other hand, the active load unit 30 can have a smaller second impedance during the voltage sensing stage; this reduces the voltage division of the active load unit 30 during the voltage sensing stage, thereby increasing the voltage division of the cross-coupling unit 20; thus, the amplification effect of the cross-coupling unit 20 on the voltage difference is accelerated, and the sensing rate is improved.

[0051] In some embodiments of this disclosure, such as Figure 2 As shown, the sensing amplifier circuit also includes an isolation unit 40. The isolation unit 40 is coupled between the two input terminals of the cross-coupling unit 20 and the corresponding two bit lines, and is configured to control the input signal I. cell and reference signal I ref Input to cross-coupled unit 20.

[0052] In this embodiment of the disclosure, the isolation unit 40 is configured to turn on the cross-coupling unit 20 and the corresponding two bit lines during the equalization phase and the current sensing phase, thereby turning on the input signal I. cell and reference signal I ref Input is sent to cross-coupling unit 20; and, during the voltage sensing phase, cross-coupling unit 20 and the corresponding two bit lines are disconnected.

[0053] In this embodiment of the disclosure, the input signal I cell It is transmitted to the coupling cross-coupled unit 20 via the bit line BL, while the reference signal I ref The signal is transmitted to the cross-coupling unit 20 via the reference bit line BLB. During the equalization and current sensing phases, the isolation unit 40 is activated, allowing the bit line BL and the reference bit line BLB to be connected to the cross-coupling unit 20 respectively, thereby enabling the input signal I... cell and reference signal I ref The input is sent to the cross-coupling unit 20. Additionally, during the voltage sensing phase, the isolation unit 40 is turned off, isolating the bit line BL and the reference bit line BLB from the cross-coupling unit 20, thereby preventing the bit line BL and the reference bit line BLB from affecting voltage sensing.

[0054] It should be noted that parasitic capacitance exists in the memory circuit. Since bit line BL and reference bit line BLB are connected to cross-coupling unit 20, the parasitic capacitance is also connected to cross-coupling unit 20. During the voltage sensing stage, the input signal I... cell and reference signal I ref The difference between them is further amplified; that is, during the voltage sensing stage, the input signal I... cell and reference signal I refIn this process, the higher voltage is further increased to its maximum value, and the lower voltage is further decreased to its minimum value; thus, a large voltage difference is formed with the original voltage on the parasitic capacitor, so that if the parasitic capacitor is connected to the cross-coupling unit 20, the parasitic capacitor will be charged.

[0055] It is understood that, in this embodiment of the disclosure, an isolation unit 40 is provided to control the input signal I. cell and reference signal I ref The input is sent to the cross-coupling unit 20, which controls the connection and isolation of the control bit line BL and the reference bit line BLB with the cross-coupling unit 20. On one hand, during the equalization and current sensing phases, the isolation unit 40 is activated, and the bit line BL and the reference bit line BLB are connected to the cross-coupling unit 20 respectively. This ensures the input signal I... cell and reference signal I ref On the one hand, during the voltage sensing phase, the isolation unit 40 is turned off, and the bit line BL and the reference bit line BLB are isolated from the cross-coupling unit 20. This avoids charging the parasitic capacitance and thus avoids additional power consumption.

[0056] In some embodiments of this disclosure, such as Figure 3 As shown, the sensing amplifier circuit further includes an equalization unit 50. The equalization unit 50, coupled between the two outputs of the cross-coupled unit 20, is configured to equalize the first sensed voltage V during the equalization phase. SA Second sensing voltage V SAB Pull until they are equal.

[0057] refer to Figure 3 During the equalization phase, the equalization unit 50 is activated, thereby directly connecting the two output terminals of the cross-coupling unit 20 and converting the first sensed voltage V... SA Second sensing voltage V SAB By equalizing the voltages at both output terminals, residual voltage on both terminals can be prevented from affecting the sensing. Accordingly, during the current sensing and voltage sensing phases, the equalization unit 50 is turned off to prevent the two output terminals of the cross-coupling unit 20 from being directly connected, thus ensuring the sensing process.

[0058] In some embodiments of this disclosure, reference is made to Figure 4 The cross-coupling unit 20 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The first transistor M1 and the second transistor M2 are NMOS transistors, while the third transistor M3 and the fourth transistor M4 are PMOS transistors.

[0059] In this embodiment of the disclosure, reference is made to Figure 4The source of the first transistor M1, the gate of the second transistor M2, the gate of the third transistor M3, and the source of the fourth transistor M4 are connected and connected to the first output terminal of the cross-coupling unit 20 (i.e., outputting the first sensing voltage V). SA One end of the first transistor M1, the source of the second transistor M2, the source of the third transistor M3, and the gate of the fourth transistor M4 are connected and connected to the second output terminal of the cross-coupling unit 20 (i.e., outputting the second sensing voltage V). SAB One end of the first transistor M1 is connected to the drain of the cross-coupled unit 20 (i.e., to receive the input signal I). cell One end of the second transistor M2 is connected to the second input terminal of the cross-coupled unit 20 (i.e., the terminal receiving the reference signal I). ref (one end).

[0060] In this embodiment of the disclosure, reference is made to Figure 4 The first transistor M1 and the second transistor M2 form a transistor pair, and the parameters of the first transistor M1 and the second transistor M2 should be matched. Similarly, the third transistor M3 and the fourth transistor M4 also form a transistor pair, and the parameters of the third transistor M3 and the fourth transistor M4 should be matched. The first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are cross-coupled, thereby enabling the input signal I at the input terminal to be... cell and reference signal I ref The difference is amplified, and the first sensing voltage V is output. SA Second sensing voltage V SAB .

[0061] In some embodiments of this disclosure, reference is made to Figure 4 The bias unit 10 includes: an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14.

[0062] Continue to refer to Figure 4 The source of the eleventh transistor M11 is connected to the drain of the third transistor M3 and the drain of the fourth transistor M4. The drain of the eleventh transistor M11 is connected to the first voltage source V. DD The gate of the eleventh transistor M11 receives the inverted signal V of the first readout control signal. SAENB .

[0063] Continue to refer to Figure 4 The source of the twelfth transistor M12 is connected to the drain of the thirteenth transistor M13 and the drain of the fourteenth transistor M14. The drain of the twelfth transistor M12 is connected to the first voltage source V. DD The gate of the twelfth transistor M12 receives the inverted signal C of the second readout control signal. SAENB .

[0064] Continue to refer to Figure 4 The source of the thirteenth transistor M13 is connected to the source of the first transistor M1. The source of the fourteenth transistor M14 is connected to the source of the second transistor M2. The gates of both the thirteenth transistor M13 and the fourteenth transistor M14 receive the first readout control signal V. SAEN .

[0065] Combination Figure 4 and Figure 7 Before the current sensing phase begins, the inverted signal C of the second readout control signal... SAENB When the signal transitions to a low level, the twelfth transistor M12 is turned on, and simultaneously, the first readout control signal V... SAEN When the voltage is low, transistors thirteenth (M13) and fourteenth (M14) are turned on; thus, the first voltage source V... DD The cross-coupled unit 20 is connected via the twelfth transistor M12, the thirteenth transistor M13 and the fourteenth transistor M14 to provide a bias voltage for the cross-coupled unit 20.

[0066] Continue to combine Figure 4 and Figure 7 During the voltage sensing phase, the first readout control signal V SAEN When the voltage level is high, the eleventh transistor M11 is turned on; thus, the first voltage source V... DD The cross-coupled unit 20 is connected via the eleventh transistor M11 to provide a bias voltage to the cross-coupled unit 20.

[0067] In some embodiments of this disclosure, reference is made to Figure 4 The active load unit 30 includes: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.

[0068] Continue to refer to Figure 4 The fifth transistor M5 and the seventh transistor M7 are connected in parallel. The sources of both transistors M5 and M7 are connected to the first input terminal of the cross-coupling unit 20, meaning they are both connected to the drain of the first transistor M1. The drains of both transistors M5 and M7 are connected to the second voltage source V. SS .

[0069] Continue to refer to Figure 4The sixth transistor M6 and the eighth transistor M8 are connected in parallel. The sources of both transistors M6 and M8 are connected to the second input terminal of the cross-coupling unit 20; that is, the sources of both transistors M6 and M8 are connected to the drain of the second transistor M2. The drains of both transistors M6 and M8 are connected to the second voltage source V. SS .

[0070] In this embodiment of the disclosure, reference is made to Figure 4 The impedance of the active load unit 30 includes: the first input terminal of the cross-coupling unit 20 (i.e., the terminal receiving the input signal I). cell One end) is connected to the second voltage source V SS The impedance between them, and the second input terminal of the cross-coupling unit 20 (i.e., receiving the reference signal I) ref One end) is connected to the second voltage source V SS The impedance between them. The fifth transistor M5 and the sixth transistor M6 form a transistor pair, and their parameters should be matched. Similarly, the seventh transistor M7 and the eighth transistor M8 also form a transistor pair, and their parameters should be matched.

[0071] In this embodiment of the disclosure, combined with Figure 4 and Figure 7 The gates of both the seventh transistor M7 and the eighth transistor M8 receive the first readout control signal V. SAEN The gates of the fifth transistor M5 and the sixth transistor M6 are connected to the first voltage source V. DD During the current sensing phase, the seventh transistor M7 and the eighth transistor M8 are in the off state, while only the fifth transistor M5 and the sixth transistor M6 are in the on state, resulting in a high first impedance for the active load unit 30. During the voltage sensing phase, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all in the on state, resulting in a low second impedance for the active load unit 30.

[0072] In some embodiments of this disclosure, reference is made to Figure 4 The impedance of the seventh transistor M7 is less than that of the fifth transistor M5, and the impedance of the eighth transistor M8 is less than that of the sixth transistor M6.

[0073] It should be noted that, on the one hand, considering the transistor pair mismatch in the cross-coupling unit 20 and the bias unit 10, in order to improve the accuracy of the current sensing stage, the equivalent impedance of the fifth transistor M5 and the sixth transistor M6 should be very large (e.g., tens of kΩ or more). Thus, compared to the first impedance of the active load unit 30, the impedance difference between the cross-coupling unit 20 and the bias unit 10 is so small that it can be ignored; thereby, the adverse effects of the transistor pair mismatch in the cross-coupling unit 20 and the bias unit 10 are reduced, ensuring the accuracy of the sensing and avoiding data access errors.

[0074] On the other hand, during the voltage sensing phase, if the impedance of the active load unit 30 is too high, it will lead to an excessive voltage drop, that is, the voltage V at the first input terminal of the cross-coupling unit 20 will drop. P and the voltage V at the second input terminal of the cross-coupling unit 20 Q If the voltage is too high, it will make it difficult for the third transistor M3 and the fourth transistor M4 to turn on, thus reducing the sensing rate. Therefore, the equivalent impedance of the seventh transistor M7 and the eighth transistor M8 is smaller, much smaller than the equivalent impedance of the fifth transistor M5 and the sixth transistor M6. This can significantly reduce the impedance of the active load unit 30 during the voltage sensing stage, thereby reducing the voltage V. P and V Q This reduces the gate voltage of the third transistor M3 and the fourth transistor M4, forming a cross-coupled positive feedback, and accelerating the sensing rate.

[0075] In some embodiments of this disclosure, reference is made to Figure 5 The isolation unit 40 includes: a ninth transistor M9 and a tenth transistor M10.

[0076] Continue to refer to Figure 5 The source of the ninth transistor M9 receives the input signal I. cell The drain of the ninth transistor M9 is connected to the first input terminal of the cross-coupling unit 20, that is, the drain of the ninth transistor M9 is connected to the drain of the first transistor M1. The source of the tenth transistor M10 receives the reference signal I. ref The drain of the tenth transistor M10 is connected to the second input terminal of the cross-coupled unit 20, that is, the drain of the tenth transistor M10 is connected to the drain of the second transistor M2.

[0077] Combination Figure 5 and Figure 7 The gates of both the ninth transistor M9 and the tenth transistor M10 receive the inverted signal V of the first readout control signal. SAENB During the equalization and current sensing phases, the first readout control signal V... SAENWhen the signal is low, the gate of the ninth transistor M9 and the tenth transistor M10 are turned on, and the input signal I... cell and reference signal I ref It can be transmitted to the cross-coupled unit 20.

[0078] During the voltage sensing phase, the first readout control signal V SAEN When the signal is high, the gate of the ninth transistor M9 and the tenth transistor M10 are turned off, which isolates the bit line BL and the reference bit line BLB from the cross-coupled unit 20, avoiding interference with the parasitic capacitance C. BL and C BLB Charging, thus avoiding additional power consumption.

[0079] In some embodiments of this disclosure, reference is made to Figure 5 The equalization unit 50 includes: the fifteenth transistor M15 and the sixteenth transistor M16.

[0080] Continue to refer to Figure 5 The source of the fifteenth transistor M15 and the source of the sixteenth transistor M16 are both connected to the first output terminal of the cross-coupled unit 20 (i.e., outputting the first sensing voltage V). SA One end). The drain of the fifteenth transistor M15 and the drain of the sixteenth transistor M16 are both connected to the second output terminal of the cross-coupled unit 20 (i.e., outputting the second sensing voltage V). SAB (One end). The gate of the fifteenth transistor M15 receives the equalization signal P. EQ The gate of the sixteenth transistor M16 receives the equalization signal P. EQB Among them, the equalization signal P EQ and P EQB They are opposites.

[0081] In this embodiment of the disclosure, combined with Figure 5 and Figure 7 During the equilibrium phase, the equilibrium signal P EQ When the voltage is high, transistors M15 and M16 are turned on, directly connecting the two outputs of cross-coupling unit 20 and transmitting the first sensed voltage V. SA Second sensing voltage V SAB The voltage is pulled to be equal to avoid residual voltage on both output terminals affecting the sensing. Correspondingly, the equalization signal P is adjusted during both the current sensing and voltage sensing phases. EQ When the signal is low, the fifteenth transistor M15 and the sixteenth transistor M16 are turned off, thereby preventing the two output terminals of the cross-coupling unit 20 from being directly connected and ensuring that sensing can proceed.

[0082] The source and drain terminals of the above transistors are not specifically defined and can be interchanged according to actual needs in practical applications.

[0083] It should be noted that, Figure 6 This is a schematic diagram of another optional structure of the sensing amplifier circuit provided in the embodiments of this disclosure. Figure 6 The waveforms of each signal can be referenced. Figure 7 .Will Figure 5 The transformation type of transistors M1 to M14 can be obtained Figure 6 The circuit diagram shown is, that is, Figure 5 The PMOS transformation in Figure 6 NMOS in, and Figure 5 The NMOS in the circuit is converted to PMOS.

[0084] Correspondingly, for transistors M1 to M14 after the type conversion, their connected voltage sources and control signals also need to be converted accordingly; for example, Figure 5 power supply terminal V DD Transform into Figure 6 grounding terminal V SS , Figure 5 grounding terminal V SS Transform into Figure 6 power supply terminal V DD , Figure 5 The signal V in SAEN Transform into Figure 6 The signal V in SAENB , Figure 5 The signal V in SAENB Transform into Figure 6 The signal V in SAEN , Figure 5 Signal C in SAENB Transform into Figure 6 Signal C in SAEN .

[0085] Figure 6 The illustrated sensing amplifier circuit can achieve and Figure 5 The function of the sensing amplifier circuit shown is similar and will not be described again here.

[0086] This disclosure also provides a memory, such as... Figure 8 As shown, the memory 70 includes a plurality of sensing amplifier circuits 60, wherein the sensing amplifier circuits 60 include the technical features described in the foregoing embodiments.

[0087] In some embodiments of this disclosure, reference is made to Figure 8The memory 70 may include DRAM. The memory 70 has multiple row word lines WL and multiple column bit lines BL, as well as memory cells coupled between the word lines WL and the bit lines BL. Each sensing amplifier circuit is coupled to two corresponding bit lines, wherein the two bit lines can be mutually reference bit lines. The memory cell can be a 2T0C structure; that is, the memory cell in the memory 70 includes two transistors but not capacitors.

[0088] This disclosure also provides a data access method, the data access method including... Figure 9 Steps S101 to S102 shown will be explained in conjunction with each step.

[0089] S101. During the current sensing stage, the cross-coupling unit acquires the input signal and the reference signal, and under the action of at least the first voltage source and the second voltage source, initially amplifies the difference between the input signal and the reference signal; wherein, during the current sensing stage, the active load unit coupled to the cross-coupling unit has a first impedance.

[0090] S102. During the voltage sensing stage, at least under the action of the second voltage source, the cross-coupling unit further amplifies the difference between the input signal and the reference signal, and outputs the first sensing voltage and the second sensing voltage; wherein, during the voltage sensing stage, the active load unit has a second impedance; the first impedance is greater than the second impedance.

[0091] In this embodiment of the disclosure, combined with Figure 5 and Figure 7 During the equilibrium phase, the equilibrium signal P EQ When the voltage is high, transistors M15 and M16 are turned on, thus directly connecting the two outputs of cross-coupled unit 20, and the first sensed voltage V... SA Second sensing voltage V SAB Pull them to equal values ​​to avoid residual voltage on both output terminals affecting the sensing. During the equalization phase, V... SA and V SAB The voltage value is located between the first voltage source and the second voltage source, that is, V SA and V SAB The voltage value is less than the power supply terminal V DD And greater than the ground terminal V SS .

[0092] Continue to combine Figure 5 and Figure 7 Before the current sensing phase begins, the inverted signal C of the second readout control signal... SAENB When the signal transitions to a low level, the twelfth transistor M12 is turned on, and simultaneously, the first readout control signal V... SAENWhen the voltage is low, transistors thirteenth (M13) and fourteenth (M14) are turned on; thus, the first voltage source V... DD The cross-coupling unit 20 is connected via the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14, providing a bias voltage to the cross-coupling unit 20. Thus, during the current sensing phase, the cross-coupling unit 20 can sense the input signal I... cell and reference signal I ref The difference was initially amplified.

[0093] Meanwhile, during the current sensing phase, the seventh transistor M7 and the eighth transistor M8 are in the off state, while only the fifth transistor M5 and the sixth transistor M6 are in the on state, resulting in a higher first impedance for the active load unit 30. Thus, compared to the first impedance of the active load unit 30, the impedance difference between the cross-coupling unit 20 and the bias unit 10 is negligible due to its small size; consequently, the adverse effects of transistor pair mismatch in the cross-coupling unit 20 and the bias unit 10 are reduced, ensuring sensing accuracy and preventing data access errors.

[0094] Continue to combine Figure 5 and Figure 7 During the voltage sensing phase, the first readout control signal V SAEN When the voltage level is high, the eleventh transistor M11 is turned on; thus, the first voltage source V... DD The eleventh transistor M11 is connected to the cross-coupling unit 20, providing a bias voltage to the cross-coupling unit 20. Thus, during the voltage sensing phase, the cross-coupling unit 20 can convert the input signal I at the input terminal... cell and reference signal I ref The difference is further amplified, and the first sensing voltage V is output. SA Second sensing voltage V SAB .

[0095] When the accessed data is "1", the input signal I cell Compared to the reference signal I ref If it is larger, then, during the voltage sensing phase, the first sensed voltage V SA Pulled up to near the power supply terminal V DD The second sensing voltage V SAB Pulled down to near ground terminal V SS Correspondingly, when the accessed data is "0", the input signal I... cell Compared to the reference signal I ref If it is smaller, then, in the voltage sensing stage, the first sensed voltage V SA Pulled down to near ground terminal V SS The second sensing voltage V SAB Pulled up to near the power supply terminal VDD .

[0096] Simultaneously, during the voltage sensing phase, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all in the ON state, and the impedance of the active load unit 30 has a lower second impedance. This significantly reduces the impedance of the active load unit 30 during the voltage sensing phase, thereby reducing the voltage V. P and V Q This reduces the gate voltage of the third transistor M3 and the fourth transistor M4, forming a cross-coupled positive feedback, and accelerating the sensing rate.

[0097] In some embodiments of this disclosure, the data access method further includes steps S201 to S203, which will be described in conjunction with each step.

[0098] S201. During the equalization and current sensing phases, the isolation unit connects the cross-coupling unit and the corresponding two bit lines, and inputs the input signal and reference signal to the cross-coupling unit.

[0099] S202. During the voltage sensing phase, the isolation unit disconnects the cross-coupling unit and the corresponding two bit lines.

[0100] S203. During the equalization phase, the equalization unit equalizes the first sensing voltage and the second sensing voltage.

[0101] In this embodiment of the disclosure, combined with Figure 5 and Figure 7 During the equalization and current sensing phases, the first readout control signal V SAEN When the signal is low, the gate of the ninth transistor M9 and the tenth transistor M10 are turned on, and the input signal I... cell and reference signal I ref It can be transmitted to the cross-coupled unit 20.

[0102] Continue to combine Figure 5 and Figure 7 During the voltage sensing phase, the first readout control signal V SAEN When the signal is high, the gate of the ninth transistor M9 and the tenth transistor M10 are turned off, which isolates the bit line BL and the reference bit line BLB from the cross-coupled unit 20, avoiding interference with the parasitic capacitance C. BL and C BLB Charging is achieved, thus avoiding additional power consumption. Furthermore, during the equalization phase, the fifteenth transistor M15 and the sixteenth transistor M16 are turned on, directly connecting the two outputs of the cross-coupled unit 20, and transmitting the first sensed voltage V. SA Second sensing voltage V SAB Pull them to the same value to avoid residual voltage on the two output terminals affecting the sensing.

[0103] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0104] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0105] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A sense amplifier circuit for amplifying a signal difference between bit lines coupled thereto during a sense phase; characterized by, The sensing stage comprises at least a current sensing stage and a voltage sensing stage; The sensing amplifier circuit comprises a cross-coupled unit, a bias unit and an active load unit; Two inputs of the cross-coupled unit are coupled to two corresponding bit lines respectively, for obtaining an input signal and a reference signal; two outputs of the cross-coupled unit are used for outputting a first sensing voltage and a second sensing voltage, wherein the first sensing voltage corresponds to the input signal, and the second sensing voltage corresponds to the reference signal; The bias unit is coupled between a first voltage source and the two outputs of the cross-coupled unit; a first end of the bias unit is connected to the first voltage source, a second end of the bias unit is connected to a first output of the cross-coupled unit, and a third end of the bias unit is connected to a second output of the cross-coupled unit; The active load unit is coupled between a second voltage source and the two inputs of the cross-coupled unit; a first end of the active load unit is connected to the second voltage source, a second end of the active load unit is connected to a first input of the cross-coupled unit, and a third end of the active load unit is connected to a second input of the cross-coupled unit; The bias unit is configured to turn on the first voltage source and the two outputs of the cross-coupled unit in the current sensing stage, and turn off the first voltage source and the two outputs of the cross-coupled unit in the voltage sensing stage; The active load unit is configured to connect the second voltage source to the two inputs of the cross-coupled unit at least in the current sensing stage and the voltage sensing stage; the active load unit has a first impedance in the current sensing stage, and has a second impedance in the voltage sensing stage; the first impedance is greater than the second impedance; The cross-coupled unit is configured to preliminarily amplify a difference between the input signal and the reference signal at least under the action of the first voltage source and the second voltage source in the current sensing stage, and further amplify the difference between the input signal and the reference signal at least under the action of the second voltage source in the voltage sensing stage.

2. The sense amplifier circuit of claim 1, wherein, The sensing amplifier circuit further comprises an isolation unit; The isolation unit is coupled between the two inputs of the cross-coupled unit and the two corresponding bit lines; The isolation unit is configured to turn on the cross-coupled unit and the two corresponding bit lines to input the input signal and the reference signal into the cross-coupled unit in the equalization stage and the current sensing stage, and turn off the cross-coupled unit and the two corresponding bit lines in the voltage sensing stage.

3. The sense amplifier circuit of claim 1, wherein, The sensing amplifier circuit further comprises: An equalization unit coupled between the two outputs of the cross-coupled unit, and configured to pull the first sensing voltage and the second sensing voltage to be equal in the equalization stage.

4. The sense amplifier circuit of any one of claims 1 to 3, wherein, The cross-coupled unit comprises a first transistor, a second transistor, a third transistor and a fourth transistor; The source of the first transistor, the gate of the second transistor, the gate of the third transistor and the source of the fourth transistor are connected and connected to the first output end of the cross-coupled unit; The gate of the first transistor, the source of the second transistor, the source of the third transistor and the gate of the fourth transistor are connected and connected to the second output end of the cross-coupled unit; The drain of the first transistor is connected to the first input end of the cross-coupled unit; The drain of the second transistor is connected to the second input end of the cross-coupled unit.

5. The sense amplifier circuit of any one of claims 1 to 3, wherein, The active load unit comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The fifth transistor and the seventh transistor are connected in parallel; the source of the fifth transistor and the source of the seventh transistor are both connected to the first input end of the cross-coupled unit; the drain of the fifth transistor and the drain of the seventh transistor are both connected to a second voltage source; The sixth transistor and the eighth transistor are connected in parallel; the source of the sixth transistor and the source of the eighth transistor are both connected to the second input end of the cross-coupled unit; the drain of the sixth transistor and the drain of the eighth transistor are both connected to a second voltage source; The gate of the seventh transistor and the gate of the eighth transistor both receive a first read control signal.

6. The sensing amplifier circuit according to claim 5, wherein, The impedance of the seventh transistor is smaller than the impedance of the fifth transistor; the impedance of the eighth transistor is smaller than the impedance of the sixth transistor.

7. The sense amplifier circuit of claim 2, wherein, The isolation unit comprises a ninth transistor and a tenth transistor; The source of the ninth transistor receives the input signal, and the drain of the ninth transistor is connected to the first input end of the cross-coupled unit; The source of the tenth transistor receives the reference signal, and the drain of the tenth transistor is connected to the second input end of the cross-coupled unit; The gate of the ninth transistor and the gate of the tenth transistor both receive an inverted signal of the first read control signal.

8. The sense amplifier circuit of claim 4, wherein, The bias unit comprises an eleventh transistor, a twelfth transistor, a thirteenth transistor and a fourteenth transistor; The source of the eleventh transistor is connected to the drain of the third transistor and the drain of the fourth transistor; the drain of the eleventh transistor is connected to a first voltage source; the gate of the eleventh transistor receives an inverted signal of the first read control signal; The source of the twelfth transistor is connected to the drain of the thirteenth transistor and the drain of the fourteenth transistor; the drain of the twelfth transistor is connected to a first voltage source; the gate of the twelfth transistor receives an inverted signal of the second read control signal; The source of the thirteenth transistor is connected to the source of the first transistor; the source of the fourteenth transistor is connected to the source of the second transistor; the gate of the thirteenth transistor and the gate of the fourteenth transistor both receive the first read control signal.

9. The sense amplifier circuit of claim 3, wherein, The equalization unit comprises a fifteenth transistor and a sixteenth transistor; The source of the fifteenth transistor and the source of the sixteenth transistor are both connected to a first output end of the cross-coupled unit; The drain of the fifteenth transistor and the drain of the sixteenth transistor are both connected to a second output end of the cross-coupled unit; The gate of the fifteenth transistor and the gate of the sixteenth transistor receive an equalization signal.

10. A memory, comprising: The memory comprises a plurality of sensing amplification circuits according to any one of claims 1 to 9; In the memory, a plurality of word lines and a plurality of bit lines are arranged, and a storage unit is coupled between the word lines and the bit lines; each sensing amplification circuit is coupled to a corresponding two bit lines.

11. An electronic device, comprising: The electronic device comprises the memory according to claim 10.

12. A data access method, characterized by, The data access method is applied to the sensing amplification circuit according to any one of claims 1 to 9, and the data access method comprises: In the current sensing stage, the cross-coupled unit acquires an input signal and a reference signal, and preliminarily amplifies a difference between the input signal and the reference signal at least under the action of a first voltage source and a second voltage source; wherein, in the current sensing stage, the active load unit has a first impedance; the active load unit is coupled between the second voltage source and two input ends of the cross-coupled unit; In the voltage sensing stage, the cross-coupled unit further amplifies the difference between the input signal and the reference signal at least under the action of the second voltage source, and outputs a first sensing voltage and a second sensing voltage; wherein, in the voltage sensing stage, the active load unit has a second impedance; the first impedance is greater than the second impedance.

13. The data access method of claim 12, wherein, The data access method further comprises: In the equalization stage and the current sensing stage, the isolation unit turns on the cross-coupled unit and the corresponding two bit lines, and inputs the input signal and the reference signal into the cross-coupled unit; In the voltage sensing stage, the isolation unit disconnects the cross-coupled unit and the corresponding two bit lines; In the equalization stage, the equalization unit pulls the first sensing voltage and the second sensing voltage to be equal.

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