Frequency-locked loop circuit device, control method, apparatus, medium and product thereof

Abstract

The embodiment of the present application provides a frequency locking circuit device, which can be applied to the technical field of integrated circuit chip control and is particularly applied to the resonance frequency locking of a target load. The frequency locking circuit device comprises an integral phase shift module and a driving control module. The integral phase shift module is used for generating a current integral phase shift signal by performing integral phase shift on a current working electrical signal of one end of the target load; wherein the current integral phase shift signal realizes 360° phase shift relative to the current working electrical signal; the driving control module is connected with the output end of the integral phase shift module and is used for updating the current working electrical signal of the target load according to the current integral phase shift signal to form a self-oscillation loop with a gain greater than or equal to 1, so as to realize resonance frequency locking. The embodiment of the present application further provides a control method, equipment, storage medium and program product of the frequency locking circuit device.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit chip control technology, specifically to the field of chip driver circuit technology, and more specifically to a frequency locking circuit device and its control method, equipment, medium and product. Background Technology

[0002] In various portable electronic products (such as mobile phones and tablets) and high-precision technology chips (such as lithography technology and artificial intelligence technology), the heat dissipation capacity of the core control chip must be considered to maintain optimal performance. For the heat dissipation of such integrated circuit chips, two methods are typically employed: active and passive. Active cooling is generally significantly more effective than passive cooling. Active cooling often relies on chip-level micro-piezoelectric ceramic air pumps and micro-cooling fans. For example, micro-piezoelectric ceramic air pumps primarily utilize the piezoelectric drive principle, using the high-frequency vibration of an electrically controlled ceramic plate to drive airflow within a cavity, thereby achieving precise microfluidic delivery and heat dissipation for the corresponding chip. This method offers advantages such as miniaturization, low power consumption, low noise, low vibration, fast response, and high reliability.

[0003] Existing active cooling methods typically employ miniature air pumps or miniature fans. To maintain optimal operating performance, their operating frequency must be consistently maintained at the resonant point (i.e., the intrinsic resonant frequency), a process known as frequency locking. Traditional frequency locking schemes primarily rely on fixed-frequency open-loop pulse width modulation (PWM) or digital sampling of the input current to achieve the resonant point (intrinsic resonant frequency) at maximum output power. However, these driving methods lack an adaptive frequency locking mechanism, resulting in an inability to dynamically adjust the frequency. Furthermore, digital sampling leads to higher system power consumption and increased circuit costs. Even existing feedback control methods based on phase-locked loops (PLLs) suffer from relatively complex control loops, high costs, poor stability, slow response speeds, and large circuit sizes, making them difficult to widely adapt to the needs of small-scale, high-efficiency applications. Summary of the Invention

[0004] Addressing at least one of the technical problems of existing resonant frequency locking schemes used in piezoelectric ceramic air pumps and micro fans for high-precision chips, such as poor frequency locking capability, high energy loss, low overall efficiency, poor frequency locking stability, and high cost and large size due to circuit complexity, embodiments of the present invention propose a frequency locking circuit device and its control method, equipment, medium and product, thereby providing a stable and dynamically adjustable novel frequency locking architecture. This aims to ensure the locking of the resonant frequency by achieving a 360° phase shift of the voltage or current phase of the target load (such as piezoelectric ceramic air pumps, micro fans, etc., based on RLC circuit models or RLC-like circuit models), thereby achieving stable maintenance of the maximum power of the target load and compensating for the gap in chip heat dissipation capacity caused by the inability of existing process technology to reach top-tier levels.

[0005] Another aspect of the present invention provides a frequency-locking circuit device for locking the resonant frequency of a target load. The frequency-locking circuit device includes an integral phase-shift module and a drive control module. The integral phase-shift module generates a current integral phase-shift signal by integrating and phase-shifting the current operating electrical signal at one end of the target load; wherein the current integral phase-shift signal is phase-shifted by 360° relative to the current operating electrical signal. The drive control module is connected to the output of the integral phase-shift module and updates the current operating electrical signal of the target load according to the current integral phase-shift signal, forming a self-oscillating loop with a gain greater than or equal to 1 to achieve resonant frequency locking.

[0006] According to one embodiment of the present invention, the frequency locking circuit device further includes a signal feedback unit and a first sensing unit. The signal feedback unit is connected in parallel with the target load and is used to provide feedback on the direction of the current operating electrical signal; the first sensing unit is connected in series with the target load and is used to detect the current operating electrical signal.

[0007] According to an embodiment of the present invention, the integral phase shift module includes a first integral unit and a second integral unit. The input terminal of the first integral unit is connected to both ends of the first sensing unit in a differential input form, and is used to perform a first integral phase shift on the current working electrical signal to generate a first integral phase shift signal; the input terminal of the second integral unit is connected to the output terminal of the first integral unit in a differential input form, and is used to perform a second integral phase shift on the first integral phase shift signal to generate a second integral phase shift signal.

[0008] According to one embodiment of the present invention, the integral phase shift module further includes a waveform conversion unit and a phase conversion unit. The input terminal of the waveform conversion unit is connected to the output terminal of the second integral unit in a differential input form, and is used to perform waveform conversion processing on the second integral phase shift signal to generate a waveform conversion signal; the input terminal of the phase conversion unit is connected to the output terminal of the waveform conversion unit, and is used to perform phase conversion processing on the waveform conversion signal to generate the current integral phase shift signal.

[0009] According to one embodiment of the present invention, the first integrating unit includes a first integrating amplifier, a first resistor, and a first capacitor. A first input terminal of the first integrating amplifier is connected to one end of a first sensing unit, and a second input terminal is connected to the other end of the first sensing unit; one end of the first resistor is connected to a first output terminal of the first integrating amplifier, and the other end is connected to a second output terminal of the first integrating amplifier; one end of the first capacitor is connected to the first output terminal of the first integrating amplifier, and the other end is connected to the second output terminal of the first integrating amplifier; wherein the first resistor and the first capacitor are connected in parallel.

[0010] According to one embodiment of the present invention, the second integrating unit includes a second integrating amplifier, a second resistor, and a second capacitor. The first input terminal of the second integrating amplifier is connected to the first output terminal of the first integrating unit, and its second input terminal is connected to the second output terminal of the first integrating unit. One end of the second resistor is connected to the first output terminal of the second integrating amplifier, and the other end is connected to the second output terminal of the second integrating amplifier. One end of the second capacitor is connected to the first output terminal of the second integrating amplifier, and the other end is connected to the second output terminal of the second integrating amplifier. The second resistor and the second capacitor are connected in parallel.

[0011] According to one embodiment of the present invention, the integral phase shift module further includes a signal processing unit. The input terminal of the signal processing unit is connected to the output terminal of the first integral unit, and is used to perform signal biasing and signal isolation processing on the first integral phase shift signal.

[0012] According to an embodiment of the present invention, the signal processing unit includes a signal isolator for performing signal isolation processing on the first integrated phase-shift signal. The signal isolator includes a third capacitor and a fourth capacitor. One end of the third capacitor is connected to the first output terminal of the first integrating unit, and the other end is connected to the first input terminal of the second integrating unit; one end of the fourth capacitor is connected to the second output terminal of the first integrating unit, and the other end is connected to the second input terminal of the second integrating unit.

[0013] According to an embodiment of the present invention, the signal processing unit includes a signal biaser for performing signal biasing processing on the first integral phase-shift signal. The signal biaser includes a third resistor and a fourth resistor. One end of the third resistor is connected to the first output terminal of the first integral unit and the first input terminal of the second integral unit; one end of the fourth resistor is connected to the second output terminal of the first integral unit and the second input terminal of the second integral unit, and the other end is connected to the other end of the third resistor and connected to a preset bias voltage.

[0014] According to an embodiment of the present invention, the drive control module includes a first inverting unit, a first driving unit, a second driving unit, and a full-bridge driving unit. The input terminal of the first inverting unit is connected to the output terminal of the phase conversion unit, and is used to invert the current integral phase shift signal to generate an inverted processing signal. The input terminal of the first driving unit is connected to the output terminal of the first inverting unit, and is used to generate a first driving signal and a second driving signal based on the inverted processing signal. The input terminal of the second driving unit is connected to the output terminal of the phase conversion unit, and is used to generate a third driving signal and a fourth driving signal based on the current integral phase shift signal. The input terminal of the full-bridge driving unit is correspondingly connected to the output terminals of the first driving unit and the second driving unit, and is used to control a preset input power supply connected to the full-bridge driving unit to update the current operating electrical signal applied to the target load based on the first driving signal, the second driving signal, the third driving signal, and the fourth driving signal.

[0015] According to one embodiment of the present invention, a first driving unit includes two inverters connected in parallel, and a second driving unit includes two inverters connected in parallel. According to one embodiment of the present invention, a full-bridge driving unit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate of the first transistor is connected to the first output terminal of the first driving unit, its source is connected to a preset input power supply, and its drain is connected to a first sensing unit, for controlling the conduction and disconnection of the first transistor according to a first driving signal; the gate of the second transistor is connected to the second output terminal of the first driving unit, its source is grounded, and its drain is connected to the drain of the first transistor, for controlling the conduction and disconnection of the second transistor according to a second driving signal; the gate of the third transistor is connected to the first output terminal of the second driving unit, its source is connected to a preset input power supply, and its drain is connected to a target load, for controlling the conduction and disconnection of the third transistor according to a third driving signal; the gate of the fourth transistor is connected to the second output terminal of the second driving unit, its source is grounded, and its drain is connected to the drain of the third transistor, for controlling the conduction and disconnection of the fourth transistor according to a fourth driving signal.

[0016] According to an embodiment of the present invention, the drive control module includes a second inverting unit, a fifth transistor, a sixth transistor, and a seventh transistor. The input terminal of the second inverting unit is connected to the output terminal of the phase conversion unit, and is used to invert the current integral phase shift signal to generate a fifth drive signal. The gate of the fifth transistor is connected to the output terminal of the second inverting unit, its source is grounded, and its drain is connected to the target load, used to control the conduction and disconnection of the fifth transistor according to the fifth drive signal. The gate of the sixth transistor is connected to the output terminal of the phase conversion unit, and its source is grounded, used to control the conduction and disconnection of the sixth transistor according to the current integral phase shift signal. The gate of the seventh transistor is connected to the drain of the sixth transistor, its source is connected to a preset input power supply and is used to connect to the gate of the seventh transistor, and its drain is connected to the target load. One end of the first sensing unit is connected to a reference input power supply, and the other end is connected to the target load.

[0017] According to one embodiment of the present invention, the drive control module further includes a fifth resistor and a sixth resistor. One end of the fifth resistor is connected to the source of the sixth transistor, and the other end is grounded; one end of the sixth resistor is connected to the gate of the seventh transistor and the drain of the sixth transistor, and the other end is connected to the source of the seventh transistor and a preset input power supply.

[0018] Another aspect of the present invention provides a control method for the above-described frequency-locking circuit device, applied to the resonant frequency locking of a target load. The frequency-locking circuit device includes an integral phase-shift module and a drive control module, used to form a self-oscillating loop with a gain greater than or equal to 1. The control method includes: generating a current integral phase-shift signal by integrally phase-shifting the current operating electrical signal at a first terminal of the target load; wherein the current integral phase-shift signal is phase-shifted by 360° relative to the current operating electrical signal; and updating the current operating electrical signal of the target load according to the current integral phase-shift signal to achieve resonant frequency locking.

[0019] Another aspect of the present invention provides an electronic device including one or more processors and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to perform the control method of the frequency locking circuit device described above.

[0020] Another aspect of the present invention provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the control method of the frequency locking circuit device described above.

[0021] Another aspect of the present invention provides a computer program product, including a computer program that, when executed by a processor, implements the control method of the frequency locking circuit device described above.

[0022] The frequency locking circuit device and control method provided in this invention can at least partially solve the technical problems of high energy loss, low overall efficiency, poor frequency locking stability, high cost and large size caused by circuit complexity in related technologies, and thus can achieve at least one of the following technical effects:

[0023] (1) First, by constructing a 360° phase-shifted frequency-locking feedback loop, the resonant frequency of the target load can be accurately locked, which can realize an adaptive frequency-locking mechanism with higher response speed, effectively ensure the maximum working efficiency of the target load, significantly improve the working efficiency and working stability of the target load, and at the same time, it can dynamically adjust the frequency-locking of the target LC resonant frequency according to the individual characteristics and life changes of the target load, realize automatic tracking and stable driving of the resonant frequency, further ensure its frequency-locking stability, and achieve the effect of dynamic frequency-locking.

[0024] (2) In addition, in the frequency locking circuit device in the embodiments of the present invention, the more complex circuit design usually used in the existing digital sampling and phase-locked loop frequency locking scheme can be directly eliminated, thereby effectively avoiding additional power loss and efficiency loss caused by the presence of complex circuit components, greatly saving costs, further improving the operating power of the target load (such as a piezoelectric ceramic air pump), and greatly improving working efficiency.

[0025] (3) Furthermore, the application of ADC converter and MCU microcontroller can be eliminated. On this basis, there is no need for other circuit components to cooperate with them. This greatly simplifies the composition of the frequency locking circuit structure. Efficient and accurate frequency locking dynamic control can be achieved based only on basic circuit components such as integral phase shift and drive bridge. This further reduces the power consumption caused by complex circuit components in the system, and also significantly reduces the circuit cost and overall circuit size (such as the area occupied).

[0026] Therefore, the frequency locking circuit device and control method described in the embodiments of the present invention can be more widely adapted to the needs of small and high-efficiency scenarios. Even under the current chip manufacturing process level, it can be better applied to high-precision electronic products (such as micro heat sinks for automotive chips or mobile phone chips) or equipment (such as micro heat sinks for extreme ultraviolet light source chips in lithography machines), so that its chips can achieve the same or even better operating capabilities as chips with higher chip manufacturing processes, and have a very wide range of product applications.

[0027] Therefore, the frequency locking circuit device and its control method based on the embodiments of the present invention can provide a dynamic frequency locking technology that is more efficient, more stable, lower power consumption, lower cost, more practical, and easier to implement and promote compared with existing frequency locking schemes. It can accurately lock the optimal resonant frequency of existing micro heat dissipation devices such as piezoelectric ceramic air pumps, and has extremely important practical value and economic benefits.

[0028] It should be understood that the above general description and the following specific embodiments are merely exemplary and illustrative, and do not limit the scope of the invention. Attached Figure Description

[0029] The above-described features, other objects, and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0030] Figure 1 A schematic diagram illustrating the circuit structure of a frequency-locking circuit device according to an embodiment of the present invention is shown.

[0031] Figure 2 A schematic diagram illustrating the circuit structure of a frequency-locking circuit device according to another embodiment of the present invention is shown.

[0032] Figure 3A The illustration shows a corresponding embodiment of the invention. Figure 1 Another circuit structure diagram of the frequency locking circuit device shown;

[0033] Figure 3B The illustration shows a corresponding embodiment of the invention. Figure 2 Another circuit structure diagram of the frequency locking circuit device shown;

[0034] Figure 4 The illustration schematically depicts an application scenario of a frequency-locking circuit device, control method, apparatus, medium, and program product according to embodiments of the present invention.

[0035] Figure 5 A flowchart illustrating a control method for a frequency-locking circuit device according to an embodiment of the present invention is shown schematically; and

[0036] Figure 6 A block diagram of an electronic device suitable for implementing a frequency-locking circuit device according to an embodiment of the present invention is shown schematically.

[0037] The accompanying drawings mentioned above are part of the specification of embodiments of the present invention, illustrating exemplary embodiments of the invention. The drawings, together with the description in the specification, serve to illustrate the principles of the embodiments of the present invention. It should be understood that the above general description with reference to the drawings and the following detailed description are merely exemplary and illustrative, and do not limit the scope of the invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the spirit of the contents disclosed in the present invention will be clearly explained below with reference to the accompanying drawings and detailed description. After understanding the embodiments of the present invention, any person skilled in the art can make changes and modifications based on the technology taught in the present invention without departing from the spirit and scope of the present invention.

[0039] The illustrative embodiments and descriptions of the present invention are used to explain the invention, but are not intended to limit the invention. Furthermore, elements / components using the same or similar reference numerals in the drawings and embodiments are used to represent the same or similar parts.

[0040] The terms "first," "second," etc., used in this invention do not specifically refer to any order or sequence, nor are they intended to limit the invention; they are merely used to distinguish elements or operations described using the same technical terms.

[0041] The directional terms used in this invention, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the scope of this invention.

[0042] The terms “comprising,” “including,” “having,” “containing,” etc., used in this invention are all open-ended terms, meaning that they include but are not limited to.

[0043] The term "and / or" as used in this invention includes any or all combinations of the things mentioned.

[0044] In this invention, "multiple" includes "two" and "more than two"; in this invention, "multiple groups" includes "two groups" and "more than two groups".

[0045] The terms "approximately," "about," etc., used in this invention are intended to modify any quantity or error that may vary slightly, but these slight variations or errors do not change the essence of the quantity or error. Generally, the range of slight variations or errors modified by such terms may be 20% in some embodiments, 10% in some embodiments, 5% in some embodiments, or other values. Those skilled in the art should understand that the aforementioned values ​​can be adjusted according to actual needs and are not limited thereto.

[0046] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0047] When expressions such as "at least one of A, B, and C" are used, they should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). When expressions such as "at least one of A, B, or C" are used, they should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). A person skilled in the art should also understand that any conjunction and / or phrase that substantially arbitrarily indicates two or more optional items, whether in the specification, claims, or drawings, should be understood to indicate the possibility of including one of these items, either of these items, or both items. For example, the phrase “A or B” should be understood as including the possibility of “A” or “B”, or “A and B”.

[0048] Piezoelectric ceramic pumps are widely used in heat dissipation, air inflation, and other applications, and their resonant characteristics can effectively improve energy transfer efficiency. The general electrical model of a conventional piezoelectric ceramic pump can typically be equivalent to a parallel connection of multiple series LC branches and one series RC branch. When the pump reaches its inherent resonant frequency, it exhibits characteristics of minimum phase shift, minimum impedance, maximum output power, and maximum energy conversion efficiency.

[0049] Therefore, in the field of driving micro heat sinks for chips such as piezoelectric ceramic air pumps, when these target loads operate at their intrinsic resonant frequency (resonant point), it can ensure that the input and output power of the load are maximized simultaneously, thus achieving the optimal chip operating level. However, the resonant frequency is extremely sensitive to changes in mass production process deviations, load variations, power supply disturbances, and environmental parameters (such as temperature, device aging, etc.). Traditional driving circuits often cannot guarantee that the output frequency is consistent with the resonant point for a long time, causing the system to deviate from the optimal operating point, resulting in power loss, efficiency reduction, and even device damage.

[0050] To ensure that the load devices of these miniature chip heat sinks operate near their resonant clock points, frequency locking (i.e., frequency locking) needs to be implemented in the drive circuits of these loads. Currently, common driving methods include fixed-frequency open-loop pulse width modulation (PWM) and methods that determine the resonant frequency at maximum output power by digitally sampling the input current. However, these traditional methods generally lack adaptive frequency locking mechanisms, cannot effectively and directly obtain the load's resonant frequency, and cannot dynamically adjust the frequency according to load changes (such as aging), thus easily causing resonance misalignment. Furthermore, the load's resonant frequency, impedance, temperature drift, and other parameters can vary during mass production, and the load's resonant power can degrade due to output voltage amplitude or long-term aging, leading to decreased system efficiency. Traditional digital sampling requires analog-to-digital conversion circuits and digital computing modules (such as analog-to-digital converters, microcontrollers, and drivers), resulting in high system power consumption and circuit costs. While some drive circuits introduce feedback control methods such as phase-locked loops, their control loops are complex, have slow response speeds, and are costly, making them difficult to widely adapt to the needs of small, high-efficiency scenarios.

[0051] Addressing at least one of the technical problems of existing resonant frequency locking schemes used in piezoelectric ceramic air pumps and micro fans for high-precision chips, such as poor frequency locking capability, high energy loss, low overall efficiency, poor frequency locking stability, and high cost and large size due to circuit complexity, embodiments of the present invention propose a frequency locking circuit device and its control method, equipment, medium and product, thereby providing a stable and dynamically adjustable novel frequency locking architecture. This aims to ensure the locking of the resonant frequency by achieving a 360° phase shift of the voltage or current phase of the target load (such as piezoelectric ceramic air pumps, micro fans, etc., based on RLC circuit models or RLC-like circuit models), thereby achieving stable maintenance of the maximum power of the target load and compensating for the gap in chip heat dissipation capacity caused by the inability of existing process technology to reach top-tier levels.

[0052] To enable those skilled in the art to have a clearer understanding of the frequency locking circuit device and its control method described in the embodiments of the present invention, the following further provisions are provided. Figures 1-5 Explanation.

[0053] like Figure 1 As shown, another aspect of the present invention provides a frequency locking circuit device 100 for locking the resonant frequency of a target load. The frequency locking circuit device 100 includes an integral phase shift module 103 and a drive control module 104.

[0054] The integral phase shift module 103 is used to generate a current integral phase shift signal by integrating and phase shifting the current working electrical signal at one end of the target load P; wherein the current integral phase shift signal achieves a 360° phase shift relative to the current working electrical signal;

[0055] The drive control module 104 is connected to the output of the integral phase shift module 103 and is used to update the current working electrical signal of the target load P according to the current integral phase shift signal, forming a self-oscillation loop with a gain greater than or equal to 1, so as to achieve resonant frequency locking.

[0056] In this embodiment of the invention, the target load P can be a load device based on an RLC circuit model or a similar RLC circuit model, such as a piezoelectric ceramic air pump or a micro fan. The target load P (e.g., a piezoelectric ceramic air pump) typically has its own inherent resonant frequency (i.e., intrinsic resonant frequency). Under a constant input voltage, when the actual operating frequency of the target load P is lower than its intrinsic resonant frequency, its output power (e.g., the mechanical exhaust power of the piezoelectric ceramic air pump) decreases, and the phase of its input current advances the phase of the input voltage. Conversely, when the actual operating frequency of the target load P is higher than its intrinsic resonant frequency, its output power also decreases, and the phase of its input current lags behind the phase of the input voltage. Therefore, only when the actual operating frequency of the target load P is equal to its intrinsic resonant frequency does its output power reach its maximum, and the phase of its input current is equal to or substantially equal to its voltage phase.

[0057] The target load P can be driven to work by the drive control module 104. Specifically, the drive control module 104 applies a drive electrical signal to the target load P to start and maintain the operation of the target load P. The current working electrical signal can be the actual electrical signal of the target load P at the current moment, such as the current signal or voltage signal flowing through the target load P at the current moment.

[0058] The integral phase shift module 103 mainly acquires the current working electrical signal and performs integral phase shift, enabling the current working electrical signal to achieve a 360° phase shift, forming a current integral phase shift signal. This current integral phase shift signal is used as a feedback signal for the drive control module 104 to update the current working electrical signal, so that the frequency locking circuit device 100 of this embodiment forms a positive feedback control loop with the help of the integral phase shift module 103 and the drive control module 104, and this control loop is a self-oscillating loop with a gain greater than or equal to 1. In this circuit, the current integral phase-shifted signal achieves a 360° phase shift relative to the current working electrical signal, and the gain of the entire feedback loop is greater than or equal to 1, which satisfies the phase consistency requirement. This ensures that the waveforms of the current integral phase-shifted signal, which serves as the feedback signal, and the current working electrical signal, which serves as the original input signal, are completely superimposed to form a positive excitation loop. Furthermore, the design of a loop gain greater than or equal to 1 ensures that the signal can at least maintain its original amplitude in each loop. Subsequently, the exponential growth of the amplitude can be limited by nonlinear components (such as inverters with saturation characteristics) to achieve the final dynamic equilibrium state, forming a self-oscillating loop based on positive feedback.

[0059] Therefore, by utilizing the self-oscillating positive feedback loop formed by the integral phase shift module 103 and the drive control module 104, the current operating electrical signal of the detected target load P can be adaptively and dynamically updated. This ensures that the target load P always operates at its actual intrinsic frequency under its current state. Regardless of individual differences in the target load P due to mass production processes (load variations, power supply disturbances, and environmental parameters) or changes in the circuit's operating environment (such as external temperature changes) or inherent frequency changes caused by circuit aging, it can always maintain its intrinsic frequency under the corresponding state, achieving automatic tracking and stable drive of the resonant frequency. This results in locking the actual intrinsic frequency of the target load P, with faster circuit feedback control response and more stable and reliable frequency locking, always keeping the target load P operating in its optimal state (maximum power output and maximum efficiency output). Therefore, this eliminates the disadvantages of complex circuit structures, high circuit costs, and high energy consumption inherent in traditional drive circuits or traditional frequency locking designs. As can be seen, the frequency locking circuit device 100 of the present invention can effectively solve at least one of the above-mentioned problems existing in the prior art, and has the advantages of more stable and accurate frequency locking capability, lower energy consumption and higher overall efficiency. Moreover, the overall circuit design is simpler, the circuit size is smaller and the cost is lower, and it can be effectively applied to target loads in small, high-efficiency high-precision chips, such as piezoelectric ceramic air pumps, micro fans and other loads based on RLC circuit models or RLC-like circuit models.

[0060] like Figures 1-3BAs shown, according to an embodiment of the present invention, the frequency locking circuit device 100 further includes a signal feedback unit 101 and a first sensing unit 102.

[0061] The signal feedback unit 101 is connected in parallel with the target load P and is used to feedback the direction of the current working electrical signal.

[0062] The first sensing unit 102 is connected in series with the target load P and is used to detect the current working electrical signal.

[0063] The signal feedback unit 101 can be used to feed back the direction (e.g., high or low level) of the current operating electrical signal of the target load P to the integration phase shift module 103. Specifically, it can be a feedback circuit module composed of certain circuit elements, or a signal feedback circuit element or assembly formed by a single or a few circuit elements (e.g., resistors). The signal feedback unit 101 can be connected in parallel with the target load P and can provide a feedback electrical signal to the integration phase shift module 103.

[0064] When the target load P is implemented based on an RLC circuit model, it typically has three circuit elements: inductor, capacitor, and resistor. The capacitor cannot provide feedback of a direct current (DC) signal (a DC start-up signal is usually required before startup). However, the signal feedback unit 101 can provide a feedback electrical signal to the integral phase shift module 103 to indicate the direction of application of the aforementioned DC start-up signal, thereby establishing negative (or positive) feedback in the equivalent circuit of the target load P. For example... Figure 1 As shown, negative feedback can be understood as follows: if the signal feedback unit 101 provides a low-frequency feedback signal, it means that the initial electrical signal on the right side of the target load P is a high-level signal. In order to ensure that the target load P maintains its inherent frequency, the current operating electrical signal of the target load P should be updated through the self-oscillation loop composed of the integral phase shift module 103 and the drive control module 104, so as to pull down the initial signal on the right side of the target load P in reverse. Conversely, the initial signal on the right side of the target load P can be pulled up in reverse, which will not be elaborated here.

[0065] In the circuit where the drive control module 104 applies a drive signal to the target load P, the first sensing unit 102 can be connected in series with the target load P, thereby acting as an electrical signal sampling circuit module to collect the electrical signal flowing through the target load P. Typically, the current operating electrical signal can be collected using circuit components such as high-precision, low-resistance resistors. For example, the voltage drop across the first sensing unit 102 can be used to determine the current signal flowing through it as the current operating electrical signal of the target load P at the current moment. Therefore, the first sensing unit 102 mainly functions as an electrical signal acquisition unit to acquire the actual operating electrical signal on the target load P in real time.

[0066] Therefore, the signal feedback unit 101 can very easily indicate the direction of the DC starting electrical signal applied to the target load P, thereby enabling the corresponding negative feedback adjustment to be achieved using the self-oscillation loop of the aforementioned integral phase shift module 103 and drive control module 104. Furthermore, the first sensing unit 102 can be used to accurately detect and output the actual working electrical signal (i.e., the current working electrical signal) of the target load P at the current moment.

[0067] like Figures 1-3B As shown, according to an embodiment of the present invention, the integral phase shift module 103 includes a first integral unit 301 and a second integral unit 302.

[0068] The input terminal of the first integrating unit 301 is connected to both ends of the first sensing unit 102 in a differential input form, and is used to perform the first integration phase shift on the current working electrical signal to generate the first integrated phase shift signal.

[0069] The input terminal of the second integration unit 302 is connected to the output terminal of the first integration unit 301 in a differential input form, and is used to perform a second integration phase shift on the first integration phase shift signal to generate a second integration phase shift signal.

[0070] The first input terminal of the first integrating unit 301 is connected to the first terminal of the first sensing unit 102, and the second input terminal of the first integrating unit 301 is connected to the second terminal of the first sensing unit 102. Using a differential input method, the first integrating unit 301 can input the current operating electrical signal of the target load P detected by the first sensing unit 102 at the current moment to the integrating phase shift module 103. At this time, the first integrating unit 301 can perform a first phase shift on the current operating electrical signal, achieving a 90° phase shift and generating a first integrated phase shift signal. This first integrated phase shift signal has a 90° phase shift relative to the original current operating electrical signal.

[0071] The first integral phase-shift signal can be further integrated and phase-shifted by the second integration unit 302, achieving another 90° phase shift to generate the second integral phase-shift signal. At this point, the second integral phase-shift signal has a 90° phase shift relative to the first integral phase-shift signal and a 180° phase shift relative to the original current operating electrical signal. The second integration unit 302 can be connected to the first integration unit 301. Specifically, the first input terminal of the second integration unit 302 can be connected to the first output terminal of the first integration unit 301, and the second input terminal of the second integration unit 302 can be connected to the second output terminal of the first integration unit 301, thereby enabling the input of the first integral phase-shift signal.

[0072] Therefore, a 180° phase shift of the current operating electrical signal can be achieved using the first integrating unit 301 and the second integrating unit 302. Specifically, the first integrating unit 301 and the second integrating unit 302 can be circuit elements or integrating phase shift circuits (i.e., integrators) used to perform two consecutive phase shifts on the current operating electrical signal for the target load P. For example, they can be circuit elements such as capacitors or integrating amplifiers, or circuit structures composed of these. The phase shifting process can also simultaneously achieve high-frequency filtering of the current operating electrical signal and the first integrated phase-shifted signal twice.

[0073] like Figures 1-3B As shown, according to an embodiment of the present invention, the integral phase shift module 103 further includes a waveform conversion unit 303 and a phase conversion unit 304.

[0074] The input terminal of the waveform conversion unit 303 is connected to the output terminal of the second integration unit 302 in a differential input form, and is used to perform waveform conversion processing on the second integrated phase shift signal to generate a waveform conversion signal;

[0075] The input terminal of the phase conversion unit 304 is connected to the output terminal of the waveform conversion unit 303, and is used to perform phase conversion processing on the waveform conversion signal to generate the current integral phase shift signal.

[0076] The first input terminal of the waveform conversion unit 303 is connected to the first output terminal of the second integration unit 302, and the second input terminal of the waveform conversion unit 303 is connected to the second output terminal of the second integration unit 302. This allows the waveform conversion unit 303 to convert the waveform of the second integral phase-shift signal output by the second integration unit 302, for example, converting a sine wave (sin waveform) into a square wave, or vice versa, without specific limitations. In this embodiment of the invention, the input waveform of the current working electrical signal can be a sine wave, while the waveform of the current integral phase-shift signal can be a square wave. That is, the waveform conversion signal differs from the second integral phase-shift signal only in waveform; its amplitude, period, and other signal characteristics remain unchanged. Specifically, the waveform conversion unit 303 can be implemented using a comparator (CMP) or a similar circuit element or module, which will not be elaborated further.

[0077] To further meet the 360° phase shift requirement and achieve the self-oscillating loop effect, the waveform conversion signal output by the waveform conversion unit 303 is inverted again by the phase conversion unit 304, so that the current integral phase-shifted signal has a 180° phase shift relative to the waveform conversion signal. Therefore, the current integral phase-shifted signal has a 360° phase shift relative to the current working electrical signal of the original input first integration unit 301, but it can still maintain the same phase characteristic (i.e., return to the original phase), thus completing one original oscillation process. The phase conversion unit 304 can be implemented using an inverter (PI) or a similar circuit element or module, which will not be elaborated further.

[0078] Therefore, based on the two integral phase shifts mentioned above, a current integral phase-shifted signal with the same phase and other signal characteristics as the current working electrical signal, but with a different waveform and a 360° phase shift, is further output. It can be seen that during the integral phase shift, waveform conversion, and phase inversion processes, high-frequency noise over-filtering of the current working electrical signal is achieved, effectively preventing signal interference. At the same time, it ensures that the current integral phase-shifted signal has a 360° phase shift difference from the original current working electrical signal, and its waveform also meets the drive input signal requirements of the drive control module 104, thus ensuring the frequency locking effect of the self-oscillation loop with a faster response.

[0079] like Figures 1-3B As shown, according to an embodiment of the present invention, the first integration unit 301 includes a first integrating amplifier AMP1, a first resistor R1 and a first capacitor C1.

[0080] The first input terminal of the first integrating amplifier AMP1 is connected to one end of the first sensing unit 102, and its second input terminal is connected to the other end of the first sensing unit 102.

[0081] One end of the first resistor R1 is connected to the first output terminal of the first integrating amplifier AMP1, and the other end is connected to the second output terminal of the first integrating amplifier AMP1.

[0082] One end of the first capacitor C1 is connected to the first output terminal of the first integrating amplifier AMP1, and the other end is connected to the second output terminal of the first integrating amplifier AMP1.

[0083] The first resistor R1 and the first capacitor C1 are connected in parallel.

[0084] In the first integrating unit 301, the two input terminals of the first integrating amplifier AMP1 (i.e., the amplifier) ​​can be differentially input to receive the induced electrical signal from the first sensing unit 102 as the current operating electrical signal. With the cooperation of the first integrating amplifier AMP1, the first resistor R1, and the first capacitor C1, the first integrating unit 301 can not only filter high-frequency noise from the current operating electrical signal but also perform a first integration phase shift, achieving a 90° phase shift of the first integrated phase-shifted signal relative to the current operating electrical signal.

[0085] like Figures 1-3B As shown, according to an embodiment of the present invention, the second integration unit 302 includes a second integrating amplifier AMP2, a second resistor R2, and a second capacitor C2.

[0086] The first input terminal of the second integrating amplifier AMP2 is connected to the first output terminal of the first integrating unit 301, and its second input terminal is connected to the second output terminal of the first integrating unit 301.

[0087] One end of the second resistor R2 is connected to the first output terminal of the second integrating amplifier AMP2, and the other end is connected to the second output terminal of the second integrating amplifier AMP2.

[0088] One end of the second capacitor C2 is connected to the first output terminal of the second integrating amplifier AMP2, and the other end is connected to the second output terminal of the second integrating amplifier AMP2.

[0089] The second resistor R2 and the second capacitor C2 are connected in parallel.

[0090] Similar to the first integrating unit 301 described above, in the second integrating unit 302, the two input terminals of the second integrating amplifier AMP2 can be differentially input to the first integrating phase-shifted signal of the first integrating unit 301. With the cooperation of the second integrating amplifier AMP2, the second resistor R2, and the second capacitor C2, the second integrating unit 302 can not only further filter high-frequency noise from the first integrating phase-shifted signal, but also perform a second integrating phase shift, achieving a 90° phase shift relative to the first integrating phase-shifted signal. That is, the second integrating phase-shifted signal has achieved a 180° phase shift relative to the original current operating electrical signal, and has achieved two high-frequency noise filtering effects.

[0091] like Figures 1-3B As shown, according to an embodiment of the present invention, the integral phase shift module 103 further includes a signal processing unit 305.

[0092] The input terminal of the signal processing unit 305 is connected to the output terminal of the first integration unit 301, and is used to perform signal biasing and signal isolation processing on the first integrated phase shift signal.

[0093] To further avoid error amplification caused by signal deviation during the integration phase shift process, the signal processing unit 305 can be used to perform signal biasing and signal isolation processing on the first integration phase shift signal output by the first integration unit 301. This ensures that the current integration phase shift signal obtained after the subsequent second integration phase shift, waveform conversion and inversion processing achieves a 360° phase shift and waveform change relative to the current working electrical signal, without causing changes in other signal characteristics (such as frequency, period, amplitude, phase, etc.).

[0094] like Figures 1-3B As shown, according to an embodiment of the present invention, the signal processing unit 305 includes a signal isolator for performing signal isolation processing on the first integral phase shift signal. The signal isolator includes a third capacitor C3 and a fourth capacitor C4.

[0095] One end of the third capacitor C3 is connected to the first output terminal of the first integration unit 301, and the other end is connected to the first input terminal of the second integration unit 302.

[0096] One end of the fourth capacitor C4 is connected to the second output terminal of the first integration unit 301, and the other end is connected to the second input terminal of the second integration unit 302.

[0097] The first output terminal of the first integration unit 301 and the first input terminal of the second integration unit 302 are connected to the two ends of the third capacitor C3, and the second output terminal of the first integration unit 301 and the second input terminal of the second integration unit 302 are connected to the two ends of the fourth capacitor C4, respectively. By utilizing the characteristic of capacitors to block DC and pass AC, the DC signal characteristics in the first integrated phase shift signal of the first integration unit 301 can be blocked, so that the phase information in the first integrated phase shift signal can be effectively preserved.

[0098] like Figures 1-3B As shown, according to an embodiment of the present invention, the signal processing unit 305 includes a signal biaser for performing signal biasing processing on the first integral phase shift signal. The signal biaser includes a third resistor R3 and a fourth resistor R4.

[0099] One end of the third resistor R3 is connected to the first output terminal of the first integration unit 301 and the first input terminal of the second integration unit 302;

[0100] One end of the fourth resistor R4 is connected to the second output terminal of the first integrating unit 301 and the second input terminal of the second integrating unit 302, and the other end is connected to the other end of the third resistor R3 and connected to a preset bias voltage V. REF .

[0101] Considering that the first integral phase shift signal, which serves as the input signal to the second integral unit 302, is a differential input signal, it is necessary to ensure that the differential average value is close to 0 in actual conditions (ideally, the differential average value can be equal to 0) in order for the second integral unit 302 to operate near the common-mode point and ensure the effect of the second integral phase shift. At this time, a preset bias voltage V is applied between the third resistor R3 and the fourth resistor R4. REF This can effectively eliminate the inherent error of the second integrating unit 302 (such as the second integrating amplifier AMP2), and at the same time avoid the differential deviation phenomenon (i.e. average value error) that may exist in the first integrating phase shift signal output by the first integrating unit 301, which is used as a differential signal input, thus ensuring the overall performance of the second integrating phase shift.

[0102] Among them, the third capacitor C3 and the fourth capacitor C4 can also serve as error isolation for the first integration phase shift signal of the first integration unit 301, and a preset bias voltage V is further applied between the third resistor R3 and the fourth resistor R4. REF Based on this, the differential input and differential output of the second integrating amplifier AMP2 of the second integrating unit 302 are made closer to 0.

[0103] Therefore, the second integral phase-shift signal output by the second integral unit 302 to the waveform conversion unit 303 and the phase conversion unit 304 can effectively avoid the error amplification caused by the differential input error of the first integral phase-shift signal, ensure the consistency of signal characteristics (such as frequency, period, phase, etc.) between the current integral phase-shift signal and the original current working electrical signal, and at the same time ensure the accuracy of 360° phase shift, waveform conversion and phase inversion processing.

[0104] like Figure 1 and Figure 3A As shown, according to an embodiment of the present invention, the drive control module 104 includes a first inverting unit 401, a first drive unit 402, a second drive unit 403, and a full-bridge drive unit 404.

[0105] The input terminal of the first inverting unit 401 is connected to the output terminal of the phase conversion unit 304, and is used to invert the current integrated phase shift signal to generate an inverted processed signal.

[0106] The input terminal of the first driving unit 402 is connected to the output terminal of the first inverting unit 401, and is used to generate a first driving signal and a second driving signal according to the inverted processing signal.

[0107] The input terminal of the second driving unit 403 is connected to the output terminal of the phase conversion unit 304, and is used to generate the third driving signal and the fourth driving signal according to the current integrated phase shift signal;

[0108] The input terminal of the full-bridge drive unit 404 is correspondingly connected to the output terminal of the first drive unit 402 and the output terminal of the second drive unit 403, and is used to control the preset input power supply V external to the full-bridge drive unit 404 according to the first drive signal, the second drive signal, the third drive signal and the fourth drive signal. IN Update the current operating electrical signal applied to the target load P.

[0109] The first inverting unit 401 can be implemented using an inverter or a circuit element that performs similar electrical signal inversion processing, so that the inverted signal has a 180° phase difference relative to the current integrated phase-shifted signal. The first driving unit 402 and the second driving unit 403 can be used to increase the signal driving capability of the driving signals (first driving signal, second driving signal, third driving signal, and fourth driving signal) input to the full-bridge driving unit 404. Specifically, this increase in signal driving capability can be understood as significantly shortening the charging time (e.g., transistor threshold voltage) of a certain transistor in the full-bridge driving unit 404 from 0V to the target voltage. For example, a transistor that normally requires 1 second to charge from 0V to 1V can achieve the same charging effect in only 0.1 seconds under the driving conditions of the first driving unit 402 or the second driving unit 403.

[0110] In this embodiment of the invention, the full-bridge drive unit 404 may have at least four input terminals, respectively used to receive the first and second drive signals output by the first drive unit 402, and the third and fourth drive signals output by the second drive unit 403. Thus, the full-bridge drive unit 404 can, by using the first, second, third, and fourth drive signals respectively, achieve output modulation of the drive electrical signals at both ends toward the target load P, that is, to update the current working electrical signal, for example, one end is OUT+ and the other end is OUT-, specifically OUT+=10V and OUT-=-10V square wave signal. Therefore, by using this full-bridge drive unit 404, a relatively lower preset input power supply V can be used. IN A higher drive voltage matching the target load P is achieved through a dual-ended power supply. Specifically, for example, a preset input power supply V... IN If the voltage is 10V, then the drive voltage matched to the target load P can reach 20V.

[0111] The full-bridge drive unit 404 can achieve drive control of the target load P by means of at least a number of transistors corresponding to the first drive signal, the second drive signal, the third drive signal and the fourth drive signal, which can be used to update the current operating electrical signal on the target load P.

[0112] like Figure 1 and Figure 3A As shown, according to an embodiment of the present invention, the first driving unit 402 includes two inverters connected in parallel, and the second driving unit 403 includes two inverters connected in parallel.

[0113] The first driving unit 402 can be implemented using two inverters connected in parallel. This ensures that, given the same inverted input signal, two driving signals—a first driving signal and a second driving signal—can be output in parallel through the two inverters. If the two inverters are identical circuit components, the first driving signal and the second driving signal can be the same signal.

[0114] Similarly, the second drive unit 403 can be implemented using two inverters connected in parallel. This ensures that, given the same current integrated phase shift signal input, two drive signals, namely the third drive signal and the fourth drive signal, can be output in parallel through these two inverters. If the two inverters are circuit elements of the same specification, the third drive signal and the fourth drive signal can be the same signal.

[0115] The first inverting unit 401 ensures that the signal inputs of the first driving unit 402 and the second driving unit 403 have different phases; that is, the inverted processing signal input to the first driving unit 402 has a 180° phase difference with respect to the current integrated phase-shift signal input to the second driving unit 403. Therefore, when the inverter specifications are the same, the first driving signal and the second driving signal can be electrical signals of the same phase. Similarly, the third driving signal and the fourth driving signal can be electrical signals of the same phase, and the phases of the first driving signal and the second driving signal can be opposite to those of the third driving signal and the fourth driving signal.

[0116] Therefore, by means of the above-described design of the first drive unit 402 and the second drive unit 403, efficient and precise drive control of the full-bridge drive unit 404 can be effectively achieved based on the first drive signal, the second drive signal, the third drive signal and the fourth drive signal.

[0117] like Figure 1 and Figure 3A As shown, according to an embodiment of the present invention, the full-bridge drive unit 404 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4.

[0118] The gate of the first transistor M1 is connected to the first output terminal of the first driving unit 402, and its source is connected to the preset input power supply V. IN Its drain is connected to the first sensing unit 102, and is used to control the conduction and disconnection of the first transistor M1 according to the first driving signal;

[0119] The gate of the second transistor M2 is connected to the second output terminal of the first driving unit 402, its source is grounded to G, and its drain is connected to the drain of the first transistor M1. It is used to control the conduction and disconnection of the second transistor M2 according to the second driving signal.

[0120] The gate of the third transistor M3 is connected to the first output terminal of the second driving unit 403, and its source is connected to the preset input power supply V. IN Its drain is connected to the target load P, and it is used to control the conduction and disconnection of the third transistor M3 according to the third drive signal;

[0121] The gate of the fourth transistor M4 is connected to the second output terminal of the second driving unit 403, its source is grounded, and its drain is connected to the drain of the third transistor M3, which is used to control the conduction and disconnection of the fourth transistor M4 according to the fourth driving signal.

[0122] In one embodiment of the present invention, the first transistor M1 and the third transistor M3 of the full-bridge driving unit 404 can be PMOS transistors, and the second transistor M2 and the fourth transistor M4 can be NMOS transistors. Specifically, the MOS transistor can be a metal-oxide-semiconductor field-effect transistor (MOSFET), the PMOS transistor can be a P-type doped MOS transistor, and the NMOS transistor can be an N-type doped MOS transistor.

[0123] Specifically, for the PMOS transistors M1 and M3, when their gate voltage is high, they are in the off state and no current is flowing (i.e., open state); when their gate voltage is low, they are in the on state and current is flowing (i.e., on state). Conversely, for the NMOS transistors M2 and M4, when their gate voltage is high, they are in the on state and current is flowing (i.e., on state); when their gate voltage is low, they are in the off state and no current is flowing (i.e., open state).

[0124] Therefore, as Figure 1 and Figure 3A As shown, the frequency locking implementation process of the frequency locking circuit device 100 of an embodiment of the present invention can be specifically described in the following detailed description.

[0125] (1) The negative feedback process that can be reflected in the startup process of the above target load P.

[0126] First, connect the preset input power supply V. IN The full-bridge drive unit 404 applies drive electrical signals to both ends of the target load P. At this time, the first signal feedback unit 101 can indicate the direction of application of the drive electrical signals to both ends of the target load P.

[0127] For example, when the target load P closest to the first sensing unit 102 is at a high level, and the target load P furthest from the first sensing unit 102 is at a low level, then the first sensing unit 102 closest to the target load P is at a low level, and the first sensing unit 102 furthest from the target load P is at a high level. It should be understood by those skilled in the art that "closer" or "furthest" does not refer to spatial structure, but rather to the connection relationship of the circuit.

[0128] At this time, the first input terminal of the first integrating amplifier AMP1 of the first integrating unit 301 corresponds to the low-level input of the current working electrical signal, and the second input terminal of the first integrating amplifier AMP1 corresponds to the high-level input of the current working electrical signal. Further, the first input terminal of the second integrating amplifier AMP2 of the second integrating unit 302 corresponds to the low-level input of the first integrating phase shift signal, and its second input terminal corresponds to the high-level input of the first integrating phase shift signal. This continues until the waveform conversion unit performs waveform conversion on the second integrating phase shift signal, outputting a low-level waveform conversion signal of a square wave. After the phase conversion unit 304 inverts this waveform conversion signal, a high-level current integrating phase shift signal is obtained.

[0129] At this time, the current integral phase shift signal input to the drive control module 104 is inverted again by the first inverting unit 401, resulting in a low-level inverted signal input to the first drive unit 402. The first drive unit 402 then outputs two high-level first drive signals and a second drive signal. At this time, the first transistor M1 of the full-bridge drive unit 404 enters or remains in an off state upon receiving the high-level first drive signal (preset input power supply V). IN The input from the first transistor M1 is disconnected, and the second transistor M2 enters or remains in the conducting state when it receives the high-level second drive signal (one end of the first sensing unit 102 away from the target load P is grounded by means of the second transistor M2), so that the end of the target load close to the first sensing unit 102 can be pulled down.

[0130] Simultaneously, a high-level current integral phase shift signal is input to the second drive unit 403, which then outputs two low-level third and fourth drive signals. At this time, the third transistor M3 of the full-bridge drive unit 404 enters or remains in the on state upon receiving the low-level third drive signal (preset input power supply V). IN The target load P is connected via the third transistor M3, and when the fourth transistor M4 receives the low-level fourth drive signal, it enters or remains in an off state (so that the other end of the target load away from the first sensing unit 102 cannot be grounded, and is only connected to the preset input power supply V through the third transistor). IN Therefore, it is possible to pull up the target load P that is far away from the first sensing unit 102.

[0131] The above describes the negative feedback modulation process generated during the startup of the target load P.

[0132] (2) The positive feedback process that can be manifested in the working process of the above target load P.

[0133] When the first signal feedback unit 101 can report that the end of the target load P near the first sensing unit 102 is at a low level and the other end of the target load P far away from the first sensing unit 102 is at a high level, it determines that the end of the first sensing unit 102 near the target load P is at a high level and the other end of the first sensing unit 102 far away from the target load P is at a low level.

[0134] At this time, the first input terminal of the first integrating amplifier AMP1 corresponds to the high-level input of the current working electrical signal, and the second input terminal of the first integrating amplifier AMP1 corresponds to the low-level input of the current working electrical signal. Further, the first input terminal of the second integrating amplifier AMP2 of the second integrating unit 302 corresponds to the high-level input of the first integrating phase shift signal, and its second input terminal corresponds to the low-level input of the first integrating phase shift signal. This continues until the waveform conversion unit performs waveform conversion on the second integrating phase shift signal, outputting a high-level waveform conversion signal of a square wave. After the phase conversion unit 304 inverts this waveform conversion signal, a low-level current integrating phase shift signal is obtained.

[0135] At this time, the current integral phase shift signal input to the drive control module 104 is inverted again by the first inverting unit 401, resulting in a high-level inverted signal that is input to the first drive unit 402. The first drive unit 402 then outputs two low-level first drive signals and a second drive signal. At this time, the first transistor M1 of the full-bridge drive unit 404 enters or remains in the on state when it receives the low-level first drive signal (preset input power supply V). IN(The first transistor M1 is connected to the first sensing unit 102), and the second transistor M2 enters or remains in the off state when it receives the low-level second drive signal (the end of the first sensing unit 102 far away from the target load P cannot be grounded through the second transistor M2), so it is possible to pull up the end of the target load P close to the first sensing unit 102.

[0136] Simultaneously, a low-level current integral phase shift signal is input to the second drive unit 403, which then outputs two high-level third and fourth drive signals. At this time, the third transistor M3 of the full-bridge drive unit 404 enters or remains in an off state upon receiving the high-level third drive signal (preset input power supply V). IN The third transistor M3 is disconnected from the target load P, and the fourth transistor M4 enters or remains in the conducting state when it receives the high-level fourth drive signal (so that the other end of the target load P away from the first sensing unit 102 can be grounded), thus enabling the pull-down of the other end of the target load P away from the first sensing unit 102.

[0137] The above describes the positive feedback modulation process generated by the target load P during its operation.

[0138] In this way, based on the 360° integral phase shift of the aforementioned integral phase shift module 103, a self-oscillating loop with a gain greater than 1 can be achieved by combining it with the drive control module 104. This ensures that the actual operation of the target load P can always be stably and dynamically maintained at the current inherent resonant frequency of the target load P. The design of the entire circuit has a higher response speed and maintains the optimal working efficiency of the target load P. The circuit structure is simple and does not need to consider individual characteristic differences or aging of the target load P due to various reasons.

[0139] It should be noted that, as an improvement to an embodiment of the present invention, Figure 1 The drive control module 104 shown can further incorporate one or more inverters (such as inverter 406) to achieve repeated inversion processing of the current integral phase-shift signal or the inverted processing signal, as described above. Figure 3A As shown, the connection position of the second driving unit 403 can be adaptively adjusted according to the connection relationship of the inverter 406, the first inverter 401, and the phase conversion unit 304. Specifically, it is only necessary to meet the above-mentioned positive feedback and negative feedback adjustment process, and no specific restrictions are made here.

[0140] like Figure 2 and Figure 3BAs shown, according to another embodiment of the present invention, the drive control module 104 includes a second inverting unit 405, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7.

[0141] The input terminal of the second inverting unit 405 is connected to the output terminal of the phase conversion unit 304, and is used to invert the current integral phase shift signal to generate the fifth driving signal.

[0142] The gate of the fifth transistor M5 is connected to the output terminal of the second inverting unit 405, its source is grounded to G, and its drain is connected to the target load P, which is used to control the conduction and disconnection of the fifth transistor M5 according to the fifth drive signal.

[0143] The gate of the sixth transistor M6 is connected to the output terminal of the phase conversion unit 304, and its source is grounded. It is used to control the conduction and disconnection of the sixth transistor M6 according to the current integral phase shift signal.

[0144] The gate of the seventh transistor M7 is connected to the drain of the sixth transistor M6, and its source is connected to the preset input power supply V. IN It is used to connect to the gate of the seventh transistor M7, whose drain is connected to the target load P;

[0145] One end of the first sensing unit 102 is connected to the reference input power supply V. IN0 The other end is connected to the target load P.

[0146] In another embodiment of the invention, such as Figure 2 and Figure 3B As shown, the second inverting unit 405, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 of the drive control module 104 can form a half-bridge drive structure. While the half-bridge drive structure offers a simpler design compared to the full-bridge drive unit 404, the driving voltage applied to the target load P and the preset input power supply V it connects to... IN The same. Specifically, for example, the preset input power supply V IN =10V, then the drive voltage matched to the target load P can only reach 10V.

[0147] Unlike the dual-end power supply of the full-bridge drive unit 404, the half-bridge drive structure can have at least two input terminals, which are respectively used to connect the fifth drive signal of the second inverting unit 405 and the current integral phase shift signal output by the phase conversion unit 304, to achieve a single-end power supply for the target load P. In this way, the half-bridge drive structure can output drive electrical signals towards both ends of the target load P by using the separate driving of the fifth drive signal and the current integral phase shift signal, thus updating the current operating electrical signal.

[0148] It should be noted that, in the design of the drive control module 104 of the half-bridge drive structure in another embodiment of the present invention, the prerequisite should be met: one end of the first sensing unit 102, which is far away from the target load P, is connected to a preset reference input power supply V. IN0 The reference input power supply can satisfy: V IN0 =1 / 2V IN Therefore, the half-bridge drive structure of the drive control module 104 can output a square wave (i.e., the target waveform of the target voltage) voltage signal of 0V or 10V (i.e., the target drive voltage) to the target load by grounding one end and outputting the other end to the target load.

[0149] like Figure 2 and Figure 3B As shown, according to another embodiment of the present invention, the drive control module 104 further includes a fifth resistor R5 and a sixth resistor R6.

[0150] One end of the fifth resistor R5 is connected to the source of the sixth transistor M6, and the other end is grounded to G;

[0151] One end of the sixth resistor R6 is connected to the gate of the seventh transistor M7 and the drain of the sixth transistor M6, and the other end is connected to the source of the seventh transistor M7 and the preset input power supply V. IN .

[0152] In another embodiment of the present invention, the drive control module 104 can eliminate the above-mentioned structural designs such as the first drive unit 402 and the second drive unit 403 by means of the half-bridge drive structure, thus ensuring the simplification of the circuit structure. With the assistance of the second inverting unit 405, efficient and precise drive control for the fifth transistor M5 and the sixth transistor M6 can be achieved.

[0153] In another embodiment of the present invention, the fifth transistor M5 and the sixth transistor M6 in the half-bridge drive structure can both be NMOS transistors, and the seventh transistor M7 can be a PMOS transistor. Therefore, for the NMOS transistors M5 and M6, when their gate voltage is high, they are in the ON state and current is flowing (i.e., on state); when their gate voltage is low, they are in the OFF state and current is not flowing (i.e., off state). Conversely, for the PMOS transistor M7, when its gate voltage is high, it is in the OFF state and current is not flowing (i.e., off state); when its gate voltage is low, it is in the ON state and current is flowing (i.e., on state).

[0154] Therefore, as Figure 2 and Figure 3B As shown, the frequency locking implementation process of the frequency locking circuit device 100' of another embodiment of the present invention can be specifically described in the following detailed description.

[0155] (1) The negative feedback process that can be reflected in the startup process of the above target load P.

[0156] First, connect the preset input power supply V. IN The half-bridge drive unit applies a drive signal to one end of the target load P, while the other end of the target load P can be connected to the reference input power supply V through the first sensing unit 102. IN0 =1 / 2V IN At this time, the first signal feedback unit 101 can indicate the direction of application of the driving electrical signal at both ends of the target load P.

[0157] For example, when the target load P near the first sensing unit 102 is at a low level and the target load P away from the first sensing unit 102 is at a high level, it determines that the first sensing unit 102 near the target load P is at a high level and the first sensing unit away from the target load P is at a low level (this end is connected to the reference input power supply V). IN0 ).

[0158] At this time, the first input terminal of the first integrating amplifier AMP1 of the first integrating unit 301 corresponds to the high-level input of the current working electrical signal, and the second input terminal of the first integrating amplifier AMP1 corresponds to the low-level input of the current working electrical signal. Further, the first input terminal of the second integrating amplifier AMP2 of the second integrating unit 302 corresponds to the high-level input of the first integrating phase shift signal, and its second input terminal corresponds to the low-level input of the first integrating phase shift signal. This continues until the waveform conversion unit performs waveform conversion on the second integrating phase shift signal, outputting a high-level waveform conversion signal of a square wave. After the phase conversion unit 304 inverts this waveform conversion signal, a low-level current integrating phase shift signal is obtained.

[0159] At this time, the current integral phase shift signal input to the drive control module 104 is inverted again by the second inverting unit 405, resulting in a high-level fifth drive signal input to the fifth transistor M5 of the half-bridge drive structure. Upon receiving this high-level fifth drive signal, the fifth transistor M5 either enters or remains in the on state (allowing the end of the target load P furthest from the first sensing unit 102 to be grounded via the fifth transistor M5), thus enabling a pull-down effect on the end of the target load P furthest from the first sensing unit 102. Simultaneously, a low-level current integral phase shift signal is input as a drive signal to the sixth transistor M6 of the half-bridge drive structure. Upon receiving this low-level current integral phase shift signal, the sixth transistor M6 either enters or remains in the off state (preset input power supply V). IN(It is impossible to ground through the sixth transistor M6), and at this time the gate of the seventh transistor M7 also receives a high-level preset input power supply V. IN This causes it to enter or remain in an open state (so that the other end of the target load away from the first sensing unit 102 cannot be grounded and the preset input power supply V is disconnected). IN Therefore, it can work with the fifth transistor M5 to achieve a pull-down effect on the other end of the target load P that is far away from the first sensing unit 102.

[0160] The above describes the negative feedback modulation process generated during the startup of the target load P.

[0161] (2) The positive feedback process that can be manifested in the working process of the above target load P.

[0162] For example, when the target load P near the first sensing unit 102 is at a high level and the target load P away from the first sensing unit 102 is at a low level, it determines that the first sensing unit 102 near the target load P is at a low level and the first sensing unit 102 away from the target load P is at a high level (this end is connected to the reference input power supply V). IN0 ).

[0163] At this time, the first input terminal of the first integrating amplifier AMP1 of the first integrating unit 301 corresponds to the low-level input of the current working electrical signal, and the second input terminal of the first integrating amplifier AMP1 corresponds to the high-level input of the current working electrical signal. Further, the first input terminal of the second integrating amplifier AMP2 of the second integrating unit 302 corresponds to the low-level input of the first integrating phase shift signal, and its second input terminal corresponds to the high-level input of the first integrating phase shift signal. This continues until the waveform conversion unit performs waveform conversion on the second integrating phase shift signal, outputting a low-level waveform conversion signal of a square wave. After the phase conversion unit 304 inverts this waveform conversion signal, a high-level current integrating phase shift signal is obtained.

[0164] At this time, the current integral phase shift signal input to the drive control module 104 is inverted again by the second inverting unit 405, resulting in a low-level fifth drive signal input to the fifth transistor M5 of the half-bridge drive structure. Upon receiving this low-level fifth drive signal, the fifth transistor M5 either enters or remains off (ensuring that the end of the target load P furthest from the first sensing unit 102 can no longer be grounded via the fifth transistor M5). Simultaneously, a high-level current integral phase shift signal is input as a drive signal to the sixth transistor M6 of the half-bridge drive structure. Upon receiving this high-level current integral phase shift signal, the sixth transistor M6 either enters or remains on (preset input power supply V). IN(This can be grounded via the sixth transistor M6), and at this time, the gate of the seventh transistor M7 also receives a low-level preset input power supply V. IN This causes it to enter or remain in a conductive state (so that the other end of the target load, which is far from the first sensing unit 102, can be smoothly connected to the preset input power supply V). IN Therefore, it can work with the fifth transistor M5 to achieve the pull-up effect on the other end of the target load P that is far away from the first sensing unit 102.

[0165] The above describes the positive feedback modulation process generated during the startup of the target load P.

[0166] In this way, based on the 360° integral phase shift of the aforementioned integral phase shift module 103, a self-oscillating loop with a gain greater than 1 can be achieved by combining it with the drive control module 104. This ensures that the actual operation of the target load P can always be stably and dynamically maintained at the current inherent resonant frequency of the target load P. The design of the entire circuit has a higher response speed and maintains the optimal working efficiency of the target load P. The circuit structure is simple and does not need to consider individual characteristic differences or aging of the target load P due to various reasons.

[0167] It should be noted that, as another improvement to the embodiment of the present invention, Figure 2 The drive control module 104 shown can be further equipped with one or more inverters (such as inverters 407 and 408) to achieve repeated inversion processing of the current integral phase shift signal, as described above. Figure 3B As shown, the connection position of the sixth transistor M6 can be adaptively adjusted according to the connection relationship of inverter 407, inverter 408, second inverter unit 405 and phase conversion unit 304. Specifically, it is necessary to meet the above-mentioned positive feedback and negative feedback adjustment process, and no specific restrictions are made here.

[0168] As mentioned earlier regarding the modulation process of negative and positive feedback, whether during the drive startup process of the target load P or during its current operation, the self-oscillating loop constructed based on the integral phase shift module 103 and the drive control module 104, with a loop phase shift deviation of 360° and a loop gain always greater than or equal to 1, can dynamically lock the inherent resonant frequency of the target load P without considering the individual characteristics and lifespan variations of the target load P itself. The entire circuit design is extremely simple, and the loop frequency locking response speed is extremely fast, enabling stable and accurate locking of the true inherent frequency of the target load P, ensuring automatic tracking and stable drive of the resonant frequency, thereby greatly guaranteeing the optimal operating efficiency of the target load P.

[0169] Among them, such as Figures 1-3BAs shown, when the drive circuit controls the target load P (such as a piezoelectric ceramic air pump) to operate at the resonant frequency, the phase shift between the voltage and current of the target load P is minimal, the impedance is minimal, and the output power is maximum. That is, the target load P itself has the resonant frequency selection function of an RLC model or a similar RLC model. Since the two-stage integration of the first integration unit 301 and the second integration unit 302 generates a 180° phase shift, plus the 180° inversion logic of the subsequent phase conversion unit 304 (such as an inverter), the drive voltage and current of the target load P can maintain a 360° phase shift when the entire system operates only at its inherent resonant frequency. Therefore, the energy of the non-resonant frequency continuously decays due to the loop phase shift deviating from 360°, while the energy of the resonant frequency, due to the characteristic of the entire loop's 360° phase shift, will continuously undergo frequency selection and amplification, always maintaining frequency lock. Therefore, the frequency locking circuit device described in this embodiment of the invention can always lock the operating frequency of the entire system at the inherent resonant frequency of the target load P itself, ensuring that the target load P can always maintain the highest power output and the highest efficiency output.

[0170] The frequency locking circuit device and control method provided in this invention can at least partially solve the technical problems of high energy loss, low overall efficiency, poor frequency locking stability, high cost and large size caused by circuit complexity in related technologies, and thus can achieve at least one of the following technical effects:

[0171] (1) First, by constructing a 360° phase-shifted frequency-locking feedback loop, the resonant frequency of the target load can be accurately locked, which can realize an adaptive frequency-locking mechanism with higher response speed, effectively ensure the maximum working efficiency of the target load, significantly improve the working efficiency and working stability of the target load, and at the same time, it can dynamically adjust the frequency-locking of the target LC resonant frequency according to the individual characteristics and life changes of the target load, realize automatic tracking and stable driving of the resonant frequency, further ensure its frequency-locking stability, and achieve the effect of dynamic frequency-locking.

[0172] (2) In addition, in the frequency locking circuit device in the embodiments of the present invention, the more complex circuit design usually used in the existing digital sampling and phase-locked loop frequency locking scheme can be directly eliminated, thereby effectively avoiding additional power loss and efficiency loss caused by the presence of complex circuit components, greatly saving costs, further improving the operating power of the target load (such as a piezoelectric ceramic air pump), and greatly improving working efficiency.

[0173] (3) Furthermore, the application of ADC converter and MCU microcontroller can be eliminated. On this basis, there is no need for other circuit components to cooperate with them. This greatly simplifies the composition of the frequency locking circuit structure. Efficient and accurate frequency locking dynamic control can be achieved based only on basic circuit components such as integral phase shift and drive bridge. This further reduces the power consumption caused by complex circuit components in the system, and also significantly reduces the circuit cost and overall circuit size (such as the area occupied).

[0174] Therefore, the frequency locking circuit device and control method described in the embodiments of the present invention can be more widely adapted to the needs of small and high-efficiency scenarios. Even under the current chip manufacturing process level, it can be better applied to high-precision electronic products (such as micro heat sinks for automotive chips or mobile phone chips) or equipment (such as micro heat sinks for extreme ultraviolet light source chips in lithography machines), so that its chips can achieve the same or even better operating capabilities as chips with higher chip manufacturing processes, and have a very wide range of product applications.

[0175] Therefore, the frequency locking circuit device and its control method based on the embodiments of the present invention can provide a dynamic frequency locking technology that is more efficient, more stable, lower power consumption, lower cost, more practical, and easier to implement and promote compared with existing frequency locking schemes. It can accurately lock the optimal resonant frequency of existing micro heat dissipation devices such as piezoelectric ceramic air pumps, and has extremely important practical value and economic benefits.

[0176] Based on the above-described frequency-locking circuit device, the present invention also provides a control method for the frequency-locking circuit device. The following will be combined with... Figures 1-3B The control method is described in detail.

[0177] Figure 4 The diagram illustrates an application scenario of a control method, apparatus, device, medium, and program product for a frequency-locking circuit device according to an embodiment of the present invention.

[0178] like Figure 4 As shown, application scenario 400 according to this embodiment may include terminal devices 401, 402, and 403, a network 404, and a server 405. Network 404 serves as a medium for providing a communication link between terminal devices 401, 402, and 403 and server 405. Network 404 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0179] Users can use terminal devices 401, 402, and 403 to interact with server 405 via network 404 to receive or send messages, etc. Various communication client applications can be installed on terminal devices 401, 402, and 403, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social media platform software, etc. (for example only).

[0180] Terminal devices 401, 402, and 403 can be various electronic devices with displays that support web browsing, including but not limited to smartphones, tablets, laptops, and desktop computers.

[0181] Server 405 can be a server that provides various services, such as a backend management server that supports websites browsed by users using terminal devices 401, 402, and 403 (for example only). The backend management server can analyze and process data such as received user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0182] It should be noted that the control method of the frequency locking circuit device provided in the embodiments of the present invention can generally be executed by server 405. Correspondingly, the control device of the frequency locking circuit device provided in the embodiments of the present invention can generally be located in server 405. The control method of the frequency locking circuit device provided in the embodiments of the present invention can also be executed by a server or server cluster that is different from server 405 and capable of communicating with terminal devices 401, 402, 403 and / or server 405. Correspondingly, the control device of the frequency locking circuit device provided in the embodiments of the present invention can also be located in a server or server cluster that is different from server 405 and capable of communicating with terminal devices 401, 402, 403 and / or server 405.

[0183] It should be understood that Figure 4 The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0184] The following will be based on Figure 4 The described scene, through Figure 5 The control method of the frequency locking circuit device of the disclosed embodiments will be described in detail.

[0185] like Figure 5As shown, another aspect of the present invention provides a control method for the above-described frequency-locking circuit device, applied to the resonant frequency locking of a target load, wherein the frequency-locking circuit device includes an integral phase-shift module and a drive control module for forming a self-oscillating loop with a gain greater than or equal to 1, wherein the control method of the frequency-locking circuit device 100 includes operations S501 to S502.

[0186] In operation S501, a current integrated phase-shifted signal is generated by integrating and phase-shifting the current working electrical signal at the first end of the target load; wherein, the current integrated phase-shifted signal achieves a 360° phase shift relative to the current working electrical signal;

[0187] In operation S502, the current operating electrical signal of the target load is updated according to the current integral phase shift signal to achieve resonant frequency locking.

[0188] To enable those skilled in the art to understand the above-mentioned Figure 5 The frequency locking circuit devices 100 and 100' shown in the embodiment of the present invention (e.g., Figures 1-3B The control method shown in the figure has a clearer understanding. Based on a specific implementation case where the target load P is a piezoelectric ceramic air pump, the operation process S511-S516 of this control method is explained in detail as follows:

[0189] In operation S511, the working current of the piezoelectric ceramic air pump P can be converted into a voltage signal as the current working electrical signal by using a resistor as the first sensing unit 102.

[0190] Then, in operation S512, the first integration unit 301 is used as the first-stage integrator to perform the first-stage integration phase shift on the current working electrical signal of the differential input, and a first-stage integrated phase shift signal (i.e., voltage signal) with a 90° phase shift is obtained.

[0191] Subsequently, in operation S513, the first integral phase-shift signal is DC-isolated by DC signal drift through the third capacitor C3 and the fourth capacitor C4, and then connected to a preset bias power supply V. REF The signal biasing effect of the third resistor R3 and the fourth resistor R4 can input the first integration unit 302, which is the second-stage integrator, to complete the isolation and biasing of the first integration phase shift signal (i.e., AC signal, Alternating Current, abbreviated as AC).

[0192] Furthermore, in operation S514, the AC signal undergoes a second-stage phase shift through the second-stage integration phase shift of the second integration unit 302, generating a second integrated phase shift signal with a 90° phase shift. At this point, the second-stage phase shift signal has a 180° phase shift with the actual operating current signal of the original piezoelectric ceramic pump P.

[0193] Subsequently, in operation S515, the second integral phase shift signal is input to the waveform conversion unit 303 (i.e., the comparator), which can convert the second integral phase shift signal of the sine wave signal into a square wave signal.

[0194] Furthermore, in operation S516, the square wave signal is inverted again by the phase conversion unit 304, so that the current integrated phase shift signal output by the integration phase shift module 103 has a 360° phase shift relative to the actual working electrical signal of the original piezoelectric ceramic air pump P, forming positive feedback.

[0195] At this time, with the help of the current integral phase shift signal with 360° phase shift, the drive control module 104 can drive the full bridge drive unit 404 or the half bridge drive structure, realize the pull-up or pull-down modulation of both ends of the piezoelectric ceramic air pump, and the entire loop has a gain greater than 1, which can realize self-oscillation.

[0196] In this embodiment of the invention, the self-oscillating loop formed by the frequency-locking circuit device controls the piezoelectric ceramic pump P to operate at its resonant frequency. This results in minimal phase shift between the voltage and current of the piezoelectric ceramic pump P, minimal impedance, and maximum output power. In other words, the pump itself possesses a resonant frequency selection function similar to an RLC circuit. Because the two-stage integration of the first integrator 301 and the second integrator 302 generates a 180-degree phase shift, coupled with the 180-degree inversion logic of the subsequent phase conversion unit 304, the driving voltage and current of the piezoelectric ceramic pump P maintain a 360-degree phase shift only when the entire system operates at its resonant frequency. Therefore, the energy at non-resonant frequencies continuously attenuates due to the loop phase shift deviating from 360 degrees, while the energy at resonant frequencies, due to the 360-degree phase shift of the entire loop, is continuously amplified through frequency selection, maintaining a dynamic lock on the true inherent resonant frequency. Thus, this loop design locks the operating frequency clock of the piezoelectric ceramic pump P at the pump's own true inherent resonant frequency, ensuring that the pump always maintains the highest power output and the highest efficiency output.

[0197] The beneficial effects of the control method of the frequency locking circuit device 100 in the above embodiments of the present invention can be referred to the relevant description of the frequency locking circuit device 100, which will not be repeated here.

[0198] Figure 6 A block diagram of an electronic device suitable for implementing a frequency-locking circuit device according to an embodiment of the present invention is shown schematically.

[0199] The electronic device provided in the embodiments of the present invention includes one or more processors and a memory, wherein the memory is used to store one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors execute the control method of the frequency locking circuit device described above.

[0200] like Figure 6 As shown, an electronic device 600 according to an embodiment of the present invention includes a processor 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage portion 608 into a random access memory (RAM) 603. The processor 601 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 601 may also include onboard memory for caching purposes. The processor 601 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0201] RAM 603 stores various programs and data required for the operation of electronic device 600. Processor 601, ROM 602, and RAM 603 are interconnected via bus 604. Processor 601 executes various operations of the method flow according to embodiments of the present invention by executing programs in ROM 602 and / or RAM 603. It should be noted that the programs may also be stored in one or more memories other than ROM 602 and RAM 603. Processor 601 may also execute various operations of the method flow according to embodiments of the present invention by executing programs stored in said one or more memories.

[0202] According to an embodiment of the present invention, the electronic device 600 may further include an input / output (I / O) interface 605, which is also connected to a bus 604. The electronic device 600 may also include one or more of the following components connected to the I / O interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 610 as needed so that computer programs read from it can be installed into the storage section 608 as needed.

[0203] The present invention also provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the control method of the frequency locking circuit device described above.

[0204] The computer-readable storage medium may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0205] According to embodiments of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of the present invention, a computer-readable storage medium may include ROM 602 and / or RAM 603 and / or one or more memories other than ROM 602 and RAM 603 described above.

[0206] Embodiments of the present invention also include a computer program product comprising a computer program that, when executed by a processor, implements the control method of the frequency locking circuit device described above.

[0207] The computer program includes program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to enable the computer system to implement the methods provided in the embodiments of the present invention.

[0208] When the computer program is executed by the processor 601, it performs the functions defined in the system / apparatus of this invention. According to embodiments of the invention, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0209] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via the communication section 609, and / or installed from the removable medium 611. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0210] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 609, and / or installed from the removable medium 611. When the computer program is executed by the processor 601, it performs the functions defined in the system of this embodiment of the invention. According to embodiments of the invention, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0211] According to embodiments of the present invention, program code for executing the computer programs provided in the embodiments of the present invention can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0212] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0213] Furthermore, all actions involving the acquisition of information, signals, or data in this invention are carried out in compliance with the relevant data protection laws, regulations, and policies of the country where the invention is located, and with the authorization granted by the owner of the corresponding device.

[0214] Those skilled in the art will understand that the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0215] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A frequency-locking circuit device, used for locking the resonant frequency of a target load, characterized in that, include: An integral phase-shift module is used to generate a current integral phase-shift signal by integrating and phase-shifting the current operating electrical signal at one end of the target load; wherein the current integral phase-shift signal is phase-shifted by 360° relative to the current operating electrical signal; A drive control module, which is connected to the output of the integral phase shift module, is used to update the current working electrical signal of the target load according to the current integral phase shift signal, forming a self-oscillating loop with a gain greater than or equal to 1, so as to achieve the resonant frequency locking. A signal feedback unit, connected in parallel with the target load, is used to provide feedback on the direction of the current working electrical signal; The first sensing unit is connected in series with the target load and is used to detect the current working electrical signal; The integral phase shift module includes: A first integrating unit, whose input terminals are connected to the two ends of the first sensing unit in a differential input configuration, is used to perform a first integration phase shift on the current working electrical signal to generate a first integrated phase-shift signal. The first integrating unit further includes a first integrating amplifier and a first capacitor. The first input terminal of the first integrating amplifier is connected to one end of the first sensing unit, and its second input terminal is connected to the other end of the first sensing unit. One end of the first capacitor is connected to the first output terminal of the first integrating amplifier, and its other end is connected to the second output terminal of the first integrating amplifier. The second integrator unit has its input terminal connected to the output terminal of the first integrator unit in a differential input configuration. It is used to perform a second integration phase shift on the first integrated phase shift signal to generate a second integrated phase shift signal. The second integrator unit includes a second integrator amplifier and a second capacitor. The first input terminal of the second integrator amplifier is connected to the first output terminal of the first integrator unit, and its second input terminal is connected to the second output terminal of the first integrator unit. One end of the second capacitor is connected to the first output terminal of the second integrator amplifier, and the other end is connected to the second output terminal of the second integrator amplifier.

2. The frequency locking circuit device according to claim 1, characterized in that, The integral phase shift module further includes: The waveform conversion unit has its input terminal connected to the output terminal of the second integration unit in a differential input form, and is used to perform waveform conversion processing on the second integrated phase shift signal to generate a waveform conversion signal; A phase conversion unit, whose input is connected to the output of the waveform conversion unit, is used to perform phase conversion processing on the waveform conversion signal to generate the current integral phase shift signal.

3. The frequency locking circuit device according to claim 2, characterized in that, The first integration unit further includes: The first resistor has one end connected to the first output terminal of the first integrating amplifier and the other end connected to the second output terminal of the first integrating amplifier. The first resistor and the first capacitor are connected in parallel.

4. The frequency locking circuit device according to claim 2, characterized in that, The second integration unit also includes: The second resistor has one end connected to the first output terminal of the second integrating amplifier and the other end connected to the second output terminal of the second integrating amplifier. The second resistor and the second capacitor are connected in parallel.

5. The frequency locking circuit device according to claim 2, characterized in that, The integral phase shift module further includes: The signal processing unit, whose input is connected to the output of the first integration unit, is used to perform signal biasing and signal isolation processing on the first integrated phase-shift signal.

6. The frequency locking circuit device according to claim 5, characterized in that, The signal processing unit includes a signal isolator for performing signal isolation processing on the first integral phase-shift signal, the signal isolator comprising: The third capacitor has one end connected to the first output terminal of the first integration unit and the other end connected to the first input terminal of the second integration unit. The fourth capacitor has one end connected to the second output terminal of the first integrator and the other end connected to the second input terminal of the second integrator.

7. The frequency locking circuit device according to claim 6, characterized in that, The signal processing unit includes a signal biaser for performing signal biasing processing on the first integral phase-shift signal, the signal biaser comprising: The third resistor has one end connected to the first output terminal of the first integration unit and the first input terminal of the second integration unit; The fourth resistor has one end connected to the second output terminal of the first integrator and the second input terminal of the second integrator, and the other end connected to the other end of the third resistor and connected to a preset bias voltage.

8. The frequency locking circuit device according to any one of claims 2-7, characterized in that, The drive control module includes: The first inverting unit has its input terminal connected to the output terminal of the phase conversion unit, and is used to invert the current integrated phase shift signal to generate an inverted processed signal. The first driving unit has its input terminal connected to the output terminal of the first inverting unit, and is used to generate a first driving signal and a second driving signal according to the inverting processing signal. The second driving unit has its input terminal connected to the output terminal of the phase conversion unit, and is used to generate a third driving signal and a fourth driving signal according to the current integrated phase shift signal; The full-bridge drive unit has its input terminal connected to the output terminal of the first drive unit and the output terminal of the second drive unit, and is used to control the preset input power supply connected to the full-bridge drive unit to update the current working electrical signal applied to the target load according to the first drive signal, the second drive signal, the third drive signal and the fourth drive signal.

9. The frequency locking circuit device according to claim 8, characterized in that, The first driving unit includes two inverters connected in parallel, and the second driving unit includes two inverters connected in parallel.

10. The frequency locking circuit device according to claim 8, characterized in that, The full-bridge drive unit includes: The first transistor has its gate connected to the first output terminal of the first driving unit, its source connected to the preset input power supply, and its drain connected to the first sensing unit, and is used to control the conduction and disconnection of the first transistor according to the first driving signal. The second transistor has its gate connected to the second output terminal of the first driving unit, its source grounded, and its drain connected to the drain of the first transistor, and is used to control the second transistor to turn on and off according to the second driving signal. The third transistor has its gate connected to the first output terminal of the second driving unit, its source connected to the preset input power supply, and its drain connected to the target load, and is used to control the conduction and disconnection of the third transistor according to the third driving signal. The fourth transistor has its gate connected to the second output terminal of the second driving unit, its source grounded, and its drain connected to the drain of the third transistor, and is used to control the conduction and disconnection of the fourth transistor according to the fourth driving signal.

11. The frequency locking circuit device according to any one of claims 2-7, characterized in that, The drive control module includes: The second inverting unit has its input connected to the output of the phase conversion unit and is used to invert the current integral phase shift signal to generate the fifth driving signal. The fifth transistor has its gate connected to the output terminal of the second inverting unit, its source grounded, and its drain connected to the target load, and is used to control the conduction and disconnection of the fifth transistor according to the fifth driving signal; The sixth transistor has its gate connected to the output of the phase conversion unit and its source grounded, and is used to control the conduction and disconnection of the sixth transistor according to the current integral phase shift signal; The seventh transistor has its gate connected to the drain of the sixth transistor, its source connected to a preset input power supply and used to connect to the gate of the seventh transistor, and its drain connected to the target load. One end of the first sensing unit is connected to a reference input power supply, and the other end is connected to the target load.

12. The frequency locking circuit device according to claim 11, characterized in that, The drive control module also includes: The fifth resistor has one end connected to the source of the sixth transistor and the other end grounded. The sixth resistor has one end connected to the gate of the seventh transistor and the drain of the sixth transistor, and the other end connected to the source of the seventh transistor and a preset input power supply.

13. A control method for a frequency-locking circuit device according to any one of claims 1-12, applied to locking the resonant frequency of a target load, characterized in that, The frequency locking circuit device includes an integral phase shift module and a drive control module, used to form a self-oscillating loop with a gain greater than or equal to 1. The control method includes: A current integrated phase-shifted signal is generated by integrating and phase-shifting the current operating electrical signal at the first end of the target load; wherein the current integrated phase-shifted signal is phase-shifted by 360° relative to the current operating electrical signal. The current operating electrical signal of the target load is updated based on the current integral phase shift signal to achieve the resonant frequency lock.

14. An electronic device comprising: One or more processors; Memory, used to store one or more programs. Wherein, when the one or more programs are executed by the one or more processors, the one or more processors perform the method of claim 13.

15. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the method of claim 13.

16. A computer program product comprising a computer program that, when executed by a processor, implements the method of claim 13.

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