Compact logic cell using complete backside connectivity

Abstract

Compact logic cells using complete backside connectivity are disclosed. In one aspect, a semiconductor device includes a plurality of integrated circuit cells including gates separated by source / drain (S / D) structures and including at least one channel extending through a metal structure and connecting adjacent S / D structures to each other, at least one gate forms a gate-all-around field effect transistor; an FS contact electrically connected to the S / D structure; an FS contact electrically connected to the gate electrode; a front side (FS) interlayer dielectric (ILD), the front side (FS) interlayer dielectric (ILD) being on the gate and the S / D structure; the FS zero layer metal interconnects are arranged on the FS-ILD, and one of the FS zero layer metal interconnects is electrically connected to the FS contact element; a BS contact electrically connected to the S / D structure; a BS contact electrically connected to the gate electrode; a backside (BS) ILD disposed on the gate and the S / D structure; and a BS zero layer metal interconnect disposed on the BS-ILD, one of the BS zero layer metal interconnects being electrically connected to the BS contact.

Description

Background Technology

[0001] 1. Technical Field

[0002] This disclosure relates generally to semiconductor wafer processes, and more specifically to compact logic cells using full back-side connectivity and methods for manufacturing the same.

[0003] 2. Related technical descriptions

[0004] Integrated circuit (IC) technology has made significant strides in improving computing power through the miniaturization of electrical components. IC devices can be implemented as IC chips, which have a set of circuits integrated on them, including multiple active and passive components (e.g., transistors, diodes, capacitors, inductors, and / or resistors) and layers of contacts and interconnects above the active and passive components. In some aspects, the contacts and interconnects of an IC device are formed on the active and passive components on the front side of the IC device. As the size of the IC device and the components formed on it decreases, the available area for forming the contacts and interconnects also decreases. Therefore, the routing complexity of the contacts and interconnects and / or the routing complexity of parasitic resistances and capacitances may increase, and thus the manufacturing cost or performance of the IC device may be negatively affected. Summary of the Invention

[0005] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed description presented below.

[0006] In one aspect, a semiconductor device includes: a plurality of integrated circuit cells, each of the plurality of integrated circuit cells including: a plurality of gate structures, the plurality of gate structures being spaced apart from each other by one of a first plurality of source / drain (S / D) structures, each gate structure including a channel structure and a metal gate structure, the channel structure including at least one channel extending through the metal gate structure and connecting adjacent S / D structures of the first plurality of S / D structures to each other, wherein at least one of the plurality of gate structures forms a full-around gate (G gate). AA) Field-Effect Transistor (FET); Front-Side Source / Drain Contact (FSDC) structure electrically connected to the top surface of at least one of the first plurality of S / D structures; Front-Side Contact Above Active Gate (FSCOAG) structure electrically connected to the top surface of at least one of the plurality of gate structures; Front-Side Interlayer Dielectric (FS-ILD) layer disposed on the plurality of gate structures and the first plurality of S / D structures. Structurally, it includes: a front zero-layer metal (FMO) interconnect layer disposed on the FS-ILD layer, comprising a plurality of parallel FMO interconnects, at least one of which is electrically connected to the FSDC structure or the FSCOAG structure; a back-side source / drain contact (BSDC) structure electrically connected to the bottom surface of at least one of the first plurality of S / D structures; and an active gate over-back contact (BSCOAG) structure. A backside contact (BSCOAG) structure is electrically connected to the bottom surface of at least one of the plurality of gate structures; a backside interlayer dielectric (BS-ILD) layer is disposed on the plurality of gate structures and the first plurality of S / D structures; and a backside zero-layer metal (BM0) interconnect layer is disposed on the BS-ILD layer, the backside zero-layer metal (BM0) interconnect layer includes a plurality of parallel BMO interconnects, at least one of the parallel BMO interconnects being electrically connected to the BSDC structure or the BSCOAG structure.

[0007] In one aspect, a method for manufacturing a semiconductor device includes providing a plurality of integrated circuit cells, wherein for each of the plurality of integrated circuit cells, the providing includes: providing a plurality of gate structures spaced apart from each other by one of a first plurality of S / D structures, each gate structure including a channel structure and a metal gate structure, the channel structure including at least one channel extending through the metal gate structure and connecting adjacent S / D structures of the first plurality of S / D structures to each other, wherein at least one of the plurality of gate structures forms a GAA (Gate Alignment). The device includes: a FET; an FSDC structure electrically connected to the top surface of at least one of the first plurality of S / D structures; an FSCOAG structure electrically connected to the top surface of at least one of the plurality of gate structures; an FS-ILD layer disposed on the plurality of gate structures and the first plurality of S / D structures; and an FMO interconnect layer disposed on the FS-ILD layer, the FMO interconnect layer including a plurality of parallel FMO interconnects, at least one of the plurality of parallel FMO interconnects being electrically connected to the FSDC structure or the FSCOAG structure. The system provides a BSDC structure electrically connected to the bottom surface of at least one of the first plurality of S / D structures; a BSCOAG structure electrically connected to the bottom surface of at least one of the plurality of gate structures; a BS-ILD layer disposed on the plurality of gate structures and the first plurality of S / D structures; and a BMO interconnect layer disposed on the BS-ILD layer, the BMO interconnect layer including a plurality of parallel BMO interconnects, at least one of the plurality of parallel BMO interconnects being electrically connected to the BSDC structure or the BSCOAG structure.

[0008] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0009] A more complete understanding of the various aspects of this disclosure and its many accompanying advantages will be readily available when considered in conjunction with the following detailed description taken in conjunction with the accompanying drawings, wherein similar reference numerals denote similar parts, and the drawings are given for illustrative purposes only and do not constitute any limitation on this disclosure.

[0010] Figure 1A It is a plan view of a portion of the conventional semiconductor structure of an integrated circuit (IC) device without back-side power supply or signal wiring.

[0011] Figure 1B This is an example of... Figure 1A A schematic diagram of the circuit built using the illustrated semiconductor structure.

[0012] Figure 1C This is a plan view of a conventional 5T integrated circuit cell with only front-side M0 connections.

[0013] Figure 2 A simplified plan view of a compact logic cell using full back-side connectivity is illustrated according to various aspects of this disclosure.

[0014] Figure 3A and Figure 3B This is a plan view of a portion of the semiconductor structure of an IC device according to various aspects of this disclosure, wherein elements are highlighted in different vertical regions.

[0015] Figures 3C to 3E This is a cross-sectional view of the semiconductor structure of an IC device according to various aspects of this disclosure.

[0016] Figures 4A to 4D This is a cross-section illustrating the steps in the process of manufacturing an active gate above back side contact (BSCOAG) and / or a back side gate contact (BSGC) for full back side connectivity according to various aspects of this disclosure.

[0017] Figure 5 Examples are provided comparing conventional integrated circuit cell duplexes according to various aspects of this disclosure with integrated circuit cell duplexes using compact logic cells with full back-side connectivity.

[0018] Figure 6 This is a schematic diagram of a two-input XOR circuit implemented as a compact logic unit using full back-side connectivity according to various aspects of this disclosure.

[0019] Figure 7A and Figure 7B It is a plan view of a compact XOR integrated circuit cell according to various aspects of this disclosure.

[0020] Figure 8A and Figure 8B This is a flowchart illustrating portions of an example process 800 associated with the use of full back-side connectivity to manufacture a compact logic cell according to various aspects of this disclosure.

[0021] Figure 9 Mobile devices according to some examples of this disclosure are illustrated.

[0022] Figure 10 Various electronic devices that can be integrated with any of the aforementioned integrated devices or semiconductor devices are illustrated according to various examples of this disclosure.

[0023] By convention, the features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0024] A compact logic cell using full back-side connectivity and a method for manufacturing the same are disclosed. In one aspect, a semiconductor device includes a plurality of integrated circuit cells. Each of the plurality of integrated circuit cells includes: a plurality of gate structures spaced apart from each other by one of a first plurality of source / drain (S / D) structures, each gate structure including a channel structure and a metal gate structure, the channel structure including at least one channel extending through the metal gate structure and connecting adjacent S / D structures in the first plurality of S / D structures to each other; a front-side interlayer dielectric (FS-ILD) layer disposed on the plurality of gate structures and the first plurality of S / D structures; and a front-side zero metal layer. A front-side zero-layer metal (FMO) interconnect layer is disposed on the FS-ILD layer, and the front-side zero-layer metal (FMO) interconnect layer includes a plurality of parallel FMO interconnects; a back-side interlayer dielectric (BS-ILD) layer is disposed on the plurality of gate structures and the plurality of first S / D structures; a back-side zero-layer metal (BMO) interconnect layer is disposed on the BS-ILD layer, and the back-side zero-layer metal (BMO) interconnect layer includes a plurality of parallel BMO interconnects; at least one front-side source / drain contact (FSDC) structure. The at least one front-side source / drain contact (FSDC) structure electrically connects one of the plurality of parallel FMO interconnects to the top surface of at least one of the plurality of S / D structures; the at least one active gate-above front-side contact (FSCOAG) structure electrically connects one of the plurality of parallel FMO interconnects to the top surface of at least one of the plurality of gate structures; the at least one back-side source / drain contact (BSDC) structure, the at least one back-side source / drain contact... A drain contact (BSDC) structure electrically connects one of the plurality of parallel BMO interconnects to the bottom surface of at least one of the plurality of S / D structures; and at least one active gate above back side contact (BSCOAG) structure electrically connects one of the plurality of parallel BMO interconnects to the bottom surface of at least one of the plurality of gate structures, wherein at least one of the plurality of gate structures forms a gate all around (GAA) field-effect transistor (FET).

[0025] Various aspects of this disclosure are provided in the following description and accompanying drawings of various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of this disclosure. Additionally, well-known elements of this disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of this disclosure.

[0026] The overall scope relates to integrated circuit devices and methods for manufacturing such integrated circuit devices. Some aspects more specifically relate to integrated circuit devices, novel active gate-above back-side contacts, and novel shallow trench isolation-above back-side gate contacts. These contacts are suitable for all-around gate structures and are compatible with back-side power distribution networks.

[0027] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. Back-side gate contacts constructed using unique manufacturing processes allow back-side connections to field-effect transistor (FET) gates via an active gate region or via shallow trench isolation (STI), including a gate-all-around (GAA) topology. The former is referred to herein as an over-the-gate back-side contact (BSCOAG), and the latter as a back-side gate contact (BSGC). Both gate contact structures provide a pathway to the back side of an integrated circuit cell (e.g., a standard cell) for signal routing. In contrast, conventional integrated circuit cell designs have back-side connections used only for power routing and not for signal routing. The use of back-side signal routing allows for a reduction in integrated circuit cell size and a reduction in parasitic resistance and capacitance, thereby improving integrated circuit cell performance and reducing area / cell compactness.

[0028] The terms “exemplary” and / or “example” are used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” and / or “example” is not necessarily to be construed as superior to or better than other aspects. Similarly, the term “aspects of this disclosure” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed.

[0029] Those skilled in the art will understand that any of a variety of different techniques and methods can be used to represent the information and signals described below. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the following description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof, depending in part on the specific application, in part on the desired design, in part on the corresponding technology, and so on.

[0030] Furthermore, many aspects are described according to a sequence of actions to be performed by elements of, for example, a computing device. It will be appreciated that the various actions described herein can be performed by specific circuitry (e.g., an application-specific integrated circuit (ASIC)), by program instructions executed by one or more processors, or by a combination of both. Additionally, the sequence of actions described herein can be considered to be entirely embodied in any form of non-transitory computer-readable storage medium storing a corresponding set of computer instructions that, when executed, will cause or command the associated processor of the device to perform the functionality described herein. Therefore, various aspects of this disclosure can be embodied in a variety of different forms, all of which are contemplated within the scope of the claimed subject matter. Furthermore, for each aspect described herein, any corresponding form of any such aspect may be described herein as, for example, "logic configured to perform the described actions."

[0031] Figure 1A This is a plan view of a portion of the semiconductor structure 100 of a conventional integrated circuit (IC) device without back-side power or signal wiring. In some respects, Figure 1A Some components of the semiconductor structure 100 are shown for illustrative purposes only, and Figure 1A Other elements above and / or below the shown element can be set, but Figure 1A Not shown in the image.

[0032] like Figure 1A As shown, the semiconductor structure 100 includes gate stacks 102, 104, and 106 spaced apart along a first direction (e.g., the x-direction) and cut to have lengths along a second direction (e.g., the y-direction). The semiconductor structure 100 also includes a source / drain (S / D) structure 108 between gate stacks 102 and 104, an S / D structure 110 between gate stacks 104 and 106, an S / D structure 112 between gate stacks 102 and 104, and an S / D structure 114 between gate stacks 104 and 106. S / D structures 108 and 112 are separated from each other in the second direction (e.g., the y-direction), and S / D structures 110 and 114 are also separated from each other in the second direction (e.g., the y-direction).

[0033] A portion of the gate stack 104 adjacent to the S / D structures 108 and 110 can be configured as a first gate structure, and a first channel structure can be formed through the first gate structure in a first direction. The S / D structures 108 and 110 can be electrically coupled to the first channel structure. Additionally, a portion of the gate stack 104 adjacent to the S / D structures 112 and 114 can be configured as a second gate structure, and a second channel structure can be formed through the second gate structure in a first direction. The S / D structures 112 and 114 can be electrically coupled to the second channel structure. In some aspects, the S / D structures 108 and 110 may have a first doping type, and the S / D structures 112 and 114 may have a second doping type different from the first doping type.

[0034] In some aspects, the first gate structure, the first channel structure, the S / D structure 108, and the S / D structure 110 can be configured as a first transistor of a first type; and the second gate structure, the second channel structure, the S / D structure 112, and the S / D structure 114 can be configured as a second transistor of a second type. In some aspects, the gate stacks 102 and 106 can be configured as dummy gates, which will be biased to electrically isolate the S / D structures 108, 110, 112, and 114 from adjacent S / D structures (not shown).

[0035] like Figure 1A As shown, the semiconductor structure 100 includes an S / D contact 116 electrically coupled to an S / D structure 108, an S / D contact 118 electrically coupled to S / D structures 110 and 114, and an S / D contact 120 electrically coupled to an S / D structure 112. The semiconductor structure 100 includes a first conductive structure 122, a second conductive structure 124, a third conductive structure 126, a fourth conductive structure 128, a fifth conductive structure 130, and a sixth conductive structure 132. The semiconductor structure 100 also includes a front contact 134 electrically coupling the S / D contact 116 to the first conductive structure 122, a front contact 136 electrically coupling the S / D contact 120 to the sixth conductive structure 132, a gate contact 138 electrically coupling the gate stack 104 to the fourth conductive structure 128, and a front contact 140 electrically coupling the S / D contact 118 to the second conductive structure 124.

[0036] Figure 1B This is a schematic diagram illustrating a circuit implemented by semiconductor structure 100. In some aspects, Figure 1AA portion of the semiconductor structure 100 shown forms an inverter and can be used as an integrated circuit cell for manufacturing an inverter in an IC device. In some aspects, the first conductive structure 122 may be a first power line configured to carry a first power supply voltage (e.g., VDD), and the sixth conductive structure 132 may be a second power line configured to carry a second power supply voltage (e.g., VSS or ground). In some aspects, the fourth conductive structure 128 may be a signal line configured to carry gate voltages for controlling the first gate structure of the first transistor and the second gate structure of the second transistor, such as the IN pin of the inverter. In some aspects, the second conductive structure 124 may be a signal line configured to carry S / D voltages at the S / D structure 110 of the first transistor and the S / D structure 114 of the second transistor, such as the OUT pin of the inverter.

[0037] Figure 1C This is a plan view of a standard 5T integrated circuit unit 142. Figure 1A and Figure 1B The inverter in the cell can be constructed from it. Cell 142 has a cell height. h (In the Y direction) and only on the front side of the cell, there are six wiring rails, shown as metal lines with length in the X direction and width in the Y direction, and these may correspond to conductive structures 122, 124, 126, 128, 130, and 132. The top wiring rail (e.g., the first conductive structure 122) and the bottom wiring rail (e.g., the sixth conductive structure 132) are shared with any integrated circuit cells placed above or below cell 142 (e.g., adjacent cells with a positive or negative offset in the Y direction compared to cell 142), leaving only the middle four rails (e.g., conductive structures 124, 126, 128, and 130) available for internal wiring. These internal wiring rails in Figure 1C These are numbered I1 through I4. Shared rails are typically used for power and ground. Routing rails are usually created in the metal layer closest to the chip substrate, often referred to as the zero metal layer (M0). In an integrated circuit cell library, M0 is typically reserved for wiring within the integrated circuit cell, and the metal layers above M0 (e.g., M1, M2, etc.) are used for cell-to-cell wiring.

[0038] Scaling down integrated circuit cells and other integrated circuits (reducing their size) offers advantages, including smaller chip size, faster operating speeds, and lower power consumption. One approach is to reduce the height of the integrated circuit cells. hHowever, this requires removing one or more wiring rails, resulting in 4T IC cells, 3T IC cells, etc., which reduces the availability of M0 resources. If there are not enough internal wiring resources due to the reduced cell height, the cell width must be increased to accommodate the internal wiring, a higher metal layer must be used for the internal wiring (which may interfere with cell-to-cell connections), or both of the above. In some cases, for complex cells, the IC cell width (typically measured in CPP) must be increased by 25% to 50%. Therefore, the cell area may be the same as or larger than the same circuit implemented in a 5T IC cell, meaning that the advantage of reducing cell height is offset by the requirement to increase cell width. Therefore, one of the disadvantages of a conventional IC cell such as cell 142 is that the number of M0 resources is limited.

[0039] Therefore, there is a need for integrated circuits that overcome the shortcomings of conventional standard cell designs and other integrated circuits. This paper proposes a compact logic cell (including double M0 wiring resources) using full back-side connectivity and its fabrication method.

[0040] Figure 2 A simplified plan view of a compact logic cell using full back-side connectivity is illustrated according to various aspects of this disclosure. Figure 2 Examples include 5T unit 200, 4T unit 202, and 3T unit 204, each characterized by MO wiring resources on both the front and rear sides of the unit. For example, 5T unit 200 includes front-side internal wiring rails I1 to I4 and rear-side internal wiring rails I5 to I8. 4T unit 202 has front-side internal wiring rails I1 to I3 (which may be referred to herein as a dense MO backplane) and rear-side internal wiring rails I4 to I6 (which may be referred to herein as a dense BMO backplane). The combination of dense MO backplanes and dense BMO backplanes may be referred to herein as a rear-side connectivity package.

[0041] The 3T unit 204 has front-side internal wiring rails I1 to I2 and rear-side internal wiring rails I3 to I4. Therefore, the compact 4T unit 202 has six rails available for internal wiring. Figure 1C Compared to the conventional cell 142, the compact 3T cell 204 offers 50% more internal wiring rails while having only 80% of the height of the conventional cell 142. Similarly, the compact 3T cell 204 has the same number of internal wiring rails as the conventional cell 142, but only 60% of the height of the conventional cell 142. It can be seen that the compact integrated circuit cells 202 and 204 offer the same or more internal wiring rails as cell 142, but with a 20% to 40% reduction in cell height compared to the conventional cell 142, while the 5T cell 200 has the same height as the conventional cell 142, but its internal wiring resources are twice that of the conventional cell 142.

[0042] The following figures illustrate the front and rear connections that can utilize internal cabling resources, namely the front internal cabling rails I1 to I4 and the rear internal cabling rails I5 to I8.

[0043] Figure 3A and Figure 3B This is a plan view of a portion of the semiconductor structure 300 of an IC device according to various aspects of this disclosure, emphasizing elements in different vertical regions. Specifically, Figure 3A The element shown illustrates that, when viewed from the front, it can be located in the vertical direction (e.g., the z-direction corresponding to the direction away from the drawing plane). Figure 3B The element shown is above the element. In some respects, Figure 3A and Figure 3B Some components of the semiconductor structure 300 are shown for illustrative purposes only, and Figure 3A and Figure 3B Other elements above and / or below the shown element may be positioned Figure 3A and Figure 3B In, but not shown in these two figures.

[0044] Figure 3A and Figure 3B The diagram shows portions of two integrated circuit cells (cells 302 and 304) placed side-by-side. Each cell has multiple gate structures 306, a first set of S / D structures 308, and a second set of S / D structures 310. In some respects, the S / D structures are epitaxial (EPI) structures. For ease of description, the gate structures 306 are labeled G1, G2, G3, G4, and G5. The first set of S / D structures 308 is further divided into S / D 308a, S / D 308b, S / D 308c, and S / D 308d. The second set of S / D structures is further divided into S / D 310a, S / D 310b, S / D 310c, and S / D 310d.

[0045] Figure 3A This diagram illustrates a front-side gate contact 312 positioned above and connected to the active portion of the gate G1. The front-side gate contact above the active portion of the gate may be referred to herein as an "active gate-above front contact" (FSCOAG). Figure 3A In the example shown, the FSCOAG 312 connects the gate G1 to the front-side internal wiring rail I2.

[0046] Figure 3A A front gate contact 314, located above and connected to the non-active portion of the gate G2, is also shown. This front gate contact above the non-active portion of the gate may be referred to herein as a "front gate contact" (FSGC). Figure 3AIn the example shown, the FSGC 314 connects the gate G2 to the front internal wiring rail I3.

[0047] Figure 3A The front S / D contact 316 connected to S / D 308b is also shown. Figure 3A Also shown is the front S / D contact 318 connected to S / D 310d. The front S / D contact may be referred to herein as the "front S / D contact" (FSDC). Figure 3A In the example shown, FSDC 316 connects S / D 308b to the front internal wiring rail I1, and FSDC 318 connects S / D 310d to the front internal wiring rail I4.

[0048] exist Figure 3A and Figure 3B In the example shown, portion 320 of gate G3 has been removed, effectively splitting the gate into a first portion G3 above S / D structure 308 and a second portion G3' above S / D structure 310. As will be explained in more detail below, G3 and G3' can be connected to a power supply to shut down the corresponding active portions of the gate, which allows the split gate to electrically isolate cell 302 from cell 304.

[0049] It should be noted that the general term “front contact” (FSC) can be used to refer to all types of front contacts, and can also refer to specific types such as FSCOAG, FSGC, or FSDC, depending on the context.

[0050] Figure 3B The diagram shows the back-side gate contact 322 positioned above the active portion of G3 and connected to G3. Figure 3B Also shown is a back-side gate contact 324 above the active portion of G3' and connected to G3'. The back-side gate contact above the active portion of the gate may be referred to as an "active gate above back-side contact" (BSCOAG). Figure 3B In the example shown, BSCOAG 322 connects gate G3 to back-side internal wiring rail I5, and BSCOAG 324 connects gate G3' to back-side internal wiring rail I8.

[0051] Figure 3B Also shown is a back-side gate contact 326 located below the active portion of G4 and connected to G4. The back-side contact above the active portion of the gate may be referred to herein as a "back-side gate contact" (BSGC). Figure 3B In the example shown, the BSGC 326 connects the gate G4 to the back-side internal wiring rail I6.

[0052] Figure 3BAlso shown is the back-side S / D contact 328 connected to S / D 310a. Figure 3B Also shown is a back-side S / D contact 330 connected to S / D 308d. The back-side contact to the S / D region may be referred to herein as a "back-side S / D contact" (BSDC). Figure 3B In the example shown, BSDC 328 connects S / D 310a to rear internal wiring rail I8, and BSDC 330 connects S / D 308d to rear internal wiring rail I5. In some respects, the rear wiring rails above rear internal wiring rail I5 and below rear internal wiring rail I8 can be used for power supplies, such as VDD and VSS.

[0053] It should be noted that the general term “back-side contact” (BSC) can be used to refer to all types of back-side contacts, and can also refer to specific types such as BSCOAG, BSGC, or BSDC, depending on the context.

[0054] Figure 3C This is a cross-sectional view of semiconductor structure 300 along the cutting line AA. Figure 3C Cross-sections of cells 302 and 304 are shown, as are cross-sections of gates G1 to G5 and S / D structure 308 located within EPI structure 309.

[0055] Figure 3C An etch stop layer 336 is also shown located below the EPI structure 309 and surrounding the bottom portion of each gate stack. The etch stop layer 336 is situated in the S / D region to prevent the EPI from growing from the substrate and serves as an etch stop layer for the BSDC (but not for the BSGC). The etch stop layer 336 also serves as an isolation layer between the BSCOAG and the S / D structure to prevent short circuits between them. Example materials for the etch stop layer 336 include, but are not limited to, SiON, SiCON, SiN, or combinations thereof. In some aspects, the lower surface of the etch stop layer 336 may be at approximately the same level as the lower surface of the gate structure of the gate stack.

[0056] Figure 3C Also shown is a back-side interlayer dielectric (BS-ILD) layer 338 that separates the etch stop layer 336 from the back-side internal wiring track I5. Figure 3C Also shown is the front-side interlayer dielectric (FS-ILD) layer 340 covering the EPI structure 309 and gates G1 to G5. Figure 3C The FSCOAG 312, which is connected to the top of the gate G1 via the FS-ILD layer 340, is also shown. Figure 3C The FSDC 316, which is connected to the top of the S / D 308b via the FS-ILD layer 340, is also shown. Figure 3CAlso shown is the BSCOAG 322, which is connected to the bottom of the gate G3 via the BS-ILD layer 338. Figure 3C Also shown is the BSDC 330, which is connected to the bottom of the S / D 308d via the BS-ILD layer 338. Figure 3C In the example shown, BSCOAG 322 and BSDC 330 are connected to the rear internal wiring rail I5.

[0057] exist Figure 3C In the magnified area 342, details of a portion of the gate stack are shown. Figure 3C In the example shown, each gate state includes five gate portions, each gate portion including a corresponding gate electrode (e.g., gate electrodes 344a to 344e) and a corresponding gate dielectric structure (e.g., gate dielectric structures 346a to 346e). In this disclosure, all gate electrodes in the gate stack may be collectively referred to as gate electrode structure 344. In some aspects, the top gate portion of the gate stack may include gate spacers 348a on the sidewalls of gate dielectric structure 346a. In some aspects, the gate portions of the gate stack other than the top gate portion may include internal spacers (e.g., internal spacers 348b to 348e) on the sidewalls of the corresponding gate dielectric structures (e.g., gate dielectric structures 346b to 346e). Magnified region 342 also shows the locations of channels 350a to 350d through which charge carriers travel horizontally from left to right or right to left in the figure.

[0058] like Figure 3C As shown, the first thickness T1 of the metal gate structure below the bottom channel 350d is greater than the second thickness T2 of the metal gate structure between the adjacent channels 350a and 350d. Therefore, the inner gate electrodes 344b to 344d have a second thickness T2, and the bottom gate electrode 344e has a thickness T1 greater than T2. ​​The larger thickness T1 provides good margin for the etching step that creates the back-side gate contact. Specifically, the additional thickness provides greater process margin during the etching step that allows the use of the bottom gate electrode 346e through the BSCOAG 322 of the BS-ILD layer 338. In some aspects, the thickness of T1 is twice that of T2. In some aspects, the thickness of T1 is more than twice that of T2. In some aspects, T1 is thicker than T2, but less than twice the thickness of T2. In some aspects, T1 is 1.3 to 2.0 times thicker than T2.

[0059] exist Figure 3CIn the example shown, the gate stack is a full-around-gate (GAA) design that surrounds one or more channels, such as channel 350a, channel 350b, channel 350c, etc., but the BSGC disclosed herein is also applicable to FinFET and other FET designs. The BSCOAG disclosed herein will not be applicable to FinFET because there is no gate material accessible to BSCOAG beneath the FinFET channel.

[0060] Therefore, in Figure 3C In the example shown, the gate stacks G1 to G5 include a gate structure disposed between the first S / D structure and the second S / D structure. The gate structure includes a channel structure and a metal gate structure. The channel structure includes a plurality of vertically stacked horizontal channels. The horizontal channels horizontally connect the first S / D structure to the second S / D structure through the metal gate structure and a metal gate at least partially surrounding the horizontal channel structure. The first thickness T1 of the metal gate structure below the bottom channel of the plurality of horizontal channels is greater than the second thickness T2 of the metal gate structure between adjacent channels of the plurality of horizontal channels.

[0061] Figure 3D This is a cross-sectional view of semiconductor structure 300 along the cutting line BB. Figure 3D Cross-sections of gates G1 to G5 are shown, where there are no side-wing S / D structures and no channels (i.e., not above the active gates), and where the gate stacks are separated by FS-ILD 340. Figure 3D As shown, the gate stack is separated from the BS-ILD layer 338 by the shallow trench isolation (STI) layer 348.

[0062] Figure 3D The FSGC 314, which contacts G2 via the FS-ILD layer 340, is also shown. Figure 3D Also shown is a BSGC 326 that contacts a portion of the bottom surface of the gate stack of gate G4 to the back-side internal wiring rail I6.

[0063] Figure 3E This is a cross-sectional view of semiconductor structure 300 along the cutting line CC. Figure 3E A cross-section of section 320 is shown, showing gates G3 and G3' and the gate stack being removed to create two portions G3 and G3'. Figure 3E The channels 350a to 350d, the gate dielectric 346, and the gate electrode structure 344 are also shown. Figure 3EAs shown, the gate stack is separated from the BS-ILD layer 338 by the STI layer 348. BSCOAG 324 is connected to the back-side internal wiring rail I8 via the BS-ILD layer 338, while BSCOAG 322 is connected to the back-side internal wiring rail I5 via the BS-ILD layer 338. The back-side internal wiring rails are isolated from each other by the BS-IMD layer 352. Figure 3E An example of a split (or non-shared) gate is shown. In this example, gate G3 is connected to the back-side internal signal routing rail I5, and G3' is connected to the back-side internal signal routing rail I8. This concept of a non-shared gate can be extended to "gate isolation constraints" ( Figure 3E (Not shown in the diagram) In this design, the gate is split into a pFET portion and an nFET portion. The pFET portion is connected to VDD, and the nFET portion is connected to VSS, which turns both off to create an isolation effect.

[0064] Figures 4A to 4D This is a cross-section illustrating steps in the process of manufacturing a BSCOAG and / or back-side gate contact (BSGC) for full back-side connectivity according to various aspects of this disclosure. Figure 4A As shown, the process begins with a semiconductor structure 300, which includes a gate stack (e.g., gate G3) and a channel connecting a first S / D structure (e.g., S / D 308b) and a second S / D structure (e.g., S / D 308c) within an EPI structure 309, the EPI structure itself being disposed within an FS-ILD layer 340. An etch stop layer 336 separates the EPI structure 309 from the BS-ILD layer 338. Figures 4A to 4D In the example shown, the gate stack includes a GAA structure, but the same principle can be applied to finFET or other structures.

[0065] Figure 4A The results after applying the resist layer 400 and the patterning process, which may be referred to herein as the BSCOAG / BSGC lithography step, are illustrated.

[0066] Figure 4B The result is illustrated after a first etching process where the etching passes through the BS-ILD layer 338 but stops at the high-K gate dielectric 342e.

[0067] Figure 4C The result is illustrated after a second etching process in which the etching passes through the high-K gate dielectric 342e but stops at the gate metal 340e.

[0068] Figure 4DThe results are illustrated after removing the resist layer 400, metallizing BSCOAG 322 (or BSGC), and planarization steps such as chemical / mechanical polishing. The materials for BSCOAG and BSGC may include, but are not limited to, tungsten, cobalt, molybdenum, and ruthenium.

[0069] Because some integrated circuit cells may require more internal wiring pins than others, an integrated circuit cell library can include cells with different numbers of rails. In this case, the integrated circuit cells can be arranged in columns with alternating heights. An integrated circuit cell of a first height placed above or below an integrated circuit cell of a second height is called a duplex.

[0070] Figure 5 Examples are provided comparing conventional integrated circuit cell duplexes according to various aspects of this disclosure with integrated circuit cell duplexes using compact logic cells with full back-side connectivity. Figure 5 A plan view of a conventional 11T integrated circuit cell dual unit 500 is shown. Figure 5 In this configuration, the conventional duplex 500 includes conventional 5T units 142 arranged in a 5T column, which are positioned above conventional 6T units 502 arranged in a 6T column. The duplex 500 contains nine internal wiring rails.

[0071] Figure 5 Plan views of a compact 9T duplex 504 and a compact 7T duplex 506 according to various aspects of this disclosure are also shown. In some aspects, the compact 9T duplex 504 includes a compact 5T unit 200 and a compact 4T unit 202, having ten wiring rails on the front side of the duplex and another ten wiring rails on the rear side of the duplex. The fourteen internal wiring rails are labeled 1 to 14. In some aspects, the compact 7T duplex includes a compact 3T unit 204 and a compact 4T unit 202, having eight wiring rails on the front side of the duplex and another eight wiring rails on the rear side of the duplex. The ten internal wiring rails are labeled 1 to 10. It can be seen that... Figure 5 The compact duplexes 504 and 506 shown offer the technical advantage of having more internal wiring rails than the conventional duplex 500, but with a 17% to 34% reduction in unit height compared to the conventional duplex 500.

[0072] Additional wiring rails are particularly useful for reducing the size of integrated circuit cells that implement relatively complex gates. This will be illustrated using XOR (Exclusive OR).

[0073] Figure 6 This is a schematic diagram of a two-input XOR (Exclusive Orb) circuit 600, which has two input terminals labeled A and B, and an output terminal labeled C. Figure 6In the example shown, the first inverter (INV1) generates signal A', and the second inverter (INV2) generates signal B'. Each control signal A, A', B, and B' is connected to the gate of a corresponding pair of FETs, including a PFET and an NFET. Figure 6 In the XOR circuit 600 shown, control signal A is connected to the gate of PFET P3 and the gate of NFET N3, and control signal A' is connected to the gate of PFET P1 and the gate of NFET N1, etc.

[0074] Figure 7A and Figure 7B This is a plan view of a compact integrated circuit cell 700 implementing the XOR function according to various aspects of this disclosure, showing the back and front connections, both of which are shown from the front view. Figure 7A As shown, the compact integrated circuit cell 700 uses front-side S / D diffusion contacts such as FSDC 702 and active gate-above front-side contacts such as FSCOAG 704 to connect to one or more of the front-side internal wiring rails I1 to I4. Figure 7B As shown, the compact integrated circuit cell 700 uses a back-side S / D diffusion contact such as BSDC 706 and an active gate-above back-side contact such as BSCOAG 708 to connect to one or more of the back-side internal wiring rails I5 to I8. Due to the abundant resources of M0 (front side) and BM0 (back side), the XOR cell is fully wired in M0 / BM0, thus eliminating the need for high metal layers for connections within a theoretically minimum 8 CPP layout.

[0075] Figure 8A and Figure 8B This is a flowchart illustrating portions of an example process 800 associated with the use of full back-side connectivity to manufacture a compact logic cell according to various aspects of this disclosure.

[0076] like Figure 8A As shown, process 800 may include providing multiple integrated circuit cells at 802. (As illustrated...) Figures 8A to 8B As shown, this includes the following steps for each of the plurality of integrated circuit cells.

[0077] like Figure 8AAs shown, 802 may include providing a plurality of gate structures at 804, the plurality of gate structures being spaced apart from each other by one of the first plurality of source / drain (S / D) structures, each gate structure including a channel structure and a metal gate structure, the channel structure including at least one channel extending through the metal gate structure and connecting adjacent S / D structures of the first plurality of S / D structures to each other, wherein at least one of the plurality of gate structures forms a gate all-around (GAA) field-effect transistor (FET).

[0078] like Figure 8A As shown, 802 may include a front-side source / drain contact (FSDC) structure provided at 806, the front-side source / drain contact (FSDC) structure being electrically connected to the top surface of at least one of the first plurality of S / D structures.

[0079] like Figure 8A As shown, 802 may include an active gate above front side contact (FSCOAG) structure provided at 808, the active gate above front side contact (FSCOAG) structure being electrically connected to the top surface of at least one of the plurality of gate structures.

[0080] like Figure 8A As shown, 802 may include a front-side interlayer dielectric (FS-ILD) layer provided at 810, the front-side interlayer dielectric (FS-ILD) layer being disposed on the plurality of gate structures and the first plurality of S / D structures.

[0081] like Figure 8A As shown, 802 may include a front zero metal (FMO) interconnect layer provided at 812, the front zero metal (FMO) interconnect layer being disposed on the FS-ILD, the front zero metal (FMO) interconnect layer including a plurality of parallel FMO interconnects, at least one of the parallel FMO interconnects being electrically connected to the FSDC structure or the FSCOAG structure.

[0082] like Figure 8B As shown, 802 may include a back-side source / drain contact (BSDC) structure provided at 814, the back-side source / drain contact (BSDC) structure being electrically connected to the bottom surface of at least one of the first plurality of S / D structures.

[0083] like Figure 8B As shown, 802 may include an active gate above back side contact (BSCOAG) structure provided at 816, the active gate above back side contact (BSCOAG) structure being electrically connected to the bottom surface of at least one of the plurality of gate structures.

[0084] like Figure 8B As shown, 802 may include a back-side interlayer dielectric (BS-ILD) layer provided at 818, the back-side interlayer dielectric (BS-ILD) layer being disposed on the plurality of gate structures and the first plurality of S / D structures.

[0085] like Figure 8B As shown, 802 may include a back-side zero-layer metal (BMO) interconnect layer provided at 820, the back-side zero-layer metal (BMO) interconnect layer being disposed on the BS-ILD, the back-side zero-layer metal (BMO) interconnect layer including a plurality of parallel BMO interconnects, at least one parallel BMO interconnect being electrically connected to the BSDC or the BSCOAG.

[0086] In some aspects, providing the FM0 interconnect layer includes providing six or fewer parallel FM0 interconnects, and wherein providing the BM0 interconnect layer includes providing six or fewer parallel BM0 interconnects.

[0087] In some aspects, providing the FM0 interconnect layer includes providing five or fewer parallel FM0 interconnects, and wherein providing the BM0 interconnect layer includes providing five or fewer parallel BM0 interconnects.

[0088] In some aspects, providing the FM0 interconnect layer includes providing four or fewer parallel FM0 interconnects, and wherein providing the BM0 interconnect layer includes providing four or fewer parallel BM0 interconnects.

[0089] In some aspects, providing the FM0 interconnect layer includes providing three or fewer parallel FM0 interconnects, and wherein providing the BM0 interconnect layer includes providing three or fewer parallel BM0 interconnects.

[0090] In some respects, each of the first plurality of S / D structures includes an EPI layer.

[0091] In some respects, the metal gate structure includes a high-k dielectric layer that at least partially surrounds the work function metal layer.

[0092] In some respects, the channel structure is contained within a first portion of the metal gate structure, but not within a second portion of the metal gate structure.

[0093] In some respects, the second portion of the metal gate structure is separated from the BS-ILD layer by a shallow trench isolation (STI) layer.

[0094] In some aspects, the plurality of gate structures are spaced apart from each other in the column direction by one of the second plurality of S / D structures offset from the first plurality of S / D structures in the row direction, each gate structure including a second channel structure and a second metal gate structure, the second channel structure including at least one channel extending in the column direction and connecting adjacent S / D structures in the second plurality of S / D structures to each other.

[0095] Process 800 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in conjunction with one or more other processes described elsewhere herein. Although Figures 8A to 8B An example block diagram of process 800 is shown, but in some specific implementations, process 800 may include... Figures 8A to 8B The boxes depicted in the diagram may be fewer, different, or arranged differently than additional boxes. Alternatively, two or more boxes in the process 800 may be executed in parallel.

[0096] Figure 9 A mobile device 900 according to various aspects of this disclosure is illustrated. In some aspects, the mobile device 900 may be implemented by including one or more IC devices manufactured based on the examples described in this disclosure.

[0097] In some aspects, the mobile device 900 can be configured as a wireless communication device. As shown, the mobile device 900 includes a processor 902. The processor 902 is communicatively coupled to a memory 904 via a link, which can be a die-to-die or chip-to-chip link. The mobile device 900 also includes a display 906 and a display controller 908, wherein the display controller 908 is coupled to the processor 902 and the display 906. The mobile device 900 may include an input device 910 (e.g., a physical or virtual keyboard), a power supply 912 (e.g., a battery), a speaker 914, a microphone 916, and a wireless antenna 918. In some aspects, the power supply 912 may directly or indirectly provide power voltage for some or all of the components of the mobile device 900.

[0098] In some respects, Figure 9 It may include a decoder / decoder (codec) 920 (e.g., an audio and / or voice codec) coupled to the processor 902; a speaker 914 and a microphone 916 coupled to the codec 920; and a wireless circuit 922 (which may include a modem, RF circuitry, filters, etc.) coupled to the wireless antenna 918 and coupled to the processor 902.

[0099] In some aspects, one or more of the processor 902, display controller 908, memory 904, CODEC 920, and wireless circuit 922 may include one or more IC devices, which include semiconductor structures manufactured according to the examples described in this disclosure.

[0100] It should be noted that, although Figure 9 Mobile device 900 is described, but devices including set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed location data units, computers, laptops, tablets, communication devices, mobile phones, or other similar devices can be implemented using a similar architecture.

[0101] Figure 10 Examples of various electronic devices that may integrate any of the following: the aforementioned devices, semiconductor devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, stacked package (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1002, laptop computer device 1004, fixed-location terminal device 1006, wearable device 1008, or automobile 1010 may include semiconductor devices 1000 as described herein (which may include compact logic cells 200, 202, 204, etc.). Figure 10 The illustrated devices 1002, 1004, 1006, and 1008, as well as vehicle 1010, are merely exemplary. Other devices or equipment may also feature semiconductor device 1000, including but not limited to a group of devices comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0102] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features than those explicitly mentioned in each clause. Rather, the various aspects of this disclosure may include fewer features than those in the individual example clauses disclosed. Therefore, the following clauses should be regarded accordingly as incorporated into the description, where each clause may serve as a separate example. Although each dependent clause may refer in the clause to a specific combination with one of the other clauses, the aspect of that dependent clause is not limited to that specific combination. It should be understood that other example clauses may also include combinations of aspects of a dependent clause with the subject matter of any other dependent or independent clause, or combinations of any feature with other dependent and independent clauses. The various aspects disclosed herein explicitly include these combinations unless explicitly stated or readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of a clause may be included in any other independent clause, even if that clause does not directly depend on the independent clause.

[0103] Specific implementation examples are described in the following numbered clauses: Clause 1. A semiconductor device comprising: a plurality of integrated circuit cells, each of the plurality of integrated circuit cells comprising: a plurality of gate structures, the plurality of gate structures being spaced apart from each other by one of a first plurality of source / drain (S / D) structures, each gate structure comprising a channel structure and a metal gate structure, the channel structure comprising at least one channel extending through the metal gate structure and connecting adjacent S / D structures of the first plurality of S / D structures to each other, wherein the at least one gate structure of the plurality of gate structures forms a full surround. Gate (GAA) field-effect transistor (FET); front-side source / drain contact (FSDC) structure, the front-side source / drain contact (FSDC) structure being electrically connected to the top surface of at least one of the first plurality of S / D structures; active gate above front contact (FSCOAG) structure, the active gate above front contact (FSCOAG) structure being electrically connected to the top surface of at least one of the plurality of gate structures; front-side interlayer dielectric (FS-ILD) layer, the front-side interlayer dielectric (FS-ILD) layer being disposed on the plurality of gate structures and the first plurality of S / D structures. On the S / D structure: a front zero metal (FMO) interconnect layer disposed on the FS-ILD layer, the front zero metal (FMO) interconnect layer including a plurality of parallel FMO interconnects, at least one parallel FMO interconnect electrically connected to the FSDC structure or the FSCOAG structure; a back source / drain contact (BSDC) structure, the back source / drain contact (BSDC) structure electrically connected to the bottom surface of at least one of the first plurality of S / D structures; and a back contact (BSCOAG) structure above the active gate, the active gate... The upper back-side contact (BSCOAG) structure is electrically connected to the bottom surface of at least one of the plurality of gate structures; a back-side interlayer dielectric (BS-ILD) layer is disposed on the plurality of gate structures and the first plurality of S / D structures; and a back-side zero-layer metal (BMO) interconnect layer is disposed on the BS-ILD layer, the back-side zero-layer metal (BMO) interconnect layer includes a plurality of parallel BMO interconnects, at least one of the parallel BMO interconnects being electrically connected to the BSDC structure or the BSCOAG structure.

[0104] Clause 2. The semiconductor device according to Clause 1, wherein the FMO interconnect layer comprises six or fewer parallel FMO interconnects, and wherein the BMO interconnect layer comprises six or fewer parallel BMO interconnects.

[0105] Clause 3. The semiconductor device according to any one of Clauses 1 to 2, wherein the FMO interconnect layer comprises five or fewer parallel FMO interconnects, and wherein the BMO interconnect layer comprises five or fewer parallel BMO interconnects.

[0106] Clause 4. A semiconductor device according to any one of Clauses 1 to 3, wherein the FMO interconnect layer comprises four or fewer parallel FMO interconnects, and wherein the BMO interconnect layer comprises four or fewer parallel BMO interconnects.

[0107] Clause 5. A semiconductor device according to any one of Clauses 1 to 4, wherein the FMO interconnect layer comprises three or fewer parallel FMO interconnects, and wherein the BMO interconnect layer comprises three or fewer parallel BMO interconnects.

[0108] Clause 6. The semiconductor device according to any one of Clauses 1 to 5, wherein each of the first plurality of S / D structures includes an EPI layer.

[0109] Clause 7. A semiconductor device according to any one of Clauses 1 to 6, wherein the metal gate structure comprises at least a high-k dielectric layer surrounding a work function metal layer.

[0110] Clause 8. A semiconductor device according to any one of Clauses 1 to 7, wherein the channel structure is contained within a first portion of the metal gate structure but not within a second portion of the metal gate structure.

[0111] Clause 9. The semiconductor device according to Clause 8, wherein the second portion of the metal gate structure is separated from the BS-ILD layer by a shallow trench isolation (STI) layer.

[0112] Clause 10. A semiconductor device according to any one of Clauses 1 to 9, wherein the plurality of gate structures are spaced apart from each other by one of a plurality of second S / D structures offset from the first plurality of S / D structures, each gate structure including a second channel structure and a second metal gate structure, the second channel structure including at least one channel connecting adjacent S / D structures of the second plurality of S / D structures to each other.

[0113] Clause 11. A method for manufacturing a semiconductor device, the method comprising: providing a plurality of integrated circuit cells, wherein for each of the plurality of integrated circuit cells, the providing comprises: providing a plurality of gate structures, the plurality of gate structures being spaced apart from each other by one of a first plurality of S / D structures, each gate structure including a channel structure and a metal gate structure, the channel structure including at least one channel extending through the metal gate structure and connecting adjacent S / D structures of the first plurality of S / D structures to each other, wherein at least one of the plurality of gate structures forms a GAA (Gate Alignment). The device includes: a field-effect FET; an FSDC structure electrically connected to the top surface of at least one of the plurality of S / D structures; an FSCOAG structure electrically connected to the top surface of at least one of the plurality of gate structures; an FS-ILD layer disposed on the plurality of gate structures and the plurality of S / D structures; and an FMO interconnect layer disposed on the FS-ILD layer, the FMO interconnect layer including a plurality of parallel FMO interconnects, at least one of the plurality of parallel FMO interconnects being electrically connected to either the FSDC structure or the FSCOAG structure. The system provides a BSDC structure electrically connected to the bottom surface of at least one of the first plurality of S / D structures; a BSCOAG structure electrically connected to the bottom surface of at least one of the plurality of gate structures; a BS-ILD layer disposed on the plurality of gate structures and the first plurality of S / D structures; and a BMO interconnect layer disposed on the BS-ILD layer, the BMO interconnect layer including a plurality of parallel BMO interconnects, at least one of the plurality of parallel BMO interconnects being electrically connected to the BSDC structure or the BSCOAG structure.

[0114] Clause 12. The method according to Clause 11, wherein providing the FMO interconnect layer includes providing six or fewer parallel FMO interconnects, and wherein providing the BMO interconnect layer includes providing six or fewer parallel BMO interconnects.

[0115] Clause 13. The method according to any one of Clauses 11 to 12, wherein providing the FMO interconnect layer comprises providing five or fewer parallel FMO interconnects, and wherein providing the BMO interconnect layer comprises providing five or fewer parallel BMO interconnects.

[0116] Clause 14. The method according to any one of Clauses 11 to 13, wherein providing the FMO interconnect layer comprises providing four or fewer parallel FMO interconnects, and wherein providing the BMO interconnect layer comprises providing four or fewer parallel BMO interconnects.

[0117] Clause 15. The method according to any one of Clauses 11 to 14, wherein providing the FMO interconnect layer comprises providing three or fewer parallel FMO interconnects, and wherein providing the BMO interconnect layer comprises providing three or fewer parallel BMO interconnects.

[0118] Clause 16. The method according to any one of Clauses 11 to 15, wherein each of the first plurality of S / D structures includes an EPI layer.

[0119] Clause 17. The method according to any one of Clauses 11 to 16, wherein the metal gate structure comprises at least a high-k dielectric layer surrounding the work function metal layer.

[0120] Clause 18. The method according to any one of Clauses 11 to 17, wherein the channel structure is contained within a first portion of the metal gate structure but not within a second portion of the metal gate structure.

[0121] Clause 19. The method according to Clause 18, wherein the second portion of the metal gate structure is separated from the BS-ILD layer by an STI layer.

[0122] Clause 20. The method according to any one of Clauses 11 to 19, wherein the plurality of gate structures are spaced apart from each other by one of a plurality of S / D structures offset from the first plurality of S / D structures, each gate structure including a second channel structure and a second metal gate structure, the second channel structure including at least one channel connecting adjacent S / D structures of the second plurality of S / D structures to each other.

[0123] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0124] Furthermore, those skilled in the art will understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0125] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0126] The methods, sequences, and / or algorithms described in conjunction with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or a combination of both. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. Example storage media are coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., a UE). Alternatively, the processor and storage medium may reside as discrete components in the user terminal.

[0127] In one or more examples, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and is accessible to a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of a medium. As used herein, disks and optical discs include: compact optical discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0128] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. Furthermore, the functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Moreover, although elements of this disclosure may be described or claimed in the singular, the plural form may also be considered unless expressly stated as limited to the singular.

Claims

1. A semiconductor device comprising: a plurality of integrated circuit units, each integrated circuit unit of the plurality of integrated circuit units comprising: a plurality of gate structures spaced apart from one another by one source / drain (S / D) structure of a first plurality of S / D structures, each gate structure comprising a channel structure and a metal gate structure, the channel structure comprising at least one channel extending through the metal gate structure and connecting adjacent S / D structures of the first plurality of S / D structures to one another, wherein at least one gate structure of the plurality of gate structures forms a gate-all-around (GAA) field effect transistor (FET); a front side source / drain contact (FSDC) structure electrically connected to a top surface of at least one S / D structure of the first plurality of S / D structures; a front side contact over active gate (FSCOAG) structure electrically connected to a top surface of at least one gate structure of the plurality of gate structures; a front side interlayer dielectric (FS-ILD) layer disposed on the plurality of gate structures and the first plurality of S / D structures; a front side zero metal (FM0) interconnect layer disposed on the FS-ILD layer, the front side zero metal (FM0) interconnect layer comprising a plurality of parallel FM0 interconnects, at least one parallel FM0 interconnect electrically connected to the FSDC structure or the FSCOAG structure; a back side source / drain contact (BSDC) structure electrically connected to a bottom surface of at least one S / D structure of the first plurality of S / D structures; a back side contact over active gate (BSCOAG) structure electrically connected to a bottom surface of at least one gate structure of the plurality of gate structures; a back side interlayer dielectric (BS-ILD) layer disposed on the plurality of gate structures and the first plurality of S / D structures; and a back side zero metal (BM0) interconnect layer disposed on the BS-ILD layer, the back side zero metal (BM0) interconnect layer comprising a plurality of parallel BM0 interconnects, at least one parallel BM0 interconnect electrically connected to the BSDC structure or the BSCOAG structure.

2. The semiconductor device of claim 1, wherein the FM0 interconnect layer comprises six or fewer parallel FM0 interconnects, and wherein the BM0 interconnect layer comprises six or fewer parallel BM0 interconnects.

3. The semiconductor device of claim 1, wherein the FM0 interconnect layer comprises five or fewer parallel FM0 interconnects, and wherein the BM0 interconnect layer comprises five or fewer parallel BM0 interconnects.

4. The semiconductor device of claim 1, wherein the FM0 interconnect layer comprises four or fewer parallel FM0 interconnects, and wherein the BM0 interconnect layer comprises four or fewer parallel BM0 interconnects.

5. The semiconductor device of claim 1, wherein the FM0 interconnect layer comprises three or fewer parallel FM0 interconnects, and wherein the BM0 interconnect layer comprises three or fewer parallel BM0 interconnects.

6. The semiconductor device of claim 1, wherein each S / D structure of the first plurality of S / D structures comprises an EPI layer.

7. The semiconductor device of claim 1, wherein the metal gate structure comprises a high-K dielectric layer at least partially surrounding a work function metal layer.

8. The semiconductor device of claim 1, wherein the channel structure is contained within a first portion of the metal gate structure and is not contained within a second portion of the metal gate structure.

9. The semiconductor device of claim 8, wherein the second portion of the metal gate structure is separated from the BS-ILD layer by a shallow trench isolation (STI) layer.

10. The semiconductor device of claim 1, wherein the plurality of gate structures are spaced apart from each other by one S / D structure of a second plurality of S / D structures that are offset from the first plurality of S / D structures, each gate structure comprising a second channel structure and a second metal gate structure, the second channel structure comprising at least one channel connecting adjacent S / D structures of the second plurality of S / D structures to each other.

11. A method for fabricating a semiconductor device, the method comprising: providing a plurality of integrated circuit units, for each integrated circuit unit of the plurality of integrated circuit units, the providing comprising: providing a plurality of gate structures spaced apart from each other by one source / drain (S / D) structure of a first plurality of S / D structures, each gate structure comprising a channel structure and a metal gate structure, the channel structure comprising at least one channel extending through the metal gate structure and connecting adjacent S / D structures of the first plurality of S / D structures to each other, wherein at least one gate structure of the plurality of gate structures forms a gate-all-around (GAA) field effect transistor (FET); providing a front side source / drain contact (FSDC) structure electrically connected to a top surface of at least one S / D structure of the first plurality of S / D structures; providing an active gate over front side contact (FSCOAG) structure electrically connected to a top surface of at least one gate structure of the plurality of gate structures; A front-side interlayer dielectric (FS-ILD) layer is provided, the front-side interlayer dielectric (FS-ILD) layer being disposed on the plurality of gate structures and the first plurality of S / D structures; A front zero metal (FMO) interconnect layer is provided, the front zero metal (FMO) interconnect layer is disposed on the FS-ILD layer, the front zero metal (FMO) interconnect layer includes a plurality of parallel FMO interconnects, at least one of the plurality of parallel FMO interconnects is electrically connected to the FSDC structure or the FSCOAG structure. A back-side source / drain contact (BSDC) structure is provided, the back-side source / drain contact (BSDC) structure being electrically connected to the bottom surface of at least one of the first plurality of S / D structures; An active gate above back side contact (BSCOAG) structure is provided, the active gate above back side contact (BSCOAG) structure being electrically connected to the bottom surface of at least one of the plurality of gate structures; A back-side interlayer dielectric (BS-ILD) layer is provided, the BS-ILD layer being disposed on the plurality of gate structures and the first plurality of S / D structures; and A back-side zero-layer metal (BMO) interconnect layer is provided, the back-side zero-layer metal (BMO) interconnect layer is disposed on the BS-ILD layer, the back-side zero-layer metal (BMO) interconnect layer includes a plurality of parallel BMO interconnects, at least one of the plurality of parallel BMO interconnects being electrically connected to the BSDC structure or the BSCOAG structure.

12. The method of claim 11, wherein providing the FMO interconnect layer comprises providing six or fewer parallel FMO interconnects, and wherein providing the BMO interconnect layer comprises providing six or fewer parallel BMO interconnects.

13. The method of claim 11, wherein providing the FMO interconnect layer comprises providing five or fewer parallel FMO interconnects, and wherein providing the BMO interconnect layer comprises providing five or fewer parallel BMO interconnects.

14. The method of claim 11, wherein providing the FMO interconnect layer comprises providing four or fewer parallel FMO interconnects, and wherein providing the BMO interconnect layer comprises providing four or fewer parallel BMO interconnects.

15. The method of claim 11, wherein providing the FMO interconnect layer comprises providing three or fewer parallel FMO interconnects, and wherein providing the BMO interconnect layer comprises providing three or fewer parallel BMO interconnects.

16. The method of claim 11, wherein each of the first plurality of S / D structures comprises an EPI layer.

17. The method of claim 11, wherein the metal gate structure comprises at least a high-k dielectric layer surrounding the work function metal layer.

18. The method of claim 11, wherein the channel structure is contained within a first portion of the metal gate structure but not within a second portion of the metal gate structure.

19. The method of claim 18, wherein the second portion of the metal gate structure is separated from the BS-ILD layer by a shallow trench isolation (STI) layer.

20. The method of claim 11, wherein the plurality of gate structures are spaced apart from each other by one of a plurality of S / D structures offset from the first plurality of S / D structures, each gate structure including a second channel structure and a second metal gate structure, the second channel structure including at least one channel connecting adjacent S / D structures of the second plurality of S / D structures to each other.

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