Low-on-resistance high-power switch

Abstract

An electrical power switch, the power switch comprising: an array of rows and columns of lateral field effect (LFET) transistors, each transistor having a source, a drain, and a gate; a plurality of internal interconnect layers, the plurality of internal interconnect layers including a metallization configured to connect the transistors to operate in parallel; a source electrode and a drain electrode for connecting the source electrode and the drain electrode of the transistor to an external circuit, respectively; and a bridge interconnect layer, the bridge interconnect layer comprising: a plurality of undulating source bridge conductors, the undulating source bridge conductors providing an electrical connection for the source of the transistor to the source electrode; and a plurality of undulating drain bridge conductors providing an electrical connection for the drain of the transistor to the drain.

Description

Related applications

[0001] This application claims the benefit of U.S. Application 18 / 457,362, filed August 29, 2023, pursuant to 35 USC 120, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the present invention relate to high-voltage, high-power switches including a low-resistance redistribution layer (RDL). background

[0003] Almost all types of modern optical and electronic devices (from computers to power systems) include power switching circuits for generating timing pulses, data packets, and / or transmitting power. To deliver power to electric powertrains (such as those powering electric vehicles), power switches are required to be able to carry large currents, quickly switch on and off to couple and decouple high-voltage power supplies from the powertrain, and have relatively low on-resistance when switched on.

[0004] For example, a high-voltage power inverter operated to deliver AC power from a DC power source to a vehicle traction motor may include a half-bridge with high-side switches, low-side switches, and PCB control circuitry to control the switches that invert DC power to AC power. To provide the high current and voltage required by the power inverter, the high-side and low-side switches may be lateral field-effect transistor (LFET) switches, each comprising a relatively large array of LFET transistors. The LFET electrical connections operate in parallel to support the high current and voltage through a complex layered conductor network called a redistribution layer (RDL). The RDL includes relatively long conductive interconnects in different layers of the RDL that cover and connect to the sources, drains, and / or gates of the LFET transistors, as well as vias connecting the interconnects in the different layers.

[0005] For efficient operation of high-power inverters and to achieve low on-resistance, it is advantageous for the high-side and low-side switches to have low drain-source resistance (RDS(on)) when on, for the RDL interconnects to be appropriately insulated from each other, and for the RDL to have low resistance. However, configuring the interconnects and the vias connecting these appropriately insulated interconnects to provide an RDL with relatively low resistance is a complex task. This complexity increases with the number of LFETs that facilitate support for high currents and voltages. Overview

[0006] One aspect of embodiments of this disclosure relates to providing a high-voltage, high-power LFET switch comprising an array of a large number of LFET transistors and a relatively low-resistance RDL. The RDL includes a bridging interconnect layer and a plurality (optionally three) of internal interconnect layers having metallization layers that connect transistor features together. The bridging interconnect layers include relatively low-resistance corrugated strips and / or wire-bonded conductors, commonly referred to as bridging conductors, that connect the internal interconnect layers to external electrodes that can be used to connect the LFET power switch and the LFET transistor array to external circuitry. Metallization layers in different layers of a relatively small number of internal interconnect layers are connected by conductive plugs that fill a plurality of vias formed in insulating layers separating the interconnect layers. The metallization layers and conductive plugs deliver current from the bridging conductors to the LFET transistors and return current from the LFET transistors to the bridging conductors along relatively short, low-resistance conductive paths perpendicular to the internal metallization layers. The short conductive paths contribute to reducing the resistance of the RDL.

[0007] In an embodiment, the plurality of internal interconnect layers include a first interconnect layer, a second interconnect layer, and a third interconnect layer. The first interconnect layer (also referred to as a gate interconnect layer) electrically connects the gates of a plurality of LFET transistors, and optionally all the gates of the LFET transistors together. The second interconnect layer includes a first metallization region and a second metallization region, optionally referred to as source and drain metallization layers, each having source and drain conductive forks covering the LFET transistors, respectively. The source conductive forks and drain conductive forks are interleaved, and electrically connect the sources of the plurality of LFET transistors, and optionally all the sources of the LFET transistors together. The drain conductive forks electrically connect the drains of the plurality of LFET transistors, and optionally all the drains of the LFET transistors together. The third interconnect layer (optionally referred to as a strip interconnect layer) includes a source metallization strip and a drain metallization strip. Each source metallization strip connects a plurality of source forks of the second interconnect layer, and optionally all the source forks together. Each drain metallization strip connects a plurality of drain forks of the second interconnect layer, and optionally all the drain forks together.

[0008] The bridging interconnect layer includes multiple source bridging conductors and multiple drain bridging conductors. Each source bridging conductor connects multiple, and optionally all, source bands of the third interconnect layer together. Each drain bridging conductor connects multiple, and optionally all, drain bands of the third interconnect layer together. The source and drain bridging conductors are staggered and substantially parallel. Each bridging conductor exhibits at least one undulation perpendicular to the bridging layer, optionally referred to as "ripples." The ripples, varying along the length of adjacent bridging conductors, are substantially out of phase, such that the undulations along adjacent strips are staggered, and displacements in the same direction caused by the undulations are not adjacent.

[0009] Out-of-phase ripples are used to increase the average distance between adjacent bridging conductors and facilitate the encapsulation of bridging conductors with insulating material by reducing the flow resistance between the bridging conductors and the insulating material used to package the LFET switch. The reduction in flow resistance contributes to the integrity of the insulating package. The increased average distance helps increase the resistance between the bridging conductors and improves the LFET switch's ability to prevent electrical breakdown.

[0010] This overview is provided to introduce, in a simplified form, some selected concepts that are further described in the detailed description below. This overview is not intended to show key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Brief description of the attached diagram

[0011] Non-limiting examples of embodiments of the invention are described below with reference to the accompanying drawings listed after this paragraph. Identical structures, elements, or parts appearing in more than one drawing are generally labeled with the same numerals in all the drawings in which they appear. The dimensions of parts and features shown in the drawings are chosen for ease of presentation and clarity and are not necessarily shown to scale.

[0012] Figures 1-8 The configuration and manufacture of an LFET power switch according to an embodiment of the present disclosure are illustrated schematically.

[0013] Figure 1 An optional ceramic substrate having a semiconductor substrate on which an LFET power switch is fabricated is schematically shown according to an embodiment of the present disclosure. Figure 2 The illustration schematically shows an optional partition formed in accordance with an embodiment of the present disclosure. Figure 1 The two portions of the LFET transistor on the semiconductor substrate shown; Figure 3 A first interconnect layer according to an embodiment of the present disclosure is schematically shown, the first interconnect layer having formed on Figure 2 The metallization layer on the semiconductor substrate shown can optionally electrically connect all the gates of the LFET transistor; Figure 4 A second interconnect layer of a power switch according to an embodiment of the present disclosure is schematically shown, which covers the first interconnect and is separated from the first interconnect by an insulating layer (not shown); Figure 5 An insulating layer formed above a second interconnect layer and having a source opening, a drain opening and a gate opening, according to an embodiment of the present disclosure, is schematically shown. Figure 6 A strip interconnect layer including a source metallization strip, a drain metallization strip, and a gate pad is schematically shown according to an embodiment of the present disclosure; Figure 7A The illustration schematically shows an embodiment of the present disclosure. Figure 6 The source and drain metallization bands shown are connected to the bridging conductive strips of the contact electrodes; Figure 7B The illustration schematically shows an embodiment of the present disclosure. Figure 6 The source and drain metallization bands shown are connected to the wire-joint bridging conductors of the contact electrodes; and Figure 8 The illustration schematically shows the completed product, after being encapsulated in an insulating package, according to an embodiment of the present disclosure. Figures 1 to 7A The LFET power switch shown is shown. Detailed description

[0014] In the discussion, unless otherwise stated, adjectives such as “substantially” and “approximately” modifying one or more features of embodiments of this disclosure are to be understood as indicating that the condition or feature is defined within acceptable tolerances for operation of the embodiments in their intended application. Wherever generic terms in this disclosure are explained by reference to example instances or lists of example instances, the one or more instances mentioned are non-limiting example instances of the generic terms, and the generic terms are not intended to be limited to the one or more specific example instances mentioned. The phrase “in embodiments,” whether associated with a loose form (such as “may,” “optionally,” or “by way of example”), is used to introduce configurations of possible embodiments of this disclosure for consideration as examples but not necessarily required. The verbs “comprise,” “include,” and “have,” and each of their variations, are used to indicate a complete list of parts, elements, or portions of the verb whose one or more objects are not necessarily the subjects of the verb. Unless otherwise expressly stated or indicated by the context, the word "or" in the specification and claims is to be considered inclusive "or" rather than exclusive "or" and means any combination of at least one or more of the items it combines.

[0015] Figures 1 to 8 The configuration and manufacture of an LFET power switch 20 according to an embodiment of the present disclosure are illustrated schematically. Figure 1 Throughout Figures 7, the symbol 20 is used to indicate that when the EFET power switch shown is in an incomplete manufacturing stage, it represents a stage in the manufacturing process of the LFET switch 20. Figure 8 The embodiments of this disclosure are shown as a completed LFET switch.

[0016] Figure 1An optional ceramic substrate 22 on which an LFET power switch 20 is fabricated according to an embodiment of the present disclosure is schematically shown. A configuration of contact electrodes is formed on the ceramic substrate 22, including a center electrode 22-2 and lateral electrodes 22-1 and 22-3 on which a semiconductor substrate 24 is mounted. The LFET transistor of the power switch 20 is formed on the semiconductor substrate 24, and the lateral electrodes 22-1 and 22-2 are used to electrically couple the power switch to an external circuit. For ease of illustration, it is assumed that the LFET transistor is an n-channel transistor.

[0017] Figure 2 A partitioned array 30 of rows 31 and columns 32 of LFET transistors 40 is schematically shown, which is optionally divided into two parts 30-1 and 30-2 by separators 33 formed on the semiconductor substrate 24. Some LFET transistors are surrounded by dashed rectangles indicated by markings 40 to aid in visual identification of each LFET transistor 40 and its components. Each LFET transistor 40 includes a source 41, a gate 42, and a drain 43. It should be noted that in the array 30, the same source 41 can serve as the source of two adjacent transistors 40.

[0018] Figure 3 A first interconnect layer 50 is schematically shown, having a metallization layer 51 formed on a semiconductor substrate 24 to optionally electrically connect all gates 42 of the LFET transistor 40. The metallization layer includes a relatively wide central trunk 53 and a plurality of branches 55 extending from the trunk, these branches connecting to the gates 42 of the transistor 40. According to an embodiment of the present disclosure, after formation, the interconnect layer 50 and the segmented array 30 of the transistor 40 are covered by an insulating layer (not shown), on which a first interconnect layer 50 is formed. Figure 4 The second interconnect layer 60 is schematically shown in the diagram.

[0019] Interconnect layer 60 includes a source metallization layer 62 and a drain metallization layer 63. Source metallization layer 62 includes a plurality of optionally tapered source forks 64 optionally joined via a backbone 66. Each source fork 64 optionally covers the same row 31 (…). Figure 2 All transistors 40 in the row are electrically coupled to the sources 41 of optionally all transistors in that row via conductive plugs (not shown) filling vias (not shown) formed in an insulating layer, which communicate with interconnect layers 50 and 60. Drain metallization layer 63 includes a plurality of optionally tapered drain forks 65, which are optionally joined by a trunk 67 and staggered with the source forks 63. Each drain fork 65 optionally covers the row 31 of transistors (…). Figure 2 All transistors 40 in the row are electrically coupled to the drains 43 of all transistors in the row via conductive plugs (not shown) formed in vias in the insulating layer between interconnect layers 50 and 60.

[0020] When transistor 40 is turned on, each source socket 64 provides current from the current flowing in the source socket, which enters row 31 located below the source socket. Figure 2 The source fork 64 of the optional transistors 40 in the main stem 66 receives current flowing through the transistor and exiting the transistor via their respective drains 43. Each drain fork 65 receives current flowing from the drain 43 of the optional transistors 40 in the row 31 below the drain fork. The source fork 64 is optionally tapered with distance from the main stem 66, as the number of transistors to which the fork provides current can decrease with distance from the main stem 66. As a result, the magnitude of the current flowing in the source fork 64 required to provide current to the transistors 40 can decrease with distance from the main stem 66. This tapering operation helps to achieve a uniform current density of current flowing along the source fork 64. Similarly, the drain fork 65 is advantageously tapered with distance from the main stem 67, as the number of transistors 40 to which the drain fork receives current through the drain 43 can decrease with distance from the main stem. As a result, the magnitude of the current flowing in the drain fork 65 can decrease with distance from the main stem 66. This tapering operation supports a uniform current density of current flowing along the drain fork teeth.

[0021] After the interconnect layer 60 is formed, it is covered by an insulating layer 70, which in turn... Figure 5 The diagram is schematically indicated by dots. The insulating layer 70 is formed having a source opening 71, a drain opening 72, and a gate opening 74. These openings are filled with a conductive filler containing a material used to form the covering third strip interconnect layer 80 (e.g., ...). Figure 6 The conductive elements (illustrated schematically) are made of this material when they are deposited on the insulating layer 70. The strip interconnect layer 80 optionally includes a source metallization strip 81, a drain metallization strip 82, and a gate pad 84. The source metallization 81 fills the source opening 71 (…). Figure 5 The conductive filler is electrically connected to the source fork 64 ( Figure 4 In one embodiment, it is formed closer to the trunk 66 ( Figure 4 The source opening 71 is larger than the source openings formed further away from the main stem, allowing the conductive filler filling these openings to adapt to the tapering and current density supported by the source serrations 64. The drain metallization band 82 fills the drain opening 72 ( Figure 5 The conductive filler is electrically connected to the drain fork 65. In an embodiment, closer to the main shaft 67 ( Figure 4The drain opening 72 formed is larger than the drain opening further away from the main trunk, allowing the conductive filler filling the drain opening to adapt to the tapering and current density supported by the drain fork 65. The gate pad 74 is electrically connected to the gate metallization layer 50 via the conductive filler filling the gate opening 74. Figure 5 ).

[0022] In one embodiment, the source metallization strip 81 and the drain metallization strip 82 are electrically connected to the contact electrodes 22-1 and 22-3 respectively via bridging conductors, which optionally take the form of source conductive strips 91 and drain conductive strips 92 respectively. Figure 7A In the bridging interconnect layer 90 schematically shown, each source strip 91 electrically connects the source metallization strips 81 together (optionally all) to the contact electrode 22-1. Each drain strip 92 electrically connects the drain metallization strips 82 together (optionally all) to the contact electrode 22-2.

[0023] According to embodiments of this disclosure, source strips 91 and 92 are corrugated strips, characterized by corrugations 91-1 and 92-1, respectively, which provide displacement of regions of the strips perpendicular to the plane of the interconnect layer 80 including metallization strips 81 and 82. Corrugations 91-1 are staggered relative to corrugations 92-1, such that corrugations 91-1 and 92-1 in adjacent strips 91 and 92 are not adjacent to each other and are displaced relative to each other in the direction in which strips 91 and 92 extend. Optionally, corrugations 91-1 and 92-1 are substantially harmonic.

[0024] The corrugations 91-1 and 92-1 and their relative displacement facilitate the flow of potting material used to encapsulate the LFET power switch 20 within an insulating package and help increase the average distance between adjacent metallized strips, thereby improving package integrity and inter-strip resistance. The average distance between adjacent metallized strips 91 and 92 can have a value equal to the average distance between the nearest points along the edges of the strips facing each other.

[0025] although Figure 7A A bridging interconnect layer 90, including bridging conductors as conductive strips 91 and 92, is schematically shown; however, the practice of embodiments of this disclosure is not limited to bridging interconnect layers including conductive strips. According to embodiments of this disclosure, an LFET power switch similar to power switch 20 may have a bridging interconnect layer including at least one bridging conductor that is a wavy conductive wire bond. Figure 7B A power switch 220 according to an embodiment of the present disclosure is illustrated schematically by way of example. The power switch includes an LFET power switch 220 having a bridging interconnect layer 290, which includes wire-bonded bridging conductors 291 and 292.

[0026] Figure 8 The illustration shows the packaged contents. Figure 8 The insulating encapsulation 100, schematically shown, is subsequently completed according to the embodiment. Figures 1-7A The LFET power switch 20 is shown. The low-resistance RDL LFET power switch can be connected as a component of external circuitry to function as a power switch by electrically coupling contact electrodes 22-1 and 22-2 to the circuitry and connecting the gate pad 84 to a controller that controls the LFET switch 40 to turn on and off. When transistor 40 is turned on to activate power switch 20, current optionally flows from contact electrode 22-1 to source strip 91, and from there through source metallization strip 81 and source fork 64, through source 41, across the transistor, and exits the transistor through drain 43. The current exiting transistor 40 flows to drain fork 65, through drain metallization strip 82, and from there through drain strip 92 to contact electrode 22-2.

[0027] As a numerical example, an LFET power switch, similar to power switch 20 or 220, is configured to turn on and off currents of up to about 200 amps at voltages up to about 1200 volts. It may include 3000 LFET transistors and is fabricated on a substrate approximately 12.5 mm long and about 8 mm wide. The metallization layer 51 may have a thickness of about 1 μm. The source fork 64 and drain fork 65 may optionally taper from about 325 μm to about 110 μm, are separated by a gap of about 27 μm width, and have a thickness of about 4.5 μm. The source strip 81 and drain strip 82 may have a thickness of about 4.5 μm and may be separated by a gap of about 500 μm width. As an example, the strip bridging connector is formed of aluminum or copper and has a thickness of about 100 μm, and may be separated by a lateral space of about 500 μm width. Simulations show that the power switch 20 with the RDL of the above dimensions has an on-resistance of approximately 5.5 mΩ (milliohms). On the other hand, there is no... Figures 5-7A The RDL layer shown is formed in Figure 4 The conventional power switch above layer 60, and having metallization layers 62 and 63 directly connected to lateral electrodes 22-1 and 22-3 respectively for coupling to external circuits, has an on-resistance of approximately 8 mΩ. Figure 8 The power switch 20 shown reduces the on-resistance by approximately 30%.

[0028] Note that although the LFET power switch is described as including an n-channel LFET, the practice of embodiments of this disclosure is not limited to n-channel transistors or LFET transistors. For example, the LFET transistor in the power switch according to the embodiments may be p-channel and may be normally on or normally off transistors. It should also be noted that although in one embodiment the forks 64 and 65 are described as tapered and connected to the trunk, the forks may not be tapered or may not be connected through the trunk.

[0029] Therefore, embodiments of the present disclosure provide an electrical power switch comprising: an array of rows and columns of transistors, each transistor having a source, a drain, and a gate; a plurality of internal interconnect layers including metallizations configured to connect the transistors for parallel operation; source and drain electrodes for connecting the source and drain of the transistors to an external circuit, respectively; and a bridging interconnect layer comprising: a plurality of wavy source bridging conductors providing an electrical connection from the source of the transistor to the source electrode; and a plurality of wavy drain bridging conductors providing an electrical connection from the drain of the transistor to the drain electrode.

[0030] Optionally, each corrugated bridging connector includes at least one corrugation, in which the region of the bridging connector is shifted perpendicular to the plane of the transistor array. Optionally, at least one corrugation varying along the length of the source bridging conductor adjacent to the drain bridging conductor is out of phase with at least one corrugation varying along the length of the source bridging conductor. Alternatively or additionally, the at least one corrugation has a harmonic shape.

[0031] In one embodiment, at least one of the bridging conductors has a strip shape. In another embodiment, at least one of the bridging conductors has a line shape.

[0032] In one embodiment, the plurality of interconnect layers include a first interconnect layer comprising a metallization layer that connects the gates of all transistors in an array of transistors together. Optionally, the plurality of interconnect layers include a second interconnect layer comprising a first source metallization region that connects a plurality of sources of transistors together and a second drain metallization region that connects a plurality of drains of transistors together. Optionally, the source metallization region includes a plurality of source forks, each of the plurality of source forks extending from a common source backbone and covering a row of transistors and electrically connecting the sources of a plurality of transistors in that row together. Additionally, or alternatively, the drain metallization region includes a plurality of drain forks, each of the plurality of drain forks extending from a common drain backbone and covering a row of transistors and electrically connecting the drains of a plurality of transistors in that row together. In one embodiment, the source forks and / or drain forks are tapered.

[0033] In one embodiment, the plurality of interconnect layers include a third strip interconnect layer comprising a plurality of source metallization strips interleaved with a plurality of drain metallization strips. Optionally, each source metallization strip electrically connects a plurality of source forks in the second interconnect layer together. Optionally, each drain metallization strip electrically connects a plurality of drain forks in the second interconnect layer together.

[0034] In one embodiment, each of the plurality of wavy source bridging conductors connects a plurality of source bands together in the third interconnect layer. In one embodiment, each of the plurality of wavy drain bridging conductors connects a plurality of drain bands together in the third interconnect layer. In one embodiment, the transistor is a lateral field-effect (LFET) transistor.

[0035] The description of embodiments of the invention in this application is provided by way of example and is not intended to limit the scope of the invention. The described embodiments include different features, and not all embodiments of the invention require all of these features. Some embodiments utilize only some features or possible combinations of features. Those skilled in the art will conceive of variations of the described embodiments of the invention, as well as embodiments of the invention that include different combinations of the features mentioned in the described embodiments. The scope of the invention is limited only by the claims.

Claims

1. An electrical power switch, the power switch comprising: An array of rows and columns of transistors, each transistor having a source, a drain, and a gate; Multiple internal interconnect layers, the multiple internal interconnect layers including metallizations configured to connect the transistors for parallel operation; The source electrode and drain electrode are used to connect the source and drain of the transistor to an external circuit, respectively. and A bridging interconnect layer, the bridging interconnect layer comprising: - A plurality of wavy source bridging conductors, the plurality of wavy source bridging conductors providing an electrical connection from the source of the transistor to the source electrode; and - A plurality of wavy drain bridging conductors, the plurality of wavy drain bridging conductors providing an electrical connection from the drain of the transistor to the drain electrode.

2. The power switch according to claim 1, wherein, Each corrugated bridging connector includes at least one corrugation, in which a region of the bridging connector is shifted perpendicular to the plane of the array of transistors.

3. The power switch according to claim 2, wherein, The at least one ripple that varies along the length of the source bridging conductor adjacent to the drain bridging conductor is out of phase with the at least one ripple that varies along the length of the source bridging conductor.

4. The power switch according to claim 2, wherein, The at least one wave has a harmonic shape.

5. The power switch according to claim 1, wherein, At least one of the bridging conductors has a strip shape.

6. The power switch according to claim 1, wherein, At least one of the bridging conductors has a linear shape.

7. The power switch according to claim 1, wherein, The plurality of interconnect layers include a first interconnect layer, the first interconnect layer including a metallization layer that connects the gates of all transistors in the array of transistors together.

8. The power switch according to claim 7, wherein, The plurality of interconnect layers include a second interconnect layer, the second interconnect layer including a first source metallization region connecting the plurality of sources of the transistor together and a second drain metallization region connecting the plurality of drains of the transistor together.

9. The power switch according to claim 8, wherein, The source metallization region includes a plurality of source forks, each of which extends from a common source trunk and covers a row of transistors and electrically connects the sources of the plurality of transistors in that row together.

10. The power switch according to claim 9, wherein, The source fork tooth is conical.

11. The power switch according to claim 9, wherein, The drain metallization region includes a plurality of drain forks, each of which extends from a common drain backbone and covers a row of transistors and electrically connects the drains of a plurality of transistors in that row together.

12. The power switch according to claim 11, wherein, The drain fork is tapered.

13. The power switch according to claim 11, wherein, The plurality of interconnect layers include a third strip interconnect layer having a plurality of source metallization bands interleaved with a plurality of drain metallization bands.

14. The power switch according to claim 13, wherein, Each of the source metallization bands electrically connects multiple source forks in the second interconnect layer together.

15. The power switch according to claim 13, wherein, Each of the drain metallization bands electrically connects multiple drain forks in the second interconnect layer together.

16. The power switch according to claim 13, wherein, Each of the plurality of wavy source bridging conductors connects the plurality of source bands in the third interconnect layer together.

17. The power switch according to claim 13, wherein, Each of the plurality of wavy drain bridging conductors connects the plurality of drain bands together in the third interconnect layer.

18. The power switch according to any one of the preceding claims, wherein, The transistor is a lateral field-effect (LFET) transistor.

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