Printed circuit board defect detection method based on improved RT-DETR model

Abstract

The invention discloses a detection method, and particularly relates to a printed circuit board defect detection method based on an improved RT-DETR model, which comprises the following steps of: S1, acquiring a printed circuit board defect image data set, and dividing the printed circuit board defect image data set into a training set, a verification set and a test set in proportion; s2, an improved RT-DETR model is constructed; s3, using the training set and the verification set to train an improved RT-DETR model; s4, performing printed circuit board defect identification on the trained model by using the test set; and S5, the recognition result is evaluated, and the accuracy rate, the recall rate, the average precision, the average precision mean value, the F1 score, the parameter quantity and the number of floating point operation times are calculated. According to the provided detection framework, a multi-scale attention mechanism, a gating aggregation technology and a context perception optimization module are integrated, the real-time reasoning speed is kept, meanwhile, the detection precision is remarkably improved, and the parameter quantity and the calculation complexity of the model are reduced.

Description

Technical Field

[0001] This invention belongs to the field of defect detection technology, and specifically relates to a method for detecting defects in printed circuit boards based on an improved RT-DETR model. Background Technology

[0002] As the precision of the electronics manufacturing industry continues to increase, the inspection of printed circuit boards (PCBs) for defects faces growing technical challenges. Traditional manual inspection methods suffer from low efficiency and poor consistency, making it difficult to meet the high quality control requirements of modern industry.

[0003] Currently, deep learning-based object detection methods offer a new technical approach for PCB defect detection. However, mainstream algorithms such as the YOLO series and Faster R-CNN still have significant limitations when dealing with PCB defects: on the one hand, they are insufficient in extracting features from small-sized defects, and on the other hand, their generalization ability is limited under complex background interference. These factors make it difficult to achieve the expected detection accuracy in real-world industrial scenarios.

[0004] RT-DETR (Real-Time Detection Transformer), as an emerging real-time detection architecture, achieves a good balance between detection accuracy and speed through an end-to-end detection paradigm and a multi-scale feature fusion mechanism. However, there is still room for improvement in the specific task of PCB defect detection, especially in its ability to perceive the features of small defects and distinguish complex texture backgrounds.

[0005] To address the aforementioned issues, this study proposes an improved PCB defect detection scheme based on the RT-DETR framework. This is achieved by optimizing the feature extraction network, enhancing local detail perception capabilities, and refining multi-scale feature fusion strategies. The scheme aims to improve the detection accuracy of minute defects while maintaining the model's real-time inference capabilities, thus providing a more reliable quality inspection solution for industrial applications. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a PCB defect detection method based on an improved RT-DETR model. By using deep learning, target detection and other related technologies, the computational load and complexity of the network are reduced, and the detection efficiency and accuracy of PCB defects are improved.

[0007] To achieve the above objectives, the present invention is implemented as follows: A PCB defect detection method based on an improved RT-DETR model includes the following steps: Step S1: Obtain PCB defect image data and randomly divide the PCB defect image data into training set, validation set and test set in a ratio of 8:1:1; Step S2: Improve the BasicBlock module in the RT-DETR backbone network using the Faster Multi-Scale Attention (FMA) module. The FMA module is obtained by fusing the improved FasterNet Block with the Efficient Multi-Scale Attention (EMA) mechanism. Step S3: Improve the RT-DETR encoder structure by replacing the original RepC3 module with a Fast Gated Aggregation Block (FGAB) module. The FGAB module is obtained by fusing a FasterNet Block and a Convolutional Gated Linear Unit (CGLU) with an improved Mixed Aggregation Network. Step S4: Improve the CCFF module in the RT-DETR encoder by introducing the Pyramid Context-Enhanced Feature Network (PCEFN) module. The PCEFN module is obtained by introducing the Context-Guided Spatial Feature Reconstruction Network (CGRSeg) architecture. Step S5: Use the training and validation sets of the PCB defect detection dataset to train the RT-DETR model improved by steps S2, S3 and S4.

[0008] Step S6: Input the test set images into the trained model for inference, and obtain and evaluate the detection results of PCB defects.

[0009] Furthermore, a preferred implementation is provided, wherein the PCB defect dataset in step S1 is the DsPCBSD+ dataset created by Lü Shengping et al., which includes 9 types of PCB defects, namely short circuit (SH), burr (SP), excess copper (SC), open circuit (OP), mouse bite (MB), hole (HB), conductor scratch (CS), conductor foreign object (CFO) and substrate foreign object (BMFO), and is randomly divided into training set, validation set and test set according to the sample size ratio of 8:1:1.

[0010] Furthermore, a preferred embodiment is provided, wherein the FMA module described in step S2 integrates partial convolution and an efficient multi-scale attention mechanism, and the specific processing includes: The input feature map is segmented along the channel dimension, and spatial convolution is performed on only some channels to extract local features, while the remaining channels are preserved. Then, two 1×1 convolutions are used to refine the features and adjust the channel dimension. Next, the EMA attention mechanism is applied, and spatial attention weights are generated by pooling and convolution in the height and width directions of the feature map to focus on key regions and suppress the background. Finally, the weighted features are fused with the original input through residual connections to ensure stable gradient propagation.

[0011] Furthermore, a preferred embodiment is provided, wherein the FGAB module described in step S3 is designed to integrate lightweight spatial mixing and gated linear units, and the specific processing includes: First, channel projection is performed on the input features to unify the dimensions; then, lightweight spatial feature mixing is performed through depthwise convolution; next, the features are fed into the CGLU unit, which achieves adaptive feature selection by splitting the features into value branches and gate branches and dynamically modulating the response of the value branches using the gate branches; finally, training stability is enhanced by combining the output results with residual connections of random depth.

[0012] Furthermore, a preferred embodiment is provided, wherein the PCEFN module described in step S4 employs a hierarchical and progressive structure to enhance multi-scale context information, and the specific processing includes: First, the Pyramid Context Extraction (PCE) unit performs resolution alignment and concatenation of features from different levels of the future autonomous backbone network, forming a rich multi-scale feature aggregation. Then, the aggregated features are input into a core network composed of multiple stacked Residual Context Mixers (RCMs). Each RCM module contains a Rectangular Self-calibration Attention (RCA) unit and a lightweight Convolutional Multilayer Perceptron (ConvMLP). The RCA unit performs one-dimensional pooling along both the height and width directions and uses rectangular convolutional kernels to capture long-range spatial dependencies, generating calibration maps to refine local feature representations. In the feature fusion stage, the refined multi-scale features are modulated and fused across levels using an Adaptive Upsample Fusion (AUF) module and a Fuse Block Multi (FBM) module. In this process, FBM selectively enhances shallow features by generating a spatially gated map, while AUF achieves smooth integration of shallow and deep features through upsampling and feature addition. After multiple cycles of cascaded RCM-AUF-FBM processing, the output is enhanced features rich in global context and local details, which are finally sent to the detection head to complete the prediction task.

[0013] Furthermore, a preferred embodiment is provided, wherein in step S5, the improved RT-DETR algorithm PCB defect detection model obtained in steps S2, S3, and S4 is trained using the training set and validation set obtained in step S1, and the method for obtaining the trained PCB defect detection model is as follows: Based on the improved RT-DETR algorithm, the key parameters of the model were configured: the optimizer was Adam, the number of training epochs was 100, the learning rate was 0.0001, and the training batch size was 4. The model weights were also initialized.

[0014] Furthermore, a preferred embodiment is provided, wherein the method for verifying the trained PCB defect detection model described in step S5 using the test set from step S1 in step S6 is as follows: Step S61: Use the test set divided in step S1 to verify the PCB defect detection model, ensuring that the test set and the training set have the same class distribution and data quality during the defect detection model verification process; Step S62: Perform performance testing on the trained PCB defect detection model using the test set. The test includes key metrics such as precision, recall, F1 score, and mean precision. Step S63: Compare and analyze the evaluation results of the test set with the performance of the training set to verify the generalization ability of the model and ensure its applicability in real industrial scenarios.

[0015] Compared with the original RT-DETR model for PCB defect detection, the PCB defect detection method based on the improved RT-DETR model provided in this invention has the following advantages: (1) The proposed detection framework integrates multi-scale attention mechanism, gating aggregation technology and context-aware optimization module, which significantly improves detection accuracy while maintaining real-time inference speed, and effectively reduces the number of model parameters and computational complexity, providing a reliable solution for achieving efficient and accurate defect detection in resource-constrained industrial environments.

[0016] (2) A lightweight and efficient feature enhancement module, FMA, was designed. By optimizing spatial encoding and attention weight allocation, the module significantly enhances the backbone network’s ability to extract fine-grained defect features. While improving the representation effect of small defects, it effectively reduces the computational redundancy and number of parameters of the model.

[0017] (3) An adaptive multi-scale semantic fusion module FGAB was developed. This module improves the alignment and fusion efficiency of cross-scale features in the detection head by introducing gated linear units and lightweight spatial interaction mechanisms, thereby enhancing the semantic consistency and robustness of the model in multi-scale defect detection.

[0018] (4) A pyramid context enhancement feature network (PCEFN) was constructed. This module effectively improves the model’s ability to perceive and locate defects with elongated shape, irregular shape and background interference by modeling anisotropic context dependencies and hierarchical feature refinement mechanism, and further enhances the overall performance of the detection system. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic flowchart of the method of the present invention; Figure 2 A schematic diagram of the improved RT-DETR network architecture; Figure 3 This is a schematic diagram of the structure of the FMA module described in this invention; Figure 4 This is a schematic diagram of the FGAB module described in this invention; Figure 5 This is a schematic diagram of the PCEFN module described in this invention; Figure 6 This is a diagram showing the detection results of the present invention. Detailed Implementation

[0021] This embodiment provides a PCB defect detection method based on an improved RT-DETR model, such as... Figure 1 As shown, it includes the following steps: Step S1: Obtain PCB defect image data and randomly divide the data into training set, validation set and test set in a ratio of 8:1:1; In this step, the PCB defect dataset obtained is the DsPCBSD+ dataset created by Lü Shengping et al., which includes 9 types of PCB defects: short circuit (SH), burr (SP), excess copper (SC), open circuit (OP), mouse bite (MB), hole (HB), conductor scratch (CS), conductor foreign object (CFO), and substrate foreign object (BMFO). It is randomly divided into training set, validation set and test set according to the sample size ratio of 8:1:1.

[0022] Step S2: Build a PCB defect detection model based on the improved RT-DETR algorithm, such as... Figure 2 As shown; In this step, the improved RT-DETR architecture consists of three main parts: a feature extraction backbone network, an adaptive detection head, and a context-enhanced Transformer encoder. The backbone network uses ResNet18 as the feature extractor and improves the BasicBlock module with the FMA module to enhance fine-grained feature representation, while reducing redundant parameters through optimized spatial encoding. The original RepC3 structure in the RT-DETR encoder is replaced with the FGAB module, which achieves adaptive cross-scale fusion through gated channel interaction, thereby enhancing semantic consistency and improving computational efficiency. In the encoder, the PCEFN module is introduced to optimize multi-scale feature representation by modeling hierarchical and anisotropic contextual dependencies, thus improving the localization accuracy of small and elongated defects. The improved RT-DETR framework effectively integrates multi-scale attention, gated aggregation, and context-aware optimization, achieving high-precision defect detection under complex background interference and real-time constraints.

[0023] PCB defect detection faces challenges such as identifying minute defects and handling complex background interference. The original BasicBlock module in ResNet18 has limitations in fine-grained feature extraction and has a relatively large number of parameters. To address these issues, this implementation introduces an FMA module to improve the BasicBlock module. For example... Figure 2 As shown, the FMA module achieves efficient feature extraction by optimizing spatial encoding and attention weight allocation. Given an input feature map X with dimensions C×H×W, the module's processing procedure is as follows: First, channel segmentation and spatial convolution operations are performed to divide the input feature map into two parts, and convolution processing is performed only on a subset of channels: ; in, `concat` represents a standard convolution operation with a kernel size of 3×3, and `concat` represents a concatenation operation along the channel dimension. This design performs convolution operations only on the first 1 / 4 of the channels, significantly reducing computational cost while maintaining feature extraction performance.

[0024] The features are then refined using two consecutive 1×1 convolutions: ; Here, δ represents the ReLU activation function. The first 1×1 convolution is used to expand the channel dimension to enhance feature representation, and the second 1×1 convolution restores the number of channels to the original dimension.

[0025] Subsequently, spatial attention weights are calculated using the EMA attention mechanism. The feature map Z is divided into G groups, and for each group of features... Calculate the attention weights separately: ; in, and These represent adaptive average pooling operations along the height and width directions, respectively. σ represents the sigmoid activation function, and ⊙ represents element-wise multiplication.

[0026] Finally, the weighted features are fused with the original input features through residual connections: ; This residual connection design ensures stable gradient propagation while preserving low-frequency information of the original features.

[0027] like Figure 3 As shown, the FGAB module achieves efficient feature fusion through a gating mechanism. Given input features... Its size is The processing procedure of this module is as follows: First, adjust the channel dimension of the input features: ; When input channel number When the number of channels is inconsistent with the target number C, the number of channels is unified by 1×1 convolution.

[0028] Spatial features are then blended using depthwise convolution: ; in, This indicates a depthwise separable convolution operation.

[0029] Next, adaptive feature selection is achieved through the CGLU mechanism: ; ; ; in, and The parameters are the learnable convolution kernel parameters, and GELU is the Gaussian error linear unit activation function. This indicates a depthwise separable convolution with a kernel size of 3×3.

[0030] The final output is achieved through residual connections with random depth: ; in, The DropPath parameter is a learnable channel-level scaling parameter, and it is a random depth operation. This design effectively improves the training stability and generalization ability of the model.

[0031] like Figure 4 As shown, the PCEFN module enhances its multi-scale contextual information modeling capabilities through a hierarchical and progressive structure. This module employs a multi-level feature refinement and fusion strategy, with the specific processing steps as follows: First, multi-scale features from the backbone network are integrated using a PCE unit. This unit receives feature maps from three different levels. , , These correspond to low-level, mid-level, and high-level features, respectively. Adaptive average pooling is used to unify these feature maps to the same spatial resolution, and they are then concatenated along the channel dimension to form a comprehensive multi-scale feature representation. ; Here, Pool represents the adaptive average pooling operation, which adjusts feature maps from different levels to a uniform resolution.

[0032] In the feature refinement stage, multiple cascaded RCMs are used for deep feature processing. Each RCM module contains two core components: RCA and ConvMLP. The RCA unit uses a unique rectangular convolutional kernel design to model long-range spatial dependencies along the horizontal and vertical directions, respectively. In practice, the input features are first subjected to one-dimensional average pooling in the height and width directions to obtain feature statistics in the two directions. These statistics are then added together and the spatial relationships are extracted using a rectangular convolutional kernel, ultimately generating a spatial calibration map that reflects the anisotropic context.

[0033] The calibration map is element-wise multiplied with local features extracted through a 3×3 depthwise convolution, achieving an organic fusion of global context and local details. This process can be represented as: ; Where A represents the spatial calibration map, and ⊙ represents element-wise multiplication.

[0034] In the feature fusion stage, a dual-path fusion strategy is adopted. On the one hand, the FBM module realizes cross-level feature modulation. This module selectively enhances shallow features by generating spatial gating maps, highlighting spatial locations related to defects. On the other hand, the AUF module realizes feature upsampling and fusion. High-level semantic features are upsampled to the same resolution as shallow features through bilinear interpolation, and then added to the shallow features after adjusting the number of channels through 1×1 convolution, achieving smooth integration of deep and shallow features.

[0035] After multiple RCM-AUF-FBM processing loops, the final output feature map contains rich global contextual information while retaining necessary local detail features, providing high-quality feature representations for subsequent detection heads. The entire processing forms a complete closed loop from feature extraction, refinement to fusion, effectively improving the model's ability to detect multi-scale defects, especially slender and small target defects.

[0036] Step S3: Use the training set and validation set obtained in step S1 to train the PCB defect detection model of the improved RT-DETR algorithm obtained in step S2, and obtain the trained PCB defect detection model. In this step, the model is built using the PyTorch deep learning framework. During training, the Adam optimizer is used, with 100 training epochs, a learning rate of 0.0001, and a batch size of 4. The model weights are also initialized.

[0037] Step S4: Using the test set obtained in step S1, perform PCB defect identification on the RT-DETR model trained in step S3 to obtain the identification results; In this step, the improved RT-DETR algorithm model is deployed to a computer platform. The model is trained using a divided training and validation set. Finally, the trained model is applied to the PCB defect detection task, and the detection results are shown in the figure below. Figure 6 As shown in the figure. Experimental results show that the detection system can effectively identify various defect features of PCBs, and significantly improves detection efficiency and recognition accuracy compared with traditional detection methods.

[0038] Step S5: Evaluate the trained RT-DETR model based on the recognition results in step S4, and calculate the precision P, recall R, mean precision AP, mean mean precision mAP, F1-score, number of parameters, and gigabit-per-second (GFLOPs).

[0039] In this step, to further explore the effectiveness of the improved RT-DETR model, ablation experiments were conducted to evaluate the contribution of each component to the overall model performance. All experiments were performed under the same hardware environment and training parameters to ensure accurate evaluation of the impact of each improved module on model performance. The results of the ablation experiments are shown in Table 1: Table 1 Ablation Experiment Data Model FMA FGAB PCEFN mAP50(%) mAP50-95% (%) Parameter (M) GFLOPs(G) 1 85.1 51.5 19.88 57.0 2 ✓ 87.1 52.2 16.91 51.5 3 ✓ 86.9 52.2 19.52 51.4 4 ✓ 86.9 53.2 19.24 48.2 5 ✓ ✓ 87.6 53.1 16.54 45.9 6 ✓ ✓ ✓ 88.5 54.0 16.30 42.8

[0040] Based on the ablation experiment results in Table 1, the model performance showed a continuous improvement after sequentially introducing the FMA, FGAB, and PCEFN modules: the basic model's mAP50 and mAP50-95 were 85.1% and 51.5%, respectively; after adding FMA, these figures increased to 87.1% and 52.2%; further introduction of FGAB resulted in 87.6% and 53.1%; and finally, the introduction of the PCEFN module further improved mAP50 and mAP50-95 to 88.5% and 54.0%, respectively. Simultaneously, the number of model parameters decreased from 19.88M to 16.30M, and GFLOPs decreased from 57.0G to 42.8G. The experimental results demonstrate that each module effectively reduced model complexity while enhancing feature extraction capabilities, achieving a synergistic optimization of detection accuracy and inference efficiency.

[0041] To comprehensively evaluate the overall performance of this invention, a comparative experiment was conducted with current mainstream target detection models. The specific results are shown in Table 2.

[0042] Table 2 Comparative Experimental Data Model P(%) R(%) mAP50(%) mAP50-95% (%) F1 score (%) Faster R-CNN 46.0 72.2 61.3 28.9 56.0 SSD 10.7 84.6 65.6 27.4 18.9 YOLOv8 82.9 79.9 85.7 51.3 81.1 YOLOv10 83.4 79.4 86.0 51.0 81.2 YOLOv11 82.8 80.5 86.0 51.3 81.5 YOLOv12 80.1 80.2 85.8 51.6 80.1 YOLOv13 80.3 82.4 86.3 51.9 81.1 YOLOX 82.9 78.0 83.7 48.4 80.4 DEIM 81.3 81.0 86.0 52.4 81.1 RT-DETR 84.8 80.5 85.1 51.5 82.3 OURS 85.4 84.2 88.5 54.0 84.7

[0043] Based on the comparative experimental results shown in Table 2, the method of this invention outperforms the listed mainstream detection models in all key indicators. Specifically, this method achieves the best results in precision (85.4%), recall (84.2%), mAP50 (88.5%), mAP50-95 (54.0%), and F1 score (84.7%), comprehensively surpassing the comparative models such as Faster R-CNN, SSD, YOLO series and its variants, and DETR. The experimental data fully demonstrate that this invention has significant advantages in detection accuracy and overall performance.

[0044] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0045] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for detecting defects in printed circuit boards based on an improved RT-DETR model, characterized in that, Includes the following steps: Step S1: Obtain the printed circuit board defect image dataset and divide it into training set, validation set and test set according to the proportion; Step S2: Construct the improved RT-DETR model; Step S3: Train the improved RT-DETR model using the training set and validation set; Step S4: Use the test set to identify printed circuit board defects in the trained model; Step S5: Evaluate the recognition results by calculating precision, recall, mean precision, mean mean precision, F1 score, number of parameters, and number of floating-point operations.

2. The printed circuit board defect detection method based on the improved RT-DETR model according to claim 1, characterized in that, The printed circuit board defect dataset mentioned in step S1 includes nine types of printed circuit board defects: short circuit, burr, excess copper, open circuit, rodent bite, hole, conductor scratch, conductor foreign object, and substrate foreign object. It is randomly divided into training set, validation set and test set according to the sample size ratio of 8:1:

1.

3. The printed circuit board defect detection method based on the improved RT-DETR model according to claim 1, characterized in that, The step S2 of building the improved RT-DETR algorithm includes: Step S21: Improve the BasicBlock module in the RT-DETR backbone network using a fast multi-scale attention module; Step S22: Improve the RT-DETR encoder structure by replacing the original RepC3 module with the fast gate aggregation block module; Step S23: Improve the RT-DETR encoder using the pyramid context enhancement feature network module.

4. The printed circuit board defect detection method based on the improved RT-DETR model according to claim 3, characterized in that, The processing procedure of the fast multi-scale attention module in step S21 includes: First, the input feature map is segmented along the channel dimension, and spatial convolution is performed on only some channels. Then, two 1×1 convolutional layers are used to refine the features and adjust the channel dimension. Next, a grouped, efficient multi-scale attention mechanism is applied, which generates spatial attention weights by pooling and convolution in the height and width directions of the feature map. Finally, the weighted features are fused with the original input through residual connections.

5. The printed circuit board defect detection method based on the improved RT-DETR model according to claim 3, characterized in that, The processing procedure of the fast gating aggregation block module in step S22 includes: First, channel projection is performed on the input features to unify the dimension, and the number of input channels is adjusted to the target dimension through 1×1 convolution. Then, lightweight spatial feature mixing is performed through depthwise convolution to enhance the spatial feature representation while keeping the feature map size unchanged. Next, the features are fed into a convolutional gated linear unit, which splits the features into value branches and gate branches, and uses the activation function of the gate branch to activate the output to dynamically modulate the response of the value branch, thereby achieving adaptive feature selection. Finally, the processed features are added to the original input features by combining residual connections of random depth to output the result.

6. The printed circuit board defect detection method based on the improved RT-DETR model according to claim 3, characterized in that, The processing procedure of the pyramid context enhancement feature network module in step S23 includes: First, the pyramid context extraction unit performs resolution alignment and concatenation of features from different levels of the future backbone network to form aggregated features containing multi-scale information. Then, the aggregated features are input into the core network, which consists of multiple stacked residual context mixers. Each residual context mixer contains a rectangular self-calibrating attention unit and a lightweight convolutional multilayer perceptron, which are used to capture long-distance feature associations in different directions in the image and to refine and enhance features in local regions, respectively. Finally, the refined multi-scale features are modulated and fused across levels through an adaptive upsampling fusion module and a fusion block multi-scale module. The fusion block multi-scale module selectively enhances shallow features by generating spatial gating weights, while the adaptive upsampling fusion module achieves adaptive integration of deep and shallow features through learnable upsampling operations, ultimately outputting an enhanced feature representation rich in global semantics and local details.

7. The printed circuit board defect detection method based on the improved RT-DETR model according to claim 1, characterized in that, The training process described in step S3 uses the Adam optimizer, with 100 training rounds, a learning rate of 0.0001, and a batch size of 4.

8. The printed circuit board defect detection method based on the improved RT-DETR model according to claim 1, characterized in that, The evaluation described in step S5 includes: Step S51: Verify the model's generalization ability using the test set; Step S52: Calculate the precision, recall, F1 score, mean precision, and mean precision metric. Step S53: Calculate the number of model parameters and the number of floating-point operations to evaluate computational efficiency.

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