Interpolation type time-to-digital converter based on pre-decision partial activation

Abstract

An interpolation type time-to-digital converter based on pre-judgment partial activation comprises a reference voltage generating circuit, a parallel converter array, a parallel pre-judgment circuit array, an interpolation TDC, a one-hot code encoder and a binary encoder which are connected in sequence, and a pre-judgment auxiliary converter which is connected with the parallel converter array and the parallel pre-judgment circuit array respectively, dynamic partial activation is achieved through a pre-judgment mechanism, and the method is suitable for any VTC structure and has wider applicability and lower dynamic power consumption. Meanwhile, the decoding logic structure is simple, extra delay is not introduced, and the method is suitable for a high-speed low-power-consumption time domain ADC system.

Description

Technical Field

[0001] This invention relates to a technology in the field of analog-to-digital conversion, specifically an interpolation-type time-to-digital converter (TDC) based on pre-decision part activation. Background Technology

[0002] High-speed time-domain analog-to-digital converters (ADCs) typically employ fully parallel voltage-time conversion (VTC) and time-delay conversion (TDC) to achieve faster sampling rates and lower conversion delays. Traditional architectures often use fully active TDC to achieve high-speed parallel time measurement; however, this architecture still activates unnecessary TDC when the input voltage differs significantly from the reference voltage, resulting in wasted power and severely limiting its application in low-power scenarios. Existing multi-stage TDC ADC technologies lack a mechanism to predict the necessity of conversion at the front end, thus failing to avoid power waste caused by ineffective conversions. Summary of the Invention

[0003] To address the aforementioned shortcomings of existing technologies, this invention proposes an interpolation-based time-to-digital converter (TD-RCD) with pre-decision partial activation. This pre-decision mechanism enables dynamic partial activation, making it applicable to any VTC structure and offering wider applicability and lower dynamic power consumption. Furthermore, the decoding logic structure is simple, introducing no additional delay, and is suitable for high-speed, low-power time-domain ADC systems.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to an interpolation-type time-to-digital converter based on pre-decision activation, comprising: a reference voltage generation circuit, a parallel converter array, a parallel pre-decision circuit array, an interpolation TDC, a one-hot code encoder, a binary encoder, and a pre-decision auxiliary converter connected in sequence. Specifically: the parallel converter array, composed of several differential VTC circuits connected in parallel, converts the differential input signal in the voltage domain into multiple differential signals in the time domain according to the voltage steps of the reference voltage generation circuit; the pre-decision auxiliary converter generates a pre-decision phase time signal based on a preset voltage and half of the reference voltage, and sends it to the parallel pre-decision circuit array; the parallel pre-decision circuit, composed of several pre-decision circuits connected in parallel, determines the phase of the converted multiple differential signals in the time domain based on the pre-decision phase time signal, and generates corresponding enable signals based on the timing of the pulse edge relative to the edge to control the operating state of each TDC in the interpolation TDC and the one-hot code encoder; the interpolation TDC converts the interpolated time signal into a differential digital domain thermometer code according to the enable signal, and sends it to the one-hot code encoder, which then outputs it as a binary digital signal through the binary encoder.

[0006] The aforementioned enable signal, when the output edge of the multi-channel time-domain differential signal is earlier than the reference voltage edge, enables the TDC interpolation path of the corresponding channel in the interpolation TDC to be turned off in advance.

[0007] The interpolation TDC includes an interpolation structure and a latch array (SR-Latch), wherein the interpolation structure, composed of time-domain interpolation (TDI) units, interpolates the time-domain signal output by the VTC to form a higher resolution time-domain signal, and the latch array outputs the digital domain one-hot code result based on the interpolated time-domain signal.

[0008] Technical effect

[0009] This invention employs a pre-decision-based dynamic partial activation control architecture between the parallel VTC array and the interpolated TDC to perform pre-decision assistance, pre-decision enable, and interpolation activation. It determines whether to pre-shut down based on the output edge, achieving on-demand dynamic activation of the TDC and significantly reducing dynamic power consumption. The corresponding TDC channel is activated only when the input voltage is within the range of the corresponding reference voltage; when the difference is large, the relevant channel is shut down to avoid unnecessary power consumption. This mechanism has a simple structure, does not introduce additional delay, and balances high speed with low power consumption. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of the present invention;

[0011] Figure 2 This is a schematic diagram of the VTC circuit at the p-end;

[0012] Figure 3 This is a schematic diagram illustrating the output and pre-decision principle of a parallel converter array;

[0013] Figure 4 This is a schematic diagram of the pre-decision circuit;

[0014] Figure 5 Schematic diagram of interpolation activation switch;

[0015] Figure 6 This is a schematic diagram of the pre-decision enable module;

[0016] Figure 7 This is a schematic diagram of the pre-judgment result transmission module;

[0017] Figure 8 This is a schematic diagram of the 8x interpolation TDC in the embodiment;

[0018] Figure 9 This is a schematic diagram of a time-domain interpolation unit based on an inverter;

[0019] Figure 10 The diagram shows two types of latch circuit structures in a latch array.

[0020] Figure 11 This is a schematic diagram of a one-hot code encoder.

[0021] Figure 12 and Figure 13 This is a schematic diagram illustrating the effect of an example. Detailed Implementation

[0022] like Figure 1 As shown, this embodiment relates to an interpolation-type time-to-digital converter based on pre-decision partial activation, comprising: a reference voltage generation circuit and a parallel converter array VTC connected in sequence. 0-8 Parallel pre-decision circuit array, interpolation TDC, one-hot code encoder and binary encoder, and pre-decision auxiliary converter VTC e Wherein: Parallel converter array VTC 0-8 The differential voltage domain input signal V is generated based on the voltage steps of the reference voltage generation circuit. inp V inn Convert to phase Φ xp<0> ~Φ xp<8> and Φ xn<0> ~Φ xn<8> Differential time domain signal; pre-decision auxiliary converter VTC e According to the preset voltage V set and reference voltage V ref / 2 Generates the pre-decision phase time signal Φ e To a parallel pre-decision circuit array; each pre-decision circuit in the parallel pre-decision circuit array determines the pre-decision phase time signal Φ e The phase of each converted time signal is determined based on the pulse edge relative to Φ. e Early or late generation of the edge output enable signal en op<0> ~en op<8> en on<0> ~en on<8> The interpolation TDC controls and determines the operating state of the interpolation TDC. Based on the time-domain interpolation unit (TDI), the interpolation TDC receives the decided time signal and performs interpolation. The time-domain interpolation unit is based on an inverter and converts the interpolated time signal into differential digital temperature code D. p<0> ~D p<64> and D n<0> ~D n<64> To a one-hot encoder; the one-hot encoder is enabled by the output enable signal en from the parallel pre-decision circuit array. op<0> ~en op<8> en on<0> ~en on<8> For thermometer code D p<0> ~D p<64> and Dn<0> ~D n<64> Re-encoded as one-hot code D out The binary encoder will convert the one-hot code D out Encoded as a binary digital signal B out And output it.

[0023] The reference voltage V ref =V ref_top -V ref_btm , where: V ref_top and V ref_btm These are the highest and lowest potentials of the reference voltage step, respectively.

[0024] The parallel converter array VTC 0-8 It consists of nine identical differential VTC circuits connected in parallel. Each differential VTC circuit comprises a p-terminal VTC circuit and an n-terminal VTC circuit of identical structure. The k-th differential circuit VTC... <k>< / k> The inputs of the p-terminal VTC circuit and the n-terminal VTC circuit are V... inp V inn The outputs are Φ xp <k>< / k> and Φ xn <k>< / k> .like Figure 2 The diagram shown is a schematic of the VTC circuit at the p-end.

[0025] like Figure 2 As shown, the pre-decision auxiliary converter VTC e It adopts the same structure as the p-terminal VTC circuit or the n-terminal VTC circuit, including: a switching network S 1-6 and the input capacitor C connected to it respectively in Reference capacitor C ref Current source I charge And an inverter, where: input capacitor C in Set at input terminal V inp <k>< / k> Between the reference capacitor and ground potential, the reference capacitor is set at the reference voltage V. ref <k>< / k> Between the power supply point and the ground potential, the current source is located between the power supply point and the inverter input terminal; the inverter output terminal is connected to the output terminal of the VTC system.

[0026] The switch network S 1-6 Includes: a setting at the input terminal and the input capacitor C in The first switch S1 is located between the reference voltage terminal and the reference capacitor C. ref The second switch S2, the third switch S3 located between the input terminal and the ground terminal of the inverter, and the current source I respectively located between the input terminal and the ground terminal of the inverter. charge Input capacitor C in and reference capacitor C refThe fourth to sixth switches S4-S6 are between the following: the first to third switches S1-S3 are controlled by the sampling clock clks, and the fourth to sixth switches S4-S6 are controlled by the inverted signal of the sampling clock.

[0027] When the sampling clock clks is high, the input and reference capacitors sample the input voltage signal and reference voltage, respectively. When the sampling clock clks returns to ground, sampling is turned off, and the upper plate of the capacitor is shorted for charge redistribution. At this time, the upper plate potential V cp <k>< / k> It will step upwards, and the magnitude of the step is equal to V. inp <k>< / k> and V ref <k>< / k> Proportional correlation, and then the current source charges the upper plate of the capacitor at a slower rate than the redistribution process, when V cp <k>< / k> Exceeding the inverter flip threshold V th At this time, a pulse edge is formed at the input terminal, and the phase Φ of the edge is... xp<0> ~Φ xp<8> It can characterize the time signal after VTC conversion.

[0028] The aforementioned pre-decision auxiliary converter VTC e Control of the parallel converter array VTC 0-8 The outputs of the p-terminal and n-terminal VTC circuits in each differential VTC circuit are enabled only when VTC... e Generate the pre-decision phase time signal Φ e Only then can the outputs of the remaining VTCs be transmitted to the TDC.

[0029] like Figure 3 As shown, taking the p-terminal VTC circuit as an example, when the pre-decision auxiliary converter VTC... e The generated time signal Φ e The phase is relatively early; taking the situation in the figure as an example, Φ xp<0> and Φ xp<1> Too early at the edge, via Φ e The enable signal after the decision selects not to activate the interpolation paths of VTC0 and VTC1; while Φ xp<2> Φ xp<3> The subsequent time signal edges are all later than Φ. e Therefore, the subsequent interpolation circuit is activated normally. Redundancy is retained here for the interpolation process to ensure Φ xp<3> It can perform upward interpolation normally; assuming the effective interpolation process occurs at Φ xp<2> Φ xp<3> Between, then Φ xp<4> Although the interpolation path corresponding to the phases later than it is enabled by default, it does not cause state flipping in actual operation and does not generate additional dynamic energy consumption. Therefore, we ignore the extra attention to its interpolation activation.

[0030] For cases where the input voltage is significantly higher than the reference voltage, an additional VTC stage can be used. e The generated time output shuts off the outputs of other VTCs; for problems where the input voltage is significantly lower than the reference voltage, the VTC will not generate a time output by default. That is, only TDCs with a reference voltage within a certain range (e.g., ±8 LSB) near the input voltage will be activated, thereby reducing the dynamic power consumption of the TDC. Taking VTC3 as an example, when V... in <V ref3 At -8LSB, the VTC charging start voltage is low, making it unable to generate an effective time output. The corresponding time-domain interpolation unit will not flip, thus this architecture inherently possesses certain selective activation characteristics. When V... in >V ref3 At +8LSB, VTC generates a time output and activates TDC, resulting in dynamic power consumption. However, note that subsequent interpolation results will always be all 1s, indicating that the time-domain interpolation unit does not need to operate under these conditions. Only when V... in In V ref Subsequent time-domain interpolation units only need to operate within ±8 LSB.

[0031] In addition, when the time domain interpolation unit is not working, it will produce an error output. Therefore, a one-hot encoder is set at the 8x interpolation TDC output. The original TDC output is only transmitted to the encoder when the outputs of adjacent VTCs are different. Otherwise, it is fixed to 0 or 1. This one-hot encoder is preferably implemented through a NOR gate.

[0032] like Figure 4 As shown, taking a single-ended circuit structure as an example, each pre-decision circuit in the parallel pre-decision circuit array includes: an interpolation activation switch, a pre-decision enable module, and a pre-decision result transmission module, wherein: the pre-decision enable module transmits the pre-decision result based on the pre-decision phase time signal Φ. e For Φ xp <k>< / k> Generate the decision enable signal en p <k>< / k> The interpolation activation switch is enabled by the decision enable signal en. p <k>< / k> The control module determines whether subsequent time-domain interpolation units are activated; the pre-decision result transmission module transmits the results based on the decision enable signal en. p <k>< / k> Generate output enable signal en op <k>< / k> And transmit it to the unique hot code encoder.

[0033] like Figure 5 As shown, the interpolation activation switch adopts a transmission gate structure with NMOS and PMOS sources and drains shorted respectively.

[0034] like Figure 6As shown, the pre-decision enable module includes: a decision circuit composed of gated inverters and a positive feedback loop comprising two inverters and a transmission gate structure, wherein: the positive feedback loop pulls the level of the pre-decision signal to the power rail to avoid the floating level problem of the decision result output level, when Φ e When Φ is high level xp <k>< / k> Upon arrival, output enable signal en p <k>< / k> A high level controls the interpolation activation switch to turn on; conversely, a low level indicates "en". p <k>< / k> Low level, no activation of interpolation.

[0035] like Figure 7 As shown, the pre-decision result transmission module includes: a transmission circuit composed of two gated inverters and a driver stage composed of inverters, wherein: the gated inverters are controlled by a sampling clock, and the input is an enable signal en. p <k>< / k> and output en op <k>< / k> The result of the pre-decision is sent to the one-hot code encoder.

[0036] like Figures 8-10 As shown, in this embodiment, the interpolation TDC is an 8x interpolation TDC structure, including: an interpolation structure and a latch array (SR-Latch), wherein: the interpolation structure composed of 65 TDI units interpolates the time domain signal output by the VTC to form a higher resolution time domain signal, and the latch array outputs the digital domain one-hot code result based on the interpolated time domain signal.

[0037] like Figure 8 As shown, the 8x interpolation TDC structure is divided into two layers of staggered connections of 33+32 units by 65 TDI units. It adopts, but is not limited to, the technology described by D.-R. Oh et al. in "A 65-nm CMOS 6-bit 2.5-GS / s 7.5-mW 8 ×Time-Domain Interpolating Flash ADC With Sequential Slope-Matching OffsetCalibration" (IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 288-297, Jan. 2019).

[0038] like Figure 9 As shown, the TDI unit includes two sets of inverter pairs connected in parallel, wherein each inverter pair is based on the input time signal Φ. a Φ b This generates a time signal with a phase between the two, and the phase is Φ. interpolated .

[0039] like Figure 10 As shown, the latch array includes several groups of latch units connected in parallel. Each latch unit is an SRL structure based on NAND gates or an SRL structure based on NOR gates. The SRL structure based on NAND gates outputs the decision result of the corresponding bit according to the order of the rising edges of the time domain signal, and the SRL structure based on NOR gates outputs the decision result of the corresponding bit according to the order of the falling edges of the time domain signal. The decision result is used as the temperature code digital output of the TDC.

[0040] like Figure 11 As shown, the unique thermal code encoder uses a five-input NOR gate array, based on the thermometer code D output by the TDC. p<0> ~D p<64> D n<0> ~D n<64> and the result of the pre-judgment op<0> ~en op<8> en on<0> ~en on<8> Generate a 65-bit one-hot code D out<0> ~D out<64> .

[0041] The binary encoder is implemented using a circuit based on Fat Tree topology logic. The digital circuit connection logic is shown in Table 1, where "||" represents OR logic. A 6-bit binary digital output B is generated based on the 65-bit one-hot code. out .

[0042] Table 1

[0043] The input connections of the one-hot code encoder are shown in Table 2.

[0044] Table 2

[0045] A test circuit was built on the Cadence platform for actual simulation to test the interpolation-type time-to-digital converter based on pre-decision activation of this invention. Under a 1.26GHz single-frequency sine wave input test, the dynamic parameters of the digital output were obtained: effective number of bits (ENoB) approximately 5.5 bits, signal-to-noise ratio (SNDR) approximately 34.8 dB, and spurious-free dynamic range (SFDR) approximately 46.6 dBc. Under different preset reference voltages V... set Under various conditions, multiple tests were conducted, and the obtained power and effective number of bits increased with V. set Changes such as Figure 12 , Figure 13 As shown, within the range where the ENOB index is not degraded, Vset The power consumption P of TDC at 250mV TDC Compared to V set At 400mV, the power consumption of the TDC decreases by more than 23%, significantly reducing the power consumption of the interpolated TDC. If V set If the value is large, then the pre-decision reference phase Φ e The late appearance of the pre-decision mechanism results in most VTC output edges being earlier than the reference phase, thus increasing the number of channels deemed valid. This weakens the selectivity of the pre-decision mechanism for the activation range of the time-domain interpolation units. In this situation, when the input signal differs significantly from the reference voltage, many time-to-digital converters remain active, leading to increased dynamic power consumption. Dynamic power consumption is highest when the pre-decision function completely fails, i.e., in the traditional structure. However, at the same time... Figure 13 China V set =200mV, as shown, when V set When the value is too small, the pre-decision reference phase Φ e If it occurs too early, some VTC outputs that should participate in the effective interpolation conversion may be judged as invalid and turned off prematurely. This will result in insufficient signal redundancy available for interpolation, or even loss of effective time information, affecting the overall accuracy and linearity of analog-to-digital conversion and reducing the effective number of bits ENOB.

[0046] Based on simulation results and principle analysis, compared with existing technologies, with reasonable V... set For example, if the voltage is >250mV, this invention can effectively reduce the overall dynamic power consumption of the converter without sacrificing conversion accuracy through pre-decision technology.

[0047] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. An interpolation-type time-to-digital converter based on pre-decision partial activation, characterized in that, include: The circuit consists of a reference voltage generation circuit, a parallel converter array, a parallel pre-decision circuit array, an interpolation TDC, a one-hot code encoder, a binary encoder, and a pre-decision auxiliary converter connected in sequence. Specifically: the parallel converter array, composed of several differential VTC circuits connected in parallel, converts the differential input signal in the voltage domain into multiple differential signals in the time domain based on the voltage steps of the reference voltage generation circuit; the pre-decision auxiliary converter generates a pre-decision phase time signal based on a preset voltage and half of the reference voltage, and sends it to the parallel pre-decision circuit array; the parallel pre-decision circuit, composed of several pre-decision circuits connected in parallel, judges the phase of the converted multiple differential signals in the time domain based on the pre-decision phase time signal, and generates corresponding enable signals based on the timing of the pulse edge relative to the edge, controlling the operating state of each TDC in the interpolation TDC and the one-hot code encoder; the interpolation TDC converts the interpolated time signal into a differential digital domain thermometer code based on the enable signal, and sends it to the one-hot code encoder, which then outputs it as a binary digital signal through the binary encoder.

2. The interpolation-type time-to-digital converter based on pre-decision partial activation according to claim 1, characterized in that, The parallel converter array consists of nine differential VTC circuits of the same structure connected in parallel. Each differential VTC circuit consists of a p-terminal VTC circuit and an n-terminal VTC circuit of the same structure. The aforementioned pre-decision auxiliary converter adopts the same structure as the p-end VTC circuit or the n-end VTC circuit.

3. The interpolation-type time-to-digital converter based on pre-decision partial activation according to claim 2, characterized in that, The VTC circuit includes a switching network and an input capacitor, a reference capacitor, a current source, and an inverter connected thereto. The input capacitor is located between the input terminal and ground potential, the reference capacitor is located between the reference voltage and ground potential, and the current source is located between the power supply point and the input terminal of the inverter. The output terminal of the inverter is connected to the output terminal of the VTC system. The switching network includes: a first switch disposed between the input terminal and the input capacitor; a second switch disposed between the reference voltage terminal and the reference capacitor; a third switch disposed between the input terminal of the inverter and the ground terminal; and fourth to sixth switches disposed between the input terminal of the inverter and the current source, the input capacitor, and the reference capacitor, respectively. The first to third switches are controlled by a sampling clock, and the fourth to sixth switches are controlled by the inverted signal of the sampling clock.

4. The interpolation-type time-to-digital converter based on pre-decision partial activation according to claim 1, characterized in that, Each pre-decision circuit in the parallel pre-decision circuit array includes: an interpolation activation switch, a pre-decision enable module, and a pre-decision result transmission module, wherein: the pre-decision enable module generates a decision enable signal based on the pre-decision phase time signal; the interpolation activation switch is controlled by the decision enable signal to determine whether subsequent time domain interpolation units are activated; the pre-decision result transmission module generates an output enable signal based on the decision enable signal and transmits it to the one-hot code encoder.

5. The interpolation-type time-to-digital converter based on pre-decision partial activation according to claim 4, characterized in that, The pre-decision enable module includes: a decision circuit composed of gated inverters and a positive feedback loop including two inverters and a transmission gate structure. The positive feedback loop pulls the level of the pre-decision signal to the power rail to avoid the floating level of the decision result output. When the pre-decision phase time signal is high, the decision enable signal arrives and the output enable signal is high to control the interpolation activation switch to be turned on. Otherwise, it is low and no interpolation is activated.

6. The interpolation-type time-to-digital converter based on pre-decision partial activation according to claim 4, characterized in that, The pre-decision result transmission module includes: a transmission circuit consisting of two gated inverters and a drive stage consisting of inverters, wherein: the gated inverters are controlled by a sampling clock, the input is an enable signal, and the output pre-decision result is sent to the one-hot code encoder.

7. The interpolation-type time-to-digital converter based on pre-decision partial activation according to claim 1, characterized in that, The interpolation TDC includes an interpolation structure and a latch array (SR-Latch), wherein: the interpolation structure composed of TDI units interpolates the time domain signal output by the VTC to form a higher resolution time domain signal, and the latch array outputs the digital domain one-hot code result based on the interpolated time domain signal.

8. The interpolation-type time-to-digital converter based on pre-decision partial activation according to claim 7, characterized in that, The TDI unit includes two sets of inverter pairs connected in parallel, wherein each inverter pair generates a time signal with a phase between the input time signal and the input time signal.

9. The interpolation-type time-to-digital converter based on pre-decision partial activation according to claim 7, characterized in that, The latch array includes several groups of latch units connected in parallel. Each latch unit is an SRL structure based on NAND gates or an SRL structure based on NOR gates. The SRL structure based on NAND gates outputs the decision result of the corresponding bit according to the order of the rising edges of the time domain signal, and the SRL structure based on NOR gates outputs the decision result of the corresponding bit according to the order of the falling edges of the time domain signal. The decision result is used as the temperature code digital output of the TDC.

10. The interpolation-type time-to-digital converter based on pre-decision partial activation according to claim 1, characterized in that, The unique thermal code encoder uses a five-input NOR gate array to generate a 65-bit unique thermal code based on the thermometer code output by the TDC and the result of the pre-decision.

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