Apparatus and method for clock recovery based on transition sensing in burst mode time division multiple access communication system

Abstract

The invention discloses a burst mode communication system, which may include one or more channels. Each channel is configured to receive a burst data stream transmitted according to a clock signal and recover the clock signal. The channel can receive a first burst data stream and a second burst data stream in two adjacent clock periods of a clock signal, convert the first burst data stream into a first pulse signal and convert the second burst data stream into a second pulse signal. The channel may recover the clock signal by detecting a time interval between rising edges of the first pulse signal and the second pulse signal. The burst data streams are different signals and are transmitted to a burst mode communication system in a time division multiple access (TDMA) scheme. And a clock recovery circuit is also arranged in the channel and is used for recovering a clock signal.

Description

Technical Field

[0001] This invention relates to the field of burst-mode communication, and in particular, in some embodiments, to techniques and mechanisms for clock recovery based on transition sensing in burst-mode time-division multiple access communication systems. Background Technology

[0002] In burst-mode communication systems, multiple network units share the same bus or line to exchange information or data. For example, a central unit or master node can continuously broadcast data packets to sub-terminals or slave nodes. Each sub-terminal or slave node can choose to receive a data packet sent to it and / or send the data packet back to the central unit / master node or other slave nodes. In burst mode, the central terminal / master node and sub-terminals / slave nodes can send and receive burst data packets / data streams via the bus or line. Each burst data packet is sent at a high frequency for a short period within a clock cycle. To avoid interference between data packets, uplink and downlink transmissions on the bus / line can be managed using a Time Division Multiple Access (TDMA) scheme.

[0003] Examples of burst-mode communication systems include, but are not limited to, automotive bus communication systems (such as Media Oriented System Transport (MOST) or Automotive Audio Bus (A2B) systems) and Gigabit Ethernet Passive Optical Network (GE-PON) systems.

[0004] MOST and A2B systems are well-known TDMA-based communication systems where all nodes are synchronized to the data sampling rate. MOST systems provide low-overhead, low-cost point-to-point networks for multimedia communication and can be implemented in ring, star, or daisy-chain topologies over plastic fiber optic cables or unshielded twisted-pair (UTP) cables. A2B systems can be implemented in a daisy-chain topology over UTP cables.

[0005] In a PON system, a single optical fiber branches at a splitter and is shared by multiple users. The Optical Line Terminal (OLT) at the central office communicates with multiple Optical Network Units (ONUs) located at the user ends via the splitter and the split fiber. The OLT can continuously broadcast burst data packets to the ONUs. Each ONU can receive one or more data packets sent to it and send one or more data packets to the OLT. Uplink transmission (from ONU to OLT) is managed using a TDMA scheme to avoid interference between data packets. The OLT may be equipped with a burst optical receiver, which may include, for example, a photodiode, a transimpedance amplifier (TIA), a limiting amplifier (LA), and clock and data recovery circuitry. The OLT needs to receive signals of different power and phase and recover the clock and data within a short time.

[0006] In a burst-mode communication system, no specific clock information is required for data transmission. The receiving end (or receiver) needs to recover the clock of the input data in order to correctly sample and receive the input data. The recovered clock can also be used to retime the input data. This process is called Clock and Data Recovery (CDR).

[0007] Traditional methods can recover the clock by phasing the input data based on a reference frequency and extracting the clock signal from the input signal / data using a phase-locked loop (PLL). An example of burst-mode CDR is the multi-phase clocking method, where multiple clock signals with the same frequency but different phases are generated based on a reference frequency and used to determine the correct clock for the input burst data packet. Another example of burst-mode CDR is the gated voltage-controlled oscillator (GVCO) method, where the GVCO re-aligns the phase based on a gating signal generated after detecting an input data transition to generate the clock signal.

[0008] However, traditional solutions typically occupy a large chip area and require high power consumption. Developing a clock recovery mechanism that can provide higher performance while reducing chip area footprint is therefore essential. Summary of the Invention

[0009] The embodiments of the present invention provide a method and apparatus for clock recovery based on transition sensing in a burst-mode time division multiple access communication system, thereby achieving technical advantages.

[0010] On one hand, the present invention provides a channel for a burst-mode communication system, comprising: a transceiver for receiving burst data streams transmitted according to a clock signal having a clock frequency; and a clock recovery circuit communicating with the transceiver. The clock recovery circuit is configured to: receive a first burst data stream in a first clock cycle of the clock signal and a second burst data stream in a second clock cycle of the clock signal from the transceiver, wherein the second clock cycle is adjacent to the first clock cycle; convert the first burst data stream into a first pulse signal and the second burst data stream into a second pulse signal; and recover the clock signal based on the time interval between the rising edges of the first and second pulse signals.

[0011] On the other hand, the present invention provides a burst-mode communication system including at least one channel, comprising: a transceiver for receiving burst data streams transmitted to the burst-mode communication system according to a clock signal having a clock frequency; and a clock recovery circuit communicating with the transceiver. The clock recovery circuit is configured to: receive a first burst data stream in a first clock cycle of the clock signal and a second burst data stream in a second clock cycle of the clock signal from the transceiver, wherein the second clock cycle is adjacent to the first clock cycle; convert the first burst data stream into a first pulse signal and the second burst data stream into a second pulse signal; and recover the clock signal based on the time difference between the rising edges of the first pulse signal and the second pulse signal.

[0012] On the other hand, the present invention provides a method comprising: receiving, on a channel of a burst-mode communication system, a first burst data stream and a second burst data stream transmitted according to a clock signal having a clock frequency, wherein the first burst data stream and the second burst data stream are transmitted within two adjacent clock cycles of the clock signal; converting the first burst data stream into a first pulse signal on the channel, and converting the second burst data stream into a second pulse signal on the channel; and recovering the clock signal on the channel based on a time interval between the rising edges of the first pulse signal and the second pulse signal.

[0013] To better understand the detailed description herein, the technical features and advantages of the present invention have been generally outlined above. The following will further describe the additional features and advantages of the invention, which constitute the subject matter of the claims. Those skilled in the art will understand that the concepts and specific embodiments of the present invention can be readily used as the basis for modifications or for designing other structures or methods to achieve the same purpose as the present invention. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. Attached Figure Description

[0014] To more fully understand the technical features and advantages of the present invention, reference is now made to the following description in conjunction with the accompanying drawings, wherein: Figure 1 is an example burst signal diagram according to an embodiment of the present invention; Figure 2 is a block diagram of an example burst-mode communication system according to an embodiment of the present invention; Figure 3 is a block diagram of a channel in a burst mode communication system according to an embodiment of the present invention; Figure 4 is a block diagram of a clock recovery module according to an embodiment of the present invention; Figure 5 is an example circuit diagram for implementing the clock recovery module in Figure 4 according to an embodiment of the present invention; Figure 6 shows an example waveform of the circuit in Figure 5; Figure 7 shows an example of an input burst signal and a pulse signal generated based on the input burst signal using the circuit in Figure 5; Figure 8 This is a flowchart of an example clock recovery method according to an embodiment of the present invention; Figure 9 This is for implementation according to embodiments of the present invention. Figure 4 A schematic diagram of another example circuit for the clock recovery module.

[0015] Unless otherwise stated, different corresponding numbers and symbols in the figures generally refer to corresponding components. These figures are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale. Detailed Implementation

[0016] The following section will discuss in detail the fabrication and application of embodiments of the present invention. However, it should be understood that the concept of the present invention can be embodied in various specific circumstances, and the specific embodiments discussed herein are for reference only and are not intended to limit the scope of the claims. Furthermore, it should be understood that various modifications, substitutions, and alterations can be made to the present invention without departing from the spirit and scope defined by the claims.

[0017] Furthermore, one or more features in the embodiments described below may be combined to form alternative embodiments not explicitly described, and features suitable for such combinations should be understood to be within the scope of the invention. Therefore, the appended claims are intended to cover any such modifications or embodiments.

[0018] It should be noted that in this invention, relational terms such as "first," "second," and "third" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion; for example, a process, method, article, or apparatus that comprises a set of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other elements in the process, method, article, or apparatus that includes that element.

[0019] This invention will be described in conjunction with embodiments in a specific scenario, namely, clock recovery based on transition sensing in a burst-mode time-division multiple access communication system. However, this invention can also be applied to various communication systems, such as burst-mode two-wire bus communication systems or burst-mode serial communication systems. The various embodiments will be described in detail below with reference to the accompanying drawings.

[0020] Embodiments of the present invention provide a system, method, and apparatus for clock recovery of signals / data transmitted in burst mode using time division multiple access. These embodiments provide instantaneous phase locking, reducing overhead time and improving transmission efficiency. The provided solution reduces the complexity of conventional mechanisms, lowers power consumption, and achieves clock recovery using compact circuitry.

[0021] In burst mode, signals / data are transmitted in bursts, measured in clock cycles (or burst periods). Signals / data are transmitted at a high data rate for a short period within each clock cycle. Signals transmitted in burst mode can be called burst signals. Burst signals can be burst data packets or burst data streams with a high data rate.

[0022] Figure 1 is a schematic diagram of a burst signal example 100 according to an embodiment of the present invention. The horizontal axis represents time, and the vertical axis represents the amplitude of the burst signal. The burst signal is transmitted according to a clock signal having a clock frequency. The clock signal has a clock period, the period or interval of which in the time domain is Tc. The burst signal is transmitted within the clock period. Figure 1 shows a first burst signal 110 transmitted in the first clock cycle 130, and a second burst signal 120 transmitted in the next clock cycle (not shown). The burst signal in each clock cycle may only occupy a portion of that clock cycle, while the signal energy of the remaining portion of the clock cycle may be zero or within the energy range considered as noise. The length (or width) of the burst signal transmitted in different clock cycles may be different in the time domain. For example, the length of the first burst signal 110 in the first clock cycle may be Tbl, while the length of the second burst signal 120 in the second clock cycle may be Tb2. Tbl and Tb2 may be much smaller than the length of the clock cycle Tc. The lengths of Tbl, Tb2, and Tc may vary depending on the specific application. Burst signals in each clock cycle are transmitted at a frequency higher than the clock signal. The frequencies of the burst signals and the clock signal may vary depending on the specific application.

[0023] As shown in the example in Figure 1, burst signals can begin at the start of each clock cycle. The first burst signal 110 can begin and end at time t1, and the second burst signal 120 can begin and end at time t21. The interval between t1 and t2 is the period of the clock cycle. The first clock cycle begins at t1, and the second clock cycle begins at t21. In other examples, each burst signal transmission can also begin after the start of the corresponding clock cycle. The following explanation will use the case where each burst signal begins at the start of each clock cycle as an example.

[0024] Figure 2 is a block diagram of an example burst-mode communication system 200 according to an embodiment of the present invention. System 200 can be applied to Media-Oriented Transport System (MOST) systems, Automotive Audio Bus (A2B) systems, Gigabit Ethernet Passive Optical Network (GE-PON) systems, or other suitable communication systems, such as two-wire bus communication systems or serial communication systems. System 200 can be used to implement a central unit, master node, sub-terminal, slave node, optical line terminal (OLT), and / or optical network unit. As shown, system 200 includes a Physical Coding Sublayer (PCS) 210, a Clock Multiplier Unit (CMU) 220, and channels, such as channels 232 and 234.

[0025] PCS 210 connects to CMU 220 and the channel. PCS 210 is used for communicating burst signals with the channel, converting data (received from or transmitted to the high-speed interface) to the digital domain, performing data encoding / decoding and symbol alignment, and performing data scrambling / descrambling. The structure and function of the PCS are well-known and will not be described further here. Any existing or future-developed PCS capable of implementing the functions of PCS 210 in System 200 can be used to implement PCS 210.

[0026] CMU 220 is also connected to the channel. CMU 220 is used to manage the peripherals and clock generation of system 200. Specifically, CMU 220 can be used to determine and generate the data frequency of the burst signal based on the clock signal of the recovered burst signal, and send this data frequency information to PCS 210. PCS 210 can then perform data recovery on the burst signal received from the channel based on this data frequency. For example, CMU 220 can obtain the recovered clock signal from the channel (e.g., channel 232) and multiply the clock frequency of that clock signal by a number (e.g., a clock multiplier, which is known) to obtain the data frequency of the burst signal from that channel. In this document, the frequency of the clock signal is referred to as the clock frequency, and the frequency of the burst signal is referred to as the data frequency. CMU 220 can be implemented using a phase-locked loop (PLL) frequency multiplier circuit. For example, CMU 220 can include an internal phase-locked loop (PLL) and a reference clock input buffer. Any existing or future-developed CMU capable of implementing the functions of CMU 220 in System 200 can be used to implement CMU 220.

[0027] System 200 may include one or more channels, such as channel 1 (232), channel 2 (not shown), ... and channel n (234). These channels can be used as transceivers to receive burst signals from outside system 200 via a bus and to transmit burst signals to outside system 200, and to perform clock recovery on the received burst signals. System 200 can communicate with external systems or devices in half-duplex mode via the bus. The burst signals received and transmitted by each channel via the bus can be differential signals, communicating using a time division multiple access (TDMA) scheme.

[0028] As an example, Figure 3 shows a block diagram of a channel 300 according to an embodiment of the present invention. Channel 300 can be used to implement a channel in system 200. As shown, channel 300 includes a transmitter 310, a receiver 320, and a clock recovery circuit / module 330. The transmitter 310 and receiver 320 can be combined and implemented as a transceiver.

[0029] Transmitter 310 is used to receive burst signals from, for example, PCS 210, which the communication system 200 intends to send to an external system or device (referred to as an external receiver), and to send the burst signals to the external receiver via bus 340 according to a clock signal.

[0030] Receiver 320 receives burst signals from an external system or device (referred to as an external transmitter) (e.g., another system 200) and transmits the received burst signals to PCS 210 and clock recovery module / circuit 330. Clock recovery module 330 performs clock recovery on the received burst signals to restore the clock signal of the received burst signals and transmits the restored clock signal to CMU 220. PCS 210 performs data recovery on the burst signals based on the data frequency generated by CMU 220 based on the restored clock signal. Figure 3 shows the burst signal 350 received by receiver 320, which forwards the burst signal 350 to clock recovery module 330. Clock recovery module 330 performs clock recovery and outputs the restored clock signal 360.

[0031] In some embodiments, the clock recovery module 330 can recover the clock signal of a burst signal by detecting the start time of the burst signal in two consecutive (or adjacent) clock cycles and determining the clock frequency based on the detected start time. Returning to the example in Figure 1, the clock recovery module 330 can detect the start time t1 of burst signal 110 and the start time t21 of burst signal 120 to determine the period Tc of the first clock cycle 130, thereby obtaining a clock frequency fc = 1 / Tc. Based on this clock frequency, the CMU 220 can generate the data frequency fd of the first burst signal 110 in the first clock cycle 130. Then, the PCS 210 can perform data recovery on the burst signal 110 according to this data frequency fd. In one embodiment, the system 200 can use this data frequency fd to recover other burst signals in subsequent clock cycles. In another embodiment, the clock recovery module 330 can continuously perform clock recovery on the input burst signals. In one example, when a channel receives a burst signal, the channel's clock recovery module 330 can perform clock recovery based on the detection of the burst signal in every two consecutive clock cycles (referred to as the first clock cycle and the second clock cycle) to recover a clock signal for data recovery of the burst signal in the first clock cycle.

[0032] In some embodiments, clock signal information embedded in a burst signal can be extracted to recover the clock signal. In one embodiment, the clock recovery module 330 can convert the burst signal in each clock cycle into a pulse signal and determine the period Tc of the clock cycle based on the time difference between the rising edges of two consecutive pulse signals. The clock signal is recovered by generating two consecutive pulse signals. A burst signal (analog) in the time domain typically refers to a signal whose amplitude oscillates rapidly between negative and positive values ​​(i.e., zero-crossing) for a short period of time within a clock cycle. For the remainder of the clock cycle, the signal energy is zero or very small (e.g., noise). Converting such a burst signal into a pulse signal can preserve and extract the timing information of the burst signal, such as the start time of the burst signal. A pulse signal is a single pulse containing a rising edge and a falling edge, corresponding to the start time and end time of the burst signal, respectively. The width of the pulse is approximately the same as the length of the burst signal, such as the length Tbl in Figure 1. In some embodiments, converting a burst signal into a pulse signal can include eliminating amplitude oscillations. In some embodiments, converting a burst signal into a pulse signal can include eliminating the rising and falling edges between the start and end times of the burst signal.

[0033] The burst signal in each clock cycle can be a differential signal Sb containing a positive component / signal Sbp and a negative component / signal Sbn. The differential signal Sb can be referred to as a differential signal pair Sb containing Sbp and Sbn. The positive component / signal Sbp and the negative component / signal Sbn have the same signal amplitude but opposite polarities (180 degrees out of phase with each other) and are transmitted through corresponding lines in the bus. In some embodiments, the clock recovery module 330 can be used to convert the differential signal received within a clock cycle into a pulse signal.

[0034] Figure 4 A block diagram of a clock recovery circuit 400 according to an embodiment of the present invention is shown. This clock recovery circuit 400 can be used to implement... Figure 3 The clock recovery module 330 is included. The clock recovery circuit 400 includes amplifier circuits 410 and 420, differential-to-single-ended conversion circuits 430 and 440, and filter circuit 450.

[0035] Clock recovery circuit 400 receives an input differential signal (e.g., different voltage / current signals) containing a positive component Sbp and a negative component Sbn at inputs 402 and 404, respectively. Clock recovery circuit 400 can receive this input differential signal from receiver 320. Amplifier circuit 410 receives Sbp and Sbn at its positive and negative inputs, respectively, and generates and outputs a first differential signal pair at its outputs 412 and 414. Amplifier circuit 410 functions as a comparator circuit and outputs a high-level voltage signal or a low-level voltage signal based on the relative value of the voltage at terminals 412 and 414 relative to a threshold. The first differential signal pair contains timing information of the input differential signal, as well as the portion of the input differential signal with an amplitude greater than the threshold. The first differential signal pair is fed into differential-to-single-ended converter circuit 430, which generates and outputs a first single-ended signal at its output 432.

[0036] Amplifier circuit 420 receives Sbp and Sbn at its negative and positive input terminals, respectively, and generates and outputs a second differential signal pair at its output terminals 422 and 424. Amplifier circuit 420 functions as a comparator circuit and outputs a high-level voltage signal or a low-level voltage signal based on the amplitude of the voltage at terminals 422 and 424 relative to a threshold. The second differential signal pair contains timing information of the input differential signals and includes the portion of the input differential signals whose amplitude exceeds the threshold. The second differential signal pair is fed into differential-to-single-ended converter circuit 440, which generates and outputs a second single-ended signal at its output terminal 442. Amplifier circuits 410 and 420 may use the same or different threshold values.

[0037] The first and second single-ended signals are input to and processed by filter 450. Filter 450 generates and outputs a pulse signal of the input differential signal at its output terminal 452. This pulse signal contains clock frequency information and can then be sent to CMU 220, such as... Figure 2 As shown, the clock recovery circuit 400 continuously receives the differential signal within a clock cycle and continuously generates pulse signals corresponding to the clock cycle. Typically, the clock recovery circuit 400 aims to smooth the amplitude oscillations of the input differential signal while preserving the start time and length information of the differential signal within each clock cycle.

[0038] Figure 5 is a schematic diagram of an example circuit 500 for implementing a clock recovery circuit 400 according to an embodiment of the present invention. The circuit 500 includes switches Q1-Q6, loads L1-L4, current sources 512 and 514, differential-to-single-ended conversion circuits 430 and 440 as shown in Figure 4, OR gates 516 and 520, and a delay circuit 518.

[0039] Switches Q1-Q6 can be field-effect transistors (FETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs), as well as other types of transistors. They can be P-type or N-type. In this example, Q1-Q6 are N-type transistors. Loads L1-L4 can be resistive elements or transistors, such as field-effect transistors (FETs). Loads L1-L4 are connected to power supply 546, which is a voltage power supply. Q2, Q3, Q5, and Q6 can be the same transistor. The dimensions of Q1 and Q4 can be smaller than those of Q2, Q3, Q5, and Q6. That is, the on-resistance of Q1 and Q4 is smaller than that of Q2, Q3, Q5, and Q6.

[0040] Switches Q1-Q3, loads L1 and L2, and current source 512 constitute... Figure 4 Amplifier circuit 410 is described. Q2 (together with Q1) and Q3 form the differential pair of amplifier circuit 410. Due to the addition of Q1, the differential pair is asymmetrical. The gates of Q1 and Q2 are connected to input terminal 404, receiving the negative component Sbn of the input differential signal. Q1 and Q2 are connected in parallel between load L1 and current source 512. The drains of Q1 and Q2 are connected to load L1 at node 532, and the sources of Q1 and Q2 are connected to the grounded current source 512. The drain of Q3 is connected to load L2 at node 534, and the source of Q3 is connected to current source 512. The gate of Q3 is connected to input terminal 402, which receives the positive component Sbp of the input differential signal. Current source 512 is a constant current source used to provide bias current to the differential pair of amplifier circuit 410.

[0041] When the gate voltage of Q2 or Q3 rises above the voltage threshold, Q2 or Q3 turns on; when the gate voltage of Q2 or Q3 falls below the voltage threshold, Q2 or Q3 turns off. Since the gates of Q2 and Q3 are connected to Sbn and Sbp, respectively, Q2 and Q3 conduct alternately. Similarly, Q1 turns on when its gate voltage is above the voltage threshold and turns off when it is below the voltage threshold. The on-resistance of Q1 is less than that of Q2 and Q3.

[0042] Switches Q4-Q6, loads L3 and L4, and current source 514 constitute amplifier circuit 420 in Figure 4. Current source 514 can be the same as current source 512. Q5 (together with Q4) and Q6 form the differential pair of amplifier circuit 420; the differential pair is asymmetrical due to the addition of Q4. The gates of Q4 and Q5 are connected to input 402, receiving the positive component Sbp of the input differential signal. Q4 and Q5 are connected in parallel between load L3 and current source 514. The drains of Q4 and Q5 are connected to load L3 at node 536, and the sources of Q4 and Q5 are connected to the grounded current source 514. The drain of Q6 is connected to load L4 at node 538, and the source of Q6 is connected to current source 514. The gate of Q6 is connected to input 404, which receives the negative component Sbn of the input differential signal. Current source 514 is a constant current source used to provide bias current to the differential pair of amplifier circuit 420.

[0043] When the gate voltage of Q5 or Q6 rises above the voltage threshold, Q5 or Q6 turns on; when the gate voltage of Q5 or Q6 falls below the voltage threshold, Q5 or Q6 turns off. Since the gates of Q5 and Q6 are connected to Sbp and Sbn respectively, Q5 and Q6 alternately turn on and off. Similarly, when the gate voltage of Q4 is above or below the voltage threshold, Q4 also turns on and off.

[0044] Nodes 532 and 534 are connected to the input of differential-to-single-ended converter 430. A first differential signal pair is generated at nodes 532 and 534 and fed to differential-to-single-ended converter 430, which generates and outputs a first single-ended signal at its output terminal 432.

[0045] Nodes 536 and 538 are connected to the input of differential-to-single-ended converter 440. A second differential signal pair is generated at nodes 536 and 538 and fed to differential-to-single-ended converter 440, which generates and outputs a second single-ended signal at its output terminal 432.

[0046] OR gates 516 and 520, along with delay circuit 518, constitute filter 450. OR gate 516 performs an OR operation on the first single-ended signal and the second single-ended signal, and outputs a first filtered signal at its output 540. The first filtered signal is delayed by delay circuit 518 for a delay time L1t, and then delay circuit 518 outputs the delayed signal to the first input 542 of OR gate 520. The delay time L1t can be configured / set and adjusted according to the signal output from the preceding node / terminal to generate a pulse signal at output 452 corresponding to the input burst signal. Delay circuits are well known in the art. Any existing or future-developed delay circuit capable of delaying the first filtered signal by a delay time L1t can be used to implement delay circuit 518. The first filtered signal is also fed to the second input 544 of OR gate 520. OR gate 520 performs an OR operation on the delayed signal at input 542 and the first filtered signal at input 544, and generates a pulse signal at output 452.

[0047] In addition to the above, amplifier circuits 410, 420 and filter 450 may include other suitable circuits / components, or may have different configurations. For example, circuit 500 may include a second delay circuit and a third OR gate connected to terminal 452. The pulse signal at output terminal 452 can be further delayed by the second delay circuit to generate a second delayed signal. The third OR gate can perform an OR operation on the second delayed signal and the pulse signal at output terminal 452 to generate another pulse signal, which is further smoothed. In some embodiments, delay circuit 518 and OR gate 520 may constitute a pulse filter. The circuit may include multiple cascaded pulse filters to generate a low-noise pulse signal corresponding to the burst signal used for clock recovery. Differential-to-single-ended conversion circuits 430 and 440 may be implemented in various conventionally known and employed manners, which will not be described further herein.

[0048] Figure 6 is an example waveform diagram of circuit 500. Figure 6 shows the waveforms at terminals 402, 404, 432, 442, 540, 542, and 452, as well as nodes 532-538. In this example, the burst signal of input circuit 500 within one clock cycle is a signal containing a positive component Sbp and a negative component. The voltage differential signal of Sbn.

[0049] Figure 7 (700) illustrates the input burst signal 710 and the pulse signal 720 generated by the clock recovery circuit 500 based on the input burst signal 710. The period Tp of the pulse signal (i.e., the time interval between the rising edges of two adjacent pulses) is equal to the period Tc of the clock signal of the burst signal 710. The width W of each pulse within each clock cycle corresponds to the width of the burst signal in that clock cycle. The pulse signal 720 can be used as the clock signal for the burst signal 710. A channel can continuously generate pulse signals of the input burst signal and send these pulse signals to the CMU. The CMU uses these pulse signals to generate a data frequency for the PCS to recover the data of the burst signal.

[0050] Figure 8 This is a flowchart of an example method 800 for burst signal clock recovery according to an embodiment of the present invention. Method 800 can be executed on a channel of a burst-mode communication system (e.g., channels 232 and 234 of system 200) and can be executed using a clock recovery circuit / module (e.g., clock recovery module 400 or circuit 500). As shown, in step 810, the clock recovery circuit receives a first burst data stream in the first clock cycle of the clock signal and a second burst data stream in the second clock cycle of the clock signal, wherein the second clock cycle is adjacent to the first clock cycle. The first and second data streams are transmitted according to a clock signal having a clock frequency.

[0051] In step 820, the clock recovery circuit converts the first burst data stream into a first pulse signal and the second burst data stream into a second pulse signal. In step 830, the clock recovery circuit recovers the clock signal by detecting the time difference between the rising edges of the first and second pulse signals. The conversion of the burst data stream to pulses can be implemented as described above, for example, using circuit 500. Method 800 may further include determining a clock frequency based on the detected time interval. In some embodiments, method 800 may further include sending the recovered clock signal to a clock multiplier unit, which generates the data frequency of the burst data stream based on the clock frequency of the clock signal.

[0052] Without departing from the spirit and principles of the invention, method 800 can be implemented using circuits other than those in embodiments 400 or 500. The above-described embodiments of the invention for clock recovery can be implemented using hardware, firmware, software, or any combination thereof.

[0053] For example, embodiments of the invention can be performed as computer-implemented methods. These methods can be implemented in software. In one embodiment, the software can be obtained and loaded into a computer, processor, or any other machine capable of running the software. Embodiments of the invention can also be implemented as instructions stored on a computer-readable storage device or medium that can be read and executed by at least one processor to perform the methods described herein. A computer-readable storage device can include any non-transitory mechanism for storing information in a machine-readable (e.g., computer) form. For example, a computer-readable storage device can include read-only memory (ROM), random access memory (RAM), disk storage media, optical storage media, flash memory devices, solid-state storage media, and other storage devices and media. For example, a channel device for a burst-mode communication system can include one or more processors and a non-transitory memory storing computer-readable instructions. One or more processors can be used to execute instructions to perform the clock recovery described in embodiments of the invention.

[0054] Figure 9 is a schematic diagram of another example circuit 900 implementing the clock recovery circuit 400 according to an embodiment of the present invention. The difference between circuit 900 and circuit 500 is that switches Q1-Q6 in circuit 900 are P-type transistors. In this example, the first terminal of current source 512 is coupled to the source of Q1-Q3, and the second terminal of current source 512 is coupled to power supply 546. The first terminal of current source 514 is coupled to the source of Q4-Q6, and the second terminal of current source 514 is coupled to power supply 546. Load L1 is coupled to Q1 and Q2 at node 532 and is coupled between node 532 and ground. Load L2 is coupled to Q3 at node 534 and is coupled between node 534 and ground. Load L3 is coupled to Q4 and Q5 at node 536 and is coupled between node 536 and ground. Load L4 is coupled to Q6 at node 538 and between node 538 and ground. Other components of circuit 900 are similar to their counterparts in circuit 500. The operation of circuit 900 is similar to that of circuit 500 and will not be described further here.

[0055] Although this specification has described in detail, it should be understood that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims. Furthermore, the scope of the invention is not limited to the specific embodiments described herein. Those skilled in the art will readily understand from this invention that existing or subsequently developed processes, machines, manufactures, material compositions, apparatuses, methods, or steps, as long as they can perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, can be used according to the invention. Therefore, the appended claims are intended to cover such processes, machines, manufactures, material compositions, apparatuses, methods, or steps within their scope.

Claims

1. A channel for a burst mode communication system, characterized by include: A transceiver is used to receive bursts of data transmitted according to a clock signal having a clock frequency; as well as A clock recovery circuit, communicating with the transceiver, is used for: The transceiver receives a first burst data stream in a first clock cycle of the clock signal and a second burst data stream in a second clock cycle of the clock signal, wherein the second clock cycle is adjacent to the first clock cycle. The first burst data stream is converted into a first pulse signal and the second burst data stream is converted into a second pulse signal; as well as The clock signal is recovered based on the time interval between the rising edges of the first pulse signal and the second pulse signal.

2. The passage of claim 1, wherein, Restoring the clock signal includes determining the clock frequency based on the time interval.

3. The channel of claim 1, wherein Each of the aforementioned burst data streams is a differential signal, which includes a first signal as a positive component of the differential signal and a second signal as a negative component of the differential signal.

4. The passage of claim 3, wherein, The clock recovery circuit includes: A first amplifier circuit having a first positive input terminal and a first negative input terminal, wherein the first amplifier circuit is configured to: receive a first signal of the burst data stream at the first positive input terminal, receive a second signal of the burst data stream at the first negative input terminal, and generate a first differential signal of the burst data stream; A second amplifier circuit having a second positive input terminal and a second negative input terminal, wherein the second amplifier circuit is used to: receive a first signal of the burst data stream at the second negative input terminal, receive a second signal of the burst data stream at the second positive input terminal, and generate a second differential signal of the burst data stream; A first differential-to-single-ended converter circuit is connected to the first amplifier circuit and is used to convert the first differential signal of the burst data stream into a first single-ended signal. A second differential-to-single-ended converter circuit, connected to a second amplifier circuit, is used to convert the second differential signal of the burst data stream into a second single-ended signal; and A filtering circuit is connected to the first differential-to-single-ended conversion circuit and the second differential-to-single-ended conversion circuit, and is used to process the first single-ended signal and the second single-ended signal to generate a pulse signal for a burst data stream.

5. The passage of claim 4, wherein, The first amplifier circuit includes: A first switch and a second switch are connected in parallel between a first node and a first current source, wherein the drains of the first switch and the second switch are connected to the first node, the sources of the first switch and the second switch are connected to the first current source, and the gates of the first switch and the second switch are connected to a second signal of the burst data stream; and A third switch has its gate connected to the first signal of the burst data stream, its source connected to the first current source, and its drain connected to the second node, wherein the first node and the second node are connected to the first differential-to-single-ended converter circuit; and The second amplifier circuit includes: A fourth and a fifth switch are connected in parallel between the third node and the second current source, wherein the drains of the fourth and fifth switches are connected to the third node, the sources of the fourth and fifth switches are connected to the second current source, and the gates of the fourth and fifth switches are connected to the first signal of the burst data stream; and A sixth switch has its gate connected to the second signal of the burst data stream, its source connected to the second current source, and its drain connected to the fourth node, wherein the third node and the fourth node are connected to the second differential-to-single-ended conversion circuit.

6. The passage of claim 5, wherein, Also includes: The first load, the second load, the third load, and the fourth load are respectively coupled to the first node, the second node, the third node, and the fourth node.

7. The channel of claim 5 wherein, The on-resistance of the first switch and the fourth switch is less than the on-resistance of the second switch, the third switch, the fifth switch and the sixth switch.

8. The channel of claim 5 wherein, The first to sixth switches are field-effect transistors.

9. The channel of claim 4 wherein, The filtering circuit includes: A first OR gate has its first input terminal connected to the first differential-to-single-ended converter circuit and its second input terminal connected to the second differential-to-single-ended converter circuit. The first OR gate is used to perform an OR operation on the first single-ended signal and the second single-ended signal to generate a first filtered signal of the burst data stream at the output terminal of the first OR gate. A delay circuit, connected to the output of the first OR gate, wherein the delay circuit is used to delay the first filtered signal to generate a delayed signal; and A second OR gate is used to receive the delayed signal and the first filtered signal, and to generate a pulse signal for the burst data stream.

10. A burst mode communication system characterized by Includes at least one channel, said at least one channel comprising: A transceiver for receiving burst data streams transmitted to the burst-mode communication system according to a clock signal having a clock frequency; and A clock recovery circuit, communicating with the transceiver, is used for: The transceiver receives a first burst data stream in a first clock cycle of the clock signal and a second burst data stream in a second clock cycle of the clock signal, wherein the second clock cycle is adjacent to the first clock cycle. Convert the first burst data stream into a first pulse signal, and convert the second burst data stream into a second pulse signal; and The clock signal is recovered by detecting the time difference between the rising edges of the first pulse signal and the second pulse signal.

11. The burst mode communication system according to claim 10, characterized in that, Recovering the clock signal includes determining the clock frequency based on the detected time difference.

12. The burst mode communication system according to claim 10, characterized in that, Each of the burst data streams is a differential signal, which includes a first signal as a positive component of the differential signal and a second signal as a negative component of the differential signal.

13. The burst mode communication system according to claim 12, characterized in that, The clock recovery circuit includes: A first amplifier circuit has a first positive input terminal and a first negative input terminal, wherein the first amplifier circuit is used to: receive a first signal of the burst data stream at the first positive input terminal, receive a second signal of the burst data stream at the first negative input terminal, and generate a first differential signal of the burst data stream; The second amplifier circuit has a second positive input terminal and a second negative input terminal, wherein the second amplifier circuit is used to: receive a first signal of the burst data stream at the second negative input terminal, receive a second signal of the burst data stream at the second positive input terminal, and generate a second differential signal of the burst data stream; A first differential-to-single-ended converter circuit is coupled to the first amplifier circuit and is used to convert the first differential signal of the burst data stream into a first single-ended signal. A second differential-to-single-ended converter circuit, coupled to a second amplifier circuit, is used to convert the second differential signal of the burst data stream into a second single-ended signal; and A filtering circuit is connected to the first differential-to-single-ended conversion circuit and the second differential-to-single-ended conversion circuit, and is used to process the first single-ended signal and the second single-ended signal to generate the pulse signal of the burst data stream.

14. The burst mode communication system according to claim 13, characterized in that, The first amplifier circuit includes: A first switch and a second switch are connected in parallel between a first node and a first current source, wherein the drains of the first switch and the second switch are connected to the first node, the sources of the first switch and the second switch are connected to the first current source, and the gates of the first switch and the second switch are connected to a second signal of the burst data stream; and A third switch has its gate connected to the first signal of the burst data stream, its source connected to the first current source, and its drain connected to the second node, wherein the first node and the second node are connected to the first differential-to-single-ended converter circuit; and... The second amplifier circuit includes: A fourth and a fifth switch are connected in parallel between the third node and the second current source, wherein the drains of the fourth and fifth switches are connected to the third node, the sources of the fourth and fifth switches are connected to the second current source, and the gates of the fourth and fifth switches are connected to the first signal of the burst data stream; and A sixth switch has its gate connected to the second signal of the burst data stream, its source connected to the second current source, and its drain connected to the fourth node, wherein the third node and the fourth node are connected to the second differential-to-single-ended conversion circuit.

15. The burst mode communication system according to claim 14, characterized in that, The clock recovery circuit also includes: The first load, the second load, the third load, and the fourth load are respectively coupled to the first node, the second node, the third node, and the fourth node.

16. The burst-mode communication system according to claim 14, characterized in that, The first switch and the fourth switch have a lower on-resistance than the second switch, the third switch, the fifth switch and the sixth switch.

17. The burst-mode communication system according to claim 14, characterized in that, The first to sixth switches are field-effect transistors.

18. The burst mode communication system according to claim 13, characterized in that, The filtering circuit includes: A first OR gate has its first input terminal connected to the first differential-to-single-ended converter circuit and its second input terminal connected to the second differential-to-single-ended converter circuit. The first OR gate is used to perform an OR operation on the first single-ended signal and the second single-ended signal to generate a first filtered signal of the burst data stream at the output terminal of the first OR gate. A delay circuit connected to the output of the first OR gate, wherein the delay circuit is used to delay the first filtered signal to generate a delayed signal; and The second OR gate is used to receive the delayed signal and the first filtered signal, and to generate the pulse signal of the burst data stream.

19. A method, characterized in that, include: On a channel of a burst mode communication system, a first burst data stream and a second burst data stream transmitted according to a clock signal having a clock frequency are received, wherein the first burst data stream and the second burst data stream are transmitted within two adjacent clock cycles of the clock signal; On the channel, the first burst data stream is converted into a first pulse signal, and the second burst data stream is converted into a second pulse signal; and The clock signal is recovered on the channel based on the time interval between the rising edges of the first pulse signal and the second pulse signal.

20. The method according to claim 19, characterized in that, Also includes: The clock frequency is determined based on the detected time interval.

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