Comprehensive aircraft suspension object high-speed network interface test system and method

Abstract

The invention provides a comprehensive aircraft suspension object high-speed network interface test system and method, and belongs to the field of high-speed network interface test.The comprehensive aircraft suspension object high-speed network interface test system comprises a test host and a plurality of optical fiber bus board cards, and the optical fiber bus board cards are connected with the test host through PXIE interfaces; the plurality of optical fiber bus board cards comprise a first optical fiber bus board card, a second optical fiber bus board card and a third optical fiber bus board card which communicate with one another, the test host comprises an optical fiber test module, an optical fiber analysis module, an analogue simulation module and a display unit, and the optical fiber test module is in communication connection with the first optical fiber bus board card. The optical fiber analysis module is in communication connection with the second optical fiber bus board card, and the analogue simulation module is in communication connection with the third optical fiber bus board card. The high-speed network interface test system provided by the invention can realize the functions of simulating an optical fiber switch, a network controller and a network terminal, providing various ports, performing communication test and the like in the high-speed network interface test work of the aircraft suspension.

Description

Technical Field

[0001] This invention relates to the field of high-speed network interface testing, and specifically to a comprehensive high-speed network interface testing system and method for aircraft suspension devices. Background Technology

[0002] In the field of aerospace technology, high-speed networks for aircraft suspended structures (SSCs) serve as the core data transmission and control carrier between aircraft and SSCs. Their performance and stability directly determine the operational effectiveness of SSCs and the safety of flight missions. This high-speed network, based on fiber optic interfaces, enables the aggregation and exchange of various data types. Specifically, it is responsible for transmitting critical data such as high-definition video, real-time audio, and mission files from the aircraft to the SSCs. Simultaneously, it supports the precise control and efficient use of SSCs by the aircraft, making it a core hub ensuring collaborative operation between the aircraft and SSCs.

[0003] As a crucial payload for aircraft in combat, reconnaissance, and training missions, the performance testing of aircraft suspension components during the design finalization phase is a critical step in ensuring product quality and operational reliability. Among these components, the high-speed network interface of the aircraft suspension component, as a core node for data interaction, directly impacts the operational effectiveness of the entire collaborative system due to its communication bandwidth, transmission latency, data integrity, and connection stability. Therefore, testing the high-speed network interface of the aircraft suspension component is an indispensable core item in the design finalization testing of suspension components.

[0004] However, in current practical testing, existing high-speed network interface testing systems for aircraft suspensions have many shortcomings that urgently need to be addressed, severely restricting the efficiency, accuracy, and versatility of testing work. Specifically, these shortcomings are as follows: Firstly, the core components of the testing system are distributed. Core equipment such as the fiber channel analyzer, analog switches, analog network controllers, and analog network terminals, as well as various test interfaces and test points, are all independent and dispersed modules. These modules require numerous dedicated cables for physical connection to form test links. Because modules from different manufacturers lack unified standards in interface definitions, communication protocols, and signal standards, compatibility between modules is extremely poor, easily leading to link interruptions, signal interference, and data packet loss. Furthermore, the distributed connection makes fault location difficult, requiring a step-by-step inspection of multiple aspects, including the module itself, cable connections, and interface compatibility, significantly increasing the time cost and technical difficulty of fault diagnosis and repair.

[0005] Secondly, the core testing instrument in the existing testing system only has basic signal acquisition and simple analysis functions, lacking a complete data recording and traceability module. When communication anomalies or data transmission failures occur during testing, it cannot fully record crucial information such as data flow, link status, and parameter changes before and after the fault, resulting in a lack of effective data support for fault analysis. To achieve fault traceability, an additional independent recorder device is required, which not only increases system complexity but may also affect data accuracy due to synchronization issues between the recorder and the testing system, further reducing troubleshooting efficiency.

[0006] Third, the setup and operation of existing testing systems require significant manual intervention, including cable connections between modules, interface plugging and unplugging, parameter configuration, data acquisition, and result comparison. Manual operation is not only cumbersome and time-consuming, but also prone to errors that could lead to test link anomalies or test data deviations. Especially in batch testing scenarios, repetitive manual operations significantly extend the testing cycle, making it difficult to meet the needs of efficient testing during the design finalization phase of suspended objects.

[0007] In summary, existing high-speed network interface testing systems for aircraft suspensions have significant shortcomings in terms of compatibility, versatility, fault handling capabilities, testing efficiency, and ease of operation. They cannot meet the requirements for high efficiency, reliability, and accuracy of high-speed network interface testing during the design finalization stage of suspensions, thus hindering the development progress and testing quality of suspensions. There is an urgent need for a new testing system that can solve the above problems. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention provides a comprehensive high-speed network interface testing system and method for aircraft suspension components. This overcomes the problems of poor integration, difficulty in repairing faults, low automation, and cumbersome and inefficient operation found in current fiber optic testing instruments. The high-speed network interface testing system provided by this invention can simulate fiber optic switches, network controllers, and network terminals, providing various port and communication testing functions in high-speed network interface testing of aircraft suspension components.

[0009] Specifically, in a first aspect, the present invention provides a comprehensive high-speed network interface testing system for aircraft suspension components, comprising a test host and multiple fiber optic bus cards, the multiple fiber optic bus cards being connected to the test host via PXIE interfaces; the multiple fiber optic bus cards include a first fiber optic bus card, a second fiber optic bus card, and a third fiber optic bus card that communicate with each other; the test host includes a fiber optic testing module, a fiber optic analysis module, a simulation module, and a display unit; the fiber optic testing module is communicatively connected to the first fiber optic bus card, the fiber optic analysis module is communicatively connected to the second fiber optic bus card, and the simulation module is communicatively connected to the third fiber optic bus card; The first fiber optic bus board has multiple test ports; the second fiber optic bus board has multiple analysis ports; the third fiber optic bus board has multiple simulation ports; the test host has a VGA port and a LAN port; the VGA port and LAN port are used to connect to other devices; the fiber optic test module calls a preset high-speed network interface test protocol for aircraft suspended objects and outputs high-speed network test signals through the first fiber optic bus board; the fiber optic analysis module receives the high-speed network test signals through the second fiber optic bus board, performs real-time test analysis, and sends the parsed data to the display unit and the simulation module respectively; the simulation module uses the third fiber optic bus board to simulate the target state of the aircraft suspended object, generates expected data under the target state, and judges the high-speed network test signal data; the specific method for judging the high-speed network test signal data is as follows: Obtain a single frame of received data D, and divide the single frame of received data D into N fields. Determine the length of each field. And assign weights to each field. Prioritize and sort according to the weight of each field. The calculation formula is: ; in, This is the functional importance coefficient. The error impact coefficient. These are the weights for the functional importance coefficient and the error impact coefficient, respectively. Compare each field one by one Actual received data Compared with expected data ), calculate matching degree Combined with a preset threshold T, incorrect fields are identified, and the matching degree is determined. The calculation formula is: ; in, Let be the matching degree of the i-th field. This is a statistical function used to calculate the number of error bits in a field. This is a bitwise XOR operation used to compare whether the actual data of the i-th field matches the expected data. S4. Count the number of error frames and the weighted error data volume, and output them to the display unit for display.

[0010] Preferably, the fiber optic testing module includes a port management unit, a network configuration unit, a data transceiver unit, a data editing unit, and a first discrimination unit; the fiber optic analysis module includes a data analysis unit; the simulation module includes a simulation unit and a second discrimination unit; the port management unit includes a port state machine, which is used to automatically perform link initialization and initiate the network login process after system startup, continuously monitor the link status after successful login, and automatically trigger re-initialization when the link is abnormal; the network configuration unit is used to set the functions simulated by the high-speed network testing system, the provided port types, and the form of information transmission; the data editing unit is used to perform... The data editing process involves the first discrimination unit performing an initial discrimination of the data. If the discrimination passes, the data is sent to the data transceiver unit; if the discrimination fails, the data is fed back to the data editing unit for re-editing. The data transceiver unit is used to send high-speed network test signals. The data analysis unit performs protocol analysis and decoding on the fiber optic channel. By capturing the data stream in the fiber optic channel, it extracts frame and primitive information, performs in-depth analysis, and then sends the data to the display unit and the second discrimination unit. The simulation unit simulates the target state of the aircraft's suspended objects, generates expected data under the target state, and the second discrimination unit performs a second discrimination of the data. If the discrimination passes, the test is completed.

[0011] Preferably, the first, second, and third fiber optic bus boards are all equipped with a 1188B high-speed bus interface, NC communication, and a software programming configuration terminal. The bus interface meets the communication protocol requirements of the GJB1188B standard. The NC communication can initiate NC-NT interaction, NT-NC interaction, and vector word exchange operations. The software programming configuration terminal can switch the fiber optic bus board between communication mode and batch transmission mode through the control commands of the test chassis.

[0012] Preferably, the test chassis is compatible with the Windows operating system and is pre-installed with drivers and dynamic library functions adapted to the first fiber optic bus board, the second fiber optic bus board, and the third fiber optic bus board. The drivers are used to establish hardware communication connections between the test chassis and the fiber optic bus boards, and the dynamic library functions are used to support software calls for the functions of the fiber optic bus boards.

[0013] Preferably, the 1188B high-speed bus interface includes an 1188B bus protocol controller, an isolation transformer, and a bus connector.

[0014] Preferably, the first fiber optic bus board, the second fiber optic bus board, and the third fiber optic bus board are all equipped with programming logic chips.

[0015] Preferably, the programming logic chip of the first fiber optic bus board includes FLOGIN, a configuration register, TC_MST, TC_SLV, TX FIFO, RX FIFO, FC MAC, FC PHY, and DDR3. FLOGIN is used for port management; the configuration register is used to store network configuration parameters; TC_MST, TC_SLV, TX FIFO, RX FIFO, FC MAC, and FC PHY are used together to complete data transmission and reception; the TC_MST module and TC_SLV module, according to the software configuration register information and stack information, complete the reading of data from DDR3 during transmission and send the data to the TX FIFO module, and during reception, read data from the RX FIFO module and write the data to the DDR3 module; DDR3 is used to write user-edited data.

[0016] Preferably, DDR3 is used to store test data to be sent or response data already received. Before the test starts, the test data to be sent and data statistics information are written into DDR3. Then, the test data in DDR3 is read and sent. During the test, the programming logic chip parses the received response frame, writes the received response data into DDR3, and then the first discrimination unit reads the response data and compares it with the expected data.

[0017] Preferably, the TC_MST and TC_SLV modules include DATAMOVER, TX / RX RAM, instruction FIFO, TC descriptor RAM, configuration register, storage state machine, and frame state machine. The instruction FIFO stores the starting address, data byte length, and operation instructions for writing / reading DDR3 data to be processed. The TXRAM temporarily stores data read from DDR3 in the form of data frames, with each frame corresponding to one instruction in the instruction FIFO. The RXRAM temporarily stores data to be written to DDR3, with each frame corresponding to one instruction in the instruction FIFO. The DATAMOVER reads instructions from the instruction FIFO through the storage state machine and converts them into AXIS commands conforming to the DAMAMOVER IP core, controlling the DATAMOVER to perform data writing / reading. The configuration register stores network configuration. The TC descriptor RAM stores the status and control information for data transmission and reception, including a TC transmit configuration stack and a TC receive status stack. The frame state machine completes the framing of test data and parses the responses.

[0018] Secondly, the present invention provides a comprehensive method for testing high-speed network interfaces of aircraft suspension devices, which includes the following steps: S1. Insert the first fiber optic bus board, the second fiber optic bus board, and the third fiber optic bus board into the corresponding slots of the test host. The first fiber optic bus board is used to output high-speed network test signals; the second fiber optic bus board is used to receive and parse test signals; and the third fiber optic bus board is used to distinguish the received data. S2. Connect the first fiber optic board and the second fiber optic board to form a test signal transmission link, and connect the second fiber optic board and the third fiber optic board to form a data judgment link. S3. Power on the test host and start the fiber optic test module, fiber optic analysis module, and simulation module to perform test and analysis on the fiber optic cable under test. The fiber optic test module calls the preset high-speed network interface test protocol for aircraft suspension devices and outputs high-speed test signals to the test link through the first fiber optic bus board. The simulation module loads the preset network interface working scenario model for the suspension device and simulates the network interface signal response of the suspension device under different flight attitudes and load conditions through the third fiber optic bus board, generates expected data, and judges the received data. The fiber optic analysis module collects test signals through the second fiber optic bus board and sends them to the display unit and the simulation module respectively. S4. During the test, the fiber optic analysis module performs real-time analysis and transmission of the collected test data, which is then displayed on the display unit of the test host.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention employs an integrated architecture design, integrating core functional modules such as the fiber channel analyzer and analog switch into a single unit. This significantly improves the compatibility between modules and reduces the occurrence of faults such as link interruptions and signal interference at their source. Simultaneously, the integrated layout enables rapid fault location, significantly reducing the time cost and technical difficulty of fault diagnosis and repair, ensuring the continuity of testing work, and recording key information such as data flow, link status, and parameter changes during the testing process in real time and completely. This simplifies the system architecture, provides comprehensive and accurate data support for fault analysis, helps to quickly clarify the cause of faults, and improves troubleshooting efficiency and accuracy.

[0020] (2) The method of the present invention introduces automated control technology to realize the automated operation of processes such as test link construction, parameter configuration, data acquisition, and result comparison, reducing manual intervention. It not only avoids test anomalies or data deviations caused by human error, but also significantly shortens the time of a single test. Especially in batch testing scenarios, it effectively meets the needs of efficient testing in the design finalization stage of suspended objects and accelerates the research and development progress. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall system of the present invention; Figure 2This is a schematic block diagram of the overall structure of the test host of the present invention; Figure 3 This is a structural block diagram of the fiber optic channel tester of the present invention; Figure 4 This is a schematic diagram of the internal architecture of the TC_MST (TC_SLV) module of the present invention; Figure 5 This is a schematic diagram of the method flow of the present invention. Detailed Implementation

[0022] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0023] Specifically, in a first aspect, the present invention provides a comprehensive high-speed network interface testing system for aircraft suspension devices, such as... Figure 1 As shown, it includes a test host 1 and multiple fiber optic bus boards, which are connected to the test host via PXIE interfaces. The multiple fiber optic bus boards include a first fiber optic bus board 21, a second fiber optic bus board 22, and a third fiber optic bus board 23 that communicate with each other. The test host 1 includes a fiber optic test module 11, a fiber optic analysis module 12, a simulation module 13, and a display unit 14. The fiber optic test module 11 communicates with the first fiber optic bus board 21, the fiber optic analysis module 12 communicates with the second fiber optic bus board 22, and the simulation module 13 communicates with the third fiber optic bus board 23. Besides power supply, reset, and clock interfaces, the fiber optic bus boards mainly include a minimum system based on a K7 core, bus interfaces, and an 1188B bus interface. The K7 is configured with NOR FLASH memory for storing software images; the K7 is also configured with a 256Mb×32bit DDR3 SDRAM memory for interface data management.

[0024] The first fiber optic bus board 21 has multiple test ports; the second fiber optic bus board has multiple analysis ports; the third fiber optic bus board has multiple simulation ports; the test host 1 has a VGA port and a LAN port; the VGA port and LAN port are used to connect to other devices; the fiber optic test module 11 calls the preset aircraft suspended high-speed network interface test protocol and outputs high-speed network test signals through the first fiber optic bus board; the fiber optic analysis module 12 receives the high-speed network test signals through the second fiber optic bus board, performs real-time test analysis, and sends the parsed data to the display unit and simulation module respectively; the simulation module 13 uses the third fiber optic bus board to simulate the target state of the aircraft, generates expected data under the target state, and judges the high-speed network test signal data. In use, any test port is connected to the analysis port, and the analysis port is further connected to the simulation port. The display unit 14 is used to display relevant data.

[0025] The fiber optic testing module 11 includes a port management unit 111, a network configuration unit 112, a data transceiver unit 113, a data editing unit 114, and a first discrimination unit 115; the fiber optic analysis module 12 includes a data analysis unit 121; and the simulation module 13 includes a simulation unit 131 and a second discrimination unit 132.

[0026] The port management unit 111 includes a port state machine. This machine automatically performs link initialization and initiates the network login process after system startup. After successful login, it continuously monitors the link status and automatically triggers re-initialization if a link anomaly occurs. The fiber optic testing module utilizes an FPGA to implement the port state machine, ensuring automatic link initialization after system startup. The link status is stored in registers and displayed in the graphical interface module. After link activation, the network login process is initiated, a process completed collaboratively by the FPGA and software. To support network login testing, this module allows users to modify the data content and transmission format of the login frame in the software display unit. The data content and transmission control information of the login frame are written by the user to a fixed area via application software and stored in the FPGA's login register. After the user configures the login information, the software writes it to the login register.

[0027] The network configuration unit 112 is used to set the functions simulated by the high-speed network testing system, the types of ports provided, and the format of information transmission. The functions simulated by the high-speed network testing system (switch, network controller, or network terminal), the types of ports provided (AE, F, N, etc.), and the format of information transmission (cyclic repetition or fixed interval) need to be configured by the user through software and written to the configuration register and internal RAM configuration stack area. Custom test data to be transmitted is written to DDR3 under software control. Users can configure this information either through the software display unit or by importing a structured information file.

[0028] The data editing unit 114 is used for data editing. The first discrimination unit 115 is used to perform the first discrimination of the data, that is, to judge its own working status to avoid generating erroneous data. If the discrimination is successful, it is sent to the data transceiver unit 113; if the discrimination fails, it is fed back to the data editing unit for re-editing. The data transceiver unit 113 is used to send high-speed network test signals. The data analysis unit is used to perform protocol analysis and decoding on the fiber optic channel. By capturing the data stream in the fiber optic channel, extracting frame and primitive information, and performing in-depth analysis processing, the data is further sent to the display unit and the second discrimination unit. The simulation unit is used to simulate the target state of the aircraft's suspended objects and generate expected data under the target state. In practical applications, the expected data under each state can also be stored in advance in the simulation unit and called during the simulation. The second discrimination unit is used to perform a second discrimination of the data. If the discrimination is successful, the test is completed. If there is a data transmission error, it is displayed on the display unit.

[0029] In practical applications, the discrimination method of the second discrimination unit 132 can be achieved by comparing data. For example, it can automatically monitor the received data area in DDR3, compare the actual received data with the expected data field by field to achieve automatic identification of error fields, and simultaneously count the number of error frames, the amount of error data, and the error location value, which are then displayed in the graphical interface unit. The specific method for judging high-speed network test signal data in this embodiment is as follows: First, obtain the single-frame received data D, and divide the single-frame received data D into N fields. Determine the length of each field. The unit is bits. Weights are assigned to each field. Priority is sorted according to the weight of each field, and key fields with high priority are identified first. The calculation formula is: ; in, This is the functional importance coefficient. The error impact coefficient. These are the weights for the functional importance coefficient and the error impact coefficient, respectively. In practical applications, This can be obtained by fitting historical data. The above formula allows for the assignment of appropriate weights to each field. The sum of the weights of all fields is 1.

[0030] Secondly, each field is compared field by field. Actual received data Compared with expected data Calculate the matching degree Combined with a preset threshold T, incorrect fields are identified, and the matching degree is determined. The calculation formula is: ; in, Let represent the matching degree of the i-th field, with a value between 0 and 1. This quantifies the degree of match between the actual received data and the expected data for that field. 1 indicates a perfect match (no errors), while values ​​closer to 0 indicate more severe errors. When the value is less than the threshold T, the field to be judged is... For error, when When the value is greater than or equal to the threshold T, the field to be judged is... That is correct.

[0031] This is a statistical function used to calculate the number of error bits in a field, i.e., the number of errors with a result of 1. This is a bitwise XOR operation used to compare whether the actual data of the i-th field matches the expected data. A value of 1 indicates a difference between the actual and expected data of the i-th field, while a value of 0 indicates a match.

[0032] Finally, the number of erroneous data frames and the amount of erroneous data are counted and output to the display unit for display. The statistics are based on the actual number of erroneous frames, and the results are displayed.

[0033] The first fiber optic bus board 21, the second fiber optic bus board 22, and the third fiber optic bus board 23 are each equipped with one 1188B high-speed bus interface, NC communication, and a software programming configuration terminal. The bus interface meets the communication protocol requirements of the GJB1188B standard. The NC communication can initiate NC-NT interaction, NT-NC interaction, and vector word exchange operations. The software programming configuration terminal can switch the fiber optic bus board between communication mode and batch transmission mode through control commands from the test chassis. The test chassis is compatible with the Windows operating system and comes pre-installed with drivers and dynamic library functions adapted to the first, second, and third fiber optic bus boards. The drivers are used to establish hardware communication connections between the test chassis and the fiber optic bus boards, and the dynamic library functions are used to support software calls to the fiber optic bus board functions. The 1188B high-speed bus interface includes an 1188B bus protocol controller, an isolation transformer, and a bus connector.

[0034] In specific applications, the first fiber optic bus board 21, the second fiber optic bus board 22, and the third fiber optic bus board 23 are all equipped with programming logic chips.

[0035] The programming logic chip of the first fiber optic bus board 21 includes FLOGIN, configuration register, TC_MST, TC_SLV, TX FIFO, RX FIFO, FC MAC, FC PHY, and DDR3. FLOGIN is used for port management; the configuration register is used to store network configuration parameters; TC_MST, TC_SLV, TX FIFO, RX FIFO, FC MAC, and FC PHY are used together to complete data transmission and reception; the TC_MST module and TC_SLV module, based on the software configuration register information and stack information, complete the reading of data from DDR3 during transmission and send the data to the TX FIFO module, and during reception, read data from the RX FIFO module and write the data to the DDR3 module; DDR3 is used to write user-edited data.

[0036] DDR3 is used to store test data to be sent or response data already received. Before the test starts, the test data to be sent and data statistics information are written into DDR3. Then, the test data in DDR3 is read and sent. During the test, the programming logic chip parses the received response frame, writes the received response data into DDR3, and then the first discrimination unit reads the response data and compares it with the expected data.

[0037] The TC_MST and TC_SLV modules include DATAMOVER, TX / RX RAM, instruction FIFO, TC descriptor RAM, configuration register, storage state machine, and frame state machine. The instruction FIFO stores the starting address, data byte length, and operation instructions for writing / reading DDR3 data. The TX RAM temporarily stores data read from DDR3 in data frames, with each frame corresponding to one instruction in the instruction FIFO. The RX RAM temporarily stores data to be written to DDR3, with each frame corresponding to one instruction in the instruction FIFO. DATAMOVER reads instructions from the instruction FIFO through the storage state machine and converts them into AXIS commands conforming to the DAMAMOVER IP core, controlling DATAMOVER to perform data writing / reading. The configuration register stores network configuration. The TC descriptor RAM stores data transmission and reception status and control information, including the TC transmit configuration stack and the TC receive status stack. The frame state machine completes the framing of test data and parses the responses.

[0038] In a specific embodiment, the FPGA design scheme of the fiber optic channel tester is as follows: Figure 3 As shown, FLOGIN is used for port management; the configuration register stores network configuration parameters; TC_MST, TC_SLV, TX FIFO, RX FIFO, FC MAC, and FC PHY work together to complete data transmission and reception; user-edited data is written to DDR3 via software.

[0039] In the system, DDR3 is used to store test data to be sent or response data already received. The storage format is shown in Tables 3 and 5. Before the test starts, the software writes the test data to be sent and data statistics information into DDR3 according to the format in Table 3. Then, the FPGA reads the test data in DDR3 and sends it under the control of the software. During the test, the FPGA parses the received response frames and writes the received response data into DDR3 according to the storage format shown in Table 5. Then, the software reads the response data and compares it with the expected data.

[0040] The TC_MST (TC_SLV) module reads data from the DDR3 module during transmission and sends the data to the TX FIFO module based on the software configuration register information and stack information, and reads data from the RX FIFO module and writes the data to the DDR3 module during reception.

[0041] The TC_MST (TC_SLV) module includes DATAMOVER, TX / RX RAM, instruction FIFO, TC descriptor RAM, configuration register, storage state machine, and frame state machine. The instruction FIFO stores the starting address, data byte length, and operation instructions (write / read) for writing / reading DDR3 data to be processed. The TXRAM temporarily stores data read from DDR3, stored in data frames, with each frame corresponding to one instruction in the instruction FIFO. The RXRAM temporarily stores data to be written to DDR3, with each frame corresponding to one instruction in the instruction FIFO. The DATAMOVER uses the VIVADO 2018.3 IP core, configured to enable dual-channel modes of MM2S and S2MM. The module reads instructions from the instruction FIFO through a storage state machine and converts them into AXIS commands conforming to the DAMAMOVER IP core, controlling the DATAMOVER to perform data writing / reading. The configuration register stores network configuration information (see Table 1). The TC descriptor RAM stores data transmission and reception status and control information, functionally divided into a TC transmit configuration stack and a TC receive status stack (see Table 2). The correspondence between the TC descriptor RAM and external systems is shown in Table 2. Figure 4 The TC descriptor RAM corresponds to the internal RAM 4K*32bit shown in the diagram. The TXBUF_PT in the TC transmit configuration stack is the transmit pointer, which defines the starting position of the data frame to be transmitted in DDR3. The RXBUF_PT in the TC receive status stack is the receive pointer, which specifies the starting position of the received data frame in DDR3. Figure 4 The registers in the table correspond to those in Table 1. The TCRX_START_PT register stores the starting address of the instruction in the TC transmit configuration stack to be processed, the TCRX_START_PT register stores the starting address of the first status information in the TC receive status stack to be processed, the TCRX_END_PT register stores the starting address of the last status information in the TC receive status stack to be processed, the RXBUF_START_PT register stores the starting address of the received data in DDR3, and the RXBUF_END_PT register stores the ending address of the received data in DDR3. The frame state machine completes the framing of the test data and implements the parsing of the response.

[0042] After being framed by the frame state unit, the test data is buffered in the TX FIFO and then enters the FC MAC module. The FC MAC module's functions include frame transmission and flow control; it works in conjunction with... Figure 3 The FC PHY physical layer jointly completes data transmission. The RX FIFO is used as a buffer for response frames, and the frame state machine reads and parses the data when it detects that the RX FIFO is not empty.

[0043] The TC_SLV module is only enabled during parallel switching tests. TC_MST can only start one switch at a time, and the next switch can only start after the current switch is completed. However, parallel testing requires multiple switches to run simultaneously, so the TC_SLV module is introduced. Its structure is the same as TC_MST and both share DDR3, but their registers and RAM addresses are different.

[0044] The FLOGIN module connects to the FC MAC and has a built-in receive state machine, transmit state machine, request frame register, and acknowledge frame register. The receive state machine monitors the parsed frames of the FC MAC in real time. If an FLOGIN request frame is detected, the frame content is saved to the request frame register. After detecting an FLOGIN request frame, the transmit state machine replies with an acknowledge frame, the content of which comes from the acknowledge frame register, the value of which can be modified by software.

[0045] Table 1 TC_MST (TC_SLV) Module Configuration Registers Table 2 TC Transmission Configuration Stack Table 3. Transmit Frame Definitions in DDR3 Table 4 TC Receive Configuration Stack Table 5 Receive Frame Definitions in DDR3 Secondly, this invention provides a comprehensive method for testing high-speed network interfaces on aircraft suspension devices, such as... Figure 5 As shown, it includes the following steps: S1. Insert the first fiber optic bus board, the second fiber optic bus board, and the third fiber optic bus board into the corresponding slots of the test host. The first fiber optic bus board is used to output high-speed network test signals; the second fiber optic bus board is used to receive and parse test signals; and the third fiber optic bus board is used to simulate the working state of the suspended object and to judge the received data.

[0046] S2. Connect the first fiber optic board and the second fiber optic board to form a test signal transmission link, and connect the second fiber optic board and the third fiber optic board to form a data judgment link.

[0047] S3. Power on the test host and start the fiber optic test module, fiber optic analysis module, and simulation module to perform test analysis on the fiber optic cable under test. The fiber optic test module calls the preset high-speed network interface test protocol for aircraft suspension and outputs high-speed test signals to the test link through the first fiber optic bus board. The simulation module loads the preset suspension network interface working scenario model and simulates the network interface signal response of the suspension under different flight attitudes and load conditions through the third fiber optic bus board, generates expected data, and judges the received data. The fiber optic analysis module collects test signals through the second fiber optic bus board and sends them to the display unit and the simulation module respectively.

[0048] S4. During the test, the fiber optic analysis module collects the test data in real time, providing detailed information on the currently collected messages. Simultaneously, the received data is displayed on the test host's display unit. In other embodiments, the display unit can also display the data in a visual format, including data tables, pass / fail indicators, etc.

[0049] The working steps of this embodiment will be described in detail below: This specific embodiment discloses an interface testing device for an aircraft suspension electrical connection system, which is rectangular in shape. The test chassis includes a card slot end, a host computer end, and an interface end. The card slot end includes eight PXIE interfaces; the bus board is inserted into the card slot before use. The host computer end includes a screen and a keyboard, and the analysis software and test software can be launched through the host computer end to complete the basic functions of this invention. The interface end includes XT1, XT2, XA1, XA2, XN1, XN2, VGA, and a LAN port. The VGA and LAN ports can be connected to other devices. XT1 and XT2 represent test port 1 and test port 2, XA1 and XA2 represent analysis port 1 and analysis port 2, and XN1 and XN2 represent simulation port 1 and simulation port 2. When verifying its own continuity, XT1 and XA1 are connected, and XA2 and XN1 are connected. When testing the target under test, XT1 and XA1 are connected, and XA1 and XN1 are connected.

[0050] The steps for using the device of the present invention are as follows: First, insert the three cards into the card slots to connect test port 1 and analysis port 1.

[0051] Secondly, after powering on, open and run the analyzer software, tester software, and simulation software respectively.

[0052] Third, configure the tester software according to the user's required rate, add a new test case or open an existing test case and click send.

[0053] Finally, you can see the current test case sending and running status in the display unit.

[0054] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A comprehensive high-speed network interface testing system for aircraft suspension devices, characterized in that: It includes a test host and multiple fiber optic bus cards, which are connected to the test host via PXIE interfaces. Multiple fiber optic bus boards include a first fiber optic bus board, a second fiber optic bus board, and a third fiber optic bus board that communicate with each other. The test host includes a fiber optic test module, a fiber optic analysis module, a simulation module, and a display unit. The fiber optic test module is communicatively connected to the first fiber optic bus board, the fiber optic analysis module is communicatively connected to the second fiber optic bus board, and the simulation module is communicatively connected to the third fiber optic bus board. The first fiber optic bus board has multiple test ports; The second fiber optic bus board has multiple analysis ports; The third fiber optic bus board has multiple simulation ports; The test host is equipped with a VGA port and a LAN port; the VGA port and LAN port are used to connect to other devices; the fiber optic test module calls the preset high-speed network interface test protocol for aircraft suspended objects and outputs high-speed network test signals through the first fiber optic bus board; the fiber optic analysis module receives the high-speed network test signals through the second fiber optic bus board, performs real-time test analysis, and sends the parsed data to the display unit and simulation module respectively; the simulation module uses the third fiber optic bus board to simulate the target state of the aircraft suspended object, generates expected data under the target state, and judges the high-speed network test signal data; the specific method for judging the high-speed network test signal data is as follows: First, obtain the single-frame received data D, and divide the single-frame received data D into N fields. Determine the length of each field And assign weights to each field. Prioritize and sort according to the weight of each field. The calculation formula is: ； in, This is the functional importance coefficient. The error impact coefficient. These are the weights for the functional importance coefficient and the error impact coefficient, respectively. Secondly, each field is compared field by field. Actual received data Compared with expected data Calculate the matching degree Combined with a preset threshold T, incorrect fields are identified, and the matching degree is determined. The calculation formula is: ； in, Let be the matching degree of the i-th field. This is a statistical function used to calculate the number of error bits in a field. This is a bitwise XOR operation used to compare whether the actual data of the i-th field matches the expected data. Finally, the number of frames with errors and the amount of erroneous data are counted and output to the display unit for display.

2. The integrated high-speed network interface testing system for aircraft suspension devices according to claim 1, characterized in that: The fiber optic testing module includes a port management unit, a network configuration unit, a data transceiver unit, a data editing unit, and a first discrimination unit; the fiber optic analysis module includes a data analysis unit; the simulation module includes a simulation unit and a second discrimination unit; the port management unit includes a port state machine, which automatically performs link initialization and initiates the network login process after system startup, continuously monitors the link status after successful login, and automatically triggers re-initialization when the link is abnormal; the network configuration unit is used to set the functions simulated by the high-speed network testing system, the provided port types, and the form of information transmission; the data editing unit is used for data editing, and the first discrimination unit is used to perform the first discrimination on the data. If the discrimination is successful, the data is sent to the data transceiver unit; if the discrimination fails, it is fed back to the data editing unit for re-editing; the data transceiver unit is used to send high-speed network test signals. The data analysis unit is used to perform protocol analysis and decoding on the fiber optic channel. By capturing the data stream in the fiber optic channel, extracting frame and primitive information, and performing in-depth analysis, the data is further sent to the display unit and the second discrimination unit. The simulation unit is used to simulate the target state of the aircraft's suspended object and generate expected data under the target state. The second discrimination unit is used to perform a second discrimination on the data. After the discrimination is passed, the test is completed.

3. The integrated high-speed network interface testing system for aircraft suspension devices according to claim 1, characterized in that: The first, second, and third fiber optic bus boards are all equipped with a 1188B high-speed bus interface, NC communication, and a software programming configuration terminal. The bus interface meets the communication protocol requirements of the GJB1188B standard. The NC communication can initiate NC-NT interaction, NT-NC interaction, and vector word exchange operations. The software programming configuration terminal can switch the fiber optic bus board between communication mode and batch transmission mode through the control commands of the test chassis.

4. The integrated high-speed network interface testing system for aircraft suspension devices according to claim 3, characterized in that: The test chassis is compatible with the Windows operating system and comes pre-installed with drivers and dynamic library functions adapted to the first fiber optic bus board, the second fiber optic bus board, and the third fiber optic bus board. The drivers are used to establish hardware communication connections between the test chassis and the fiber optic bus boards, and the dynamic library functions are used to support software calls to the functions of the fiber optic bus boards.

5. The integrated high-speed network interface testing system for aircraft suspension devices according to claim 3, characterized in that: The 1188B high-speed bus interface includes the 1188B bus protocol controller, isolation transformer, and bus connector.

6. The integrated high-speed network interface testing system for aircraft suspension devices according to claim 1, characterized in that: The first, second, and third fiber optic bus boards are all equipped with programming logic chips.

7. The integrated high-speed network interface testing system for aircraft suspension devices according to claim 6, characterized in that: The programming logic chips of the first fiber optic bus board include FLOGIN, configuration register, TC_MST, TC_SLV, TX FIFO, RX FIFO, FC MAC, FC PHY, and DDR3. FLOGIN is used for port management; the configuration register is used to store network configuration parameters; TC_MST, TC_SLV, TX FIFO, RX FIFO, FC MAC, and FC PHY are used together to complete data transmission and reception; the TC_MST module and TC_SLV module, based on the software configuration register information and stack information, complete the reading of data from DDR3 during transmission and send the data to the TX FIFO module, and during reception, read data from the RX FIFO module and write the data to the DDR3 module; DDR3 is used to write user-edited data.

8. The integrated high-speed network interface testing system for aircraft suspension devices according to claim 7, characterized in that: DDR3 is used to store test data to be sent or response data that has been received. Before the test starts, the test data to be sent and data statistics information are written into DDR3. Then, the test data in DDR3 is read and sent. During the test, the programming logic chip parses the received response frame, writes the received response data to DDR3, and then the first discrimination unit reads the response data and compares it with the expected data.

9. The integrated high-speed network interface testing system for aircraft suspension devices according to claim 7, characterized in that: The TC_MST and TC_SLV modules include DATAMOVER, TX / RX RAM, instruction FIFO, TC descriptor RAM, configuration register, storage state machine, and frame state machine; the instruction FIFO is used to store the starting address, data byte length, and operation instruction of the write / read DDR3 operation of the data to be processed; TXRAM is used to temporarily store data read from DDR3 in the form of data frames, with each data frame corresponding to one instruction in the instruction FIFO; The RXRAM is used to temporarily store data to be written to DDR3, with each frame of data corresponding to one instruction in the instruction FIFO. The DATAMOVER reads instructions from the instruction FIFO through a storage state machine and converts them into AXIS commands conforming to the DAMAMOVER IP core, controlling the DATAMOVER to perform data writing / reading. The configuration register is used to store network configuration. The TC descriptor RAM is used to store the status and control information for data transmission and reception. The TC descriptor RAM includes the TC transmit configuration stack and the TC receive status stack. The frame state machine is used to complete the framing of test data and to parse the response.

10. A method for testing high-speed network interfaces of aircraft suspensions based on the integrated aircraft suspension high-speed network interface testing system according to claim 1, characterized in that: It includes the following steps: S1. Insert the first fiber optic bus board, the second fiber optic bus board, and the third fiber optic bus board into the corresponding slots of the test host respectively. The first fiber optic bus board is used to output high-speed network test signals. The second fiber optic bus board is used to receive and parse test signals; The third fiber optic bus board is used to identify the received data; S2. Connect the first fiber optic board and the second fiber optic board to form a test signal transmission link, and connect the second fiber optic board and the third fiber optic board to form a data judgment link. S3. Power on the test host and start the fiber optic test module, fiber optic analysis module, and simulation module to perform test and analysis on the fiber optic cable under test. The fiber optic test module calls the preset high-speed network interface test protocol for aircraft suspension devices and outputs high-speed test signals to the test link through the first fiber optic bus board. The simulation module loads the preset network interface working scenario model for the suspension device and simulates the network interface signal response of the suspension device under different flight attitudes and load conditions through the third fiber optic bus board, generates expected data, and judges the received data. The fiber optic analysis module collects test signals through the second fiber optic bus board and sends them to the display unit and the simulation module respectively. S4. During the test, the fiber optic analysis module performs real-time analysis and transmission of the collected test data, which is then displayed on the display unit of the test host.

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