Semiconductor device
By setting a metal oxide layer in the air gap, the problem of the air gap structure being easily broken down in subsequent processes is solved, thereby improving the stability and reliability of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2026-01-14
- Publication Date
- 2026-04-14
AI Technical Summary
In semiconductor devices, air gap structures are easily broken down by mechanical stress or plasma impact during subsequent process steps, leading to structural collapse and affecting device performance.
A metal oxide layer is formed within the air gap to enhance mechanical strength and prevent structural collapse.
This improves the structural stability of the dielectric layer, prevents the structure from collapsing in subsequent processes, and enhances the reliability of semiconductor devices.
Smart Images
Figure CN121865614A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology
[0002] Dynamic random access memory (DRAM) is a type of volatile memory that includes an array area consisting of multiple memory cells. Each memory cell consists of a transistor and a capacitor electrically connected to the transistor, with the capacitor's electrodes electrically connected by metal wires and contact plugs.
[0003] As semiconductor device dimensions continue to shrink, the industry commonly employs the technique of introducing air gaps in the dielectric layer to reduce parasitic capacitance between metal interconnect layers. However, the air gap structure itself has weak mechanical strength. In subsequent process steps after the air gap is formed (such as via etching, deposition of barrier layers or metal layers), the top film of the air gap is easily broken down by mechanical stress or plasma impact, which can even cause the entire air gap structure to collapse, affecting device performance. Summary of the Invention
[0004] One objective of this application is to provide a semiconductor device that, by forming a metal oxide layer in the air gap, avoids the filling of the air gap by process materials in subsequent manufacturing processes, and can also prevent structural collapse.
[0005] To achieve the above objectives, one embodiment of this application provides a semiconductor device, comprising:
[0006] Substrate;
[0007] Multiple metal interconnect structures are located on the substrate, each metal interconnect structure including a metal layer and a conductive plug located on the metal layer;
[0008] A dielectric layer is located between adjacent metal interconnect structures and has multiple air gaps;
[0009] A metal oxide layer covers the inner surface of at least one of the air gaps.
[0010] Furthermore, the at least one of the air gaps is located between adjacent metal interconnect structures on the same horizontal plane.
[0011] Furthermore, the bottom of the at least one of the air gaps is lower than the top surface of the metal layer in the metal interconnect structure located on both sides thereon, and higher than the bottom surface of the metal layer.
[0012] Furthermore, the top of the at least one of the air gaps is lower than the top surface of the dielectric layer between the adjacent metal interconnect structures located on the same horizontal plane.
[0013] Furthermore, the metal oxide layer discontinuously covers the inner surface of the at least one of the air gaps.
[0014] Furthermore, the metal oxide layer is aluminum oxide.
[0015] Furthermore, the top of the metal oxide layer covering the at least one of the air gaps is lower than the top surface of the conductive plugs in the metal interconnect structure located on both sides thereon.
[0016] Furthermore, the width of the air gap between adjacent metal interconnect structures on the same horizontal plane in the horizontal direction is smaller than the width of the dielectric layer between adjacent metal interconnect structures on the same horizontal plane in the horizontal direction.
[0017] Furthermore, the metal oxide layer is in physical contact with the dielectric layer.
[0018] Furthermore, the semiconductor device also includes:
[0019] Multiple bit lines are disposed on the substrate, spaced apart from each other;
[0020] Multiple contact structures are located between adjacent bit lines;
[0021] Multiple connecting pad structures are located on the contact structure;
[0022] Multiple capacitor structures are located on the connecting pad structure;
[0023] The upper electrode plate layer is located on the plurality of capacitor structures.
[0024] To achieve the above objectives, one embodiment of this application provides a semiconductor device, comprising:
[0025] Substrate;
[0026] Multiple plugs are located on the substrate;
[0027] A dielectric layer is located between adjacent plugs and has multiple air gaps;
[0028] A metal oxide layer covers the inner surface of at least one of the air gaps;
[0029] Wherein, the at least one air gap is located between adjacent plugs on the same horizontal plane, the bottom of the at least one air gap is higher than the bottom surface of the plugs located on both sides thereon, the top of the at least one air gap is lower than the top surface of the plug, and the top of the at least one air gap is lower than the top surface of the dielectric layer between the adjacent plugs on the same horizontal plane.
[0030] To achieve the above objectives, one embodiment of this application provides a semiconductor device, comprising:
[0031] The substrate includes a first region and a second region;
[0032] A capacitor structure is located on the first region;
[0033] Multiple metal interconnect structures are spaced apart from each other in the horizontal direction and stacked on the second region in the vertical direction. Each metal interconnect structure includes a metal layer and a conductive plug located on the metal layer.
[0034] A multilayer dielectric layer is provided between adjacent metal interconnect structures located on the same horizontal plane, and at least one air gap is provided within the dielectric layer;
[0035] A metal oxide layer covers the inner surface of the air gap.
[0036] Furthermore, the bottom of the air gap between adjacent metal interconnect structures on the same horizontal plane is lower than the top surface of the metal layer in the metal interconnect structures on both sides of it, and higher than the bottom surface of the metal layer, while the top of the air gap is lower than the top surface of the dielectric layer between the adjacent metal interconnect structures on the same horizontal plane.
[0037] Furthermore, the bottom of all the air gaps is higher than the top surface of the capacitor structure.
[0038] Furthermore, the bottom of the air gap is higher than the top surface of the capacitor structure.
[0039] Furthermore, the bottom of the metal oxide layer is higher than the top surface of the capacitor structure.
[0040] As described above, the semiconductor device of this application includes multiple metal interconnect structures, a dielectric layer, and a metal oxide layer. The dielectric layer is located between adjacent metal interconnect structures and has multiple air gaps; the metal oxide layer covers the inner surface of at least one air gap. Because the metal oxide layer is disposed on the inner surface of the air gap, the metal oxide layer has high mechanical strength, which can improve the structural stability of the dielectric layer, thereby effectively resisting stress in subsequent processes (such as etching and film deposition) and preventing structural collapse. Attached Figure Description
[0041] The accompanying drawings provide a more in-depth understanding of embodiments of this application and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams and are for illustrative and drawing convenience, and relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.
[0042] Figure 1 This is a partial structural cross-sectional view of the semiconductor device in the first embodiment of this application;
[0043] Figure 2 This is a partial structural cross-sectional view of the semiconductor device in the second embodiment of this application;
[0044] Figure 3 This is a partial structural cross-sectional view of the semiconductor device in the third embodiment of this application;
[0045] The attached figures are labeled as follows:
[0046] 100 - Substrate, 101 - First region, 102 - Second region, STI - Trench structure, 110 / 210 - Insulating layer, 120 - Bit line, 220 - Gate structure, 121 / 221 - Semiconductor layer, 122 / 222 - Barrier layer, 123 / 223 - Metal layer, 124 / 224 - Cap layer, 130 / 230 - Sidewall structure, 131 / 231 - First sidewall, 132 / 232 - Second sidewall, 140 - Contact structure, 150 - Silicide layer, 160-connector pad structure, 161-first connector pad layer, 162-second connector pad layer, 170-isolation structure, 180-capacitor structure, 181-lower electrode layer, 182-dielectric layer, 183-upper electrode layer, 190-upper electrode plate, 251-plug, 240-dielectric layer, 260-metal interconnect structure, 261-metal layer, 262-conductive plug, OP1 / OP2 / OP3-air gap, 270-metal oxide layer.
[0047] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation
[0048] To make the technical solutions and advantages of the embodiments of this application clearer, the technical solutions of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this application are shown in the accompanying drawings, it should be understood that this application can be implemented in various forms and should not be limited to the implementation methods described herein. Rather, these implementation methods are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.
[0049] The present application is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present application will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and are only used to facilitate and clarify the illustration of the embodiments of the present application. It is understood that the meanings of "on," "above," and "over" in the present application should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer. In the embodiments of the present application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present application can be arbitrarily combined without conflict.
[0050] Please refer to Figure 1 As shown, the illustration is a partial structural cross-sectional view of the semiconductor device in the first embodiment of this application. Figure 1 As shown, the semiconductor device in the first embodiment of this application includes a substrate 100, a plurality of metal interconnect structures 260, a dielectric layer 240, an air gap OP located in the dielectric layer 240, and a metal oxide layer 270 located in at least one air gap OP.
[0051] In this embodiment, the substrate 100 can be any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), or a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. Furthermore, the substrate 100 can be specifically divided into a first region 101 and a second region 102. The first region 101 is, for example, a cell region of a semiconductor device, and the second region 102 is, for example, a peripheral region of a semiconductor device. The second region 102 and the first region 101 are arranged adjacent to each other, but are not limited thereto. Multiple trench structures STI are provided in both the first region 101 and the second region 102 of the substrate 100, and the multiple trench structures STI define multiple active areas (AA, not shown in the figure) on the substrate 100. For example, the trench structure STI may include a single layer or multiple layers of dielectric material. Suitable dielectric materials may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or combinations of the above materials, but are not limited thereto. For example, the trench structure STI in this embodiment may be elongated with its long axis extending along a direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction). In addition, an insulating layer is also provided on the substrate 100. For ease of distinction, in this embodiment, the insulating layer located in the first region 101 is identified by reference numeral 110, and the insulating layer located in the second region 102 is identified by reference numeral 210. Specifically, the insulating layer (110, 210) can be a single-layer structure, such as a silicon oxide layer or a silicon nitride layer, or it can be a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, but is not limited thereto.
[0052] Furthermore, the semiconductor device in this embodiment also includes a plurality of bit lines 120 and a gate structure 220. The plurality of bit lines 120 are disposed on a first region 101 of the substrate 100 with spacing between them, and have multiple layers of bit line material, such as a semiconductor layer 121, a barrier layer 122, a metal layer 123, and a capping layer 124 stacked sequentially from bottom to top. The material of the semiconductor layer 121 may include crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon-germanium (SiGe), or other suitable semiconductor materials, but is not limited thereto. The material of the barrier layer 122 may include metals, metal silicides, or metal nitrides, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), and tungsten nitride (WN), but is not limited thereto. The material of metal layer 123 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but is not limited thereto. Cap layer 124 may include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but is not limited thereto. It should be understood that during the formation of multiple bit line material layers in the first region 101 of substrate 100 to construct multiple bit lines 120, a discrete structure composed of the multiple bit line material layers, namely gate structure 220 (located on insulating layer 210 in the second region 102), is simultaneously formed on the second region 102 of substrate 100. Thus, for ease of distinction, in this embodiment, the corresponding multiple bit line material layers in gate structure 220 are respectively identified by reference numerals 221 (semiconductor layer), 222 (barrier layer), 223 (metal layer), and 224 (cap layer). Furthermore, sidewall structures (130, 230) are respectively provided on the sidewalls of bit line 120 and gate structure 220. The sidewall structures (130, 230) can be composite structures, for example... Figure 1 As shown, the sidewall structure (130) is a composite structure consisting of a first sidewall (131) and a second sidewall (132) stacked from the inside out along a direction perpendicular to the bit line 120. The sidewall structure (230) is a composite structure consisting of a first sidewall (231) and a second sidewall (232) stacked from the inside out along a direction perpendicular to the sidewall of the gate structure 220. Exemplarily, the first sidewall (131, 231) and the second sidewall (132, 232) may each include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but are not limited thereto.
[0053] In this embodiment, a plurality of contact structures 140, a silicide layer 150, a connection pad structure 160, an isolation structure 170, and a capacitor structure 180 are further disposed on the first region 101 of the substrate 100. The contact structures 140 are located between adjacent bit lines 120, and their sides are separated from the bit lines 120 by sidewall structures 130 and do not directly contact them, while their bottom directly contacts the end of the active region (substrate 100). Exemplarily, the material of the contact structures 140 may include crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon-germanium (SiGe), or other suitable silicon-containing semiconductor materials, but is not limited thereto. Preferably, the material of the contact structures 140 is phosphorus-doped silicon (SiP). The silicide layer 150 is located above the contact structure 140, and the connecting pad structure 160 conformally covers the top surface of the contact structure 140, the top surface of the sidewall structure 130, and the top surface of the bit line 120. Furthermore, in this embodiment, the connecting pad structure 160 includes a first connecting pad layer 161 and a second connecting pad layer 162 stacked sequentially from bottom to top in a vertical direction, with the bottom surface of the second connecting pad layer 162 being higher than the top surface of the bit line 120. Specifically, the first connecting pad layer 161 in the connecting pad structure 160 can wrap around the outer surface of the bit line 120 and the silicide layer 150, with its top surface exceeding the top surface of the bit line 120, while the second connecting pad layer 162 in the connecting pad structure 160 covers the first connecting pad layer 161. In one embodiment, the material of the first connection pad layer 161 may include titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN) and other conductive barrier materials, and is preferably titanium nitride (TiN), but is not limited thereto. The material of the second connection pad layer 162 may include metals, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys, and / or composite layers of the aforementioned materials, and is preferably tungsten (W), but is not limited thereto. The isolation structure 170 is disposed between adjacent connection pad structures 160 and passes through the corresponding connection pad structure 160, bit line 120, and sidewall structure 130. The capacitor structure 180 is disposed on the connection pad structure 160 between adjacent bit lines 120 and includes a lower electrode layer 181, a dielectric layer 182, and an upper electrode layer 183. The lower electrode layer 181 is disposed on the connecting pad structure 160, while the upper electrode layer 183 is disposed on the lower electrode layer 181, and the dielectric layer 182 is disposed between the upper electrode layer 181 and the lower electrode layer 183.
[0054] It should be noted that the semiconductor device in this embodiment also includes an upper electrode plate 190. Specifically, the upper electrode plate 190 is disposed on top of multiple capacitor structures 180 and buries the capacitor structures 180, meaning the top surface of the upper electrode plate 190 is higher than the top surface of the capacitor structures 180 (or, more accurately, higher than the top surface of the upper electrode layer 183 within the capacitor structures 180). By placing the upper electrode plate 190 on the upper electrode layer 183, the resistivity of the capacitor structures 180 is improved (resistivity is reduced), while simultaneously reducing the bonding difficulty of the capacitor electrodes (i.e., making bonding easier) and the manufacturing process complexity, ultimately improving the performance and reliability of the semiconductor device. For example, the upper electrode plate 190 can be a conductive material, such as metallic copper or germanium silicide, but is not limited thereto.
[0055] In this embodiment, the upper electrode plate 190 in the first region 101 and the gate structure 220 in the second region 102 are each formed with multiple layers of dielectric layers 240 stacked in the vertical direction (for the sake of simplicity, different dielectric layers are all identified by the same reference numeral "240"), as well as multiple metal interconnect structures 260 and multiple air gaps OP disposed in the dielectric layers 240; wherein, at least one air gap OP is further provided with a metal oxide layer 270 on its inner surface.
[0056] Specifically, for the first region 101 of the substrate 100, at least one plug 251 (material such as copper) for electrically leading out of the upper electrode plate 190 is provided in the dielectric layer 240 (hereinafter referred to as the first dielectric layer 240) located on the upper electrode plate 190 and in direct contact with the upper electrode plate 190; while metal interconnect structure 260 is formed in the multilayer dielectric layers 240 such as the second dielectric layer 240 and the third dielectric layer 240 located on the first dielectric layer 240. Each metal interconnect structure 260 includes a metal layer 261 and a conductive plug 262 located on the metal layer 261; and the metal interconnect structures 260 and plugs 251 in the multilayer dielectric layer 240 are aligned in the vertical direction. In this way, the upper electrode plate 190 is electrically led out layer by layer through the plugs 251 and the multiple metal interconnect structures 260 disposed in the multilayer dielectric layer 240, and there is no specific limitation on the number of dielectric layers 240 disposed on the upper electrode plate 190.
[0057] For the second region 102 of the substrate 100, at least two plugs 251 are also provided in the first dielectric layer 240 surrounding the gate structure 220, the second dielectric layer 240 located on the first dielectric layer 240, and the third dielectric layer 240 located on the second dielectric layer 240, so as to electrically lead out the source (not shown) and drain (not shown) on both sides of the gate structure 220 by aligning the plugs 251 of different layers and electrically connecting them layer by layer. At least one more dielectric layer 240 is provided on the third dielectric layer 240, and at least two metal interconnect structures 260 are provided in the dielectric layer 240 (aligned with the plugs 251 of the lower layer respectively), and the two metal interconnect structures 260 respectively include a metal layer 261 and a conductive plug 262 located on the metal layer 261. It should be understood that the number of dielectric layers 240 with plug 251 and dielectric layers 240 with metal interconnect structure 260 is not limited in the embodiments of this application. As long as the function of the embodiments of this application can be realized, and the metal interconnect structure 260 is provided in at least the top dielectric layer 240, it is within the protection scope of the embodiments of this application.
[0058] It should be noted that, in this embodiment, at least one air gap OP1 is provided within the top dielectric layer 240 of the second region 102 of the substrate 100, and a metal oxide layer 270 is provided on the inner surface of the air gap OP1, thus making physical contact between the metal oxide layer 270 and the dielectric layer 240 where the air gap OP1 is located. For example, the shape of the air gap OP1 can be elliptical. Furthermore, the air gap OP1 is located between adjacent metal interconnect structures 260 on the same horizontal plane, that is, the air gap OP1 is located between two adjacent metal interconnect structures 260 in the top dielectric layer 240. Secondly, the bottom (or the lowest surface of the bottom surface) of the air gap OP1 is lower than the top surface of the metal layer 261 in the metal interconnect structures 260 located on both sides of it, and higher than the bottom surface of the metal layer 261; moreover, the top of the air gap OP1 is lower than the top surface of the dielectric layer 240 between adjacent metal interconnect structures 260 on the same horizontal plane, that is, as shown in the figure. Figure 1 As shown, the top of the air gap OP1 is lower than the top surface of the top dielectric layer 240 in the second region 102 of the substrate 100.
[0059] In one embodiment, the metal oxide layer 270 may continuously cover the entire inner surface of the air gap OP1. In other embodiments, the metal oxide layer 270 may discontinuously cover the entire inner surface of the air gap OP1, that is, only a portion of the inner surface of the air gap OP1 is covered with the metal oxide layer 270. Regardless of whether the metal oxide layer 270 is continuous or discontinuous, its higher mechanical strength relative to the air gap OP1 provides support or protection to a certain extent. This prevents subsequent processes such as etching and film deposition from penetrating the dielectric layer 240 on top of the air gap OP1, which would allow other process materials to fill the air gap OP1 and cause electrical connections between these materials and the metal interconnect structure 260, resulting in semiconductor device failure and reduced reliability. It also prevents structural collapse.
[0060] Based on this purpose, it is known that the material of the metal oxide layer 270 disposed on the inner surface of the air gap OP1 is preferably an insulating material such as aluminum oxide, and the top surface of the metal oxide layer 270 must be lower than the top surface of the conductive plugs 262 in the metal interconnect structures 260 located on both sides of it, so that other conductive materials will not be filled into the air gap OP1 during the etching, filling and other processes of forming the conductive plugs 262; and the width of the air gap OP1 in the direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction) is preferably smaller than the width of the dielectric layer 240 between the adjacent metal interconnect structures 260 located on both sides of the air gap OP1 in the horizontal direction; in other words, the width of the dielectric layer 240 between the two adjacent metal interconnect structures 260 in the top dielectric layer 240 in the second region 102 of the substrate 100 in the horizontal direction is greater than the width of the air gap OP1 in the horizontal direction.
[0061] It should be understood that "common" in the embodiments of this application refers to constructing a continuous structural shape by utilizing the morphological similarity and correlation between two or more shapes.
[0062] Those skilled in the art to which this application pertains will readily understand that, to meet actual product requirements, the semiconductor device of this application may have other forms and is not limited to those described above. Further embodiments or variations of the semiconductor device of this application will be described below. For the sake of simplicity, identical components in the various embodiments of this application are designated with the same reference numerals to facilitate comparison between embodiments.
[0063] Please refer to Figure 2 , Figure 2 The illustration shows a partial structural cross-sectional view of the semiconductor device in the second embodiment of this application. Figure 2As shown, the structure of the semiconductor device in the second embodiment of this application is largely the same as that in the first embodiment. For example, the semiconductor device also includes a substrate 100, multiple bit lines 120, a gate structure 220, a contact structure 140, a silicide layer 150, multiple connection pad structures 160, multiple isolation structures 170, multiple capacitor structures 180, an upper electrode plate layer 190, a multilayer dielectric layer 240, multiple air gaps located within the dielectric layer 240, and a metal oxide layer 270 covering the inner surface of the air gaps. The substrate 100 (material such as a silicon wafer) is also divided into a first region 101 and a second region 102. The second region 102 and the first region 101 are arranged adjacent to each other. The second region 102 of the substrate 100 also contains air gaps such as OP1; similarities will not be described further here. The main difference between the semiconductor device in this embodiment and the first embodiment described above is that, in this second embodiment, not only is an air gap OP1 provided in the top dielectric layer 240 of the second region 102, but an air gap, such as air gap OP2, is also provided in the top dielectric layer 240 of the first region 101, and a metal oxide layer 270 is also provided on the inner surface of air gap OP2. Furthermore, the shape of air gap OP2 can be elliptical, or it can be different from the shape of air gap OP1, depending on the actual process. Air gap OP2 is located on one side of the metal interconnect structure 260 in the top dielectric layer 240 of the first region 101; thus, when performing subsequent processes such as etching and film deposition, it avoids the subsequent processes from etching through the dielectric layer 240 on top of air gap OP2, causing other process materials to fill into air gap OP2, and resulting in electrical connection between other process materials and the metal interconnect structure 260, which could lead to failure and reduced reliability of the semiconductor device, and also prevents structural collapse.
[0064] Those skilled in the art will readily understand that, since air gap OP2 is located within the top dielectric layer 240 of the first region 101 in this embodiment, the bottom of air gap OP2 is higher than the top surface of capacitor structure 180; and since air gap OP1 is located within the top dielectric layer 240 of the second region 102, the bottom of air gap OP2 is also higher than the top surface of capacitor structure 180 in the vertical direction; thus, it can be seen that the bottom of all air gaps in this embodiment is higher than the top surface of capacitor structure 180. Similarly, the bottom of the metal oxide layer 270 located on the inner surface of air gaps (OP1, OP2) is also higher than the top surface of capacitor structure 180.
[0065] Those skilled in the art to which this application pertains will readily understand that, to meet actual product requirements, the semiconductor device of this application may have other forms and is not limited to those described above. Further embodiments or variations of the semiconductor device of this application will be described below. For the sake of simplicity, identical components in the various embodiments of this application are designated with the same reference numerals to facilitate comparison between embodiments.
[0066] Please refer to Figure 3 , Figure 3 The illustration shows a partial structural cross-sectional view of the semiconductor device in the third embodiment of this application. Figure 3 As shown, the structure of the semiconductor device in the third embodiment of this application is largely the same as that in the second embodiment. For example, the semiconductor device also includes a substrate 100, multiple bit lines 120, a gate structure 220, a contact structure 140, a silicide layer 150, multiple connection pad structures 160, multiple isolation structures 170, multiple capacitor structures 180, an upper electrode plate layer 190, a multilayer dielectric layer 240, multiple air gaps (OP1, OP2) located within the dielectric layer 240, and a metal oxide layer 270 covering the inner surface of the air gaps. The substrate 100 (material such as a silicon wafer) is also divided into a first region 101 and a second region 102, and the second region 102 and the first region 101 are arranged adjacent to each other. The similarities will not be repeated here. The main difference between the semiconductor device in this embodiment and the aforementioned second embodiment is that, in this third embodiment, not only is an air gap OP1 provided in the topmost dielectric layer 240 of the second region 102, but also multiple air gaps are provided in other multilayer dielectric layers 240 in the second region 102 where multiple plugs 251 are provided, for example... Figure 3 The air gap OP3 is provided in the middle, and a metal oxide layer 270 is also provided on the inner surface of the air gap OP3. Secondly, the shape of the air gap OP3 can also be elliptical, and of course it can be different from the shape of the air gaps (OP1, OP2), depending on the actual process.
[0067] Specifically, the air gap OP3 is located within the other multilayer dielectric layers 240 in the second region 102, where multiple plugs 251 are disposed, and is specifically located between adjacent plugs 251. The metal oxide layer 270 disposed on the inner surface of the air gap OP3 also serves to protect and support the air gap OP3. Furthermore, the bottom of the air gap OP3 is higher than the bottom surfaces of the plugs 251 located on both sides; while the top of the air gap OP3 is lower than the top surfaces of the plugs 251 on both sides, or lower than the top surface of the dielectric layer 240 between the two plugs 251 on both sides.
[0068] In summary, the semiconductor device of this application includes multiple metal interconnect structures, a dielectric layer, and a metal oxide layer. The dielectric layer is located between adjacent metal interconnect structures and has multiple air gaps; the metal oxide layer covers the inner surface of at least one air gap. Because the metal oxide layer is disposed on the inner surface of the air gap, the metal oxide layer has high mechanical strength, which can improve the structural stability of the dielectric layer, thereby effectively resisting stress in subsequent processes (such as etching and film deposition) and preventing structural collapse.
[0069] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A semiconductor device, characterized in that, include: Substrate; Multiple metal interconnect structures are located on the substrate, each metal interconnect structure including a metal layer and a conductive plug located on the metal layer; A dielectric layer is located between adjacent metal interconnect structures and has multiple air gaps; A metal oxide layer covers the inner surface of at least one of the air gaps.
2. The semiconductor device as claimed in claim 1, characterized in that, The at least one of the air gaps is located between adjacent metal interconnect structures on the same horizontal plane.
3. The semiconductor device as described in claim 2, characterized in that, The bottom of the at least one of the air gaps is lower than the top surface of the metal layer in the metal interconnect structure located on both sides thereon, and higher than the bottom surface of the metal layer.
4. The semiconductor device as described in claim 2, characterized in that, The top of at least one of the air gaps is lower than the top surface of the dielectric layer between adjacent metal interconnect structures located on the same horizontal plane.
5. The semiconductor device as claimed in claim 1, characterized in that, The metal oxide layer discontinuously covers the inner surface of at least one of the air gaps.
6. The semiconductor device as claimed in claim 1, characterized in that, The metal oxide layer is aluminum oxide.
7. The semiconductor device as claimed in claim 2, characterized in that, The top of the metal oxide layer covering the at least one of the air gaps is lower than the top surface of the conductive plugs in the metal interconnect structure located on both sides thereon.
8. The semiconductor device as claimed in claim 2, characterized in that, The width of the air gap between adjacent metal interconnect structures on the same horizontal plane in the horizontal direction is smaller than the width of the dielectric layer between adjacent metal interconnect structures on the same horizontal plane in the horizontal direction.
9. The semiconductor device as claimed in claim 1, characterized in that, The metal oxide layer is in physical contact with the dielectric layer.
10. The semiconductor device as claimed in claim 1, characterized in that, Also includes: Multiple bit lines are disposed on the substrate, spaced apart from each other; Multiple contact structures are located between adjacent bit lines; Multiple connecting pad structures are located on the contact structure; Multiple capacitor structures are located on the connecting pad structure; The upper electrode plate layer is located on the plurality of capacitor structures.
11. A semiconductor device, characterized in that, include: Substrate; Multiple plugs are located on the substrate; A dielectric layer is located between adjacent plugs and has multiple air gaps; A metal oxide layer covers the inner surface of at least one of the air gaps; Wherein, the at least one air gap is located between adjacent plugs on the same horizontal plane, the bottom of the at least one air gap is higher than the bottom surface of the plugs located on both sides thereon, the top of the at least one air gap is lower than the top surface of the plug, and the top of the at least one air gap is lower than the top surface of the dielectric layer between the adjacent plugs on the same horizontal plane.
12. A semiconductor device, characterized in that, include: The substrate includes a first region and a second region; A capacitor structure is located on the first region; Multiple metal interconnect structures are spaced apart from each other in the horizontal direction and stacked on the second region in the vertical direction. Each metal interconnect structure includes a metal layer and a conductive plug located on the metal layer. A multilayer dielectric layer is provided between adjacent metal interconnect structures located on the same horizontal plane, and at least one air gap is provided within the dielectric layer; A metal oxide layer covers the inner surface of the air gap.
13. The semiconductor device as claimed in claim 12, characterized in that, The bottom of the air gap between adjacent metal interconnect structures on the same horizontal plane is lower than the top surface of the metal layer in the metal interconnect structures on both sides of it, and higher than the bottom surface of the metal layer, while the top of the air gap is lower than the top surface of the dielectric layer between the adjacent metal interconnect structures on the same horizontal plane.
14. The semiconductor device as claimed in claim 12, characterized in that, The bottom of all the air gaps is higher than the top surface of the capacitor structure.
15. The semiconductor device as claimed in claim 12, characterized in that, The bottom of the air gap is higher than the top surface of the capacitor structure.
16. The semiconductor device as claimed in claim 12, characterized in that, The bottom of the metal oxide layer is higher than the top surface of the capacitor structure.