Superlattice infrared focal plane detector assembly and method of making same, infrared detector
By optimizing the passivation layer thickness and indium pillar height, and employing reverse soldering interconnect technology, the performance issues caused by dispensing process defects were resolved, thereby improving the overall performance of the superlattice infrared focal plane detector.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 山西创芯光电科技有限公司
- Filing Date
- 2026-03-19
- Publication Date
- 2026-05-19
AI Technical Summary
Existing superlattice infrared detector focal plane array chips are prone to defects during the dispensing process, resulting in filling voids and affecting device performance.
By optimizing the passivation layer thickness and indium pillar height, the dispensing step is eliminated. Inverted soldering interconnect technology is used to fill the gaps with indium pillars. The height and diameter of the indium pillars are designed to meet a specific mathematical relationship to ensure the interconnect effect.
While ensuring the interconnection effect, the impact of dispensing process defects on chip performance was avoided, thus improving the overall performance of the superlattice infrared focal plane detector assembly.
Smart Images
Figure CN121865717B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of infrared detector technology, and in particular to a superlattice infrared focal plane detector assembly and its fabrication method, as well as an infrared detector. Background Technology
[0002] Infrared focal plane array detectors play a vital role in national security, military equipment, and the national economy. Superlattice infrared focal plane array detectors have attracted considerable attention due to their wide spectral response range, high detection sensitivity, fast response speed, low noise level, and good integrability.
[0003] After the existing superlattice infrared detector focal plane array (FPA) chips are fabricated, the chip needs to be flip-soldered to the readout circuitry. Following this flip-soldering, a dispensing process is used to fill the gaps between the indium pillars, increasing chip reliability. Epoxy resin is used for this gap filling; however, defects on the chip surface during manufacturing can cause voids in the resin, ultimately affecting the overall device performance. Therefore, optimizing the dispensing process or developing a new FPA chip fabrication process to replace it is a pressing issue in the manufacturing of infrared FPA detector components. Summary of the Invention
[0004] To address the aforementioned technical issues, this application proposes a superlattice infrared focal plane detector assembly and its fabrication method, as well as an infrared detector. By optimizing the passivation layer thickness and rationally designing the indium pillar height, the existing dispensing step is eliminated, thus avoiding the impact of dispensing process defects on the performance of the superlattice infrared detector focal plane chip.
[0005] The technical solution adopted in this application is as follows: a superlattice infrared focal plane detector assembly, including a focal plane chip end and a readout circuit end interconnected by flip-chip bonding. The focal plane chip end has pixels arranged in an array. A flat chip end passivation layer is disposed on the upper surface of the focal plane chip end. The height of the chip end passivation layer is higher than that of the pixels. A chip end contact hole is opened in the chip end passivation layer corresponding to each pixel. A chip end indium pillar is disposed in the chip end contact hole. A flat readout circuit end passivation layer is disposed on the upper surface of the readout circuit end. A readout circuit end contact hole is opened on the readout circuit end passivation layer. A readout circuit end indium pillar is disposed in the readout circuit end contact hole. The readout circuit end contact hole corresponds one-to-one with the chip end contact hole. The chip end indium pillar and the readout circuit end indium pillar are interconnected.
[0006] Furthermore, one-third of the height of the indium pillars at the chip end extends beyond the passivation layer at the chip end.
[0007] Furthermore, one-third of the height of the indium pillar at the readout circuit end extends beyond the passivation layer at the readout circuit end.
[0008] Furthermore, the height of the indium pillar at the chip end is H1, the diameter of the indium pillar at the chip end is D1, and the diameter of the contact hole at the chip end is D2, which conforms to the following mathematical relationship:
[0009] ;
[0010] Where v is the indium column Poisson's ratio.
[0011] Furthermore, the height of the indium pillar at the readout circuit terminal is H2, the diameter of the indium pillar at the readout circuit terminal is D3, and the diameter of the contact hole at the readout circuit terminal is D4, which conforms to the following mathematical relationship:
[0012] ;
[0013] Where v is the indium column Poisson's ratio.
[0014] Furthermore, the focal plane chip end adopts a type II superlattice epitaxial material, which consists of a GaSb substrate, a GaSb buffer layer, a P-type ohmic contact layer, an absorption region, a barrier layer, and an N-type ohmic contact layer from bottom to top.
[0015] Furthermore, both the N-type ohmic contact layer and the barrier layer are composed of InAs / AlSb.
[0016] Furthermore, both the absorption region and the P-type ohmic contact layer are composed of InAs / GaSb.
[0017] This application also proposes a method for fabricating a superlattice infrared focal plane detector assembly, comprising the following steps:
[0018] S1: The focal plane chip is isolated by ICP etching process to obtain the focal plane chip end;
[0019] S2: Deposit a chip-end passivation layer on the upper surface of the chip end at the focal plane;
[0020] S3: The passivation layer at the chip end is processed using CMP technology, and the surface of the passivation layer at the chip end is polished to a plane;
[0021] S4: The chip-end contact hole is opened on the pixel by photolithography, etching, and resist removal and cleaning.
[0022] S5: The indium pillars at the chip end for flip-chip interconnects are fabricated by photolithography, evaporation, and stripping and cleaning.
[0023] The focal plane chip of the superlattice infrared focal plane detector assembly is prepared through the above steps S1-S5.
[0024] S6: Readout circuit chip fabrication: First, a passivation layer for the readout circuit is deposited at the readout circuit end. Then, the readout circuit contact hole is fabricated on the passivation layer by photolithography, etching, and resist removal cleaning. Finally, the indium pillars for the readout circuit end for flip-soldering interconnect are fabricated by photolithography, evaporation, and stripping cleaning, thereby obtaining the readout circuit chip of the superlattice infrared focal plane detector assembly.
[0025] S7: The focal plane array chip and the readout circuit chip are interconnected by a flip soldering machine to obtain a superlattice infrared focal plane array detector assembly.
[0026] This application also proposes an infrared detector, including a superlattice infrared focal plane detector assembly prepared according to the method for preparing a superlattice infrared focal plane detector assembly described above.
[0027] The advantages of this application over the prior art are as follows: By optimizing the chip structure and designing the indium pillar height, this application can eliminate the influence of the dispensing process on the performance of the superlattice infrared detector focal plane chip while ensuring the flip-soldering interconnect effect, thereby improving the overall performance of the superlattice infrared focal plane detector assembly. Attached Figure Description
[0028] The following description, in conjunction with the accompanying drawings, further illustrates this application:
[0029] Figure 1 A schematic diagram of the focal plane chip-end isolation pixel structure obtained by ICP etching in an embodiment of this application;
[0030] Figure 2 In order to be in Figure 1 A schematic diagram after the passivation layer has been deposited on the substrate;
[0031] Figure 3 To use CMP process Figure 2 A schematic diagram of the passivation layer deposited on the chip surface after it has been polished into a plane;
[0032] Figure 4 This is a schematic diagram showing the contact hole opening process of a pixel after photolithography, etching, and resist removal cleaning.
[0033] Figure 5 To achieve this through photolithography, evaporation, and lift-off processes Figure 4 A schematic diagram showing the indium pillars prepared inside the contact holes;
[0034] Figure 6 The flowchart for reading the indium pillars at the circuit terminals;
[0035] Figure 7 This is a schematic diagram of the structure of a superlattice infrared focal plane detector assembly obtained after flip-flop interconnection.
[0036] Figure 8 This is a schematic diagram of the structure of the type II superlattice epitaxial material used in this application;
[0037] In the figure: 1 is the focal plane chip end, 2 is the pixel, 3 is the chip end passivation layer, 4 is the chip end contact hole, 5 is the chip end indium pillar, 6 is the readout circuit end, 7 is the readout circuit end passivation layer, 8 is the readout circuit end contact hole, 9 is the readout circuit end indium pillar, 11 is the GaSb substrate, 12 is the GaSb buffer layer, 13 is the P-type ohmic contact layer, 14 is the absorption region, 15 is the barrier layer, and 16 is the N-type ohmic contact layer. Detailed Implementation
[0038] like Figures 1 to 8 As shown, this application provides a superlattice infrared focal plane detector assembly, including a focal plane chip terminal 1 and a readout circuit terminal 6 interconnected by flip-chip bonding. The focal plane chip terminal 1 has pixels 2 arranged in an array, and a flat chip terminal passivation layer 3 is disposed on the upper surface of the focal plane chip terminal 1. The height of the chip terminal passivation layer 3 is higher than that of the pixels 2. A chip terminal contact hole 4 is formed in the chip terminal passivation layer 3 corresponding to each pixel 2. A chip terminal indium pillar 5 is disposed in the chip terminal contact hole 4, and one-third of the height of the chip terminal indium pillar 5 extends beyond the chip terminal passivation layer 3. A flat readout circuit terminal passivation layer 7 is disposed on the upper surface of the readout circuit terminal 6. A readout circuit terminal contact hole 8 is formed on the readout circuit terminal passivation layer 7, and a readout circuit terminal indium pillar 9 is disposed in the readout circuit terminal contact hole 8. One-third of the height of the readout circuit terminal indium pillar 9 extends beyond the readout circuit terminal passivation layer 7. The readout circuit terminal contact hole 8 corresponds one-to-one with the chip terminal contact hole 4. The chip terminal indium pillar 5 and the readout circuit terminal indium pillar 9 are interconnected.
[0039] The focal plane chip end 1 uses a type II superlattice epitaxial material, grown by a MBE (Molecular Beam Epitaxy) device. From bottom to top, this epitaxial material consists of a GaSb substrate 11, a GaSb buffer layer 12, a P-type ohmic contact layer 13, an absorption region 14, a barrier layer 15, and an N-type ohmic contact layer 16. The N-type ohmic contact layer 16 and the barrier layer 15 are both composed of InAs / AlSb, while the absorption region 14 and the P-type ohmic contact layer 13 are both composed of InAs / GaSb.
[0040] Let the height of the indium pillar 5 at the chip end be H1, the diameter of the indium pillar 5 at the chip end be D1, and the diameter of the contact hole 4 at the chip end be D2. The following mathematical relationship applies:
[0041] ;
[0042] Where v is the Poisson's ratio of the indium column, which is typically taken as 0.45.
[0043] The above mathematical relationship ensures that one-third of the height of the indium pillar 5 at the chip end can be compressed by the flip-solder interconnect to fill the remaining gap of the contact hole 4 at the chip end, while ensuring the flip-solder interconnect effect.
[0044] Let the height of the indium pillar 9 at the readout circuit terminal be H2, the diameter of the indium pillar 9 at the readout circuit terminal be D3, and the diameter of the contact hole 8 at the readout circuit terminal be D4. The following mathematical relationships apply:
[0045] ;
[0046] Where v is the Poisson's ratio of the indium column, which is typically taken as 0.45.
[0047] The above mathematical relationship ensures that one-third of the height of the indium pillar 9 at the readout circuit end is compressed by the flip-solder interconnect and can just fill the remaining gap of the contact hole 8 at the readout circuit end, while ensuring the flip-solder interconnect effect.
[0048] This application also proposes a method for fabricating a superlattice infrared focal plane detector assembly, comprising the following steps:
[0049] S1: The focal plane chip isolation pixel 2 is fabricated by ICP (Inductively Coupled Plasma) etching process to obtain the focal plane chip end 1;
[0050] S2: Deposit a passivation layer 3 on the upper surface of the focal plane chip end 1. The passivation layer 3 is made of silicon oxide and deposited by PECVD (Plasma-Enhanced Chemical Vapor Deposition) with a thickness of 5 micrometers. The deposition program for the passivation layer 3 is as follows: gas: SiH4, flow rate 120 sccm; N2O, flow rate 700 sccm; deposition temperature 300℃; RF power 20W; chamber pressure 1 Torr; deposition rate 100 nm / min.
[0051] S3: The chip-end passivation layer 3 is processed using CMP (Chemical Mechanical Polishing / Planarization) technology, and the surface of the chip-end passivation layer 3 is polished into a plane.
[0052] S4: The chip end contact hole 4 is opened on the pixel 2 by photolithography, etching, and resist removal and cleaning.
[0053] S5: The indium pillars 5 for flip-chip interconnects are fabricated by photolithography, evaporation, and stripping and cleaning.
[0054] The focal plane chip of the superlattice infrared focal plane detector assembly is prepared through the above steps S1-S5.
[0055] In this embodiment, the height of the indium pillar 5 at the chip end is 3 micrometers.
[0056] S6: Readout Circuit Chip Fabrication: First, a passivation layer 7 for the readout circuit terminal 6 is deposited, with a deposition thickness of 2 micrometers. Then, the readout circuit terminal contact holes 8 are fabricated on the passivation layer 7 using photolithography, etching, and resist removal cleaning. Finally, the indium pillars 9 for flip-flop interconnection of the readout circuit terminal are fabricated using photolithography, evaporation, and stripping cleaning, thereby obtaining the readout circuit chip of the superlattice infrared focal plane detector assembly.
[0057] In this embodiment, the height of the indium pillar 9 at the readout circuit terminal is 3 micrometers.
[0058] S7: Finally, the focal plane chip and the readout circuit chip are interconnected by a flip soldering machine to obtain the superlattice infrared focal plane detector assembly.
[0059] Step S1 specifically includes:
[0060] S11: Epitaxial material growth;
[0061] S12: After the material growth is completed, the surface of the epitaxial material is organically cleaned: the cleaning solvents are acetone, ethanol and isopropanol in sequence, and the cleaning is carried out by water bath heating cleaning at a temperature of 70°C.
[0062] S13: After cleaning, perform mesa etching and hard mask deposition: the hard mask is silicon oxide, the deposition method is PECVD, and the deposition thickness is 600nm.
[0063] S14: Mesa lithography: The photoresist is AZ6130, and the photoresist thickness is 3 micrometers. The exposure dose is 60mJ, and the development time is 30s.
[0064] S15: Mesa hard mask etching: The silicon oxide hard mask is etched using a dry etching method to transfer the photolithography pattern onto the silicon oxide hard mask. The etching gases are CF4 and CHF3, and the etching time is 10 minutes.
[0065] S16: Photoresist Removal Cleaning: Remove the remaining photoresist on the hard mask of the platform. The cleaning solvent is acetone, and the water bath is heated to 70°C for 30 minutes.
[0066] S17: Etching of the mesa epitaxial material to obtain pixel 2: Dry etching of material using silicon oxide as a mask, using an ICP etching device, etching gases of Cl2, BCl3, and Ar, etching time of 30 min, and etching depth of 3 micrometers.
[0067] Step S4 specifically includes:
[0068] S41: Chip-side contact hole 4-aperture photolithography: Photoresist is AZ6130, photoresist thickness is 3 micrometers. Exposure dose is 90mJ, development time is 30s.
[0069] S42: Chip contact hole 4 opening etching: Dry etching method is used to etch silicon oxide, the etching gas is CF4 and CHF3, and the etching time is 60 min.
[0070] S43: Photoresist Removal Cleaning: Remove the remaining photoresist from the opening area of the chip contact hole 4. The cleaning solvent is acetone, and the cleaning is carried out in a water bath at 70°C for 1 hour.
[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for fabricating a superlattice infrared focal plane detector assembly, characterized in that: Includes the following steps: S1: The focal plane chip isolation pixel (2) is fabricated by ICP etching process to obtain the focal plane chip end (1). S2: Deposit a chip-end passivation layer (3) on the upper surface of the chip end (1) at the focal plane. S3: The chip end passivation layer (3) is processed using CMP process, and the surface of the chip end passivation layer (3) is polished into a plane; S4: The chip end contact hole (4) is opened on the pixel (2) by photolithography, etching, and resist removal and cleaning. S5: The indium pillars (5) for flip-soldering interconnects are fabricated by photolithography, evaporation, stripping and cleaning, wherein one-third of the height of the indium pillars (5) extends beyond the passivation layer (3) at the chip end. The focal plane chip of the superlattice infrared focal plane detector assembly is prepared through the above steps S1-S5. The diameter of the indium pillar (5) at the chip end is D1, and the diameter of the contact hole (4) at the chip end is D2. To ensure that one-third of the height of the indium pillar (5) at the chip end is compressed by the flip-flop interconnect and can fill the remaining gap of the contact hole (4) at the chip end, while ensuring the flip-flop interconnect effect, the two conform to the following mathematical relationship: ； Where v is the indium column Poisson's ratio; S6: Readout Circuit Chip Fabrication: First, a readout circuit passivation layer (7) is deposited on the readout circuit end (6). Then, the readout circuit contact hole (8) is fabricated on the readout circuit passivation layer (7) by photolithography, etching, and resist removal cleaning. Finally, the indium pillar (9) for flip-soldering interconnect is fabricated by photolithography, evaporation, and stripping cleaning, thereby obtaining the readout circuit chip of the superlattice infrared focal plane detector assembly. One-third of the height of the indium pillar (9) extends beyond the readout circuit passivation layer (7). The diameter of the indium pillar (9) is D3, and the diameter of the readout circuit contact hole (8) is D4. To ensure that one-third of the height of the indium pillar (9) is compressed by the flip-soldering interconnect and can fill the remaining gap of the readout circuit contact hole (8), and to ensure the flip-soldering interconnect effect, the two conform to the following mathematical relationship: ； Where v is the indium column Poisson's ratio; S7: The focal plane array chip and the readout circuit chip are interconnected by a flip soldering machine to obtain a superlattice infrared focal plane array detector assembly.
2. A superlattice infrared focal plane detector assembly prepared by the preparation method described in claim 1, comprising a focal plane chip end (1) and a readout circuit end (6) interconnected by flip-flop bonding, wherein the focal plane chip end (1) has pixels (2) arranged in an array, characterized in that: A flat passivation layer (3) is provided on the upper surface of the focal plane chip end (1). The height of the passivation layer (3) is higher than that of the pixel (2). A chip contact hole (4) is provided in the passivation layer (3) corresponding to each pixel (2). A chip indium pillar (5) is provided in the chip contact hole (4). A flat passivation layer (7) is provided on the upper surface of the read circuit end (6). A read circuit contact hole (8) is provided on the passivation layer (7). A read circuit indium pillar (9) is provided in the read circuit contact hole (8). The read circuit contact hole (8) corresponds one-to-one with the chip contact hole (4). The chip indium pillar (5) and the read circuit indium pillar (9) are interconnected.
3. The superlattice infrared focal plane detector assembly according to claim 2, characterized in that: The focal plane chip end (1) adopts a type II superlattice epitaxial material, which consists of GaSb substrate (11), GaSb buffer layer (12), P-type ohmic contact layer (13), absorption region (14), barrier layer (15) and N-type ohmic contact layer (16) from bottom to top.
4. The superlattice infrared focal plane detector assembly according to claim 3, characterized in that: The N-type ohmic contact layer (16) and the barrier layer (15) are both composed of InAs / AlSb.
5. The superlattice infrared focal plane detector assembly according to claim 4, characterized in that: The absorption region (14) and the P-type ohmic contact layer (13) are both composed of InAs / GaSb.
6. An infrared detector, characterized in that: The superlattice infrared focal plane detector assembly is prepared by the method described in claim 1.