MOS device substrate concentration monitoring structure, monitoring chip and monitoring method

Abstract

The invention provides an MOS device substrate concentration monitoring structure, a monitoring chip and a monitoring method, the monitoring structure comprises at least one group of test units, each test unit comprises a first well region and a second well region which are adjacently arranged, the doping types of the first well region and the second well region are different, a first MOS structure and a second MOS structure are arranged in the first well region at intervals, and the first MOS structure and the second MOS structure are arranged in the second well region at intervals. In the first MOS structure, a first active region and a first grid electrode are respectively connected with a first metal layer; the second MOS structure comprises a second active region, a second grid electrode and a second metal layer, the second active region is connected with the second metal layer, and the second grid electrode is not connected with top metal in the second metal layer; the distance between the first active region and the second well region is the same as the distance between the second active region and the second well region, and the structures of the first active region and the second active region, the first grid electrode and the second grid electrode, and the first metal layer and the second metal layer are respectively the same. According to the invention, the accuracy of substrate concentration monitoring is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor design and manufacturing technology, and in particular relates to a substrate concentration monitoring structure, monitoring chip and monitoring method for MOS devices. Background Technology

[0002] As technology continues to evolve and chip design dimensions shrink, smaller spacing places higher demands on the control of photoresist consumption and the monitoring of device WPE (Well Proximity Effect). Therefore, these effects are receiving increasing attention. The principle of WPE is that during the well ion implantation process, ions are scattered and reflected at the photoresist boundaries and sides. These ions penetrate the silicon surface, causing differences in doping concentration near the well boundary. The doping concentration near the well boundary is non-uniform, varying with distance from the boundary; the closer to the boundary, the higher the concentration. This non-uniform substrate concentration causes differences in the threshold voltage Vt and saturation current Id of semiconductor devices. Figure 1 Part a and Figure 1 Part b is a schematic diagram of the WPE effect. Figure 2 This is a schematic diagram showing the change in the threshold voltage of an actual device as a function of the distance between the well boundary and the active region.

[0003] Currently, one method for monitoring this phenomenon is traditional current and voltage monitoring based on the device (such as monitoring threshold voltage, saturation current, and leakage current). According to the principle behind this effect, changes in the threshold voltage are mainly caused by variations in substrate doping concentration. However, the factors influencing the threshold voltage are complex, including gate oxide layer thickness, substrate doping concentration, oxide layer positive charge, and the difference in gold half-work function. Especially for small feature-size devices, the short-channel effect also plays a role, thus the accuracy of substrate concentration monitoring is not high.

[0004] Another approach is to analyze the surface using scanning capsule microscopy (SCM), a surface analysis tool that reveals the microstructure and morphology of a material's surface. This method uses different grayscale levels after slicing to visualize the surface's contours and doping distribution. While this method can also be used for qualitative analysis, quantitative analysis is more challenging and requires a longer characterization period.

[0005] Therefore, a substrate concentration monitoring structure and testing method are needed to improve the accuracy of substrate concentration monitoring and thus quickly monitor the impact of doping concentration on devices. Summary of the Invention

[0006] To address all or part of the problems in the prior art, this application provides a MOS device substrate concentration monitoring structure, monitoring chip, and monitoring method to reduce the influence of other variables and analyze and monitor the changes in MOS device substrate concentration caused by the process.

[0007] To achieve the above objectives, this application provides a substrate concentration monitoring structure for a MOS device, comprising: at least one set of test units, each test unit including an adjacent first well region and a second well region, wherein the first well region and the second well region have different doping types, and a first MOS structure and a second MOS structure are arranged at an interval in the first well region. The first MOS structure includes a first active region, a first gate, and a first metal layer, wherein the first active region and the first gate are respectively connected to the first metal layer; The second MOS structure includes a second active region, a second gate, and a second metal layer. The second active region is connected to the second metal layer, and the second gate is not connected to the top metal layer in the second metal layer. The distance between the first active region and the second well region is the same as the distance between the second active region and the second well region. The structures of the first active region and the second active region, the first gate and the second gate, and the first metal layer and the second metal layer are the same, respectively.

[0008] In some embodiments, in the first MOS structure, the first gate is connected to the scan voltage through the first metal layer, and the first active region is connected to the test pad through the first metal layer for collecting current signals. In the second MOS structure, the second metal layer above the second gate is connected to the scan voltage, and the second active region is connected to the test pad through the second metal layer to collect current signals.

[0009] In some embodiments, the first metal layer includes an M0 layer and an M1 layer, and the first active region and the first gate are connected to the M1 layer through the M0 layer and a via, respectively. The second metal layer includes an M0 layer and an M1 layer. The second active region is connected to the M1 layer in sequence through the M0 layer and a via. The second gate is not connected to the M1 layer.

[0010] In some embodiments, the test unit further includes a third well region, the third well region having the same doping type as the second well region, and the first well region being disposed between the second well region and the third well region; the distance between the first active region and the third well region is the same as the distance between the second active region and the third well region.

[0011] In some embodiments, the MOS device substrate concentration monitoring structure includes multiple sets of test units, including: Test structures with the same design parameters, and / or at least one test structure with different design parameters; wherein the design parameters include: active region size, distances between the four boundaries of the active region and the well region, and doping concentration of the well region.

[0012] This application also provides a monitoring chip for the substrate concentration of a MOS device, comprising: the MOS device substrate concentration monitoring structure as described above.

[0013] This application also provides a method for monitoring the substrate concentration of a MOS device, applied to a MOS device substrate concentration monitoring structure as described above or a MOS device substrate concentration monitoring chip as described above, comprising the following steps: In the test unit, the channel capacitance value of the first MOS structure is determined based on the total capacitance of the first MOS structure and the second MOS structure; Obtain the fitting relationship between the channel doping concentration and capacitance of a MOS device; Based on the fitting relationship and the channel capacitance value of the first MOS structure, data processing is performed to obtain the doping concentration of the first MOS structure.

[0014] In some embodiments, determining the channel capacitance value of the first MOS structure based on the total capacitance of the first MOS structure and the second MOS structure includes: Based on the first capacitance value obtained by capacitance testing of the first MOS structure, the total capacitance of the first MOS structure is determined; the total capacitance includes channel capacitance, mid-section capacitance, and rear-section capacitance. The downstream capacitance of the second MOS structure is determined based on the second capacitance value obtained by capacitance testing of the second MOS structure. The channel capacitance of the first MOS structure is determined based on the total capacitance of the first MOS structure and the capacitance of the latter part of the second MOS structure.

[0015] In some embodiments, the fitting relationship between the channel doping concentration and capacitance of the MOS device includes: The relationship between the channel capacitance of a MOS device and the applied gate scan voltage.

[0016] In some embodiments, the fitting relationship between the channel doping concentration and capacitance of the MOS device is the Mott-Schottky equation. Then, the data processing based on the fitting relationship and the channel capacitance value of the first MOS structure to obtain the doping concentration of the first MOS structure includes: Plot the channel capacitance of the MOS device on the ordinate and the corresponding gate scan voltage on the abscissa to obtain the relationship curve; Based on the aforementioned relationship curve, determine the slope of the curve; The doping concentration of the MOS device is calculated based on the slope of the curve, the channel parameters of the MOS device, and the contact area.

[0017] The aforementioned MOS device substrate concentration monitoring structure includes at least one set of test units. Each test unit comprises an adjacent first well region and a second well region, with different doping types. A first MOS structure and a second MOS structure are arranged at an interval within the first well region. The first MOS structure includes a first active region, a first gate, and a first metal layer, with the first active region and the first gate respectively connected to the first metal layer. The second MOS structure includes a second active region, a second gate, and a second metal layer, with the second active region connected to the second metal layer. The second gate is not connected to the top metal layer of the second metal layer. Furthermore, since the structures of the first and second active regions, the first and second gates, and the first and second metal layers are identical, and the distance between the first and second active regions is the same as the distance between the second active region and the second well region, the downstream capacitances of the first and second MOS structures are identical. Therefore, the channel capacitance of the first MOS structure and the substrate doping concentration at the corresponding channel capacitance can be calculated using the first and second MOS structures. This enables analysis of substrate concentration parameters based on structural differences, improving the accuracy of substrate concentration monitoring. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 Part a and Figure 1 Part b is a schematic diagram of the WPE effect in related technologies.

[0020] Figure 2 This is a schematic diagram illustrating the variation of the threshold voltage of an actual device in related technologies with the distance from the well boundary to the active region.

[0021] Figure 3 A schematic diagram of a MOS device substrate concentration monitoring structure provided in an embodiment of this application (the second MOS structure is not shown).

[0022] Figure 4 for Figure 3A schematic diagram of the substrate concentration monitoring structure for the provided MOS device (the first MOS structure is not shown).

[0023] Figure 5 This is a schematic diagram of a MOS device substrate concentration monitoring structure provided in an embodiment of this application. Detailed Implementation

[0024] The foregoing and other technical contents, features, and effects of this application will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the scope of this application.

[0025] The Well Proximity Effect (WPE) principle states that during the well ion implantation process, ions are scattered and reflected at the photoresist boundaries and sides, allowing them to penetrate the silicon surface and creating a difference in doping concentration near the well boundary. Typically, the substrate doping concentration near the well boundary is non-uniform, and this concentration has various impacts on the threshold voltage, leakage current, and capacitance characteristics of MOS devices. With the continuous miniaturization of chip designs, the monitoring of substrate doping concentration in MOS devices faces increasingly stringent requirements.

[0026] This application provides a substrate concentration monitoring structure for MOS devices. The test structure provided can be applied to quality control, reliability analysis, performance optimization, and fault analysis research in semiconductor manufacturing processes, including but not limited to process monitoring in logic, high voltage, memory, analog, RF, and sensor technologies. By monitoring and analyzing the substrate concentration of MOS devices, process parameters can be optimized, significantly improving device performance, reliability, and manufacturing yield, thereby promoting the design, manufacturing, and application of MOS devices.

[0027] Specifically, such as Figure 3 and Figure 4 As shown, the MOS device substrate concentration monitoring structure provided in this application includes at least one set of test units. When multiple sets of test units are configured, they can be distributed at different locations on the substrate. By combining electrical parameters for data analysis, a wider range of doping concentration distribution can be monitored. Each test unit includes an adjacent first well region and a second well region, wherein the first well region and the second well region have different doping types. For example, the first well region is n-type doped, and the second well region is p-type doped, or vice versa. A first MOS structure and a second MOS structure are arranged at an interval in the first well region, with a certain distance between the two MOS structures to ensure the independence and accuracy of subsequent electrical test results.

[0028] In this embodiment, the first MOS structure includes a first active region AA, a first gate, and a first metal layer. The first active region AA and the first gate are respectively connected to the first metal layer. In some embodiments, the first active region AA and the first gate can be connected to the first metal layer through a contact hole CT. In other embodiments, the first metal layer includes an M0 layer and an M1 layer. The first active region AA and the first gate are connected to the M1 layer sequentially through the M0 layer and a via V0, respectively, to connect the first active region AA and the first gate to the test. A first source region and a first drain region are formed on the first active region AA. In some embodiments, sidewalls (spacers) are deposited on both sides of the first gate. In the first MOS structure, the first gate is connected to the scan voltage through the first metal layer. The first source region and the first drain region in the first active region AA are fixed at the same potential (generally 0V) and connected to the test pad through the first metal layer to collect the current signal, thereby allowing the calculation of the first capacitance value. Specifically, regarding the collected current signals... Time of progress t The integral is used to calculate the charge. Then according to the scanning voltage With charge Based on the relationship, the first capacitance value corresponding to the first MOS structure is calculated. The calculation formula is as follows: In this embodiment, the first capacitance value is measured through the above test. The total capacitance of the first MOS structure, including the channel capacitance. Mid-section capacitor and the downstream capacitor Among them, channel capacitance The capacitance between the first gate and the channel region in the first MOS structure, and the middle section capacitance. Including the capacitance between the first gate and the first active region AA source-drain. The capacitance between the first metal layer and the first gate and the over-coverage capacitance of the first gate Rear capacitor Including the capacitance between metal lines in the first metal layer .

[0029] In this embodiment, the second MOS structure includes a second active region AA, a second gate, and a second metal layer. The second active region AA is connected to the second metal layer, and a second source region and a second drain region are formed on the second active region AA. In some embodiments, sidewalls (spacers) are deposited on both sides of the second gate. In some embodiments, the second active region AA can be connected to the second metal layer through a contact via CT. In other embodiments, the second metal layer includes an M0 layer and an M1 layer, and the second active region AA is connected to the M1 layer sequentially through the M0 layer and a via, so as to connect the first active region AA and the second metal layer above the first gate for testing.

[0030] Unlike the first MOS structure, in the second MOS structure, the second gate is not connected to the top metal layer of the second metal layer. Specifically, the second metal layer may include one or more metal layers. When multiple metal layers are included, the connection between the second gate and the top metal layer is simply disconnected. This application does not limit the specific structure. For example, when the second metal layer includes M0 and M1 layers, the second gate is not connected to the M1 layer. Specifically, there may be no connection structure between the second gate and the M1 layer, or only the M0 layer may be provided without a via, or only a via may be provided without M0, as long as the connection between the second gate and the M1 layer is disconnected. In the second MOS structure, the second metal layer above the second gate is connected to a scanning voltage. The second source region and the second drain region in the second active region AA are fixed at the same potential (generally 0V), and test pads are connected through the second metal layer to collect current signals, thereby allowing the calculation of the second capacitance value of the second MOS structure. Specifically, regarding the collected current signals... Time of progress t The integral is used to calculate the charge. Then according to the scanning voltage With charge Based on the relationship, the second capacitance value corresponding to the second MOS structure is calculated. The calculation formula is as follows: In this embodiment, the second capacitance value is measured through the above test. This represents the total capacitance of the second MOS structure. Since the second gate in the second MOS structure is not connected to the top metal layer of the second metal layer, when a scanning voltage is applied to the second metal layer above the second gate, no voltage is applied to the second gate, thus allowing the measurement of the second capacitance value. The capacitance between metal lines in the second metal layer of the metal line That is, the capacitor in the latter part.

[0031] In addition, in this embodiment, the first active region AA and the second active region AA, the first gate and the second gate, and the first metal layer and the second metal layer have the same structure, which ensures that the two MOS structures are consistent in other structural arrangements except for the connection settings of the second gate and the second metal layer, thereby making the first MOS structure and the second MOS structure consistent in terms of the back-end capacitance characteristics.

[0032] In this embodiment, when the first capacitance value corresponding to the first MOS structure is determined... (including channel capacitance) Mid-section capacitor and the downstream capacitor ) and the second capacitance value of the second MOS structure (including downstream capacitors) After that, since the first MOS structure and the second MOS structure have the same capacitance in the latter part, the channel capacitance of the first MOS structure can be calculated. and middle section capacitor The sum is as follows: In this embodiment, within the test unit, since the doping concentration near the well boundary varies with distance from the well boundary, the first MOS structure and the second MOS structure are disposed in the first well region, and the second well region is adjacent to the first well region but has a different doping type than the first well region. Therefore, to avoid the influence of process deviations on the measurement results and to ensure the consistency of substrate concentration between the first MOS structure and the second MOS structure, the distance d between the first active region AA and the second well region in the first MOS structure and the second MOS structure is set to be the same as the distance d between the second active region AA and the second well region.

[0033] In this embodiment, based on the channel capacitance electrical data of the first MOS structure, the fitting relationship between the channel doping concentration and capacitance of the MOS device can be analyzed, and then the substrate doping concentration of the MOS device can be calculated. Specifically, when the channel capacitance of the first MOS structure is obtained... and middle section capacitor After summing, for the middle section capacitance of the first MOS structure Due to the doping concentration in the substrate channel region Primarily affected by trap ion diffusion near the channel, the parasitic capacitances of the first gate, the first metal layer, and the first active region AA source / drain significantly influence the doping concentration in the substrate channel region. The impact is minimal. After subtracting the downstream capacitor from the total capacitance measured using the second MOS structure, the mid-section capacitance is negligible. The channel capacitance of the first MOS structure is also negligible. and middle section capacitor The sum is approximately equal to the channel capacitance of the first MOS structure. .

[0034] like Figure 5 As shown, in some embodiments, based on any of the above embodiments, the test unit further includes a third well region, the doping type of which is the same as that of the second well region, and the first well region is disposed between the second well region and the third well region; the distance between the first active region and the third well region is the same as the distance between the second active region and the third well region. For example, the first well region is an N-well, and the second and third well regions are P-wells. By introducing a third well region with the same doping type as the second well region, and with the first well region located between the second and third well regions, a sandwich structure can be provided. Simultaneously, by setting the distance between the first active region and the third well region to be the same as the distance between the second active region and the third well region, the consistency of substrate concentration between the first MOS structure and the second MOS structure in the sandwich structure is ensured. By placing both sides of the first MOS structure and the second MOS structure near the well boundaries of different doping types, the test structure is made closer to the actual process environment of the MOS device, reducing the impact of process deviations and stability on the test results, thereby improving the accuracy of doping concentration monitoring.

[0035] Of course, in other embodiments, the MOS device substrate concentration monitoring structure may include multiple sets of test units, including: test structures with the same design parameters, and / or at least one test structure with different design parameters; wherein, the design parameters include: the size of the active region AA, the distance d between the four boundaries of the active region AA and the well region, and the doping concentration of the well region.

[0036] It is understandable that different designs of experiments (DOEs) can be performed based on these design parameters according to different application scenarios. For example, in actual testing, the size of the active region AA, the distances d (space X1 / X2 / Y1 / Y2) between the four boundaries of the active region AA and the boundaries of the well region, and the doping concentration of the well region (such as light doping or heavy doping processes) can be combined to obtain richer and clearer test results by changing different experimental variables, thus monitoring the substrate doping concentration of MOS devices under different application scenarios. Furthermore, since the accuracy of the testing machine in measuring capacitance is around 1pF, a larger array can be used to increase the strength of the received capacitance signal in order to ensure monitoring accuracy and increase capacitance monitoring efficiency. In some embodiments, the test unit includes a first well region, a second well region, a third well region, a fourth well region, and a fifth well region. The first well region has a different doping type than the second well region, and the second, third, fourth, and fifth well regions have the same doping type as the second well region. The first well region is disposed between the second, third, fourth, and fifth well regions. The first well region is disposed between the second and third well regions. The distance between the first active region and the third well region is the same as the distance between the second active region and the third well region. The distance between the first active region and the fourth well region is the same as the distance between the second active region and the fourth well region. The distance between the first active region and the fifth well region is the same as the distance between the second active region and the fifth well region. Thus, multiple sets of test units form a four-boundary (top and bottom, left and right) spacing structure, reflecting the influence of experimental variables (such as the well boundary to the active region AA boundary) on multiple active regions AA.

[0037] The aforementioned MOS device substrate concentration monitoring structure includes at least one set of test units. Each test unit comprises an adjacent first well region and a second well region, with the first and second well regions having different doping types. A first MOS structure and a second MOS structure are arranged at an interval within the first well region. The first MOS structure includes a first active region AA, a first gate, and a first metal layer, with the first active region AA and the first gate respectively connected to the first metal layer. The second MOS structure includes a second active region AA, a second gate, and a second metal layer, with the second active region AA connected to the second metal layer. The second gate is not connected to the top metal layer of the second metal layer. Furthermore, since the structures of the first active region AA and the second active region AA, the first gate and the second gate, and the first metal layer and the second metal layer are the same, and the distance d between the first active region AA and the second well region is the same as the distance d between the second active region AA and the second well region, the back-end capacitance of the first MOS structure and the second MOS structure are the same. Therefore, by measuring the capacitance of the first MOS structure and the second MOS structure, the channel capacitance of the first MOS structure and the substrate doping concentration under the corresponding channel capacitance can be calculated and processed, realizing the analysis of substrate concentration parameters based on structural differences and improving the accuracy of substrate concentration monitoring.

[0038] This application also provides a MOS device substrate concentration monitoring chip, comprising: the MOS device substrate concentration monitoring structure described in any of the embodiments above. The solution provided by this monitoring chip includes the implementation schemes described in the above-described MOS device substrate concentration monitoring structure, and will not be repeated here.

[0039] This application also provides a method for monitoring the substrate concentration of a MOS device, applicable to the MOS device substrate concentration monitoring structure or the MOS device substrate concentration monitoring chip described above in any of the embodiments above. Where the specific details of the MOS device substrate concentration monitoring structure in this embodiment are not mentioned, please refer to the corresponding content in the above embodiments. The method for monitoring the substrate concentration of a MOS device includes the following steps S101-S103.

[0040] Step S101: In the test unit, the channel capacitance value of the first MOS structure is determined based on the total capacitance of the first MOS structure and the second MOS structure.

[0041] In this embodiment, a MOS device substrate concentration monitoring structure or a monitoring chip including such a MOS device substrate concentration monitoring structure is provided. The MOS device substrate concentration monitoring structure includes: multiple sets of test units, each test unit including a first well region and a second well region arranged adjacent to each other, the first well region and the second well region having different doping types, and a first MOS structure and a second MOS structure arranged at intervals in the first well region.

[0042] In some embodiments, determining the channel capacitance value of the first MOS structure based on the total capacitance of the first MOS structure and the second MOS structure includes: First, the total capacitance of the first MOS structure is determined based on the first capacitance value obtained from capacitance testing. The first MOS structure includes a first active region AA, a first gate, and a first metal layer. The first active region AA and the first gate are respectively connected to the first metal layer. The first gate receives a scan voltage through the first metal layer, and the first active region AA is connected to test pads through the first metal layer to collect current signals, thereby allowing the calculation of the first capacitance value. Including channel capacitance Mid-section capacitor and the downstream capacitor Then, based on the second capacitance value obtained through capacitance testing of the second MOS structure, which includes a second active region AA, a second gate, and a second metal layer, the second active region AA is connected to the second metal layer, and the second gate is not connected to the top metal layer of the second metal layer. This allows for the determination of the downstream capacitance of the second MOS structure. The second metal layer above the second gate is connected to the scan voltage, and the second active region AA is connected to the test pad through the second metal layer to collect current signals, thereby allowing the calculation of the second capacitance value. Including the downstream capacitor .

[0043] The distance d between the first active region AA and the second well region is the same as the distance d between the second active region AA and the second well region. The structures of the first active region AA and the second active region AA, the first gate and the second gate, and the first metal layer and the second metal layer are identical, thereby ensuring that the substrate concentration and downstream capacitance characteristics of the first MOS structure and the second MOS structure are consistent. The first capacitance value of the first MOS structure is measured. (i.e., total capacitance) and the second capacitance value of the second MOS structure. (i.e., the downstream capacitor), calculate and determine the channel capacitance value of the first MOS structure.

[0044] Step S102: Obtain the fitting relationship between the channel doping concentration and capacitance of the MOS device.

[0045] In this embodiment, the concentration of the first MOS structure substrate is... N d Directly affects its channel capacitance Channel doping concentration and channel capacitance The relationship between them can be analyzed by fitting experimental data or mathematical models. Typically, a suitable mathematical model can be selected to fit the measured experimental data, and the fitted relationship can then be used for data processing. For example, based on the fitted relationship, given a measured channel capacitance value, the corresponding channel doping concentration can be deduced.

[0046] In some embodiments, the fitting relationship between the channel doping concentration and capacitance of the MOS device includes the relationship between the channel capacitance of the MOS device and the applied gate scanning voltage. Specifically, when the gate scanning voltage increases, the conductivity of the channel increases, the carrier concentration increases, and thus the channel capacitance increases. Therefore, the fitting relationship between the channel doping concentration and capacitance can be established by the relationship between the channel capacitance of the MOS device and the applied gate scanning voltage.

[0047] Step S103: Based on the fitting relationship and the channel capacitance value of the first MOS structure, perform data processing to obtain the doping concentration of the first MOS structure.

[0048] In this embodiment, based on multiple test units, once the fitting relationship between the channel doping concentration and capacitance of the MOS device is determined, the doping concentration of the first MOS structure can be obtained by substituting the calculated channel capacitance value of the first MOS structure into the test unit. This enables quantitative analysis of the substrate doping concentration of the MOS device and provides quantitative feedback for the process.

[0049] In some embodiments, in a MOS device, the channel doping concentration directly affects the semiconductor capacitance. The fitting relationship between the channel doping concentration and capacitance of a MOS device can be represented by the Mott-Schottky equation, a mathematical model characterizing the relationship between the space charge layer capacitance and potential of a semiconductor material. Through the Mott-Schottky equation, the fitting relationship between the channel doping concentration and capacitance can be obtained, thereby achieving precise measurement and control of the doping concentration. The Mott-Schottky equation is shown below: In the above formula, Channel capacitance; V is the barrier height, i.e., the energy difference from the Fermi level of the semiconductor to the conduction band bottom or valence band top at the metal-semiconductor interface; V is the scanning voltage; K is the Boltzmann constant. 8.617× (eV / K); T is the temperature, taken as room temperature 300K; q Elementary charge 1.602176634× C, fixed value); The dielectric constant is taken as in this embodiment. , The vacuum permittivity, F / cm; A is the area of ​​the physical overlap region that forms an effective capacitive coupling between the gate and the channel; This represents the doping concentration of the channel.

[0050] When the fitting relationship between the channel doping concentration and capacitance of a MOS device is the Mott-Schottky equation, the data processing based on the fitting relationship and the channel capacitance value of the first MOS structure to obtain the doping concentration of the first MOS structure includes: steps S1031-S1033.

[0051] Step S1031: Plot the relationship curve by plotting the channel capacitance of the MOS device on the vertical axis and the corresponding gate scan voltage on the horizontal axis.

[0052] In this embodiment, the first capacitance value of the first MOS structure can be measured. The second capacitance value of the second MOS structure The channel capacitance value of the first MOS structure was calculated and determined. Multiple sets of channel capacitance values ​​for the first MOS structure and their corresponding scanning voltages were recorded to form an experimental dataset. The relationship curve was obtained by plotting the experimental dataset.

[0053] Step S1032: Determine the slope of the curve based on the relationship curve.

[0054] Step S1033: The doping concentration of the MOS device is calculated based on the slope of the curve, the channel parameters of the MOS device, and the area of ​​the physical overlap region that forms an effective capacitive coupling between the gate and the channel.

[0055] In this embodiment, the relationship curve is the Mott-Schottky equation, analyzed in the reverse bias region of the MOS device. The slope of the curve related to voltage is denoted as m (unit: voltage). / Combining the Mott-Schottky equation, we can obtain the formula for calculating the doping concentration: In this embodiment, the basic charge Channel parameters, dielectric constant Substituting the area A of the physical overlap region forming effective capacitive coupling between the gate and the channel, and the slope m of the curve, into the formula for calculating the doping concentration, the doping concentration of the MOS device can be calculated. This allows us to determine the differences in substrate doping concentration for MOS devices under different process conditions.

[0056] Through the above steps, the Mott-Schottky equation provides a theoretical basis for fitting the relationship between channel doping concentration and capacitance in MOS devices. By combining experimental data and mathematical models, an accurate relationship curve can be established. By analyzing the slope of the relationship curve, the calculated doping concentration can be obtained, quantifying the impact of wave phasing (WPE) on different process environments. This provides an important reference for the design, manufacturing, and performance optimization of MOS devices.

[0057] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0058] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A substrate concentration monitoring structure for a MOS device, characterized in that, include: At least one set of test units, each test unit comprising an adjacent first well region and a second well region, wherein the first well region and the second well region have different doping types, and a first MOS structure and a second MOS structure are arranged at intervals in the first well region. The first MOS structure includes a first active region, a first gate, and a first metal layer, wherein the first active region and the first gate are respectively connected to the first metal layer; The second MOS structure includes a second active region, a second gate, and a second metal layer. The second active region is connected to the second metal layer, and the second gate is not connected to the top metal layer in the second metal layer. The distance between the first active region and the second well region is the same as the distance between the second active region and the second well region. The structures of the first active region and the second active region, the first gate and the second gate, and the first metal layer and the second metal layer are the same, respectively.

2. The MOS device substrate concentration monitoring structure according to claim 1, characterized in that, In the first MOS structure, the first gate is connected to the scan voltage through the first metal layer, and the first active region is connected to the test pad through the first metal layer to collect current signals. In the second MOS structure, the second metal layer above the second gate is connected to the scan voltage, and the second active region is connected to the test pad through the second metal layer to collect current signals.

3. The MOS device substrate concentration monitoring structure according to claim 1, characterized in that, The first metal layer includes an M0 layer and an M1 layer, and the first active region and the first gate are connected to the M1 layer through the M0 layer and a via, respectively. The second metal layer includes an M0 layer and an M1 layer. The second active region is connected to the M1 layer in sequence through the M0 layer and a via. The second gate is not connected to the M1 layer.

4. The MOS device substrate concentration monitoring structure according to claim 1, characterized in that, The test unit further includes a third well region, the doping type of the third well region being the same as that of the second well region, and the first well region being disposed between the second well region and the third well region; the distance between the first active region and the third well region is the same as the distance between the second active region and the third well region.

5. The MOS device substrate concentration monitoring structure according to claim 1, characterized in that, Includes multiple test units, including: Test structures with the same design parameters, and / or at least one test structure with different design parameters; wherein the design parameters include: active region size, distances between the four boundaries of the active region and the well region, and doping concentration of the well region.

6. A chip for monitoring substrate concentration in a MOS device, characterized in that, include: The MOS device substrate concentration monitoring structure according to any one of claims 1 to 5.

7. A method for monitoring the substrate concentration of a MOS device, applied to the MOS device substrate concentration monitoring structure as described in any one of claims 1-5 or the MOS device substrate concentration monitoring chip as described in claim 6, characterized in that, Includes the following steps: In the test unit, the channel capacitance value of the first MOS structure is determined based on the total capacitance of the first MOS structure and the second MOS structure; Obtain the fitting relationship between the channel doping concentration and capacitance of a MOS device; Based on the fitting relationship and the channel capacitance value of the first MOS structure, data processing is performed to obtain the doping concentration of the first MOS structure.

8. The method for monitoring the substrate concentration of a MOS device according to claim 7, characterized in that, The step of determining the channel capacitance value of the first MOS structure based on the total capacitance of the first MOS structure and the second MOS structure includes: Based on the first capacitance value obtained by capacitance testing of the first MOS structure, the total capacitance of the first MOS structure is determined; the total capacitance includes channel capacitance, mid-section capacitance, and rear-section capacitance. The downstream capacitance of the second MOS structure is determined based on the second capacitance value obtained by capacitance testing of the second MOS structure. The channel capacitance of the first MOS structure is determined based on the total capacitance of the first MOS structure and the capacitance of the latter part of the second MOS structure.

9. The method for monitoring the substrate concentration of a MOS device according to claim 7, characterized in that, The fitting relationship between the channel doping concentration and capacitance of the MOS device includes: The relationship between the channel capacitance of a MOS device and the applied gate scan voltage.

10. The method for monitoring the substrate concentration of a MOS device according to claim 9, characterized in that, The fitting relationship between the channel doping concentration and capacitance of the MOS device is the Mott-Schottky equation. Therefore, the data processing based on this fitting relationship and the channel capacitance value of the first MOS structure to obtain the doping concentration of the first MOS structure includes: Plot the channel capacitance of the MOS device on the ordinate and the corresponding gate scan voltage on the abscissa to obtain the relationship curve; Based on the aforementioned relationship curve, determine the slope of the curve; The doping concentration of the MOS device is calculated based on the slope of the curve, the channel parameters of the MOS device, and the area of ​​the physical overlap region that forms an effective capacitive coupling between the gate and the channel.

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