Online acquisition circuit and method for SiC MOSFET junction temperature

Abstract

This invention discloses an online junction temperature acquisition circuit for SiC MOSFETs. Connected to the SiC MOSFET under test, it acquires junction temperature. By adding an independent gate peak current acquisition circuit and employing a low-frequency intermittent sampling strategy, the sampling resistor is kept in a non-operating state most of the time, suppressing temperature rise and ensuring the stability of the sampling resistor value. This significantly improves the accuracy of gate peak current acquisition and junction temperature prediction. This invention also discloses an online junction temperature acquisition method for SiC MOSFETs. The online junction temperature acquisition circuit and method provided by this invention solve the self-heating problem of the sampling resistor under high-frequency switching by constructing a gate resistor network and a gate peak current acquisition circuit.

Description

Technical Field

[0001] This invention belongs to the field of power electronic device technology, specifically relating to an online acquisition circuit for SiC MOSFET junction temperature, and also to a method for online acquisition of SiC MOSFET junction temperature. Background Technology

[0002] As a core device of third-generation wide-bandgap semiconductors, silicon carbide metal-oxide-semiconductor field-effect transistors (SiCMOSFETs) have become key devices for achieving high power density and high-efficiency power conversion in the new energy field due to their advantages such as high voltage withstand, high switching frequency, and low conduction loss. They have been used in many extreme operating conditions. However, SiC MOSFET chips are relatively small in size and have low heat capacity. When the junction temperature changes drastically under extreme conditions, the different thermal expansion coefficients of the materials inside the device are prone to interface delamination and bond wire breakage, which seriously affects the reliability of the device and reduces its lifespan. Therefore, real-time and accurate monitoring of the junction temperature of SiC MOSFETs is of great significance for preventing thermal failure, thermal management, and evaluating device lifespan.

[0003] Thermosensitive electrical parameter methods, as a non-invasive junction temperature monitoring method, are currently a hot research topic in power device condition monitoring. Compared with other thermosensitive electrical parameters, gate peak current has advantages such as being unaffected by aging, having fewer coupling parameters, and good junction temperature linearity. Currently, most gate peak current-based monitoring schemes focus on optimizing the design of the acquisition circuit itself, aiming to improve parameter sensitivity and measurement accuracy. These schemes typically use a resistor in the gate circuit as a sampling resistor, acquiring the voltage across the sampling resistor to obtain the gate peak current. However, under high-frequency switching, continuous current acquisition generates power consumption across the sampling resistor, causing it to heat up, changing its resistance value, and severely affecting the acquisition accuracy. Therefore, solving the self-heating effect of the sampling resistor under high-frequency switching and improving the accuracy and reliability of gate peak current acquisition is crucial. Summary of the Invention

[0004] The primary objective of this invention is to provide an online junction temperature acquisition circuit for SiC MOSFETs, which solves the self-heating problem of the sampling resistor under high-frequency switching conditions by constructing a gate resistor network and a gate peak current acquisition circuit.

[0005] The second objective of this invention is to provide a method for online acquisition of SiC MOSFET junction temperature.

[0006] The first technical solution adopted in this invention is a SiC MOSFET junction temperature online acquisition circuit, which is connected to the SiC MOSFET under test for junction temperature acquisition. The circuit includes an FPGA, which has a PWM signal input terminal, a PWM drive signal output terminal, and a data processing terminal. The PWM signal input terminal receives an external PWM1 input signal, the FPGA's PWM drive signal output terminal outputs a PWM2 drive signal, and the FPGA's data processing terminal receives and processes the data output by the acquisition circuit. The FPGA is connected to a gate driver chip and a gate peak current acquisition circuit. The FPGA's PWM drive signal output terminal is connected to the input terminal of the gate driver chip, and the output terminal of the gate peak current acquisition circuit is connected to the FPGA's data processing terminal. Both the gate driver chip and the gate peak current acquisition circuit are electrically connected to a gate resistor network.

[0007] The first technical solution of this invention is also characterized in that,

[0008] The gate resistor network consists of a parallel connection of an on-resistor branch, an off-resistor branch, and a sampling resistor branch. Each parallel branch is composed of a switching element and a resistor element connected in series. The control terminal of the switching element is electrically connected to the control signal output terminal of the FPGA. The right common terminal of the gate resistor network is electrically connected to the gate of the SiC MOSFET under test. The output terminal of the gate driver chip is connected to the left common terminal of the gate resistor network. The input terminal of the gate peak current acquisition circuit is electrically connected to the two ends of the sampling resistor in the gate resistor network.

[0009] The gate peak current acquisition circuit includes a differential operational amplifier U1. The input of differential operational amplifier U1 is connected to both ends of the sampling resistor in the gate resistor network. The output of differential operational amplifier U1 is electrically connected to operational amplifier U2. The negative input of operational amplifier U2 is connected to resistors R1 and R2. The other end of resistor R1 is connected to the bias voltage VEE, and the other end of resistor R2 is connected to the output of amplifier U2. The output of operational amplifier U2 is electrically connected to transconductance operational amplifier U3. The negative input of transconductance operational amplifier U3 is connected to the OUT terminal. The output of operational amplifier U3 is connected to diodes D1 and D2. The other end of diode D2 is connected to field-effect transistor Q1 and resistor R3. Field-effect transistor Q1 is connected to power supply VCC. Field-effect transistor Q1 is also connected to resistor R4 and voltage buffer U4. Resistor R3 is connected to capacitor C1. Voltage buffer U4 is connected to the OUT terminal. The OUT terminal serves as the output of the gate peak current acquisition circuit and is connected to the data processing terminal of the FPGA.

[0010] The second technical solution adopted in this invention is an online acquisition method for SiC MOSFET junction temperature. Specifically, the method involves: receiving the PWM1 signal via an FPGA, identifying its edges and calculating the switching frequency f; the FPGA counting the rising edges of PWM1 and synchronously outputting the PWM2 drive signal to the gate driver chip; when the count value is less than the sampling threshold m, the rising edge of PWM1 selects the turn-on resistor branch and the falling edge switches to the turn-off resistor branch; when the count value reaches the sampling threshold m, the rising edge of PWM1 selects the sampling resistor branch, triggering the gate peak current acquisition circuit to acquire the peak current, and the falling edge still selects the turn-off resistor branch. After acquisition, the counter is reset to zero; the acquisition circuit processes the signal and feeds it back to the FPGA to obtain the junction temperature of the SiC MOSFET under test.

[0011] The second technical solution of the present invention is further characterized in that,

[0012] The sampling resistor in the sampling resistor branch has the same resistance value as the turn-on resistor in the turn-on resistor branch.

[0013] The sampling frequency m is determined through the following steps:

[0014] Maximum allowable sampling frequency: A PWM signal, starting from the switching frequency f of the SiC MOSFET under test and gradually decreasing, is applied to generate a gate current that flows through the gate resistor. The temperature of the sampling resistor in the sampling resistor branch rises, and the temperature change of the sampling resistor is observed using an infrared thermal imager until the temperature rise of the sampling resistor is maintained at ≤3℃. The sampling frequency at this point is the maximum allowable sampling frequency f. max ;

[0015] Minimum allowable acquisition frequency: The SiC MOSFET under test is heated at a rate of 5-10℃ / min, with a temperature range of 25-150℃. Using the junction temperature monitored by an infrared thermal imager as a reference, the junction temperature data is recorded synchronously. The acquisition frequency is gradually increased. When the fit between the acquired junction temperature curve and the reference curve is not less than 95% and the time delay is ≤10ms, the corresponding frequency is the minimum allowable acquisition frequency f. min ;

[0016] The sampling threshold m is an integer greater than 1, and f / f max ≤m≤f / f min Where f is the switching frequency of the SiC MOSFET under test, f=1 / T, and T is the switching period of the PWM1 input signal, which is calculated by the FPGA to identify the interval between the two rising edges of the PWM1 signal. At the same time, m<f, to ensure that the acquisition action interval is within the normal switching period of the SiC MOSFET under test and to suppress the self-heating effect of the sampling resistor.

[0017] The signal processing steps of the gate peak current acquisition circuit are as follows: First, differential operational amplifier U1 receives the differential signal across the sampling resistor, converts the signal, and outputs a single-ended voltage signal. Operational amplifier U2 receives the single-ended voltage signal output from differential operational amplifier U1, adds a negative bias through resistors R1 and R2, and outputs a single-ended voltage signal with the added negative bias. Transconductance operational amplifier U3 receives the single-ended voltage signal with the added negative bias, and utilizes its large output current characteristic to drive the holding capacitor C1 to charge through resistor R3, storing the gate peak signal in the form of charge in capacitor C1, capturing and storing the peak signal. Then, the source follower composed of field-effect transistor Q1 and resistor R4 receives the peak signal stored in C1 and increases the input impedance of voltage buffer U4 to reduce leakage loss of C1 and maintain the amplitude stability of the peak signal. Finally, voltage buffer U4 receives the peak signal stabilized by the source follower, enhances the driving capability of the peak signal, and then feeds the enhanced peak signal back to the data processing terminal of the FPGA through the OUT terminal to provide data for junction temperature calculation.

[0018] During the process of capacitor C1 storing charge, diode D1 simultaneously clamps and protects the voltage across C1, while diode D2 is turned on on the rising edge of the input signal and turned off on the falling edge.

[0019] The beneficial effects of this invention are:

[0020] (1) The SiC MOSFET junction temperature online acquisition circuit and method provided by the present invention, by adding an independent gate peak current acquisition circuit and adopting a low-frequency intermittent sampling strategy, makes the sampling resistor in a non-working state for most of the time, suppressing its temperature rise, thereby ensuring the stability of the sampling resistor value and significantly improving the accuracy of gate peak current acquisition and junction temperature prediction accuracy.

[0021] (2) The SiC MOSFET junction temperature online acquisition circuit and method provided by the present invention uses the same sampling resistor and turn-on resistor to ensure that the turn-on behavior of the device during the acquisition stage is completely consistent with the normal turn-on, thus avoiding the distortion of switching characteristics introduced by sampling. Attached Figure Description

[0022] Figure 1 This is a circuit diagram of the SiC MOSFET junction temperature online acquisition circuit of the present invention;

[0023] Figure 2 This is a circuit diagram of the gate peak current acquisition circuit of the present invention;

[0024] Figure 3 This is a schematic diagram of the intermittent control signal sampling of the present invention;

[0025] Figure 4This is a schematic diagram of the intermittent maximum allowable acquisition frequency of the present invention;

[0026] Figure 5 This is a schematic diagram of the intermittent minimum allowable acquisition frequency of the present invention. Detailed Implementation

[0027] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Example 1

[0029] like Figure 1 As shown, this embodiment provides an online junction temperature acquisition circuit for SiC MOSFETs, which is connected to the SiC MOSFET under test for junction temperature acquisition. The circuit includes an FPGA, which has a PWM signal input terminal, a PWM drive signal output terminal, and a data processing terminal. The PWM signal input terminal receives an external PWM1 input signal, the FPGA's PWM drive signal output terminal outputs a PWM2 drive signal, and the FPGA's data processing terminal receives and processes the data output by the acquisition circuit. The FPGA is connected to a gate driver chip and a gate peak current acquisition circuit. The FPGA's PWM drive signal output terminal is connected to the input terminal of the gate driver chip, and the output terminal of the gate peak current acquisition circuit is connected to the FPGA's data processing terminal. Both the gate driver chip and the gate peak current acquisition circuit are electrically connected to a gate resistor network.

[0030] The PWM signal input terminal of the FPGA is used to receive the PWM1 signal output from the main control MCU or DSP; the gate resistor network is a programmable impedance network composed of multiple independent resistor branches connected in parallel, and each branch is composed of a series structure of switching elements and resistor elements.

[0031] This invention constructs a driver-acquisition dual-mode collaborative architecture with an FPGA as the central hub and a gate resistor network as the execution terminal. The three types of operations—device turn-on, turn-off, and junction temperature acquisition—are mapped to three physically independent resistor branches. Precise control of the branch conduction timing is achieved through the FPGA's internal state machine, ensuring that the acquisition action only momentarily intervenes within a specific switching cycle and completely exits the loop during other periods. This fundamentally avoids the risk of continuous power consumption accumulation in the sampling resistor. Simultaneously, the FPGA's real-time parsing capability for PWM1 signals allows it to generate and align multiple control signals without the need for an external high-precision clock source or complex synchronization circuits, significantly reducing system complexity and hardware cost.

[0032] The working process and principle of this embodiment are as follows: The FPGA continuously monitors the externally input PWM1 signal, starts the internal counter at each rising edge, and determines whether it is currently in the acquisition window. When the acquisition threshold is not reached, the FPGA outputs key1=1, key2=0, and key3=0, turning on the turn-on resistor branch. The gate driver chip applies a positive drive voltage to the SiC MOSFET through this branch to complete the turn-on action. When a falling edge of PWM1 occurs, the FPGA outputs key1=0, key2=1, and key3=0, switches to the turn-off resistor branch, applies a negative drive voltage, and completes the turn-off action. When the count value reaches the preset threshold m, the FPGA outputs key1=0, key2=0, and key3=1 at the next rising edge of PWM1, turning on the sampling resistor branch. At this time, the gate peak current acquisition circuit is connected to the loop to capture the gate current peak value during this turn-on process. Throughout the process, the gate driver chip is always in working state, and only its drive path is dynamically switched with the FPGA control signal to ensure that the device switching behavior is continuous and controllable.

[0033] Example 2

[0034] Based on Example 1, the gate resistor network consists of a parallel connection of an on-resistance branch, a off-resistance branch, and a sampling resistor branch. Each parallel branch is composed of a switching element and a resistor element connected in series. The control terminal of the switching element is electrically connected to the control signal output terminal of the FPGA. The right common terminal of the gate resistor network is electrically connected to the gate of the SiC MOSFET under test. The output terminal of the gate driver chip is connected to the left common terminal of the gate resistor network. The input terminal of the gate peak current acquisition circuit is electrically connected to both ends of the sampling resistor in the gate resistor network to acquire the peak current signal of the gate drive circuit and feed it back to the FPGA.

[0035] The turn-on resistor branch consists of the switching device key1 and the turn-on resistor R. on Formed in series, used for device turn-on; Turn-off resistor branch: composed of switching device key2 and turn-off resistor R off Formed in series for device turn-off; Sampling resistor branch: composed of switching device key3 and sampling resistor R acq Formed in series for junction temperature acquisition;

[0036] The right common terminal of the gate resistor network is a node formed by connecting the ends of all the resistor elements in the three branches away from their respective switching elements. This node is directly electrically connected to the gate of the SiC MOSFET under test. The left common terminal of the gate resistor network is a node formed by connecting the ends of all the switching elements in the three branches away from their respective resistor elements. This node is connected to the output terminal of the gate driver chip, forming a common busbar for the gate drive current. The design of this left common terminal does not introduce additional parasitic inductance and distributed capacitance.

[0037] The FPGA counts based on the rising edge of the PWM1 signal. When the count value has not reached the preset threshold m, it outputs key1=1, key2=0, and key3=0 on each rising edge, turning on the on-resistor branch and turning off the other branches. On each falling edge, it outputs key1=0, key2=1, and key3=0, turning on the off-resistor branch and turning off the other branches. When the count value reaches m, it outputs key1=0, key2=0, and key3=1 on the next rising edge, turning on only the sampling resistor branch and completing one gate peak current acquisition. Subsequently, it outputs key1=0, key2=1, and key3=0 on the falling edge of the same cycle to ensure that the off-resistor path is independent and controllable. After the acquisition is completed, the FPGA's internal counter is cleared and the next round of counting begins. Throughout the entire process, only one branch is in the on state at any given time.

[0038] Example 3

[0039] Based on the above embodiments, such as Figure 2 As shown, this gate peak current acquisition circuit includes a differential operational amplifier U1. The input terminal of the differential operational amplifier U1 is connected to both ends of the sampling resistor in the gate resistor network. The output terminal of the differential operational amplifier U1 is electrically connected to an operational amplifier U2. The negative input terminal of the operational amplifier U2 is connected to resistors R1 and R2. The other end of resistor R1 is connected to the bias voltage VEE, and the other end of resistor R2 is connected to the output terminal of amplifier U2. The output terminal of operational amplifier U2 is electrically connected to a transconductance operational amplifier U3. The negative input terminal of the transconductance operational amplifier U3 is connected to the OUT terminal. The output terminal of operational amplifier U3 is connected to diodes D1 and D2. The other end of diode D2 is connected to a field-effect transistor Q1 and resistor R3. The field-effect transistor Q1 is connected to the power supply VCC. The field-effect transistor Q1 is also connected to resistor R4 and voltage buffer U4. Resistor R3 is connected to capacitor C1. Voltage buffer U4 is connected to the OUT terminal. The OUT terminal serves as the output terminal of the gate peak current acquisition circuit and is connected to the data processing terminal of the FPGA.

[0040] The differential operational amplifier U1 is used to receive the differential voltage signal across the sampling resistor and convert it into a single-ended voltage signal. It features high common-mode rejection ratio, high input impedance, and low offset voltage, and its bandwidth is compatible with the transient response characteristics of the gate current of SiCMOSFET. Its input terminal is directly connected to the two ends of the sampling resistor to achieve the initial extraction of weak gate current signals and avoid the introduction of common-mode noise interference.

[0041] Operational amplifier U2 is a non-inverting amplifier used to apply a negative bias to the single-ended voltage signal output by U1. Its negative input terminal is connected to the reference point through resistor R1. R1 and R2 form a feedback network to achieve the superposition of fixed gain and DC offset. The resistance ratio of R1 and R2 is set according to the required bias amount.

[0042] The transconductance operational amplifier U3 features high output current drive capability, fast settling time, and low input bias current characteristics, such as OPA861 or MAX436. Its negative input terminal is connected to the OUT terminal to form a feedback path, and its positive input terminal receives the biased voltage signal output by U2. U3 linearly converts the input voltage signal into an output current signal and drives capacitor C1 to charge through resistor R3. By utilizing the high current output characteristic of U3, the peak capture time of C1 is shortened, ensuring that charge injection is completed during the rising edge of the gate current.

[0043] Diode D1 is connected between the output of U3 and C1, with its cathode connected to the output of U3 and its anode grounded. It is used to limit the voltage across C1 to not exceed the safety threshold, preventing the subsequent circuit from being damaged due to signal overshoot. D1 is a transient voltage suppressor diode (TVS), such as the SMAJ5.0A series, which has an extremely fast clamping speed and can absorb large instantaneous energy, clamping the voltage within a safe value during overvoltage. The clamping voltage of D1 is set according to the output swing of U3 and the withstand voltage level of the FPGA input, such as +3.3V or +5V.

[0044] Diode D2 is connected between the output of U3 and the gate of MOSFET Q1, with its anode connected to the output of U3 and its cathode connected to the gate of Q1. It is used to turn on during the rising edge of the gate current, so that the output current of U3 is injected into the gate of Q1 through D2 and triggers Q1 to turn on, thereby activating the charging circuit of C1. During the falling edge, D2 is turned off, cutting off the charging path and putting C1 into the holding state. D2 is a high-speed switching diode, such as 1N4148 or BAS16, and its reverse recovery time is less than 1 / 5 of the rise time of the gate current of SiC MOSFET.

[0045] The field-effect transistor Q1 and resistor R4 together form a source follower structure. The field-effect transistor Q1 is an N-channel JFET, with its drain connected to the power supply VCC and its source connected to one end of R4. The other end of R4 is grounded, and the gate is controlled by D2. Q1 is a high input impedance device, which can reduce the leakage current during the holding period of C1, so that the voltage on capacitor C1 can be effectively maintained for a long time. The resistance value of R4 is set according to the transconductance of Q1 and the required source static voltage.

[0046] Capacitor C1 is used to store the charge brought in by the output current of U3 through R3 and realize the peak hold function. Voltage buffer U4 has unity gain, high input impedance, low output impedance and wide bandwidth characteristics. Its input terminal is connected to the source of Q1 and the R4 node, and its output terminal is connected to the OUT terminal.

[0047] U4 isolates and drives the peak voltage of C1 after it has been stabilized by the source follower, improving the signal's load-carrying capacity and ensuring that it is not distorted when connected to the FPGA's internal ADC input channel. Its power supply voltage range covers the peak voltage range of C1 and is compatible with the FPGA input level. The package and layout of U4 are far away from high-frequency interference sources, and power supply decoupling capacitors are added when necessary.

[0048] Resistor R4 and Q1 together form the DC bias path of the source follower. One end of R4 is connected to the source of Q1, and the other end is grounded. R4 is used to set the static operating point of Q1, which affects the amplitude and linearity of the source output voltage. The resistance value of R4 is calculated and determined based on the threshold voltage of Q1, VCC and the required output swing.

[0049] The OUT terminal is the final signal output node of the gate peak current acquisition circuit, and its level range is adapted to the input range of the FPGA's built-in ADC.

[0050] The operation of the gate peak current acquisition circuit is as follows: When the sampling resistor branch is selected by the FPGA, the gate current is generated at the moment the SiC MOSFET under test is turned on. This current flows through the sampling resistor and forms a differential voltage across its terminals. The differential operational amplifier U1 acquires this voltage in real time and outputs a single-ended signal. The operational amplifier U2 superimposes a negative bias on this signal to expand the dynamic range of subsequent processing. The transconductance operational amplifier U3 receives the biased signal and drives the current through the conduction path of diode D2 to quickly charge capacitor C1 during the rising edge, thereby achieving peak capture. D1 synchronously clamps the voltage across C1 to prevent overvoltage damage. After D2 is cut off at the falling edge, C1 stops charging. Its stored charge, under the action of the source follower composed of Q1 and R4, reduces the leakage current of capacitor C1. After the voltage buffer U4 enhances the driving capability, a stable voltage signal is output from the OUT terminal to the FPGA.

[0051] Example 4

[0052] This embodiment provides a method for online acquisition of SiC MOSFET junction temperature, using the SiC MOSFET junction temperature online acquisition circuit provided in the above embodiment, such as... Figure 3 As shown, specifically: the FPGA receives the PWM1 signal, identifies its edges and calculates the switching frequency f. The FPGA counts the rising edges of PWM1 and synchronously outputs the PWM2 drive signal to the gate driver chip. When the count value is less than the sampling threshold m, the rising edge of PWM1 selects the turn-on resistor branch and the falling edge switches to the turn-off resistor branch. When the count value reaches the sampling threshold m, the rising edge of PWM1 selects the sampling resistor branch, triggering the gate peak current acquisition circuit to acquire the peak current. The falling edge still selects the turn-off resistor branch. After acquisition, the counter is cleared. The acquisition circuit processes the signal and feeds it back to the FPGA to obtain the junction temperature of the SiC MOSFET under test.

[0053] More specifically:

[0054] Step 1: Receive the PWM1 signal through the FPGA, identify its edge and calculate the switching frequency f. The FPGA counts the rising edge of PWM1 and synchronously outputs the PWM2 drive signal to the gate driver chip.

[0055] Step 2: When the count value is less than the sampling threshold m, PWM1 selects the turn-on resistor branch on the rising edge and cuts off the turn-off resistor branch on the falling edge.

[0056] The count value is the cumulative number of rising edges of PWM1 detected by the FPGA's internal counter. The initial value is 0, and it increments by 1 each time a rising edge is detected. The sampling threshold m is an integer greater than 1, used to define the trigger period for the sampling action, and its value range satisfies f / f max ≤ m ≤ f / f min , where f max For the maximum allowable sampling frequency, f min The minimum allowable acquisition frequency is obtained through experimental calibration. "Gating" can refer to the FPGA outputting a high level to the control terminal of the corresponding branch's switching element to close the switch, thereby connecting the branch to the gate drive circuit. "Switching in" refers to the FPGA switching the control signal at the falling edge of PWM1, causing the previous conducting branch to open and the target branch to close, thus achieving a smooth switching of the drive path.

[0057] Based on whether the count value is less than m, the GPIO output state of the FPGA is dynamically configured: when the count value is less than m, key1=1, key2=0, and key3=0 are output at the rising edge to turn on the turn-on resistor branch; key1=0, key2=1, and key3=0 are output at the falling edge to turn on the turn-off resistor branch. Dual-edge response is also achieved through a state machine: the FPGA has a built-in finite state machine that triggers the turn-on state at the rising edge, driving key1; and triggers the turn-off state at the falling edge, driving key2. The state transition is strictly constrained by the count value to ensure that only the turn-on and turn-off states switch during non-acquisition cycles. Register mapping can also be used to write the key1, key2, and key3 control words into a specific address space, and the hardware logic automatically completes the edge-control signal mapping and timing alignment.

[0058] When the FPGA detects the first rising edge of PWM1, the count value is set to 1, and key1=1 is output to drive the resistor branch to turn on; when the falling edge of the same cycle arrives, key2=1 is output to drive the resistor branch to turn off, completing the first cycle switching; thereafter, the count value is incremented by 1 for each rising edge; when the count value is 2, 3, ..., m When 1 is selected, the same logic is always executed, that is, the rising edge drives key1 and the falling edge drives key2; throughout the process, key3 always remains 0, and the sampling resistor branch is in a completely isolated state.

[0059] Step 3: When the count value reaches the sampling threshold m, the rising edge of PWM1 selects the sampling resistor branch, triggering the gate peak current acquisition circuit to acquire the peak current. The falling edge still selects the turn-off resistor branch, and the counter is cleared after acquisition.

[0060] In this process, at the instant the sampling resistor branch is turned on, the gate drive current of the SiC MOSFET under test flows through this branch, and a transient voltage drop is generated across the sampling resistor. This voltage drop is captured in real time by the gate peak current acquisition circuit and converted into a peak voltage signal. The falling edge still selects the turn-off resistor branch, indicating that the acquisition action only applies to the turn-on stage, and the turn-off path is not affected, thus maintaining the turn-off behavior. The counter reset operation after acquisition means that after completing this acquisition action, the FPGA resets the count value to 0 so as to enter the counting cycle of the next acquisition cycle.

[0061] Step 4: The acquisition circuit processes the signal and feeds it back to the FPGA to obtain the junction temperature of the SiC MOSFET under test.

[0062] By using FPGA to identify and count the edges of the PWM1 signal, strong timing coupling between the acquisition action and the device switching cycle is achieved. The design of having the same resistance value for the turn-on resistor branch and the sampling resistor branch ensures that the turn-on characteristics at the acquisition time are completely consistent with conventional drives. Relying on an intermittent triggering mechanism—that is, only one acquisition is performed every m turn-on cycles—the average power consumption of the sampling resistor is significantly reduced, suppressing its temperature rise and resistance drift. Combined with designs such as an independent turn-off path throughout and a counter reset after acquisition, a stable and repeatable periodic data acquisition cycle is formed. High-precision, low-latency junction temperature estimation results are output, effectively solving the monitoring error problem caused by the self-heating of the sampling resistor under high-frequency switching, balancing drive performance and monitoring reliability.

[0063] Example 5

[0064] Based on Example 4, this example provides that the sampling resistor of the sampling resistor branch and the turn-on resistor of the turn-on resistor branch have the same resistance value. When the FPGA triggers the sampling action on the rising edge of the m-th PWM1 and outputs a control signal to turn on key3 and turn off key1, the gate drive current path switches from the original turn-on resistor branch to the sampling resistor branch; since R acq With R on With equal resistance values, the equivalent series impedance of the gate circuit at that moment remains unchanged, thus ensuring that the key switching dynamic parameters of the SiC MOSFET, such as the turn-on voltage waveform, gate current rise slope, and drain-source voltage fall time, are completely consistent with those during the normal drive phase.

[0065] Example 6

[0066] Based on Example 5, this example further provides a method for determining the sampling threshold m through the following steps:

[0067] Maximum allowable sampling frequency: A PWM signal, starting from the switching frequency f of the SiC MOSFET under test and gradually decreasing, is applied to generate a gate current that flows through the gate resistor. The temperature of the sampling resistor in the sampling resistor branch rises, and the temperature change of the sampling resistor is observed using an infrared thermal imager until the temperature rise of the sampling resistor is maintained at ≤3℃. The sampling frequency at this point is the maximum allowable sampling frequency f. max .

[0068] Minimum allowable acquisition frequency: The SiC MOSFET under test is heated at a rate of 5–10℃ / min, with a temperature range of 25–150℃. The junction temperature of the device monitored by the infrared thermal imager is used as a reference. The junction temperature data of the acquired data is recorded synchronously. The acquisition frequency is gradually increased. When the fitting degree between the acquired junction temperature curve and the reference curve is not less than 95% and the time delay is ≤10ms, the corresponding frequency is the minimum allowable acquisition frequency fmin.

[0069] The sampling threshold m is an integer greater than 1, and f / f max ≤m≤f / f min Where f is the switching frequency of the SiC MOSFET under test, f = 1 / T, and T is the switching period of the PWM1 input signal, calculated by the FPGA based on the interval between the two rising edges of the PWM1 signal. Simultaneously, m < f to ensure that the acquisition action interval is within the normal switching period of the SiC MOSFET under test, suppressing the self-heating effect of the sampling resistor. After real-time monitoring of the surface temperature change trend of the sampling resistor by an infrared thermal imager and determining whether it has entered a thermal equilibrium state, f is then determined based on the temperature rise value. max The following method is used to determine f. max Based on the set temperature rise threshold of ≤3℃ and the measured ambient temperature benchmark, the system automatically compares whether the average temperature change rate of the sampling resistor approaches zero over N consecutive sampling periods to determine whether thermal equilibrium has been reached, and thus determines the maximum allowable sampling frequency f. max This serves as the lower bound for the sampling threshold m, ensuring that the sampling resistor operates without significant self-heating over long periods.

[0070] like Figure 4As shown, PWM switching signals of different frequencies are applied to a SiC MOSFET module equipped with a drive circuit, allowing the module to operate continuously at each switching frequency for a certain period of time until thermal equilibrium is reached. The temperature of the sampling resistor is monitored using an infrared thermal imager. The frequency of the PWM signal is gradually decreased starting from the switching frequency. At a certain frequency, if the steady-state temperature rise of the sampling resistor (relative to ambient temperature) during the entire operation does not exceed 3°C, the current frequency is considered to be the maximum allowable sampling frequency.

[0071] like Figure 5 As shown, the SiC MOSFET device is actively heated using a heating stage, causing a change in junction temperature. The junction temperature monitored by an infrared thermal imager is used as a reference for the junction temperature change. Simultaneously, the acquisition circuit provided in the above embodiment is used to acquire the gate peak current in real time and convert it into junction temperature information. The acquisition frequency is gradually increased, and the junction temperature curve acquired by this circuit is compared with the junction temperature curve obtained by the infrared thermal imager. When the trends of the two are basically synchronized, the current acquisition frequency is considered to meet the real-time requirements, and this frequency is the minimum allowable acquisition frequency.

[0072] Where the sampling threshold m is an integer greater than 1, and f / f max ≤m≤f / f min Where f is the switching frequency of the SiC MOSFET under test, f=1 / T, and T is the switching period of the PWM1 input signal, which is calculated by the FPGA to identify the interval between the two rising edges of the PWM1 signal. At the same time, m<f, to ensure that the acquisition action interval is within the normal switching period of the SiC MOSFET under test and to suppress the self-heating effect of the sampling resistor.

[0073] Example 7

[0074] Based on the above embodiments, this embodiment provides signal processing steps for the gate peak current acquisition circuit, specifically as follows:

[0075] (1) First, the differential operational amplifier U1 receives the differential signal across the sampling resistor, performs signal conversion processing, and outputs a single-ended voltage signal. The two input terminals of the differential operational amplifier U1 are connected to the two ends of the sampling resistor respectively, converting the small voltage difference generated by the gate peak current flowing through the sampling resistor into a single-ended voltage signal with ground as the reference. The amplitude of the single-ended voltage signal is proportional to the instantaneous value of the gate peak current, providing the basic input for subsequent signal conditioning at each stage.

[0076] (2) Operational amplifier U2 receives the single-ended voltage signal output by differential operational amplifier U1, adds negative bias through resistors R1 and R2, and outputs the single-ended voltage signal after adding negative bias; Operational amplifier U2 adds a controllable negative DC bias voltage on the single-ended voltage signal output by U1 through the negative feedback network formed by R1 and R2, so that the output signal is shifted down as a whole, ensuring that the subsequent transconductance operational amplifier U3 works in the linear region and avoids signal clipping, especially to deal with the current spike or baseline drift that may occur during the gate drive of SiC MOSFET;

[0077] (3) The transconductance operational amplifier U3 receives the single-ended voltage signal after adding negative bias. Utilizing its large output current characteristic, it drives the capacitor C1 to charge through the resistor R3, storing the gate peak signal in the form of charge in the capacitor C1, capturing and storing the peak signal. In this embodiment, the transconductance operational amplifier U3 converts the single-ended voltage signal after negative bias into a driving current in real time, and charges C1 quickly through R3. When the input voltage reaches the peak value, the amount of charge accumulated in C1 reaches the maximum, and the corresponding voltage is the holding value of the peak voltage. This process realizes the instantaneous capture and non-volatile temporary storage of the voltage signal corresponding to the gate peak current.

[0078] (4) The source follower composed of field-effect transistor Q1 and resistor R4 receives the peak signal stored in C1. The source follower reduces the leakage loss of C1 by increasing the input impedance of voltage buffer U4, thereby maintaining the amplitude stability of the peak signal. The source follower takes the voltage across C1 as input and outputs a non-in-phase signal that follows the voltage. Voltage buffer U4 further increases the overall input impedance, reducing the leakage current of C1 to the sub-picoampere level, thereby extending the peak voltage holding time to the millisecond level or more, meeting the requirement of no signal distortion within the FPGA sampling period.

[0079] (5) Finally, the voltage buffer U4 receives the peak signal after it has been stabilized by the source follower, enhances the driving capability of the peak signal, and then feeds the stable peak signal back to the data processing terminal of the FPGA through the OUT terminal to provide effective data for junction temperature calculation.

[0080] The OUT terminal is the standard analog signal interface node between the gate peak current acquisition circuit and the FPGA. In this embodiment, after the voltage buffer U4 completes the final signal shaping and drive enhancement, it sends the stable peak voltage to the FPGA's built-in or external analog-to-digital converter (ADC) through the OUT terminal. The FPGA obtains the digitized peak voltage value and calculates the current junction temperature of the SiC MOSFET under test in real time according to the preset gate peak current-junction temperature calibration relationship model.

[0081] During the process of storing charge in capacitor C1, diode D1 simultaneously clamps and protects the voltage across C1, while diode D2 is turned on at the rising edge of the input signal and turned off at the falling edge. During the charging process of capacitor C1 driven by transconductance operational amplifier U3, when the voltage across C1 rises to the breakdown voltage threshold of diode D1, D1 enters avalanche breakdown state, forming a low-impedance discharge path, guiding excess charge to ground or a reference potential node, thereby limiting the voltage across C1 to not exceed the preset safety limit. During the rising edge of the single-ended voltage signal with added negative bias from operational amplifier U2, U3 outputs a positive drive current, and D2 is forward biased and conducts, allowing current to flow to C1 to complete charging. During the falling edge of the input signal, the output level of U3 falls back or reverses, and D2 is reverse biased and cut off, cutting off the current path between C1 and U3, preventing the charge stored in C1 from being discharged in reverse through U3. This conduction and cutoff behavior is strictly synchronized with the edge transition of the input signal, ensuring that C1 only receives charge injection during the signal rising phase and maintains charge isolation during the falling phase, thereby achieving precise locking and holding of the peak moment.

Claims

1. A SiC MOSFET junction temperature on-line acquisition circuit, connected with a to-be-tested SiC MOSFET for junction temperature acquisition, characterized in that, The system includes an FPGA, which has a PWM signal input terminal, a PWM drive signal output terminal, and a data processing terminal. The PWM signal input terminal receives an external PWM1 input signal, and the FPGA's PWM drive signal output terminal outputs a PWM2 drive signal. The FPGA's data processing terminal receives and processes the data output from the acquisition circuit. The FPGA is connected to a gate driver chip and a gate peak current acquisition circuit. The FPGA's PWM drive signal output terminal is connected to the input terminal of the gate driver chip, and the output terminal of the gate peak current acquisition circuit is connected to the FPGA's data processing terminal. Both the gate driver chip and the gate peak current acquisition circuit are electrically connected to a gate resistor network. The gate resistor network consists of a parallel connection of an on-resistor branch, a off-resistor branch, and a sampling resistor branch. Each parallel branch consists of a switching element and a resistor element connected in series. The control terminal of the switching element is electrically connected to the control signal output terminal of the FPGA. The right common terminal of the gate resistor network is connected to the SiC under test. The MOSFET's gate is electrically connected. The output terminal of the gate driver chip is connected to the left common terminal of the gate resistor network. The input terminal of the gate peak current acquisition circuit is connected to the sampling resistor in the gate resistor network. The gate peak current acquisition circuit includes a differential operational amplifier U1. The input terminal of the differential operational amplifier U1 is connected to both ends of the sampling resistor in the gate resistor network. The output terminal of the differential operational amplifier U1 is electrically connected to an operational amplifier U2. The negative input terminal of the operational amplifier U2 is connected to resistors R1 and R2. The other end of resistor R1 is connected to the bias voltage VEE, and the other end of resistor R2 is connected to amplifier U1. The output terminal of operational amplifier U2 is electrically connected to transconductance operational amplifier U3. The negative input terminal of transconductance operational amplifier U3 is connected to the OUT terminal. The output terminal of operational amplifier U3 is connected to diodes D1 and D2. The other end of diode D2 is connected to field-effect transistor Q1 and resistor R3. Field-effect transistor Q1 is connected to power supply VCC. Field-effect transistor Q1 is also connected to resistor R4 and voltage buffer U4. Resistor R3 is connected to capacitor C1. Voltage buffer U4 is connected to the OUT terminal. The OUT terminal serves as the output terminal of the gate peak current acquisition circuit and is connected to the data processing terminal of the FPGA.

2. A method for on-line acquisition of junction temperature of SiC MOSFET, characterized in that, Using the SiC MOSFET junction temperature online acquisition circuit as described in claim 1, the specific steps are as follows: the FPGA receives the PWM1 signal, identifies its edge and calculates the switching frequency f, the FPGA counts the rising edge of PWM1, and synchronously outputs the PWM2 drive signal to the gate driver chip; when the count value is less than the sampling threshold m, the rising edge of PWM1 selects the turn-on resistor branch and the falling edge switches to the turn-off resistor branch; when the count value reaches the sampling threshold m, the rising edge of PWM1 selects the sampling resistor branch, triggers the gate peak current acquisition circuit to acquire the peak current, and the falling edge still selects the turn-off resistor branch, and the counter is cleared after acquisition; the acquisition circuit processes the signal and feeds it back to the FPGA to obtain the junction temperature of the SiC MOSFET under test.

3. The SiC MOSFET junction temperature online acquisition method according to claim 2, characterized in that, The sampling resistor of the sampling resistor branch has the same resistance value as the turn-on resistor of the turn-on resistor branch.

4. The SiC MOSFET junction temperature online acquisition method according to claim 2, characterized in that, The sampling threshold m is determined through the following steps: Maximum allowable sampling frequency: A PWM signal, starting from the switching frequency f of the SiC MOSFET under test and gradually decreasing, is applied to generate a gate current that flows through the gate resistor. The temperature of the sampling resistor in the sampling resistor branch rises, and the temperature change of the sampling resistor is observed using an infrared thermal imager until the temperature rise of the sampling resistor is maintained at ≤3℃. The sampling frequency at this point is the maximum allowable sampling frequency f. max ; Minimum allowable acquisition frequency: heat the SiC MOSFET under test, the temperature rise rate is 5-10℃ / min, the temperature range is 25-150℃, the device junction temperature monitored by the infrared thermal imager is used as the reference benchmark, the output junction temperature data is recorded and collected synchronously, the acquisition frequency is gradually increased, when the fitting degree of the acquisition junction temperature curve and the reference benchmark curve is not less than 95%, the time delay is ≤10ms, the corresponding frequency is the minimum allowable acquisition frequency f min ; The sampling threshold m is an integer greater than 1, and f / f max ≤m≤f / f min Wherein f is the switching frequency of the SiC MOSFET to be measured, f=1 / T, T is the switching period of the PWM1 input signal, which is calculated by the FPGA to identify the interval between two rising edges of the PWM1 signal, and m<f, which ensures that the interval of the collection action is within the normal switching period of the SiC MOSFET to be measured, and inhibits the self-heating effect of the sampling resistor.

5. The SiC MOSFET junction temperature online acquisition method according to claim 2, characterized in that, The signal processing steps of the gate peak current acquisition circuit are as follows: First, differential operational amplifier U1 receives the differential signal across the sampling resistor, performs signal conversion processing, and outputs a single-ended voltage signal; operational amplifier U2 receives the single-ended voltage signal output by differential operational amplifier U1, adds negative bias through resistors R1 and R2, and outputs a single-ended voltage signal with added negative bias; transconductance operational amplifier U3 receives the single-ended voltage signal with added negative bias, and utilizes its large output current characteristic to drive capacitor C1 to charge through resistor R3, storing the gate peak signal in the form of charge in capacitor C1, capturing and storing the peak signal; then, the source follower composed of field-effect transistor Q1 and resistor R4 receives the peak signal stored in C1, and reduces the leakage loss of C1 by increasing the input impedance of voltage buffer U4, maintaining the amplitude stability of the peak signal; finally, voltage buffer U4 receives the peak signal stabilized by the source follower, enhances the driving capability of the peak signal, and then feeds the enhanced peak signal back to the data processing terminal of the FPGA through the OUT terminal to provide data for junction temperature calculation.

6. The SiC MOSFET junction temperature online acquisition method according to claim 5, characterized in that, During the process of storing charge in capacitor C1, diode D1 simultaneously clamps and protects the voltage across C1, while diode D2 is turned on at the rising edge of the input signal and turned off at the falling edge.

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