FPGA chip DSP module bit stream verification method and device

Abstract

The application relates to the technical field of chip verification, and discloses an FPGA chip DSP module bit stream verification method and device. In the method, a bit stream file generation method is used to convert configurable parameters of a DSP module from abstract test intentions into specific physical configuration files, the low efficiency of configuring bit stream files for the functions of each DSP module is avoided, then a two-stage routing analysis method is used for function verification of the DSP module, a complete signal path mapping between an SWH port and core logic of the DSP module is accurately constructed, the correctness of the functions of the DSP module itself is ensured, and the interconnection correctness of the DSP module and adjacent modules is ensured, then an initial verification platform is reconstructed based on a port mapping table, and a high-abstraction-level behavior model is combined for result comparison, the verification efficiency and reliability of the DSP module are greatly improved, and the efficiency and accuracy of bit stream verification of the FPGA chip DSP module are ensured.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, specifically to a method and apparatus for verifying the bitstream of an FPGA chip DSP module. Background Technology

[0002] As FPGA (Field Programmable Gate Array) chips continue to expand in size and become increasingly complex, their internal DSP (Digital Signal Processor) modules have become core components for achieving high-performance computing. DSP modules typically possess high configurability, enabling the implementation of different arithmetic and logical functions by loading different bitstream configurations. To ensure the correctness of the DSP module's functionality, thorough bitstream verification is necessary; that is, verifying whether the actual behavior (DUT, Design Under Test) of the DSP module under each bitstream configuration is consistent with the expected high-level behavioral model.

[0003] The verification method for DSP modules disclosed in related technologies is as follows: apply stimulation directly to the input port of the DSP module to be verified using an independent verification platform, and directly collect the response from its output port, and then compare it with the behavior model.

[0004] Since the DSP module in a real FPGA chip does not work independently, but is interconnected with adjacent modules through complex wiring resources, the verification methods for DSP modules disclosed in related technologies cannot guarantee the accuracy of the verification results of the DSP module's own functions. Summary of the Invention

[0005] This invention provides a bitstream verification method and apparatus for FPGA chip DSP modules, to solve the problem that the verification methods for DSP modules disclosed in related technologies are difficult to guarantee the accuracy of the verification results of the DSP module's own functions.

[0006] In a first aspect, the present invention provides a bitstream verification method for an FPGA chip DSP module, the method comprising:

[0007] Based on the DSP module to be verified, multiple bitstream files are obtained using a preset bitstream file generation method and then integrated into a bitstream file library. Each bitstream file corresponds to a functional mode of the DSP module to be verified, including multiplication mode, multiply-accumulate mode, pre-add and multiply mode, bypass and enable of input registers, configuration of output registers, rounding mode, and saturation processing.

[0008] Based on each bit stream file in the bit stream file library, combined with the wiring physical design file, a two-level routing parsing method is used to obtain the signal path from the SWH port to the DSP module to be verified, and a port mapping table is constructed.

[0009] Based on the port mapping table and the initial verification platform data, the initial verification platform is reconstructed to obtain the reconstructed verification platform;

[0010] Based on the reconstructed verification platform and combined with the pre-built high-level abstraction behavior model, all bitstream files in the bitstream file library are simulated and their responses captured in sequence. The final verification report is obtained by using the result comparison method. The verification report includes the test pass rate and functional coverage of the DSP module.

[0011] Through the above implementation method, the configurable parameters of the DSP module are transformed from abstract test intentions into specific physical configuration files using a bitstream file generation method. This avoids the inefficiency of configuring bitstream files for each DSP module individually. Subsequently, a two-level routing parsing method is used to verify the functionality of the DSP module, accurately constructing a complete signal path mapping between the SWH port and the core logic of the DSP module. This ensures both the correctness of the DSP module's own functions and the correctness of its interconnection with adjacent modules. Then, the initial verification platform is reconstructed based on the port mapping table, and the results are compared using a high-level abstraction behavioral model. This significantly improves the efficiency and reliability of DSP module verification, ensuring the high efficiency and accuracy of bitstream verification for FPGA chip DSP modules.

[0012] In one optional implementation, based on each bitstream file in the bitstream file library, and in conjunction with the wiring physical design file, a two-level routing resolution method is used to obtain the signal path from the SWH port to the DSP module to be verified, and construct a port mapping table, including:

[0013] Based on the physical connection data between logical units and cabling resources recorded in the cabling physical design file, the first-level routing parsing method is used to obtain the first mapping relationship between the ports of the DSP module to be verified and the SWH ports.

[0014] Based on the wiring physical design file and the configuration bit segments of the DSP module to be verified in each bit stream file, the second-level routing parsing method is used to obtain the selection state of the internal multiplexer corresponding to each bit stream file, and to determine the second mapping relationship between the port of the DSP module to be verified and the SWH port.

[0015] Combining the first and second mapping relationships, a port mapping table is constructed.

[0016] Through the above implementation method, the external interconnection relationship between the DSP module and the SWH port is clarified by the first-level routing parsing method, which solves the problem of missing connectivity verification between modules. Then, the dynamic selection state of the multiplexer inside the DSP is decoded by the second-level routing parsing method, filling the blind spot of internal signal path verification. Through the constructed port mapping table, the correspondence between the SWH port, the internal path of the DSP module and the core logic of the DSP module under different bit stream configurations is fully presented, which provides a key foundation for achieving high-accuracy bit stream verification of the DSP module.

[0017] In one optional implementation, the first mapping relationship between the ports of the DSP module to be verified and the SWH ports is obtained using a first-level routing resolution method based on the logical unit and cabling resource physical connection relationship data recorded in the cabling physical design file, including:

[0018] Based on the wiring physical design document, the DSP module, SWH port information and wiring connection relationship between each logic unit are extracted to obtain physical connection relationship data; the physical connection relationship data includes wire connection path, interconnection node and signal transmission direction.

[0019] Based on the physical connection relationship data, each port of the DSP module to be verified is used as an anchor point, and trace analysis is performed along the signal transmission path to record the correspondence between the current DSP port and the SWH port.

[0020] Summarize the correspondence between all ports of the DSP module to be verified and the SWH port to obtain the first mapping relationship between the ports of the DSP module to be verified and the SWH port.

[0021] Through the above implementation method, complete physical connection relationship data is first extracted from the cabling physical design document to clarify the conductor path, interconnection node and signal flow direction, providing an accurate basis for the derivation of mapping relationship; then, each port of the DSP module is used as an anchor point, and the signal transmission path is used for tracing analysis to ensure the accurate positioning of the association relationship between each DSP port and the corresponding SWH port; finally, the first mapping relationship between the port of the DSP module to be verified and the SWH port is obtained, laying a key external interconnection data foundation for subsequent construction of complete signal link and subsystem-level verification by combining internal path analysis.

[0022] In one optional implementation, the step of determining the second mapping relationship between the ports of the DSP module to be verified and the SWH ports based on the wiring physical design file and the configuration bit segments of the DSP module to be verified in each bit stream file, using a second-level routing resolution method, includes:

[0023] Based on the aforementioned wiring physical design file, the internal structure data of the DSP module to be verified is obtained using a structural data extraction method. The internal structure data includes the number of internal multiplexer groups, the port definition of each multiplexer, the physical connection relationship between the multiplexer and the core logic port of the DSP module, and the association path between the multiplexer and the external port of the DSP module.

[0024] For each bit stream file in the bit stream file library, the parsing engine is used to interpret the configuration bit fields of the DSP module to be verified, so as to obtain the specific selection state of each internal multiplexer in the functional mode corresponding to the current bit stream file.

[0025] By combining the specific selection states of each internal multiplexer in the functional mode corresponding to each bit stream file, the complete path of each signal inside the DSP module is constructed, and the second mapping relationship between the port of the DSP module to be verified and the SWH port is determined.

[0026] Through the above implementation method, the core data of the internal structure is first extracted from the wiring physical design file to clarify the number of internal multiplexer groups, port definitions, and connection relationships with the core logic ports and external ports of the DSP module. Then, the parsing engine is used to decode the exclusive configuration bit segments of each bit stream file to accurately obtain the selection state of the internal multiplexer in the corresponding functional mode. Finally, the complete transmission path of the signal inside the DSP module is constructed, forming a second mapping relationship that includes the internal selection logic. This ensures the traceability of the transmission relationship of the signal from the SWH port to the core logic of the DSP module, and together with the first mapping relationship, it provides accurate data support for the end-to-end verification.

[0027] In one optional implementation, the step of obtaining multiple bitstream files based on the DSP module to be verified using a preset bitstream file generation method and integrating them into a bitstream file library includes:

[0028] Based on the DSP module to be verified, the configuration parameters of each functional mode of the DSP module to be verified are obtained to obtain a configuration list;

[0029] Based on the configuration list, the configuration parameters of the configuration list are filled into the pre-built bitstream template using the parameter serialization method to obtain the corresponding bitstream file;

[0030] All bitstream files are numbered and stored in a preset directory to obtain a bitstream file library.

[0031] Through the above implementation method, a complete configuration list is first formed based on the configuration parameters of all functional modes of the DSP module to ensure coverage of all verifiable scenarios; then, the configuration parameters are accurately filled into the pre-built bitstream template through the parameter serialization method, which efficiently completes the conversion from abstract parameters to physical bitstream files; finally, each bitstream file is numbered and centrally stored to form a bitstream file library, avoiding the low efficiency of manually configuring bitstream files for each function, and greatly improving the verification efficiency and coverage of the DSP module.

[0032] In one optional implementation, the step of reconstructing the initial verification platform based on the port mapping table and the initial verification platform data to obtain the reconstructed verification platform includes:

[0033] Based on the port correspondence data in the port mapping table, the virtual interface of the initial verification platform is rebound using the interface reconstruction method;

[0034] Based on the input path relationship data in the port mapping table, an excitation translator is constructed in the excitation generator of the initial verification platform; the excitation translator is used to translate the abstract test vector of the core logic of the DSP module into the drive signal of the SWH output port.

[0035] Based on the output path relationship data in the port mapping table, a response mapper is constructed in the monitoring component of the initial verification platform; the response mapper is used to reconstruct the raw response data obtained from the SWH input port into the output result of the core logic of the DSP module.

[0036] Output the reconstructed verification platform.

[0037] Through the above implementation method, the virtual interface of the initial verification platform is re-bound by the interface reconstruction method to ensure seamless connection between the verification platform interface and the SWH port. Then, the abstract test vector is converted into a driving signal that the SWH port can recognize by the excitation translator to ensure accurate excitation transmission. Then, the core logic output result of the DSP module is restored by the response mapper, so that the reconstructed verification platform simulates the signal transmission path in the real chip, providing a highly adaptable and reliable test environment for subsequent automated simulation and accurate comparison based on the full bit stream file.

[0038] In one optional implementation, based on the reconstructed verification platform and combined with a pre-built high-level abstraction behavior model, simulation and response capture are performed sequentially on all bitstream files in the bitstream file library. A final verification report is obtained using a result comparison method, including:

[0039] Based on the reconstructed verification platform and combined with the pre-built high-level abstract behavior model, each bitstream file in the bitstream file library is input for simulation and response capture to obtain a first simulation result and a second simulation result for each bitstream file; wherein, the first simulation result is generated using the reconstructed verification platform and the second simulation result is generated using the high-level abstract behavior model;

[0040] Based on the first simulation results and the second simulation results, a comparison result is obtained using a result comparison method, and this result is determined as the final verification report.

[0041] Through the above implementation methods, relying on the reconstructed verification platform and the high-level abstraction behavior model, simulation and response capture are completed one by one for all bitstream files in the bitstream file library, and both actual and ideal simulation results are obtained simultaneously. The consistency between the two is accurately verified by the result comparison method, and finally a verification report containing core information such as test pass rate and functional coverage is generated. This achieves efficient verification of massive bitstream configurations, which not only ensures the correctness of the DSP module's own functions and the interconnection between modules, but also greatly improves the verification efficiency and the reliability of the results, providing an objective and comprehensive basis for the functional verification of FPGA chip DSP modules.

[0042] Secondly, the present invention provides a bitstream verification device for an FPGA chip DSP module, the device comprising:

[0043] The data construction module is used to generate multiple bitstream files based on the DSP module to be verified using a preset bitstream file generation method, and then integrate them into a bitstream file library. Each bitstream file corresponds to a functional mode of the DSP module to be verified. The functional modes include multiplication mode, multiply-accumulate mode, pre-add and multiply mode, bypass and enable of input registers, configuration of output registers, rounding mode, and saturation processing.

[0044] The mapping and parsing module is used to obtain the signal path from the SWH port to the DSP module to be verified based on each bit stream file in the bit stream file library and in combination with the wiring physical design file, using a two-level routing parsing method, and construct it as a port mapping table.

[0045] The platform reconstruction module is used to reconstruct the initial verification platform based on the port mapping table and the initial verification platform data to obtain the reconstructed verification platform.

[0046] The result output module is used to simulate and capture responses of all bitstream files in the bitstream file library in sequence based on the reconstructed verification platform and combined with the pre-built high-abstraction behavioral model, and obtain the final verification report using the result comparison method; the verification report includes the test pass rate and functional coverage of the DSP module.

[0047] Thirdly, the present invention provides an electronic device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the FPGA chip DSP module bitstream verification method described in the first aspect or any corresponding embodiment thereof.

[0048] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the FPGA chip DSP module bitstream verification method described in the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0049] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of the first step in the bitstream verification method for an FPGA chip DSP module according to an embodiment of the present invention.

[0051] Figure 2 This is a schematic diagram of the second process of the FPGA chip DSP module bit stream verification method according to an embodiment of the present invention;

[0052] Figure 3 This is a schematic diagram of the third process of the FPGA chip DSP module bit stream verification method according to an embodiment of the present invention;

[0053] Figure 4 This is a schematic diagram of the fourth process of the FPGA chip DSP module bit stream verification method according to an embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram of the fifth process of the FPGA chip DSP module bit stream verification method according to an embodiment of the present invention;

[0055] Figure 6 This is a structural block diagram of an FPGA chip DSP module bitstream verification device according to an embodiment of the present invention;

[0056] Figure 7 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0059] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0060] The DSP module verification methods disclosed in related technologies involve directly applying stimuli to the input ports of the DSP module using a constructed verification platform and directly acquiring the responses from the output ports of the DSP module, followed by comparison using a behavioral model. However, the DSP module verification methods disclosed in related technologies have at least the following drawbacks:

[0061] 1. Since the DSP module does not work independently in a real chip, but is interconnected with adjacent modules through complex wiring resources, independent DSP module verification cannot ensure that the signal routing relationship between the DSP module and the SWH port is correct. There may be wiring errors or multiplexer configuration errors, which may lead to chip-level functional failure.

[0062] 2. The bitstream configuration combinations of the DSP module are numerous. Manually creating test stimuli for each configuration, modifying the verification platform interface, and performing simulations is a huge workload, time-consuming, labor-intensive, and inefficient, and it is difficult to achieve high coverage verification.

[0063] In summary, to overcome the shortcomings of existing DSP module verification methods in related technologies, this invention provides a bitstream verification method for FPGA chip DSP modules. By utilizing a bitstream file generation method, the configurable parameters of the DSP module are transformed from abstract test intentions into specific physical configuration files, avoiding the inefficiency of configuring bitstream files for each DSP module individually. Then, a two-level routing parsing method is used to verify the functionality of the DSP module, accurately constructing a complete signal path mapping between the SWH port and the core logic of the DSP module. This ensures both the correct functionality of the DSP module itself and the correct interconnection with adjacent modules. Finally, the initial verification platform is reconstructed based on the port mapping table, and the results are compared using a high-level abstract behavioral model. This significantly improves the efficiency and reliability of DSP module verification, ensuring the high efficiency and accuracy of bitstream verification for FPGA chip DSP modules.

[0064] According to an embodiment of the present invention, an embodiment of a bitstream verification method for an FPGA chip DSP module is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0065] This embodiment provides a bitstream verification method for an FPGA chip DSP module, which can be used in a chip verification server. Figure 1 This is a flowchart of an FPGA chip DSP module bitstream verification method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0066] S101, based on the DSP module to be verified, multiple bit stream files are obtained using a preset bit stream file generation method, and then integrated into a bit stream file library; wherein, each bit stream file corresponds to a functional mode of the DSP module to be verified, the functional mode includes multiplication mode, multiply-accumulate mode, pre-add and multiply mode, bypass and enable of input register, configuration of output register, rounding mode and saturation processing.

[0067] The DSP module to be verified is a digital signal processing module in an FPGA chip used to implement high-performance arithmetic operations and logic processing. Different functions are achieved by configuring different bit stream files.

[0068] Bitstream files are configuration files for FPGA chips. They contain hardware configuration information in binary form and are used to define the operating modes and connections of DSP modules and other logic units after being loaded into the FPGA chip, enabling them to perform specific functions.

[0069] Bitstream file generation method refers to a predefined, automated batch generation process that combines configuration manifests with bitstream templates to transform abstract functional parameters into physical configuration files that can be recognized by FPGA chips.

[0070] The bitstream file library is a structured collection that centrally stores all generated bitstream files. It includes bitstream files corresponding to all configurable function modes of the DSP module. The files are numbered, classified, and archived according to preset rules, which facilitates subsequent simulation calls and traceability.

[0071] Functional modes refer to the specific operating modes or data processing logic that a DSP module can achieve through different bitstream configurations.

[0072] First, a bitstream file is constructed for each functional mode of the DSP module, and all bitstream files are aggregated into a bitstream file library. This avoids the inefficiency of manually configuring bitstream files for each function, and greatly improves the efficiency and coverage of DSP module verification.

[0073] S102, based on each bit stream file in the bit stream file library, combined with the wiring physical design file, a two-level routing parsing method is used to obtain the signal path from the SWH port to the DSP module to be verified, and a port mapping table is constructed.

[0074] The routing physical design file is the core file generated during the FPGA chip placement and routing stage. It records the physical location and port information of all logic units (such as DSP modules and SWH modules) within the chip, as well as the physical connection relationships between each unit established through routing resources (wires, interconnect nodes, etc.).

[0075] The two-level routing resolution method includes "inter-module routing resolution method" and "intra-module routing resolution method". By sequentially resolving external interconnection relationships and internal gating logic, a complete signal path mapping is constructed.

[0076] The SWH port is the input or output port of the softcore hardware module, which is a peripheral hardware unit in the FPGA chip that works in conjunction with the DSP module. Its port is the key interface for signals to enter or flow out of the DSP module.

[0077] The signal path refers to the complete transmission path of a signal starting from the SWH port, passing through the FPGA chip wiring resources and the internal logic of the DSP module (such as a multiplexer), and finally being transmitted to the input of the core logic of the DSP module, or from the output of the core logic of the DSP module through internal logic and wiring resources to the SWH port.

[0078] The port mapping table is a standardized table generated by combining the results of two-level routing resolution. It records the one-to-one correspondence between SWH ports, DSP module ports, and DSP core logic ports, and contains complete path information for signal transmission.

[0079] S103, Based on the port mapping table and the initial verification platform data, the initial verification platform is reconstructed to obtain the reconstructed verification platform.

[0080] The initial verification platform data consists of descriptive information and configuration data of the initial verification environment, including virtual interface definitions, stimulus generation rules, monitoring and comparison logic, clock and timing constraints, and environmental parameters.

[0081] The initial verification platform is the original verification environment before subsystem-level adaptation. It includes an excitation generator, driver, monitor, scoreboard, comparator, environment components, and virtual interface, and is used to perform module-level verification of the DSP module.

[0082] The reconstructed verification platform refers to the verification environment after the interface and data path have been adapted. It can apply stimuli to the DSP module and collect responses through the SWH port, while maintaining compatibility with the original test cases and stimulus logic. It is used for subsystem-level bitstream verification and regression.

[0083] S104. Based on the reconstructed verification platform and combined with the pre-built high-abstraction behavior model, all bitstream files in the bitstream file library are simulated and their responses captured in sequence. The final verification report is obtained by using the result comparison method. The verification report includes the test pass rate and functional coverage of the DSP module.

[0084] A high-level abstract behavioral model refers to a model that describes the ideal behavior of a DSP module using algorithms or functional levels. It can produce a "golden reference output" under the same input, which can be used to compare with actual simulation results.

[0085] Simulation refers to the process of loading any bitstream file into the reconstructed verification platform, configuring the functional mode of the DSP module, applying stimuli and running the simulator to obtain the actual output and internal signal behavior of the DSP module under that configuration.

[0086] Response capture is the process by which the monitoring components of the reconstructed verification platform collect output data, status information, and timing information during the simulation process at the SWH port, forming actual results that can be used for comparison.

[0087] The result comparison method is a method of comparing the "platform simulation capture results" with the "high-level abstraction behavior model output results" item by item to determine consistency and record differences.

[0088] The verification report is a summary of all bitstream configuration simulation and comparison results, and typically includes pass / fail statistics, difference details, and coverage data.

[0089] The test pass rate refers to the proportion of test cases that pass the comparison of bitstream configurations to the total number of test cases, and is used to reflect the overall functional correctness and stability.

[0090] Functional coverage refers to the proportion of test coverage of configurable functional points of a DSP module, which reflects the completeness of the verification.

[0091] The FPGA chip DSP module bitstream verification method provided in this embodiment utilizes a bitstream file generation method to transform the configurable parameters of the DSP module from abstract test intentions into specific physical configuration files. This avoids the inefficiency of configuring bitstream files for each DSP module individually. Subsequently, a two-level routing parsing method is used to verify the functionality of the DSP module, accurately constructing a complete signal path mapping between the SWH port and the core logic of the DSP module. This ensures both the correctness of the DSP module's own functions and the correctness of its interconnection with adjacent modules. Then, the initial verification platform is reconstructed based on the port mapping table, and the results are compared using a high-level abstraction behavioral model. This significantly improves the efficiency and reliability of DSP module verification, ensuring the high efficiency and accuracy of bitstream verification for FPGA chip DSP modules.

[0092] This embodiment provides a bitstream verification method for an FPGA chip DSP module, which can be used in a chip verification server. Figure 2 This is a flowchart of an FPGA chip DSP module bitstream verification method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0093] S201, based on the DSP module to be verified, multiple bit stream files are obtained using a preset bit stream file generation method, and then integrated into a bit stream file library; wherein, each bit stream file corresponds to a functional mode of the DSP module to be verified, the functional mode includes multiplication mode, multiply-accumulate mode, pre-add and multiply mode, bypass and enable of input register, configuration of output register, rounding mode and saturation processing.

[0094] Specifically, the aforementioned S201 includes:

[0095] S2011, Based on the DSP module to be verified, obtain the configuration parameters of each functional mode of the DSP module to be verified, and obtain the configuration list;

[0096] S2012, Based on the configuration list, the configuration parameters of the configuration list are filled into the pre-built bitstream template using the parameter serialization method to obtain the corresponding bitstream file;

[0097] S2013: All bitstream files are numbered and stored in a preset directory to obtain a bitstream file library.

[0098] Configuration parameters are specific settings used to define a certain functional mode of the DSP module, such as operation mode selection, register status, data format, rounding method, etc.

[0099] The configuration list is a structured list that summarizes all the functional modes of the DSP module and their corresponding configuration parameters, which is used to facilitate the subsequent batch generation of bitstream files.

[0100] The parameter serialization method is used to convert abstract parameters in the configuration manifest into binary configuration bits that can be recognized by the FPGA chip.

[0101] A bitstream template is a pre-built bitstream file framework with placeholders, where the position of each placeholder corresponds one-to-one with the configuration bits of the DSP module, and is used to generate bitstream files with different configurations in batches.

[0102] Each generated bitstream file is automatically numbered and recorded in a corresponding table. Simultaneously, the entire generation process is version-controlled to ensure the reproducibility of the bitstream set used in each verification activity. All generated bitstream files are centrally stored in a designated directory, providing input for subsequent bitstream verification of the FPGA chip's DSP module.

[0103] First, a complete configuration list is formed based on the configuration parameters of all functional modes of the DSP module to ensure coverage of all verifiable scenarios. Then, the configuration parameters are accurately filled into the pre-built bitstream template through parameter serialization, efficiently completing the conversion from abstract parameters to physical bitstream files. Finally, each bitstream file is numbered and centrally stored to form a bitstream file library, avoiding the inefficiency of manually configuring bitstream files for each function, and greatly improving the efficiency and coverage of DSP module verification.

[0104] S202: Based on each bitstream file in the bitstream file library and combined with the wiring physical design file, a two-level routing resolution method is used to obtain the signal path from the SWH port to the DSP module to be verified, and a port mapping table is constructed. For details, please refer to [link to relevant documentation]. Figure 1 S102 of the illustrated embodiment will not be described again here.

[0105] S203, based on the port mapping table and the initial verification platform data, the initial verification platform is reconstructed to obtain the reconstructed verification platform. For details, please refer to [link to relevant documentation]. Figure 1 S103 of the illustrated embodiment will not be described again here.

[0106] S204, based on the reconstructed verification platform and combined with the pre-built high-level abstraction behavior model, simulate and capture responses for all bitstream files in the bitstream file library sequentially. Using a result comparison method, a final verification report is obtained. The verification report includes the test pass rate and functional coverage of the DSP module. For details, please refer to... Figure 1 S104 of the illustrated embodiment will not be described again here.

[0107] The FPGA chip DSP module bitstream verification method provided in this embodiment utilizes a bitstream file generation method to transform the configurable parameters of the DSP module from abstract test intentions into specific physical configuration files. This avoids the inefficiency of configuring bitstream files for each DSP module individually. Subsequently, a two-level routing parsing method is used to verify the functionality of the DSP module, accurately constructing a complete signal path mapping between the SWH port and the core logic of the DSP module. This ensures both the correctness of the DSP module's own functions and the correctness of its interconnection with adjacent modules. Then, the initial verification platform is reconstructed based on the port mapping table, and the results are compared using a high-level abstraction behavioral model. This significantly improves the efficiency and reliability of DSP module verification, ensuring the high efficiency and accuracy of bitstream verification for FPGA chip DSP modules.

[0108] This embodiment provides a bitstream verification method for an FPGA chip DSP module, which can be used in a chip verification server. Figure 3 This is a flowchart of an FPGA chip DSP module bitstream verification method according to an embodiment of the present invention, such as... Figure 3 As shown, the process includes the following steps:

[0109] S301, based on the DSP module to be verified, uses a preset bitstream file generation method to obtain multiple bitstream files, which are then integrated into a bitstream file library. Each bitstream file corresponds to a functional mode of the DSP module to be verified, including multiplication mode, multiply-accumulate mode, pre-add-after-multiply mode, input register bypass and enable, output register configuration, rounding mode, and saturation processing. For details, please refer to [link to documentation]. Figure 1 S101 of the illustrated embodiment will not be described again here.

[0110] S302, based on each bit stream file in the bit stream file library, combined with the wiring physical design file, a two-level routing parsing method is used to obtain the signal path from the SWH port to the DSP module to be verified, and a port mapping table is constructed.

[0111] Specifically, S302 above includes:

[0112] S3021, based on the physical connection relationship data between logical units and cabling resources recorded in the cabling physical design file, uses the first-level routing parsing method to obtain the first mapping relationship between the port of the DSP module to be verified and the SWH port.

[0113] For example, S3021 above includes:

[0114] a1. Based on the wiring physical design document, extract the DSP module, SWH port information, and wiring connection relationships between each logic unit to obtain physical connection relationship data; the physical connection relationship data includes wire connection paths, interconnection nodes, and signal transmission directions.

[0115] a2. Based on the physical connection relationship data, each port of the DSP module to be verified is used as an anchor point, and trace analysis is performed along the signal transmission path to record the correspondence between the current DSP port and the SWH port.

[0116] a3 summarizes the correspondence between all ports of the DSP module to be verified and the SWH ports, and obtains the first mapping relationship between the ports of the DSP module to be verified and the SWH ports.

[0117] First, using the original input / output ports of the DSP module as anchor points, the engine traces and tracks the signal's origin within the wiring network. For each input port of the DSP module, the analysis engine reverse-engineers its driver network until it locates the initial source of the signal, i.e., the output port of a specific SWH module. Similarly, for each output port of the DSP module, the engine traces forward, following its load network, ultimately determining the target to which the signal is delivered, i.e., the input port of a specific SWH module.

[0118] First, complete physical connection data is extracted from the cabling physical design documents to clarify the conductor paths, interconnection nodes, and signal flow, providing a precise basis for mapping relationship derivation. Then, each port of the DSP module is used as an anchor point, and the signal transmission path is traced and analyzed to ensure the accurate positioning of the association between each DSP port and the corresponding SWH port. Finally, the first mapping relationship between the ports of the DSP module to be verified and the SWH ports is obtained, laying a key external interconnection data foundation for subsequent construction of complete signal links and subsystem-level verification by combining internal path analysis.

[0119] S3022, based on the wiring physical design file and the configuration bit segments of the DSP module to be verified in each bit stream file, the second-level routing parsing method is used to obtain the selection state of the internal multiplexer corresponding to each bit stream file, and to determine the second mapping relationship between the port of the DSP module to be verified and the SWH port.

[0120] For example, S3022 above includes:

[0121] b1. Based on the wiring physical design file, the internal structure data of the DSP module to be verified is obtained using the structural data extraction method. The internal structure data includes the number of internal multiplexer groups, the port definition of each multiplexer, the physical connection relationship between the multiplexer and the core logic port of the DSP module, and the association path between the multiplexer and the external port of the DSP module.

[0122] b2, for each bit stream file in the bit stream file library, use the parsing engine to interpret the configuration bit field of the DSP module to be verified, and obtain the specific selection state of each internal multiplexer in the functional mode corresponding to the current bit stream file;

[0123] b3, combining the specific selection states of each internal multiplexer in the functional mode corresponding to each bit stream file, constructs the complete path of each signal inside the DSP module, and determines the second mapping relationship between the port of the DSP module to be verified and the SWH port.

[0124] For the input path, it determines which DSP module core logic input terminal the signal from a specific external port is ultimately sent to after passing through the input multiplexer; for the output path, it determines which calculation result of the DSP module core logic is routed to a specific external output port through the output multiplexer.

[0125] First, the core data of the internal structure is extracted from the wiring physical design file to clarify the number of internal multiplexer groups, port definitions, and connection relationships with the core logic ports and external ports of the DSP module. Then, the exclusive configuration bit segments of each bit stream file are decoded using the parsing engine to accurately obtain the selection status of the internal multiplexers in the corresponding functional mode. Finally, the complete transmission path of the signal within the DSP module is constructed, forming a second mapping relationship that includes the internal selection logic. This ensures the traceability of the signal transmission relationship from the SWH port to the core logic of the DSP module, and together with the first mapping relationship, provides accurate data support for end-to-end verification.

[0126] S3023, Combining the first mapping relationship and the second mapping relationship, a port mapping table is constructed.

[0127] The first-level routing parsing method clarified the external interconnection between the DSP module and the SWH port, solving the problem of missing connectivity verification between modules. Then, the second-level routing parsing method decoded the dynamic selection state of the multiplexer inside the DSP, filling the blind spot in the internal signal path verification. Through the constructed port mapping table, the correspondence between the SWH port, the internal path of the DSP module, and the core logic of the DSP module under different bit stream configurations was fully presented, providing a key foundation for achieving high-accuracy bit stream verification of the DSP module.

[0128] S303, based on the port mapping table and the initial verification platform data, the initial verification platform is reconstructed to obtain the reconstructed verification platform. For details, please refer to [link to relevant documentation]. Figure 1 S103 of the illustrated embodiment will not be described again here.

[0129] S304, based on the reconstructed verification platform and combined with the pre-built high-level abstraction behavior model, simulate and capture responses for all bitstream files in the bitstream file library sequentially. Using a result comparison method, a final verification report is obtained. The verification report includes the test pass rate and functional coverage of the DSP module. For details, please refer to... Figure 1 S104 of the illustrated embodiment will not be described again here.

[0130] The FPGA chip DSP module bitstream verification method provided in this embodiment utilizes a bitstream file generation method to transform the configurable parameters of the DSP module from abstract test intentions into specific physical configuration files. This avoids the inefficiency of configuring bitstream files for each DSP module individually. Subsequently, a two-level routing parsing method is used to verify the functionality of the DSP module, accurately constructing a complete signal path mapping between the SWH port and the core logic of the DSP module. This ensures both the correctness of the DSP module's own functions and the correctness of its interconnection with adjacent modules. Then, the initial verification platform is reconstructed based on the port mapping table, and the results are compared using a high-level abstraction behavioral model. This significantly improves the efficiency and reliability of DSP module verification, ensuring the high efficiency and accuracy of bitstream verification for FPGA chip DSP modules.

[0131] This embodiment provides a bitstream verification method for an FPGA chip DSP module, which can be used in a chip verification server. Figure 4 This is a flowchart of an FPGA chip DSP module bitstream verification method according to an embodiment of the present invention, such as... Figure 4 As shown, the process includes the following steps:

[0132] S401, based on the DSP module to be verified, uses a preset bitstream file generation method to obtain multiple bitstream files, which are then integrated into a bitstream file library. Each bitstream file corresponds to a functional mode of the DSP module to be verified, including multiplication mode, multiply-accumulate mode, pre-add-after-multiply mode, input register bypass and enable, output register configuration, rounding mode, and saturation processing. For details, please refer to [link to documentation]. Figure 1 S101 of the illustrated embodiment will not be described again here.

[0133] S402: Based on each bitstream file in the bitstream file library and combined with the wiring physical design file, a two-level routing resolution method is used to obtain the signal path from the SWH port to the DSP module to be verified, and a port mapping table is constructed. For details, please refer to [link to relevant documentation]. Figure 1 S102 of the illustrated embodiment will not be described again here.

[0134] S403, Based on the port mapping table and the initial verification platform data, the initial verification platform is reconstructed to obtain the reconstructed verification platform.

[0135] Specifically, S403 includes:

[0136] S4031, Based on the port correspondence data in the port mapping table, the virtual interface of the initial verification platform is re-bound using the interface reconstruction method;

[0137] S4032, Based on the input path relationship data in the port mapping table, an excitation translator is constructed in the excitation generator of the initial verification platform; the excitation translator is used to translate the abstract test vector of the core logic of the DSP module into the drive signal of the SWH output port;

[0138] S4033, Based on the output path relationship data in the port mapping table, a response mapper is constructed in the monitoring component of the initial verification platform; the response mapper is used to reconstruct the raw response data obtained from the SWH input port into the output result of the core logic of the DSP module;

[0139] S4034 outputs the reconstructed verification platform.

[0140] By rebinding the virtual interface of the initial verification platform through interface reconstruction, the verification platform interface and the SWH port are seamlessly connected. Then, the abstract test vector is transformed into a drive signal that the SWH port can recognize by the stimulus translator, ensuring accurate stimulus transmission. Finally, the core logic output of the DSP module is restored by the response mapper, so that the reconstructed verification platform can simulate the signal transmission path in the real chip, providing a highly adaptable and reliable test environment for subsequent automated simulation and accurate comparison based on the full bit stream file.

[0141] S404, based on the reconstructed verification platform and combined with the pre-built high-level abstraction behavior model, simulates and captures responses for all bitstream files in the bitstream file library sequentially. Using a result comparison method, a final verification report is obtained. The verification report includes the test pass rate and functional coverage of the DSP module. For details, please refer to [link to relevant documentation]. Figure 1 S104 of the illustrated embodiment will not be described again here.

[0142] The FPGA chip DSP module bitstream verification method provided in this embodiment utilizes a bitstream file generation method to transform the configurable parameters of the DSP module from abstract test intentions into specific physical configuration files. This avoids the inefficiency of configuring bitstream files for each DSP module individually. Subsequently, a two-level routing parsing method is used to verify the functionality of the DSP module, accurately constructing a complete signal path mapping between the SWH port and the core logic of the DSP module. This ensures both the correctness of the DSP module's own functions and the correctness of its interconnection with adjacent modules. Then, the initial verification platform is reconstructed based on the port mapping table, and the results are compared using a high-level abstraction behavioral model. This significantly improves the efficiency and reliability of DSP module verification, ensuring the high efficiency and accuracy of bitstream verification for FPGA chip DSP modules.

[0143] This embodiment provides a bitstream verification method for an FPGA chip DSP module, which can be used in a chip verification server. Figure 5 This is a flowchart of an FPGA chip DSP module bitstream verification method according to an embodiment of the present invention, such as... Figure 5 As shown, the process includes the following steps:

[0144] S501, based on the DSP module to be verified, uses a preset bitstream file generation method to obtain multiple bitstream files, which are then integrated into a bitstream file library. Each bitstream file corresponds to a functional mode of the DSP module to be verified, including multiplication mode, multiply-accumulate mode, pre-add-after-multiply mode, input register bypass and enable, output register configuration, rounding mode, and saturation processing. For details, please refer to [link to documentation]. Figure 1 S101 of the illustrated embodiment will not be described again here.

[0145] S502, based on each bitstream file in the bitstream file library and combined with the wiring physical design file, a two-level routing resolution method is used to obtain the signal path from the SWH port to the DSP module to be verified, and a port mapping table is constructed. For details, please refer to [link to relevant documentation]. Figure 1 S102 of the illustrated embodiment will not be described again here.

[0146] S503, based on the port mapping table and the initial verification platform data, the initial verification platform is reconstructed to obtain the reconstructed verification platform. For details, please refer to [link to relevant documentation]. Figure 1 S103 of the illustrated embodiment will not be described again here.

[0147] S504, based on the reconstructed verification platform and combined with the pre-built high-abstraction behavior model, simulate and capture the response of all bitstream files in the bitstream file library in sequence, and obtain the final verification report by using the result comparison method; the verification report includes the test pass rate and functional coverage of the DSP module.

[0148] Specifically, the aforementioned S504 includes:

[0149] S5041, Based on the reconstructed verification platform and combined with the pre-built high-level abstraction behavior model, each bitstream file in the bitstream file library is input for simulation and response capture to obtain a first simulation result and a second simulation result for each bitstream file; wherein, the first simulation result is generated using the reconstructed verification platform and the second simulation result is generated using the high-level abstraction behavior model;

[0150] S5042, Based on the first simulation result and the second simulation result, a comparison result is obtained using a result comparison method, and determined as the final verification report.

[0151] Based on the reconstructed verification platform and highly abstract behavioral model, simulation and response capture were performed on all bitstream files in the bitstream file library one by one, and both actual and ideal simulation results were obtained simultaneously. The consistency between the two was accurately verified by the result comparison method, and finally a verification report containing core information such as test pass rate and functional coverage was generated. This achieved efficient verification of massive bitstream configurations, which not only ensured the correctness of the DSP module's own functions and the interconnection between modules, but also greatly improved the verification efficiency and the reliability of the results, providing an objective and comprehensive basis for the functional verification of FPGA chip DSP modules.

[0152] The FPGA chip DSP module bitstream verification method provided in this embodiment utilizes a bitstream file generation method to transform the configurable parameters of the DSP module from abstract test intentions into specific physical configuration files. This avoids the inefficiency of configuring bitstream files for each DSP module individually. Subsequently, a two-level routing parsing method is used to verify the functionality of the DSP module, accurately constructing a complete signal path mapping between the SWH port and the core logic of the DSP module. This ensures both the correctness of the DSP module's own functions and the correctness of its interconnection with adjacent modules. Then, the initial verification platform is reconstructed based on the port mapping table, and the results are compared using a high-level abstraction behavioral model. This significantly improves the efficiency and reliability of DSP module verification, ensuring the high efficiency and accuracy of bitstream verification for FPGA chip DSP modules.

[0153] This embodiment also provides an FPGA chip DSP module bitstream verification device, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0154] This embodiment provides a bitstream verification device for an FPGA chip DSP module, such as... Figure 6 As shown, it includes:

[0155] The data construction module 610 is used to obtain multiple bit stream files based on the DSP module to be verified using a preset bit stream file generation method, and integrate them into a bit stream file library; wherein, each bit stream file corresponds to a functional mode of the DSP module to be verified, and the functional mode includes multiplication mode, multiply-accumulate mode, pre-add and multiply mode, bypass and enable of input register, configuration of output register, rounding mode and saturation processing.

[0156] The mapping and parsing module 620 is used to obtain the signal path from the SWH port to the DSP module to be verified based on each bit stream file in the bit stream file library and in combination with the wiring physical design file, using a two-level routing parsing method, and to construct a port mapping table.

[0157] The platform reconstruction module 630 is used to reconstruct the initial verification platform based on the port mapping table and the initial verification platform data to obtain the reconstructed verification platform.

[0158] The result output module 640 is used to simulate and capture the response of all bitstream files in the bitstream file library in sequence based on the reconstructed verification platform and combined with the pre-built high-abstraction behavior model, and obtain the final verification report by using the result comparison method; the verification report includes the test pass rate and functional coverage of the DSP module.

[0159] In some alternative implementations, the data construction module 610 includes:

[0160] The parameter acquisition unit is used to acquire the configuration parameters of each functional mode of the DSP module to be verified based on the DSP module to be verified, and obtain a configuration list;

[0161] The file generation unit is used to fill the configuration parameters of the configuration list into a pre-built bitstream template based on the configuration list using a parameter serialization method, so as to obtain the corresponding bitstream file.

[0162] The data storage unit is used to number all the bitstream files and store them centrally in a preset directory to obtain a bitstream file library.

[0163] In some alternative implementations, the mapping resolution module 620 includes:

[0164] The first mapping parsing unit is used to obtain the first mapping relationship between the port of the DSP module to be verified and the SWH port based on the logical unit and the physical connection relationship data of the cabling resources recorded in the cabling physical design file and the first-level routing parsing method.

[0165] The second mapping parsing unit is used to obtain the selection state of the internal multiplexer corresponding to each bit stream file based on the wiring physical design file and the configuration bit field of the DSP module to be verified in each bit stream file, and to determine the second mapping relationship between the port of the DSP module to be verified and the SWH port using the second-level routing parsing method.

[0166] The mapping parsing output unit is used to combine the first mapping relationship and the second mapping relationship to construct a port mapping table.

[0167] In some optional implementations, the first mapping resolution unit is specifically used for:

[0168] Based on the wiring physical design document, the DSP module, SWH port information and wiring connection relationship between each logic unit are extracted to obtain physical connection relationship data; the physical connection relationship data includes wire connection path, interconnection node and signal transmission direction.

[0169] Based on the physical connection relationship data, each port of the DSP module to be verified is used as an anchor point, and trace analysis is performed along the signal transmission path to record the correspondence between the current DSP port and the SWH port.

[0170] Summarize the correspondence between all ports of the DSP module to be verified and the SWH port to obtain the first mapping relationship between the ports of the DSP module to be verified and the SWH port.

[0171] In some optional implementations, the second mapping resolution unit is specifically used for:

[0172] Based on the aforementioned wiring physical design file, the internal structure data of the DSP module to be verified is obtained using a structural data extraction method. The internal structure data includes the number of internal multiplexer groups, the port definition of each multiplexer, the physical connection relationship between the multiplexer and the core logic port of the DSP module, and the association path between the multiplexer and the external port of the DSP module.

[0173] For each bit stream file in the bit stream file library, the parsing engine is used to interpret the configuration bit fields of the DSP module to be verified, so as to obtain the specific selection state of each internal multiplexer in the functional mode corresponding to the current bit stream file.

[0174] By combining the specific selection states of each internal multiplexer in the functional mode corresponding to each bit stream file, the complete path of each signal inside the DSP module is constructed, and the second mapping relationship between the port of the DSP module to be verified and the SWH port is determined.

[0175] In some alternative implementations, the platform reconfiguration module 630 includes:

[0176] The interface binding unit is used to rebind the virtual interface of the initial verification platform based on the port correspondence data in the port mapping table and using the interface reconstruction method.

[0177] The first construction unit is used to construct an excitation translator in the excitation generator of the initial verification platform based on the input path relationship data in the port mapping table; the excitation translator is used to translate the abstract test vector of the core logic of the DSP module into the drive signal of the SWH output port.

[0178] The second construction unit is used to construct a response mapper in the monitoring component of the initial verification platform based on the output path relationship data in the port mapping table; the response mapper is used to reconstruct the raw response data obtained from the SWH input port into the output result of the core logic of the DSP module.

[0179] The platform reconstruction unit is used to output the reconstructed verification platform.

[0180] In some alternative implementations, the result output module 640 includes:

[0181] The data simulation unit is used to simulate and capture responses for each bitstream file in the bitstream file library based on the reconstructed verification platform and combined with a pre-built high-level abstraction behavior model, and to obtain a first simulation result and a second simulation result for each bitstream file; wherein, the first simulation result is generated using the reconstructed verification platform and the second simulation result is generated using the high-level abstraction behavior model;

[0182] The result comparison unit is used to obtain a comparison result based on the first simulation result and the second simulation result using a result comparison method, and determine it as the final verification report.

[0183] The FPGA chip DSP module bitstream verification device provided in this embodiment of the invention can execute the FPGA chip DSP module bitstream verification method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method. Further functional descriptions of the various modules and units described above are the same as in the corresponding embodiments described above, and will not be repeated here.

[0184] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0185] The following is a detailed reference. Figure 7This diagram illustrates a suitable structural schematic for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 701, which can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 702 or a program loaded from memory 708 into random access memory (RAM) 703. The RAM 703 also stores various programs and data required for the operation of the electronic device. The processor 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0186] Typically, the following devices can be connected to I / O interface 705: input devices 706 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 707 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 708 including, for example, magnetic tapes, hard disks, etc.; and communication devices 709. Communication device 709 allows electronic devices to exchange data via wireless or wired communication with other devices. Although Figure 7 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0187] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 709, or installed from a memory 708, or installed from a ROM 702. When the computer program is executed by the processor 701, it performs the functions defined in the FPGA chip DSP module bitstream verification method of the embodiments of the present invention.

[0188] Figure 7 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0189] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the FPGA chip DSP module bitstream verification method shown in the above embodiments is implemented.

[0190] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0191] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for verifying the bitstream of an FPGA chip DSP module, characterized in that, The method includes: Based on the DSP module to be verified, multiple bitstream files are obtained using a preset bitstream file generation method and then integrated into a bitstream file library. Each bitstream file corresponds to a functional mode of the DSP module to be verified, including multiplication mode, multiply-accumulate mode, pre-add and multiply mode, bypass and enable of input registers, configuration of output registers, rounding mode, and saturation processing. Based on each bitstream file in the bitstream file library, and in conjunction with the wiring physical design file, a two-level routing resolution method is used to obtain the signal path from the SWH port to the DSP module to be verified, and construct a port mapping table, including: Based on the physical connection data between logical units and cabling resources recorded in the cabling physical design file, each port of the DSP module to be verified is used as an anchor point. Tracing analysis is performed along the signal transmission path to perform first-level routing parsing and obtain the first mapping relationship between the port of the DSP module to be verified and the SWH port. Based on the wiring physical design file and the configuration bit segments of the DSP module to be verified in each bit stream file, the selection state of the internal multiplexer corresponding to each bit stream file is obtained. By combining the specific selection state of each internal multiplexer in the functional mode corresponding to each bit stream file, the complete path of each signal in the DSP module is constructed, and the second-level routing parsing is performed to determine the second mapping relationship between the port of the DSP module to be verified and the SWH port. Combining the first and second mapping relationships, a port mapping table is constructed; Based on the port mapping table and the initial verification platform data, the initial verification platform is reconstructed to obtain the reconstructed verification platform; Based on the reconstructed verification platform and combined with the pre-built high-level abstract behavior model, simulation and response capture are performed on all bitstream files in the bitstream file library in sequence. The final verification report is obtained by using the result comparison method. The verification report includes the test pass rate and functional coverage of the DSP module.

2. The method according to claim 1, characterized in that, Based on the physical connection data between logical units and cabling resources recorded in the cabling physical design file, the first-level routing resolution method is used to obtain the first mapping relationship between the ports of the DSP module to be verified and the SWH ports, including: Based on the wiring physical design document, the DSP module, SWH port information and wiring connection relationship between each logic unit are extracted to obtain physical connection relationship data; the physical connection relationship data includes wire connection path, interconnection node and signal transmission direction. Based on the physical connection relationship data, each port of the DSP module to be verified is used as an anchor point, and trace analysis is performed along the signal transmission path to record the correspondence between the current DSP port and the SWH port. Summarize the correspondence between all ports of the DSP module to be verified and the SWH port to obtain the first mapping relationship between the ports of the DSP module to be verified and the SWH port.

3. The method according to claim 1, characterized in that, Based on the wiring physical design file and the configuration bit segments of the DSP module to be verified in each bit stream file, the second-level routing parsing method is used to obtain the selection state of the internal multiplexer corresponding to each bit stream file, and to determine the second mapping relationship between the port of the DSP module to be verified and the SWH port, including: Based on the aforementioned wiring physical design file, the internal structure data of the DSP module to be verified is obtained using a structural data extraction method. The internal structure data includes the number of internal multiplexer groups, the port definition of each multiplexer, the physical connection relationship between the multiplexer and the core logic port of the DSP module, and the association path between the multiplexer and the external port of the DSP module. For each bit stream file in the bit stream file library, the parsing engine is used to interpret the configuration bit fields of the DSP module to be verified, so as to obtain the specific selection state of each internal multiplexer in the functional mode corresponding to the current bit stream file. By combining the specific selection states of each internal multiplexer in the functional mode corresponding to each bit stream file, the complete path of each signal inside the DSP module is constructed, and the second mapping relationship between the port of the DSP module to be verified and the SWH port is determined.

4. The method according to claim 1, characterized in that, The method described above, based on the DSP module to be verified, uses a preset bitstream file generation method to obtain multiple bitstream files, which are then integrated into a bitstream file library, including: Based on the DSP module to be verified, the configuration parameters of each functional mode of the DSP module to be verified are obtained to obtain a configuration list; Based on the configuration list, the configuration parameters of the configuration list are filled into the pre-built bitstream template using the parameter serialization method to obtain the corresponding bitstream file; All bitstream files are numbered and stored in a preset directory to obtain a bitstream file library.

5. The method according to claim 1, characterized in that, The process of reconstructing the initial verification platform based on the port mapping table and the initial verification platform data to obtain the reconstructed verification platform includes: Based on the port correspondence data in the port mapping table, the virtual interface of the initial verification platform is rebound using the interface reconstruction method; Based on the input path relationship data in the port mapping table, an excitation translator is constructed in the excitation generator of the initial verification platform; the excitation translator is used to translate the abstract test vector of the core logic of the DSP module into the drive signal of the SWH output port. Based on the output path relationship data in the port mapping table, a response mapper is constructed in the monitoring component of the initial verification platform; the response mapper is used to reconstruct the raw response data obtained from the SWH input port into the output result of the core logic of the DSP module. Output the reconstructed verification platform.

6. The method according to any one of claims 1 to 5, characterized in that, Based on the reconstructed verification platform and combined with a pre-built high-level abstraction behavior model, the platform sequentially performs simulation and response capture on all bitstream files in the bitstream file library. Using a result comparison method, a final verification report is obtained, including: Based on the reconstructed verification platform and combined with the pre-built high-level abstract behavior model, each bitstream file in the bitstream file library is input for simulation and response capture to obtain a first simulation result and a second simulation result for each bitstream file; wherein, the first simulation result is generated using the reconstructed verification platform and the second simulation result is generated using the high-level abstract behavior model; Based on the first simulation results and the second simulation results, a comparison result is obtained using a result comparison method, and this result is determined as the final verification report.

7. A bitstream verification device for an FPGA chip DSP module, characterized in that, The device includes: The data construction module is used to generate multiple bitstream files based on the DSP module to be verified using a preset bitstream file generation method, and then integrate them into a bitstream file library. Each bitstream file corresponds to a functional mode of the DSP module to be verified. The functional modes include multiplication mode, multiply-accumulate mode, pre-add and multiply mode, bypass and enable of input registers, configuration of output registers, rounding mode, and saturation processing. The mapping and parsing module is used to obtain the signal path from the SWH port to the DSP module under test based on each bit stream file in the bit stream file library, combined with the wiring physical design file, using a two-level routing parsing method, and construct a port mapping table, including: Based on the physical connection data between logical units and cabling resources recorded in the cabling physical design file, each port of the DSP module to be verified is used as an anchor point. Tracing analysis is performed along the signal transmission path to perform first-level routing parsing and obtain the first mapping relationship between the port of the DSP module to be verified and the SWH port. Based on the wiring physical design file and the configuration bit segments of the DSP module to be verified in each bit stream file, the selection state of the internal multiplexer corresponding to each bit stream file is obtained. By combining the specific selection state of each internal multiplexer in the functional mode corresponding to each bit stream file, the complete path of each signal in the DSP module is constructed, and the second-level routing parsing is performed to determine the second mapping relationship between the port of the DSP module to be verified and the SWH port. Combining the first and second mapping relationships, a port mapping table is constructed; The platform reconstruction module is used to reconstruct the initial verification platform based on the port mapping table and the initial verification platform data to obtain the reconstructed verification platform. The result output module is used to simulate and capture responses of all bitstream files in the bitstream file library in sequence based on the reconstructed verification platform and combined with the pre-built high-abstraction behavioral model, and obtain the final verification report using the result comparison method; the verification report includes the test pass rate and functional coverage of the DSP module.

8. An electronic device, characterized in that, include: A memory and a processor are interconnected, the memory stores computer instructions, and the processor executes the computer instructions to perform the FPGA chip DSP module bitstream verification method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute the FPGA chip DSP module bitstream verification method according to any one of claims 1 to 6.

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