Silicon-based substrate structure for semiconductor epitaxial stress regulation and preparation method thereof

Abstract

The invention discloses a silicon-based substrate structure for semiconductor epitaxial stress regulation and control and a preparation method of the silicon-based substrate structure, and belongs to the technical field of semiconductor materials. The method comprises the following steps: firstly prefabricating vacancy gradient in a silicon body by adopting silicon self-ions or inert heavy ions, and then performing helium ion implantation with a relatively low dose, so that helium atoms selectively nucleate in the formed vacancy gradient and grow through unified annealing to obtain a pore volume fraction which continuously changes along with depth. According to the invention, through a division cooperation mechanism of'vacancy prefabrication 'and'helium pore-forming', a coupling relationship between vacancy and gas is not generated by single helium injection any more, so that a pore gradient and a Young modulus gradient which can be designed and continuously adjusted in the thickness direction are realized, the controllability, stability and process compatibility of a pore-forming structure are remarkably improved, and the production cost is reduced. By constructing a modulus gradient structure in the silicon body, the problems of wafer warping, device layer cracking, bonding failure and the like are reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor materials technology, specifically to a silicon substrate with a gradually changing Young's modulus and its preparation method. Background Technology

[0002] Silicon-based materials are widely used in power devices, MEMS, and optoelectronic chips due to their mature structure and high process compatibility. However, in these applications, silicon maintains a consistently high Young's modulus (≈170 GPa) in the vertical direction, making it difficult to effectively absorb thermo-mechanical coupling stress during epitaxial growth, thermal cycling, and packaging. This often leads to problems such as wafer warpage, epitaxial layer cracking, interface delamination, and bonding failure, which become increasingly severe with the scaling up of 8-inch and 12-inch silicon wafers. This contradiction is particularly pronounced in silicon-based GaN epitaxy. Significant lattice and thermal expansion mismatch exists between GaN and Si, resulting in the accumulation of large amounts of tensile stress in the epitaxial layer during the high-temperature MOCVD process and cooling. This often causes severe warpage of large-area GaN on the silicon substrate, leading to cracks and significantly affecting growth uniformity and device yield. Therefore, constructing a continuously tunable Young's modulus gradient structure within the silicon substrate to mitigate thermal mismatch stress, reduce warpage, and improve epitaxial uniformity has become an important technological direction in the field of silicon-based III-V epitaxy.

[0003] The current mainstream method for constructing porous silicon or void layers is to directly apply light ions (such as He). + H + O + High-dose implantation followed by annealing. For example, studies have reported that multiple void layers can be obtained inside silicon by implanting helium ions at different energies and performing stepwise annealing between each implantation step (doi: 10.1016 / S0168-583X(03)00780-8). However, the void formation location is still limited by the ion range peaks corresponding to each energy, exhibiting obvious layering characteristics. To obtain sufficient pore formation, this type of method usually requires the use of 10 16 ~10 17 cm -2 High doses of He + Furthermore, to achieve sufficient pore formation, existing technologies typically employ 10... 16 ~10 17 cm -2 High-dose helium ion implantation. TEM images from related studies show that high-dose He... + The implanted silicon exhibits a high damage band of approximately 200 nm thick (doi: 10.1063 / 5.0096802), accompanied by structural degradation phenomena such as numerous bubbles and localized amorphization, which can adversely affect the structural integrity, mechanical properties, and compatibility with subsequent processes of the material.

[0004] Existing patented technologies involving the construction of porous layers also have significant limitations. For example, CN103065931A provides a Si / Ge heterolayer and a void-assisted epitaxial structure, but the voids are still constructed using a single He layer. + Damage peaks form, exhibiting a typical layered structure and lacking continuous gradient modulation capability. For example, CN120417405A uses H... + He + Constructing localized atomic vacancies to induce metal doping aims at lifetime control, resulting in defect bands with fixed positions and limited depths, without involving the construction of pore gradient or modulus gradient structures. On the other hand, structural improvement schemes for silicon-based GaN, such as CN203910838U, reduce warpage and improve thermal mismatch by introducing oxide layers or cavity structures within the Si substrate, but the depth and distribution of the resulting cavities cannot be continuously adjusted; CN105514231A constructs stress compensation structures within the Si substrate to reduce GaN epitaxial warpage, but its control methods also rely on fixed layered structures, making it impossible to form a continuous and designable mechanical gradient in the thickness direction.

[0005] Therefore, existing direct helium implantation methods generally have the following technical limitations: First, the vacancy distribution cannot be independently controlled and can only passively depend on the damage peak of helium ions; second, the resulting structures are mostly layered void bands, making it difficult to form a continuous or quasi-continuous pore gradient in the thickness direction; third, the accumulation of defects caused by high-dose implantation can easily lead to a decrease in the stability of silicon-based materials. Summary of the Invention

[0006] This invention aims to overcome the shortcomings of the prior art and proposes a new process path for constructing a porosity gradient and Young's modulus gradient inside silicon, which can effectively alleviate thermal and mechanical stress during the process and operation. By constructing a modulus gradient structure inside the silicon body, reliability problems such as wafer warpage, device layer cracking and bonding failure can be reduced.

[0007] This invention overcomes the limitations of existing "direct helium ion implantation + annealing" techniques. It is no longer constrained by the limitation that a single helium ion implantation parameter can only form a localized void layer at a fixed depth. Without introducing heterogeneous materials and complex equipment, it first pre-creates a vacancy gradient within the silicon mass using silicon self-ions or inert heavy ions, decoupling the spatial distribution of vacancy defects from the helium implantation process, allowing for independent design of their depth and concentration distribution. Subsequently, a lower dose of helium ions is used as the gas source, enabling helium atoms to selectively nucleate within the pre-formed vacancy gradient and grow through uniform annealing, ultimately achieving a pore volume fraction that continuously varies with depth. This invention, through a collaborative mechanism of "vacancy pre-creation" and "helium pore formation," eliminates the reliance on a single helium implantation simultaneously generating a coupling relationship between vacancies and gas. This allows for a designable and continuously adjustable pore gradient and Young's modulus gradient in the thickness direction while maintaining a single silicon material system. Furthermore, by combining precise and controllable mechanical grinding / chemical mechanical polishing, the distance between the void gradient layer and the final surface can be controlled within the nanometer range. A functional surface with a well-preserved lattice and excellent flatness can be obtained without the need for epitaxial deposition of a new silicon layer. At the same time, the stress distribution in the thickness direction can be redesigned, which greatly improves the stress control capability and structural reliability.

[0008] Leveraging the aforementioned mechanism, the process structure of this invention remains a single silicon system, allowing for seamless integration into existing power devices and GaN-on-Si process flows, thus exhibiting high process compatibility. Furthermore, this method is particularly suitable for large-size manufacturing scenarios involving 8-inch and 12-inch silicon substrates. Since both the porosity gradient and modulus gradient can be continuously controlled, this invention significantly alleviates the warpage and stress accumulation problems commonly found in large-area wafers at the structural level, offering a significant advantage in addressing the industry's current urgent need for stress engineering in 12-inch silicon wafers.

[0009] The silicon substrate provided by this invention includes three main structural regions, such as Figure 1 As shown, it includes:

[0010] (a) Dense silicon surface layer (undamaged area)

[0011] Located on the outermost surface, it is composed of a native silicon lattice, characterized by lattice integrity, low stress, and high flatness, ensuring the quality of subsequent device fabrication processes, bonding processes, and interfaces. The thickness of the dense silicon surface layer is preferably 100–300 nm.

[0012] (ii) Void gradient layer (functional gradient region)

[0013] Located deep within the silicon wafer, the void gradient layer is formed through pre-fabricated vacancy gradient followed by helium nucleation and annealing. The volume fraction of voids within this region varies continuously or quasi-continuously along the thickness direction, allowing for a designable Young's modulus gradient. The effective thickness of the void gradient layer is preferably 0.2–0.6 μm.

[0014] (III) Dense silicon support layer (substrate region)

[0015] Located beneath the void gradient layer, it provides mechanical support for the entire structure. In this invention, the thickness of the bottom dense silicon support layer is preferably 50–150 μm. This thickness provides sufficient bending stiffness and processing stability, preventing wafer warping or breakage caused by localized softening due to the void layer; on the other hand, its thickness is not too large, so as not to weaken the contribution of the void gradient layer to the overall mechanical behavior. For special applications requiring further thinning, the dense silicon support layer can also be controlled at 10–50 μm according to process requirements and can be used in conjunction with wafer bonding processes.

[0016] A significant structural feature of this invention is that, during the ion implantation stage, a 0.5–3 μm "surface protective layer" is intentionally retained on the silicon surface to prevent complete damage, ensuring that the densest region of voids is initially located deep within the silicon. In the final product, the dense silicon surface layer retained above the void gradient layer is preferably 100–300 nm thick, balancing structural stability and functional gradient effects.

[0017] The technical principles of this invention are explained below.

[0018] (I) Construction principle of vacancy gradient

[0019] When self-ion (Si) + When inert heavy ions are implanted into a silicon lattice, they undergo displacement collisions with silicon atoms, generating vacancies (V) and interstitial atoms (I). The distribution of vacancies along the depth direction depends on the implantation energy, with different energies corresponding to different damage peaks. By implanting multiple energies in successive stages, a continuously varying vacancy distribution along the depth direction can be formed. Vacancies are a necessary condition for subsequent helium bubble nucleation; therefore, the vacancy gradient determines the final spatial distribution of the void layer.

[0020] (II) Helium atom injection and nucleation mechanism

[0021] Helium atoms do not form stable chemical bonds in silicon and have a strong tendency to enter vacancies. When helium is injected into a vacancy-rich region, it combines with vacancies to form He–V complexes, which further aggregate into small bubbles. Because the vacancy gradient is pre-constructed, the nucleation ability of helium atoms at different depths is "guided" to the vacancy-rich region, so that the depth profile of void formation is mainly determined by the vacancy gradient, rather than solely by the helium range peak. This mechanism enables this invention to obtain continuous or quasi-continuous void gradients, rather than the discrete, layered void bands found in traditional processes.

[0022] (III) Annealing and Void Formation Principles

[0023] During high-temperature annealing, small bubbles grow and tend to stabilize into cavities, then some helium escapes, reducing the cavity pressure. The number and volume fraction of cavities are dominated by the vacancy gradient. (Void volume fraction) After continuously varying with depth, the effective modulus of porous materials can be approximated according to commonly used relationships:

[0024]

[0025] This allows us to obtain a continuously varying Young's modulus gradient. In equation (1), E(z) is the effective Young's modulus of the local void layer, and E0 is the intrinsic Young's modulus of dense silicon. Let be the void volume fraction, and k be an empirical coefficient related to the void morphology.

[0026] Specifically, the present invention provides a method for preparing the above-mentioned silicon substrate, such as... Figure 2 As shown, it includes the following steps:

[0027] S1: Substrate selection and pretreatment

[0028] Before constructing the vacancy gradient, CZ silicon substrates or high-purity FZ silicon substrates with controllable oxygen content are preferred. CZ silicon improves vacancy stability through oxygen-vacancy complexes, which is beneficial for enhancing void nucleation density; FZ silicon, on the other hand, has extremely low impurity content, making vacancy diffusion behavior more predictable, which is beneficial for achieving high-precision vacancy gradient control.

[0029] After substrate selection, RCA cleaning and light etching can be performed sequentially. The light etching can use dilute HF or buffered hydrofluoric acid (BOE) to remove a 5–50 nm surface layer, or low-power CF4 / SF6 plasma dry etching can be used to achieve equivalent surface damage layer removal, making the implantation interface more uniform. Before ion implantation, the initial stress state of the silicon substrate is preferably detected using Raman spectroscopy and / or X-ray diffraction, where the Si–LO main peak of the Raman test is relative to the stress-free reference value (approximately 520 cm⁻¹). -2 The offset |Δω| is controlled within 0.1 to 0.2 cm. -1 Within this range, the corresponding in-plane residual stress is approximately |σ| ≤ 50–100 MPa; the wafer macroscopic warpage measured by XRD is preferably less than 30–50 μm. Subsequent vacancy gradient construction and helium implantation steps are only performed when the substrate residual stress is within the aforementioned low stress range, to avoid interference from initial high stress on vacancy diffusion, void nucleation, and subsequent CMP stability.

[0030] S2: Self-ion / heavy ion multi-energy injection (forming a vacancy gradient template)

[0031] A continuously tunable vacancy gradient was constructed by multi-energy self-ion or inert heavy ion implantation. A multi-energy combination of 100–900 keV and 1×10⁻⁶ ions was used.14 ~5×10 15 cm -2 The dosage is layered progressively, creating a vacancy gradient that varies continuously along the depth direction. In this step, the surface 0.5–3 μm depth of the silicon region is intentionally left undamaged. "Strong damage" refers to structural defects such as continuous amorphous regions, large-sized bubble / void clusters, or high-density dislocation loops that remain after annealing. These defects may be characterized by, but are not limited to, continuous amorphous bands or densely packed bubble bands appearing in cross-sectional TEM images, with a void areal density exceeding approximately 10. 9 ~10 10 cm -2 These defects, or those causing significant peak broadening in Raman spectroscopy / XRD, are relatively minor. In contrast, "minor damage" mainly consists of point defects and sparse small defect clusters that can recover during pre-annealing at 200–350 °C, having little impact on the long-range order and macroscopic modulus of the crystal. In engineering applications, Raman spectroscopy can be used for determination; for example, the Raman peak of Si crystal (approximately 520 cm⁻¹) can be used to determine this. -1 The intensity decreased by more than 50%, and a significant amorphous Si broad peak (approximately 480 cm⁻¹) appeared. -1 The area defined is the "highly damaged zone". The reserved 0.5–3 μm surface layer area needs to have its injection conditions controlled so that its defect level is below the above threshold, no continuous amorphous layer is generated, and only minor point defects that can be recovered in subsequent annealing are allowed.

[0032] S3: Low-temperature pre-annealing (200~350℃) stabilizes vacancy structure

[0033] Annealing at 200–350 °C for 5–60 min removes interstitial I atoms, stabilizes vacancies and vacancy clusters, and prevents the vacancy gradient from being destroyed by rapid recombination, thereby maintaining a stable vacancy distribution during subsequent helium injection.

[0034] S4: Helium ion implantation (providing gas source)

[0035] Helium injection is performed while ensuring the range peak covers the vacancy gradient region. Due to the sufficient number of vacancies, the preferred helium injection energy range is 20–600 keV, and the injection dose can be 1 × 10⁻⁶. 15 ~5×10 16 cm -2 It is significantly lower than that of traditional processes.

[0036] S5: Stepped pre-annealing (enhances the continuity of void gradient)

[0037] To ensure the gradual stabilization of He–V complexes at different depths, a stepped pre-annealing process at 300–550°C is performed before the main annealing. This step allows the nucleation centers at different depths to stabilize sequentially, ultimately resulting in a smoother void distribution and a more continuous transition. Preferably, the stepped pre-annealing involves two or more annealing processes with progressively increasing temperatures, with temperature intervals of 50–150°C and each annealing session lasting 5–15 minutes.

[0038] S6: Main annealing (400~900℃), forming a void gradient.

[0039] The main annealing process is carried out at 400–900℃ for 10–30 min, causing the He–V complex to grow into cavities, while some helium escapes to stabilize the cavities. (Void volume fraction) The natural gradient changes continuously with the vacancy gradient, thus achieving a continuous gradient of Young's modulus.

[0040] S7: Stress distribution detection after annealing (to make CMP endpoint control more precise)

[0041] The stress distribution of the void gradient layer is detected by Raman spectroscopy, XRD or photoelasticity, and the amount of subsequent mechanical grinding or CMP (chemical mechanical polishing) removal is adjusted according to the stress distribution results so that the void gradient layer does not collapse or crack when it finally approaches the surface.

[0042] S8: Mechanical polishing or CMP to bring the void gradient layer closer to the final surface.

[0043] This is an indispensable key step in this invention. Because a dense silicon layer is pre-reserved before implantation, the void layer is not directly exposed on the surface. After annealing, Raman spectroscopy is used to scan different depths below the silicon wafer surface. When the first-order Raman phonon peak starts from 520 cm⁻¹... -1 A continuous redshift occurs, and the redshift amount reaches the typical stress response threshold (e.g., |Δω| ≥ 0.10~0.20 cm). -1 By scanning, it can be determined that the scanning position has entered the upper edge region of the void gradient layer. Within the void layer, due to a local decrease in Young's modulus and an increase in pore volume fraction, a more significant Raman softening phenomenon occurs, and the redshift usually increases further. Simultaneously, XRD rocking curves reveal an increase in the full width at half maximum (FWHM) at the corresponding depth of the void layer (typically ≥0.005°), indicating enhanced local lattice relaxation. The Raman redshift and XRD FWHM response allow for quantitative determination of the void gradient layer depth, providing a clear basis for mechanical polishing or CMP endpoint control. This step removes the injected damage layer layer by layer, ultimately bringing the upper edge of the void gradient layer close to the surface, and precisely controlling the distance from the void gradient layer to the surface within 100–300 nm. This method eliminates the need for epitaxial deposition, ensuring a final surface with a complete, flat lattice and free of interface defects.

[0044] Compared to existing direct helium implantation and multi-energy layered pore formation technologies, this invention has the following significant advantages: First, by pre-creating a vacancy gradient through multi-energy self-ion or inert heavy ion implantation, the depth and density of void formation are dominated by vacancy distribution rather than determined by the helium range peak, thus achieving a continuous pore gradient and Young's modulus gradient that cannot be obtained by existing technologies. Second, by decoupling the "vacancy generation – helium pore formation" functions, this invention significantly reduces the required helium implantation dose, effectively avoiding the amorphization, bubbling, and structural degradation problems caused by high-dose helium implantation commonly found in existing technologies. Third, the void layer is located deep within the silicon during the formation stage, allowing for subsequent precise... Polishing / CMP gradually brings the void layer closer to the surface, maintaining the integrity and flatness of the native lattice without relying on epitaxial deposition. Furthermore, the final distance from the void layer to the surface can be controlled at the nanometer level through mechanical polishing, with depth control capabilities far superior to the range controllability of ion implantation itself. The thickness of the void gradient layer, the thickness of the surface dense silicon, and the thickness of the bottom supporting silicon can be independently controlled. Therefore, substantial improvements have been achieved in terms of structural designability, surface quality, stress adjustment capability, and overall process compatibility. The mechanical stability, stress relief capability, modulus transition smoothness, and void layer position controllability of the structure are all significantly better than existing technologies. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the overall structure of the silicon substrate of the present invention, wherein 1 – dense silicon surface layer (undamaged area), 2 – porous gradient layer (functional gradient region), and 3 – dense silicon support layer (substrate region).

[0046] Figure 2 This is a flowchart illustrating the fabrication process of the silicon substrate of this invention. Detailed Implementation

[0047] The technical solution of the present invention will be described in detail below by way of example through embodiments. However, those skilled in the art should understand that the embodiments are not intended to limit the technical solution of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0048] Example 1: Method for fabricating Young's modulus gradient silicon using CZ silicon substrate

[0049] 1. Select 8×10 17 ~1×10 18 cm -3 An 8-inch CZ(100) single-crystal silicon substrate with low oxygen content was subjected to RCA cleaning and surface light etching of 10 nm using dilute HF. Initial stress was then measured using Raman spectroscopy, requiring the Raman shift of the initial residual stress |Δω| < 0.20 cm⁻¹. -1This indicates that the substrate is in a near-intrinsic low-stress state, which can serve as the starting condition for subsequent implantation and annealing.

[0050] 2. Multi-energy Si + Self-ion implantation uses the following combination (Table 1):

[0051] Table 1

[0052]

[0053] A vacancy gradient is formed, decreasing from shallow to deep, with an injection depth ranging from approximately 0.5 to 0.9 μm. During the injection process, a protective layer of approximately 0.6 μm remains undamaged on the surface.

[0054] 3. Anneal at 300℃ for 30 min in an N2 environment. This removes interstitial atoms and maintains a stable vacancy gradient.

[0055] 4. He + The injection was performed in two stages, with energies and doses of: (1) 150 keV and 2×10⁻⁶ keV, respectively. 15 cm -2 (2) 350 keV and 1×10 15 cm -2 This ensures that the range peak (Rp ≈ 0.3~0.9 μm) can largely overlap with the aforementioned vacancy gradient region of 0.5~0.9 μm, thereby forming He–V nucleation centers in the vacancy-rich region.

[0056] 5. Stepped pre-annealing is performed as follows: (1) 350℃×10 min; (2) 450℃×10 min; (3) 550℃×5 min. This process promotes the initial stabilization of small He–V complexes, preventing them from growing rapidly and causing breakage.

[0057] 6. Perform main annealing at 650℃ for 20 min to allow sufficient void formation. A void gradient layer with a thickness of approximately 0.35 μm is obtained, with the void volume fraction decreasing from approximately 10% to 2% along the depth direction.

[0058] 7. Raman spectroscopy was used to measure the position shift of the stress peak near the surface and the void gradient layer (typically Δω < 0.5cm). -1 The depth of CMP removal is determined using a method called Δω, which is used to determine the position shift of the main Si–Si vibration peak on the surface measured by Raman spectroscopy. During the stepwise removal of CMP, the shift Δω of the main peak position of the Si–Si vibration on the surface, measured by Raman spectroscopy, is used as the criterion for adjacent void layers. The absolute value of Δω gradually increases from 0 to 0.1–0.2 cm. -1 When the time is right, it indicates that the upper edge of the void gradient layer has entered the Raman detection range. Stopping CMP at this time will keep the upper edge of the void layer within the optimal range of 100-300 nm from the surface.

[0059] 8. CMP polishing

[0060] The surface damage layer of about 0.35 μm was removed, so that the upper edge of the void layer was finally located 150–200 nm below the surface.

[0061] The final result is: (1) dense silicon surface layer: 150-200 nm; (2) void gradient layer: 350 nm; (3) support layer: 100 μm (original wafer, no damage).

[0062] Example 2: A method for preparing high-precision void gradient silicon using FZ high-purity silicon substrates

[0063] 1. Use resistivity > 1000 FZ(100) monocrystalline silicon (oxygen content <10) 16 cm -3 RCA cleaning followed by 20 nm dry etching was used to ensure uniformity of the implantation interface. The initial stress was measured in the same manner as in Example 1.

[0064] 2. Multi-energy heavy ions (Ag) + For injection, this embodiment uses the following combination (Table 2):

[0065] Table 2

[0066]

[0067] Ultimately, a continuous and narrow vacancy-rich region can be formed in the range of 0.6–1 μm, while retaining an undamaged protective layer of about 0.6 μm on the surface during the injection process.

[0068] 3. Pre-anneal the Si substrate at 400℃ for 30 min to suppress I–V recombination and stabilize vacancies.

[0069] 4. Helium ion implantation conditions: (1) Energy: 200 keV (Rp ≈ 700 nm); (2) Dose: 1×10 15 cm -2 (Low dosage to prevent the connection of broken holes). This creates a "small and controllable" bubble density, making the gradient "finer".

[0070] 5. Stepped pre-annealing is performed using: (1) 300℃ × 15 min; (2) 450℃ × 5 min. This allows the shallow He–V layer to stabilize but not grow excessively.

[0071] 6. The main annealing was carried out at 600℃ for 10 min to complete the formation of voids, resulting in a void gradient layer with a thickness of about 0.35 to 0.4 μm and a volume fraction that decreased continuously from 8% to 1%.

[0072] 7. After the main annealing, this invention utilizes X-ray diffraction (XRD) rocking curves to detect lattice distortion in the silicon wafer surface structure. Due to the presence of nano-voids and localized elastic relaxation regions within the void gradient layer, its scattering characteristics manifest as a measurable increase in the full width at half maximum (FWHM) and the appearance of weak shoulder peaks on the XRD rocking curve. In this invention, the substrate XRD rocking curve after annealing but before polishing is used as the "stress baseline." Subsequently, the surface silicon is gradually removed in small amounts (100–200 nm each time), and the rocking curve is repeatedly measured. As the CMP removal thickness gradually approaches the upper edge of the void gradient layer, the FWHM of the rocking curve shows a continuous and monotonically increasing increase. An FWHM broadening of ≥ 0.005° is used as the threshold for approaching the upper edge of the void layer. When the FWHM broadening reaches this threshold and a identifiable shoulder peak begins to appear on the rocking curve, it can be determined that the CMP has approached the upper edge of the void gradient layer. Subsequently, only a small amount of removal of about 50 to 150 nm is needed to ensure that the upper edge of the void layer is eventually stably located within the target depth range of 100 to 300 nm on the silicon surface, providing a reliable endpoint control basis for forming the final structure with a continuous modulus gradient.

[0073] 8. Based on the stress distribution, 0.5 μm of the surface layer was removed using CMP, and the upper edge of the final void layer was located 100 nm below the surface.

[0074] Final structure: (1) Dense surface layer: 100 nm; (2) Void gradient layer: 200 nm; (3) Support layer: 150 μm.

[0075] Example 3: Method for fabricating Young's modulus graded silicon substrates based on Si(111) single crystal substrates

[0076] This embodiment is based on a (111) crystal orientation silicon substrate to illustrate that the present invention is applicable to different crystal orientations.

[0077] 1. 8-inch high-purity FZ Si(111) single-crystal wafers with resistivity >1000 were selected. Oxygen content <10 16 cm -3 The primary oxide layer of 5–8 nm was removed using RCA-SC1 / SC2 cleaning and dilute HF. The initial stress was measured in the same manner as in Example 1.

[0078] 2. Utilizing Si + Ion implantation was used to construct vacancy-rich regions at depths ranging from 0.5 to 1.0 μm. The implantation energy and dose were combined as follows (Table 3):

[0079] Table 3

[0080]

[0081] The injection depth ranges from approximately 0.5 to 1 μm. During the injection process, a protective layer of approximately 0.5 μm remains undamaged on the surface.

[0082] 3. Annealing was performed at 300℃ for 30 min in an N2 environment. (111) Higher vacancy migration energy in the crystal orientation makes the vacancy gradient more stable at this stage.

[0083] 4. Inject helium ions. To position the helium range peak at the center of the vacancy gradient (approximately 0.75 μm), the energy and dose selected are 450 keV (Rp≈0.74 μm) and 1×10⁻⁶ kilovolts, respectively. 15 cm -2 .

[0084] 5. Stepped pre-annealing is performed at: (1) 350℃ × 10 min; (2) 500℃ × 10 min.

[0085] 6. Perform primary annealing at 650℃ for 15 min to allow small bubbles to grow into stable cavities and produce porosity that varies continuously with depth. The thickness of the void gradient layer was approximately 0.3–0.4 μm.

[0086] 7. After annealing, the change in the full width at half maximum (FWHM) of the Si(111) reflection peak was observed using XRD or Δω was observed using Raman spectroscopy. The final removal thickness was determined using the same determination method as in Examples 1 and 2.

[0087] 8. In this embodiment, the CMP removal amount is set to 0.35 μm, so that the upper edge of the void layer is located 150 nm below the surface.

[0088] Final structure: (1) Dense surface layer: 150 nm; (2) Void gradient layer: 300 nm; (3) Support layer: ≥100 μm.

Claims

1. A silicon substrate, characterized in that, It includes a dense silicon surface layer, a void gradient layer and a dense silicon support layer, wherein the void gradient layer is located between the dense silicon surface layer and the dense silicon support layer, and the void volume fraction inside it varies continuously or quasi-continuously along the thickness direction, and has a gradually changing Young's modulus gradient.

2. The silicon substrate as claimed in claim 1, characterized in that, The thickness of the dense silicon surface layer is 100–300 nm, the thickness of the void gradient layer is 0.2–0.6 μm, and the thickness of the dense silicon support layer is 50–150 μm.

3. A method for preparing a silicon substrate with a gradually varying Young's modulus, comprising the following steps: S1: Select a CZ silicon substrate or an FZ silicon substrate and clean the surface; S2: A vacancy gradient region that varies continuously along the depth direction is formed in the silicon substrate by implanting multi-energy self-ions or inert heavy ions; S3: The silicon substrate is pre-annealed at 200-350°C to remove interstitial atoms and stabilize the vacancy structure; S4: Helium implantation is performed on the silicon substrate while ensuring that the range peak covers the vacancy gradient region; S5: Perform step-by-step pre-annealing on the silicon substrate within a temperature range of 300 to 550°C to stabilize the He–V complex at different depths segment by segment. S6: The silicon substrate is subjected to main annealing at 400-900℃, which causes the He-V complex to grow into a void, while some helium escapes to stabilize the void. S7: Stress distribution detection on silicon substrate; S8: Perform mechanical polishing or chemical mechanical polishing on the surface of the silicon substrate to remove the implanted damaged layer and control the distance from the void gradient layer to the surface.

4. The preparation method according to claim 3, characterized in that, In step S1, the silicon substrate surface is subjected to RCA cleaning, followed by light etching of 5–50 nm.

5. The preparation method according to claim 3, characterized in that, In step S2 a multi-energy combination of 100-900 keV is used, 1x10 14 ~5x10 15 cm -2 doses are superimposed layer by layer, and the surface layer 0.5-3 μm deep silicon region is not damaged by strong damage.

6. The preparation method according to claim 3, characterized in that, Step S3 involves annealing at 200–350°C for 5–60 min.

7. The preparation method according to claim 3, characterized in that, The helium implantation energy in step S4 ranges from 20 to 600 keV, and the implantation dose is 1 x 1014cm 15 ~ 5 x 1014 16 cm -2 .

8. The preparation method according to claim 3, characterized in that, The stepped pre-annealing in step S5 involves two or more annealing processes with progressively increasing temperatures, with a temperature interval of 50–150°C and an annealing time of 5–15 minutes for each process.

9. The preparation method according to claim 3, characterized in that, The main annealing time in step S6 is 10 to 30 minutes.

10. The preparation method according to claim 3, characterized in that, Step S7: Quantitative calibration of the depth position of the cavity gradient layer after annealing by Raman peak red shift and / or XRD rocking curve half-peak width response, providing the basis for mechanical polishing or chemical mechanical polishing endpoint control; wherein, by scanning different depths below the surface of the silicon wafer through Raman spectroscopy, when the Raman first-order phonon peak is red shifted from 520 cm -1 a continuous red shift occurs, and the red shift reaches a typical stress response threshold, i.e. it is determined that the scanning position enters the upper edge region of the cavity gradient layer; through XRD rocking curve detection, it is observed that the diffraction half-peak width increases at the depth corresponding to the cavity gradient layer, indicating that the local lattice relaxation is enhanced.

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