Silicon controlled rectifier power regulator and control method and system thereof

Abstract

The invention provides a silicon controlled rectifier power regulator and a control method and system thereof. The control method of the silicon controlled rectifier power regulator comprises the steps of obtaining a preset current distribution parameter and a target duty ratio, obtaining an optimized duty ratio, and obtaining a total input current of each phase; and obtaining a target switching state of the silicon controlled rectifier power regulator in each switching period according to the input total current of each phase and the current distribution parameter. And when the input voltage of the silicon-controlled power regulator is zero, controlling the on-off of the silicon-controlled power regulator according to the target switching state of the silicon-controlled power regulator in the current switching period. Therefore, according to the control method of the silicon controlled rectifier power regulator, the silicon controlled rectifier power regulator and the silicon controlled rectifier power regulation system provided by the invention, the balance degree of the three-phase input current, the heating uniformity of the load and the temperature control accuracy can be improved.

Description

Technical Field

[0001] This application relates to the field of electrical control, specifically to a thyristor power regulator and its control method and system. Background Technology

[0002] Thyristor power regulators typically employ zero-crossing control to regulate their output power. However, for thyristor power regulators with three-phase inputs and multi-channel outputs, existing zero-crossing control methods result in low current balance at the three-phase inputs. Furthermore, in applications where the load of the thyristor power regulator is a heating element, existing zero-crossing control methods may also lead to low temperature control accuracy and significant temperature fluctuations in the heating element. Summary of the Invention

[0003] In view of the above problems, this application provides a thyristor power regulator and its control method and system.

[0004] In a first aspect, this application provides a control method for a silicon controlled rectifier (SCR) power regulator, comprising: acquiring preset current distribution parameters and a target duty cycle; obtaining an optimized duty cycle based on the target duty cycle and a preset duty cycle coefficient; obtaining the total input current per phase based on the optimized duty cycle and the current distribution parameters; obtaining the target switching state of the SCR power regulator in each switching cycle based on the total input current per phase and the current distribution parameters; and controlling the switching of the SCR power regulator when the input voltage of the SCR power regulator is zero, according to the target switching state of the SCR power regulator in the current switching cycle.

[0005] In one implementation, the control method further includes: acquiring the output parameters of the thyristor power regulator; and obtaining the duty cycle coefficient based on the preset rated parameters and output parameters.

[0006] In one implementation, the current distribution parameters include a load current coefficient, and the control method further includes: obtaining the load current coefficient based on the resistance of the load of the thyristor power regulator; and obtaining the total input current per phase based on the optimized duty cycle and load current parameters.

[0007] In one implementation, the output parameters include the effective value of the output voltage and the effective value of the output current. The control method further includes: when the resistance of the load of the thyristor power regulator is variable, obtaining the load resistance of the thyristor power regulator based on the effective value of the output voltage and the effective value of the output current.

[0008] In one implementation, the output parameters include the output active power, and the corresponding rated parameters include the rated power. The control method further includes using the ratio of the rated power to the output active power as the duty cycle coefficient.

[0009] In one implementation, the rated parameters include the rated current, and the control method further includes: when the resistance of the load of the thyristor power regulator is variable, using the ratio of the rated current to the effective value of the output current as the duty cycle coefficient.

[0010] In one implementation, the rated parameters include the rated voltage, and the control method further includes: when the resistance of the load of the thyristor power regulator is constant, using the ratio of the rated voltage to the effective value of the output voltage as the duty cycle coefficient.

[0011] In one implementation, the current distribution parameters include a control cycle and an algorithm cycle. The control cycle includes m algorithm cycles, and the algorithm cycle includes n switching cycles, where n and m are positive integers. The control method further includes: obtaining the total input current of each phase based on the optimized duty cycle and load current coefficient; obtaining the algorithm cycle current based on the total input current of each phase and n; obtaining the switching cycle current based on the algorithm cycle current and m; and obtaining the target switching state of each output channel of the thyristor power regulator in each switching cycle based on the switching cycle current, thus obtaining the target switching state of the thyristor power regulator in each switching cycle.

[0012] Secondly, this application provides a thyristor power regulator, comprising: multiple input terminals and multiple output terminals, wherein the number of output terminals is greater than the number of input terminals; multiple thyristor components connected to the input terminals and the output terminals; and a main control chip connected to the multiple thyristor components, used to execute the control method of the first aspect to control the on / off state of the thyristor components.

[0013] Thirdly, this application provides a thyristor power regulation system, comprising: a thyristor power regulator as described in the second aspect; a circuit breaker connected to the input terminal; and multiple loads connected to the output terminal.

[0014] Therefore, the thyristor power regulator and its control method and system provided in this application can optimize the target duty cycle and distribute the total three-phase input current to each switching cycle and each output channel according to the current distribution parameters. By adjusting the switching state of the thyristor power regulator in each switching cycle and each output channel, current distribution can be achieved, thereby improving the balance of the three-phase input current, the heating uniformity of the load, and the temperature control accuracy. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the thyristor power regulation system provided in this application.

[0016] Figure 2 A schematic diagram of the thyristor power regulator provided in this application.

[0017] Figure 3 A flowchart of the control method for the thyristor power regulator provided in this application. Detailed Implementation

[0018] The technical solutions in the embodiments of this application will be clearly described below with reference to the accompanying drawings.

[0019] It is understood that the connection relationships described in this application refer to direct or indirect connections. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components. For example, A can be directly connected to C, and C can be directly connected to B, thus achieving a connection between A and B through C. It is also understood that the "A connects to B" described in this application can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0020] In the description of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists alone, A and B exist simultaneously, and B exists alone.

[0021] In the description of this application, the words "first," "second," etc., are used only to distinguish different objects and do not limit the quantity or order of execution, nor do they imply that they must be different. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0022] Please see Figure 1 , Figure 1 This is a schematic diagram of the thyristor power regulation system provided in this application.

[0023] The thyristor power regulation system includes a thyristor power regulator 10, a circuit breaker 20, and multiple loads 30. The thyristor power regulator 10 includes multiple input terminals I1 and multiple output terminals O1. The circuit breaker 20 is connected to the multiple input terminals I1, and the loads 30 are connected to the output terminals O1.

[0024] In this embodiment, the number of output terminals O1 is greater than the number of input terminals I1. A path from one input terminal I1 to one output terminal O1 constitutes a thyristor power regulation channel. Multiple output terminals O1 are connected to the same input terminal I1, forming multiple thyristor power regulation channels. One output terminal O1 constitutes one output channel.

[0025] For example, the plurality of input terminals I1 includes three input terminals I1, which are respectively denoted as the first input terminal I11, the second input terminal I12, and the third input terminal I13. The plurality of output terminals O1 includes M first output terminals O11, N second output terminals O12, and P third output terminals O13. The M first output terminals O11 are respectively connected to the first input terminals I11, the N second output terminals O12 are respectively connected to the second input terminals I12, and the P third output terminals O13 are respectively connected to the third input terminals I13.

[0026] In one embodiment, the circuit breaker 20 includes a three-phase circuit breaker, which has three phase output terminals, referred to simply as phase terminals, and denoted as the first phase terminal L1, the second phase terminal L2, and the third phase terminal L3, respectively. The plurality of input terminals I1 includes three input terminals I1, at least two of which are respectively connected to at least two phase terminals of the three-phase circuit breaker. The load 30 can be configured with at least one of the following: three-phase delta connection, three-phase Y connection, two-phase three-wire connection, and two-phase AC connection.

[0027] Input terminal I1 is used to connect a power signal, and output terminal O1 is used to connect a load 30. For example, in the field of photovoltaic fabrication, the load 30 can be a heating element such as a furnace tube, which is used to heat the silicon wafers during the photovoltaic cell fabrication process. The power signal can come from the output voltage of an AC power source, the mains voltage, etc.

[0028] The thyristor power regulator 10 can control the transmission of the power signal received from the input terminal I1 to the corresponding load 30 by turning it on and off. For example, by adjusting the duty cycle and switching state of the thyristor power regulator 10, the current, power, voltage, etc. output by the thyristor power regulator 10 to the load 30 can be adjusted, thereby controlling the heating time, heating temperature, etc. of the load 30.

[0029] Please see Figure 2 , Figure 2 This is a schematic diagram of the thyristor power regulator 10 provided in this application.

[0030] The thyristor power regulator 10 includes a main control chip 1, a control circuit 31, a thyristor chip 32, and an electrical signal detection circuit 33. The control circuit 31 is connected to the main control chip 1 and the thyristor chip 32, and the electrical signal detection circuit 33 is also connected to the main control chip 1 and the thyristor chip 32. The electrical signal detection circuit 33 is configured to detect the electrical signals output by the thyristor chip 32, including, for example, voltage, current, power, quantity, frequency, and peak current.

[0031] The control circuit 31 is used to trigger and control the silicon controlled rectifier (SCR) chip 32. For example, the control circuit 31 includes at least one SCR output optocoupler. In one embodiment, multiple SCR output optocouplers can be cascaded to improve the voltage withstand level of the control circuit 31, thereby improving the reliability of the SCR chip 32.

[0032] In this embodiment, a silicon controlled rectifier (SCR) chip 32 is used directly, instead of an integrated SCR module. The advantage is that the SCR chip 32 has high temperature resistance, enabling it to operate normally below 60 degrees Celsius and within its rated operating range of 60 to 80 degrees Celsius. The SCR chip 32 can be either a unidirectional or bidirectional SCR chip.

[0033] The electrical signal detection circuit 33 includes a load current detection circuit 331, a load voltage detection circuit 332, and an electrical metering chip 333. The load current detection circuit 331 is coupled between the thyristor chip 32 and each output terminal. The load current detection circuit 331 and the load voltage detection circuit 332 are respectively connected to the electrical metering chip 333, which is connected to the main control chip 1. The load current detection circuit 331 performs current detection through a sampling resistor or a current transformer. The load voltage detection circuit 332 is used for the voltage input of the electrical metering chip 333. As configurable input and output hardware, the load voltage selection can be changed according to the configuration. The electrical metering chip 333 is used for measuring electrical signals, serving as input parameters for various control algorithms, protection functions, and anomaly detection of the thyristor power regulator, and also as a basic parameter for energy consumption analysis.

[0034] The electrical signal detection circuit 33 can be connected to the main control chip 1 via any one of the following interfaces: SPI interface, I2C interface, UART interface, and I / O interface. The main control chip 1 uses these interfaces to obtain electrical performance measurement results and control the thyristor chip 32.

[0035] The thyristor power regulator 10 also includes multiple temperature control inputs for receiving temperature control signals. These signals control the output power of the thyristor power regulator 10 to stabilize the actual load temperature at a target temperature. Exemplarily, the multiple temperature control inputs include a digital temperature control input I21, an analog temperature control input I22, and a communication temperature control input I23.

[0036] The temperature control digital input terminal I21 is used to input a digital signal for controlling the temperature. For example, when the input to the temperature control digital input terminal I21 is high, the SCR chip 32 is enabled; otherwise, the SCR chip 32 is disabled. The temperature control digital input terminal I21 is suitable for zero-crossing SCR control.

[0037] The temperature control analog input terminal I22 is used to input the analog signal for temperature control. The level of the input at the temperature control analog input terminal I22 describes the magnitude of an output control percentage. The meaning of this percentage is determined according to the control algorithm, thereby controlling the operating state of the thyristor chip 32.

[0038] The temperature control communication input terminal I23 transmits the output control percentage through the communication protocol, determines the meaning of this percentage according to the control algorithm, configures various control algorithms and parameters through the communication protocol, and queries the operating status of the thyristor power regulator.

[0039] The main control chip 1 also includes a variety of thyristor control algorithm modules. The thyristor control algorithm modules are configured to control the output power of the thyristor chip 32 based on temperature control signals, electrical signals and the opening or closing of the control circuit 31.

[0040] For example, various thyristor control algorithm modules include zero-crossing control algorithm module, phase control algorithm module, zero-position fixed-cycle power output adjustment algorithm module, zero-position variable-cycle power output adjustment algorithm module, zero-position voltage limiting power adjustment algorithm module, phase and current limiting algorithm module, phase and constant current algorithm module, output current and voltage monitoring algorithm module, three-phase current detection algorithm module, phase and voltage limiting algorithm module, phase and constant voltage algorithm module, phase and voltage limiting and current limiting algorithm module, phase and power limiting algorithm module, phase and constant power algorithm module, zero-crossing three-phase balance control algorithm module, and zero-crossing peak power reduction algorithm module.

[0041] The thyristor power regulator 10 also includes a zero-crossing detection circuit 5, connected to the main control chip 1. The zero-crossing detection circuit 5 is configured independently and modularly, facilitating interrupt handling by the main control chip 1. The zero-crossing detection circuit 5 is used to perform zero-crossing detection, indicating the time start point of the thyristor control algorithm module. The zero-crossing detection circuit 5 can be shared by multiple thyristor power regulators 10.

[0042] Multiple temperature control input terminals can be selected based on configuration information. For example, one of the following can be selected as the target temperature control input terminal: temperature control digital input terminal I21, temperature control analog input terminal I22, or temperature control communication control input terminal I23. Each temperature control input terminal includes multiple temperature control input ports, and each temperature control input port corresponds to one SCR power regulation channel. For example, when the SCR power regulator 10 includes M+N+P SCR power regulation channels, the SCR power regulator 10 includes M+N+P temperature control input ports, thereby forming an M+N+P power regulation circuit.

[0043] The following is combined with Figure 2 The working principle of the thyristor power regulator 10 is explained in detail.

[0044] First, the main control chip 1 acquires preset current allocation parameters and a target duty cycle. The preset current allocation parameters include information for each load 30, such as load type, rated load resistance, load current coefficient, load voltage, current, upper and lower power limits, current imbalance fluctuation range, control cycle, and algorithm cycle. The control cycle is one complete cycle in which the main control chip 1 controls the switching of the thyristor chip 32. The algorithm cycle is the execution cycle of the thyristor control algorithm module. The control cycle includes multiple algorithm cycles, which in turn include multiple switching cycles. The switching cycle is the minimum time for the thyristor chip 32 to perform one switching operation. The load current coefficient is related to the load's resistance and is used to characterize the proportion of current to be allocated to that load 30. The target duty cycle is related to the effective value of the output voltage, effective value of the output current, and output power of the thyristor power regulator 10; the larger the target duty cycle, the larger the effective value of the output voltage, effective value of the output current, and output power of the thyristor power regulator 10.

[0045] In some embodiments, the current distribution parameters can be obtained by reading configuration data. The configuration data can be stored in the memory of the thyristor power regulator 10, or received from an external device via at least one of the temperature control digital input terminal I21, temperature control analog input terminal I22, and temperature control communication control input terminal I23. The target duty cycle can be received from an external device via at least one of the temperature control digital input terminal I21, temperature control analog input terminal I22, and temperature control communication control input terminal I23. The external device can be a higher-level controller.

[0046] In some embodiments, the control cycle is the same as that of the upper-level controller. Thus, the corresponding control of the thyristor power regulator 10 by the upper-level controller and the corresponding control of the thyristor chip 32 by the main control chip 1 can be synchronized, thereby achieving stable and precise control of the thyristor power regulator 10.

[0047] In some embodiments, the algorithm cycle includes 10-20 switching cycles. This reduces the risk of performance degradation and decreased control accuracy caused by long on / off times of the thyristor chip 32 in one algorithm cycle, while also facilitating the reasonable and periodic allocation of current to each output terminal O1.

[0048] In some embodiments, the load current coefficient can be determined based on the load resistance. Specifically, when the load resistance is a variable resistance, the load resistance can be determined by the effective values ​​of the current and voltage across the load detected by the load current detection circuit 331 and the load voltage detection circuit 332. When the load resistance is a constant resistance, the specific resistance value of the load can be stored in the memory of the thyristor power regulator 10 and determined by reading it. Alternatively, it can be received from an external device via at least one of the temperature control digital input terminal I21, temperature control analog input terminal I22, and temperature control communication control input terminal I23. Alternatively, it can be detected through methods such as the system self-test process of the thyristor power regulator 10.

[0049] Secondly, the main control chip 1 obtains the optimized duty cycle based on the target duty cycle and the preset duty cycle coefficient. The preset duty cycle coefficient can be obtained by acquiring the output parameters of the thyristor power regulator 10 and using preset rated parameters and output parameters. The optimized duty cycle is the product of the target duty cycle and the preset duty cycle coefficient.

[0050] Specifically, the output parameters include the RMS value of the output current, the RMS value of the output voltage, and the output active power. These output parameters can be detected by the load current detection circuit 331 and the load voltage detection circuit 332, and then transmitted to the electricity metering chip 333. The main control chip 1 can select a specific thyristor control algorithm module and obtain the duty cycle coefficient based on preset rated parameters and output parameters. For example, the main control chip 1 can select a constant power algorithm module, using the ratio of rated power to output active power as the duty cycle coefficient. As another example, for applications where load 30 is a fixed resistance load, the main control chip 1 can select a constant voltage algorithm module, using the ratio of rated voltage to the RMS value of the output voltage as the duty cycle coefficient. Furthermore, for applications where load 30 is a variable resistance load, the main control chip 1 can select a constant current algorithm module, using the ratio of rated current to the RMS value of the output current as the duty cycle coefficient.

[0051] In some embodiments, the power metering chip 333 and / or the main control chip 1 can filter the output parameters, thereby reducing the rapid / abnormal fluctuations in the output parameters caused by rapid / abnormal fluctuations in the power signal due to surges, lightning strikes, sudden load changes, etc.

[0052] In some embodiments, when the calculated optimized duty cycle is greater than a preset duty cycle limit, the main control chip 1 can use the preset duty cycle limit as the final optimized duty cycle. The preset duty cycle limit can be obtained from the configuration data.

[0053] Thus, by obtaining an optimized duty cycle based on the target duty cycle and the preset duty cycle coefficient, the output power inconsistency of the thyristor power regulator 10 caused by power supply voltage fluctuations or load resistance changes can be reduced. By optimizing the duty cycle, the thyristor power regulator 10 can maintain a sensitive response speed and stable output under environments such as power supply voltage fluctuations and load resistance changes.

[0054] Then, the main control chip 1 obtains the total input current of each phase based on the optimized duty cycle and current distribution parameters. Specifically, the main control chip 1 uses the product of the load current coefficient and the optimized duty cycle as the total input current of the current output terminal O1. The main control chip 1 can also use the sum of the total input currents of all output terminals O1 for each corresponding phase as the total input current of that phase, thus obtaining the total input current of each phase.

[0055] After obtaining the total input current for each phase, the main control chip 1 calculates the algorithm cycle current based on the total input current for each phase and the number of algorithm cycles *m* included in a control cycle. Specifically, the algorithm cycle current is the total current for each phase divided by *m*. Subsequently, the main control chip 1 calculates the switching cycle current based on the algorithm cycle current and the number of switches *n* included in an algorithm cycle. Specifically, the switching cycle current is the algorithm cycle current divided by *n*.

[0056] The main control chip 1 can generate the target switching state of each output terminal O1 according to the switching cycle current, and evenly distribute the total input current of each phase to each output terminal O1 in each algorithm cycle. This ensures that the current output by the thyristor power regulator 10 is equal in each switching cycle, and that only one output terminal O1 is turned on in each switching cycle. In this way, the switching states of each output terminal O1 are evenly distributed in each switching cycle, which can improve the heating control accuracy of the load 30, reduce the peak current of the thyristor power regulator 10, improve the balance of the three-phase input current, and reduce the impact on the power grid.

[0057] In some embodiments, after the main control chip 1 generates the target switching state for each output terminal O1 corresponding to the switching cycle, it can perform a balance check on it to ensure that the balance of the three-phase input current meets the actual requirements or is within the range required by the configuration data in each switching cycle.

[0058] In some embodiments, after the main control chip 1 generates the target switching state of the switching cycle corresponding to each output terminal O1, it can check whether the target switching state corresponding to each output terminal O1 in each algorithm cycle has been allocated. If not, the target switching state of the switching cycle corresponding to each output terminal O1 is regenerated for the unallocated algorithm cycles.

[0059] In some embodiments, after the main control chip 1 generates the target switching state of the switching cycle corresponding to each output terminal O1, it can detect changes in the power supply voltage and / or load resistance. In the corresponding algorithm cycle, the detected changes in the power supply voltage and / or load resistance are applied again to generate the target switching state of the switching cycle corresponding to each output terminal O1. This allows the target switching state of the switching cycle corresponding to each output terminal O1 to be dynamically adjusted based on changes in the power supply voltage and / or load resistance, thereby improving the dynamic response and stability of the thyristor power regulator 10.

[0060] When the input voltage of the thyristor power regulator 10 is zero, the main control chip 1 controls the switching of the thyristor power regulator 10 according to the target switching state of the thyristor power regulator 10 in the current switching cycle. Specifically, when the power supply voltage is zero, the main control chip 1 controls the thyristor chip 32 to be turned on or off according to the previously obtained target switching state, thereby controlling the switching state of one of the output terminals O1. In this way, the thyristor power regulator 10 adopts a zero-crossing control switching control method, resulting in smaller output current and / or voltage harmonic distortion and less impact on the power grid.

[0061] Please see Figure 3 , Figure 3 A flowchart illustrating the control method for the thyristor power regulator provided in this application. The control method for the thyristor power regulator can be executed by the thyristor power regulator 10. The control method specifically includes the following steps.

[0062] Step S1: Obtain the preset current distribution parameters and target duty cycle.

[0063] The current distribution parameters can be obtained by reading configuration data. This configuration data can be stored in the memory of the thyristor power regulator 10, or received from an external device via at least one of the temperature control digital input terminal I21, temperature control analog input terminal I22, and temperature control communication control input terminal I23. The target duty cycle can be received from an external device via at least one of the temperature control digital input terminal I21, temperature control analog input terminal I22, and temperature control communication control input terminal I23. The external device can be a higher-level controller. The preset current distribution parameters include information for each load 30, such as load type, load rated resistance, load current coefficient, load voltage, current, upper and lower power limits, current imbalance fluctuation range, control cycle, and algorithm cycle.

[0064] Step S2: Obtain the optimized duty cycle based on the target duty cycle and the preset duty cycle coefficient.

[0065] The preset duty cycle coefficient can be obtained by acquiring the output parameters of the thyristor power regulator 10 and based on the preset rated parameters and output parameters. The optimized duty cycle is the product of the target duty cycle and the preset duty cycle coefficient.

[0066] Thus, by obtaining an optimized duty cycle based on the target duty cycle and the preset duty cycle coefficient, the output power inconsistency of the thyristor power regulator 10 caused by power supply voltage fluctuations or load resistance changes can be reduced. By optimizing the duty cycle, the thyristor power regulator 10 can maintain a sensitive response speed and stable output under environments such as power supply voltage fluctuations and load resistance changes.

[0067] Step S3: Based on the optimized duty cycle and current distribution parameters, obtain the total input current for each phase.

[0068] Specifically, the main control chip 1 uses the product of the load current coefficient and the optimized duty cycle as the total input current of the current output terminal O1. The main control chip 1 can also use the sum of the total input current of all corresponding output terminals O1 as the total input current of that phase, thereby obtaining the total input current of each phase.

[0069] Step S4: Obtain the algorithm cycle current based on the total input current of each phase and the number of algorithm cycles m included in a control cycle.

[0070] Specifically, the algorithm cycle current is the total current per phase divided by m. Then, the main control chip 1 obtains the switching cycle current based on the algorithm cycle current and the number of switches n included in an algorithm cycle. Specifically, the switching cycle current is the algorithm cycle current divided by n.

[0071] Step S5: Generate the target switching state for each output terminal O1 corresponding to the switching cycle based on the switching cycle current.

[0072] Specifically, based on the switching cycle current, the total input current of each phase is evenly distributed across each output terminal O1 in each algorithm cycle, thereby ensuring that the current output by the thyristor power regulator 10 is equal in each switching cycle, and that only one output terminal O1 is turned on in each switching cycle. In this way, the switching states of each output terminal O1 are evenly distributed in each switching cycle, which improves the heating control accuracy of the load 30, reduces the peak current of the thyristor power regulator 10, improves the balance of the three-phase input current, and reduces the impact on the power grid.

[0073] Step S6: When the input voltage of the thyristor power regulator 10 is zero, control the switching on and off of the thyristor power regulator 10 according to the target switching state of the thyristor power regulator 10 in the current switching cycle.

[0074] Specifically, when the power supply voltage is zero, the main control chip 1 controls the corresponding turn-on or turn-off of the thyristor chip 32 based on the previously obtained target switching state, thereby controlling the switching state of one of the output terminals O1. In this way, the thyristor power regulator 10 adopts a zero-crossing control switching method, resulting in smaller output current and / or voltage harmonic distortion and less impact on the power grid.

[0075] Therefore, the control method, the thyristor power regulator, and the thyristor power regulation system provided in this application can optimize the target duty cycle and distribute the total three-phase input current to each switching cycle and each output channel according to the current distribution parameters. By adjusting the switching state of the thyristor power regulator in each switching cycle and each output channel, current distribution can be achieved, thereby improving the balance of the three-phase input current, the heating uniformity of the load, and the temperature control accuracy.

[0076] Those skilled in the art should recognize that the above embodiments are only used to illustrate this application and are not intended to limit this application. Any appropriate changes and variations made to the above embodiments within the essential spirit and scope of this application fall within the scope of protection claimed in this application.

Claims

1. A control method for a silicon controlled rectifier (SCR) power regulator, characterized in that, include: Obtain the preset current distribution parameters and target duty cycle; The optimized duty cycle is obtained based on the target duty cycle and the preset duty cycle coefficient. Based on the optimized duty cycle and the current distribution parameters, the total input current for each phase is obtained; Based on the total input current of each phase and the current distribution parameters, the target switching state of the thyristor power regulator in each switching cycle is obtained; When the input voltage of the thyristor power regulator is zero, the on / off state of the thyristor power regulator is controlled according to the target switching state of the thyristor power regulator in the current switching cycle.

2. The control method for the thyristor power regulator as described in claim 1, characterized in that, The control method further includes: Obtain the output parameters of the thyristor power regulator; The duty cycle coefficient is obtained based on the preset rated parameters and the output parameters.

3. The control method for the thyristor power regulator as described in claim 2, characterized in that, The current distribution parameters include the load current coefficient, and the control method further includes: The load current coefficient is obtained based on the resistance of the load of the thyristor power regulator; The total input current for each phase is obtained based on the optimized duty cycle and the load current parameters.

4. The control method for the thyristor power regulator as described in claim 3, characterized in that, The output parameters include the effective value of the output voltage and the effective value of the output current, and the control method further includes: When the resistance of the load of the thyristor power regulator is variable, the load resistance of the thyristor power regulator is obtained based on the effective value of the output voltage and the effective value of the output current.

5. The control method for the thyristor power regulator as described in claim 2, characterized in that, The output parameters include output active power; correspondingly, the rated parameters include rated power; the control method further includes: The ratio of the rated power to the output active power is used as the duty cycle coefficient.

6. The control method for the thyristor power regulator as described in claim 4, characterized in that, The rated parameters include the rated current, and the control method further includes: When the resistance of the load of the thyristor power regulator is variable, the ratio of the rated current to the effective value of the output current is used as the duty cycle coefficient.

7. The control method for the thyristor power regulator as described in claim 4, characterized in that, The rated parameters include the rated voltage, and the control method further includes: When the resistance of the load of the thyristor power regulator is constant, the ratio of the rated voltage to the effective value of the output voltage is used as the duty cycle coefficient.

8. The control method for the thyristor power regulator as described in claim 3, characterized in that, The current distribution parameters include a control cycle and an algorithm cycle. The control cycle includes m algorithm cycles, and the algorithm cycle includes n switching cycles, where n and m are positive integers. The control method further includes: The total input current per phase is obtained based on the optimized duty cycle and the load current coefficient. Based on the total input current of each phase and m, the algorithm periodic current is obtained; Based on the algorithm periodic current and n, the switching periodic current is obtained; Based on the switching cycle current, the target switching state of each output channel of the thyristor power regulator in each switching cycle is obtained, so as to obtain the target switching state of the thyristor power regulator in each switching cycle.

9. A thyristor power regulator, characterized in that, include: Multiple input terminals and multiple output terminals, wherein the number of output terminals is greater than the number of input terminals; Multiple thyristor components, wherein the thyristor components are connected to the input terminal and the output terminal; The main control chip is connected to the plurality of thyristor components and is used to execute the control method as described in any one of claims 1 to 8 to control the on / off state of the thyristor components.

10. A thyristor power regulation system, characterized in that, include: The thyristor power regulator as described in claim 9; A circuit breaker is connected to the input terminal; Multiple loads are connected to the output terminal.

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