Data recording and downloading design method for aviation starting power generation system

Abstract

The invention belongs to the field of ground maintenance of an aviation starting power generation system, and relates to a data recording and downloading design method of the aviation starting power generation system. The design method comprises the steps of memory partition function design, data recording function design and data downloading function design. The partition function of the memory is designed as follows: the FLASH memory is divided into a plurality of sectors for respectively storing control parameters of a starting power generation system, starting whole-process operation data, power generation normal operation data, power generation fault data and maintenance BIT detection result data; the data recording function is designed as follows: recording corresponding operation data, fault data or control parameters into corresponding FLASH memory sectors according to different working modes of the system; the data downloading function is designed to respond to a data downloading instruction issued by the upper computer, read data from the corresponding FLASH memory sector and upload the data to the upper computer. According to the invention, the maintainability of the system is improved.

Description

Technical Field

[0001] This application belongs to the field of ground maintenance of aircraft starting and generating systems, and specifically relates to a design method for data recording and downloading of aircraft starting and generating systems. Background Technology

[0002] More-electric aircraft require systems with high reliability, high fault tolerance, and high power density, and the aircraft starter / generator system is one of the key technologies for more-electric aircraft. The evolution of airborne generators from a single power generation function to a dual-function starter / generator represents a significant leap forward in airborne power technology. The aircraft starter / generator system utilizes the reversible principle of electric motors, allowing the generator to also function as an engine starter. Before the engine starts, it acts as an electric motor, driving the engine rotor to rotate. Once a certain speed is reached, fuel is injected and ignited, enabling the engine to enter a self-sustaining state. Afterward, the engine, in turn, drives the motor, turning it into a generator to supply power to electrical equipment. This dual-purpose motor eliminates the need for a dedicated starter, reduces the size and weight of airborne equipment, and effectively improves the reliability of the entire electrical system.

[0003] In both start-up and power generation modes, the controller has control, fault protection, and BIT testing functions. It can continuously and automatically detect faults in the aircraft start-up and power generation system, and record the system's operating status, fault information, and control parameters into the memory for use in ground maintenance.

[0004] Currently, data logging functions for aviation power systems mostly focus on recording and downloading data for a single generator controller or starter controller in its single mode. Research has not been conducted on technologies for recording and downloading normal and fault data in different modes (starting, generating, and maintenance) for integrated digital controllers that combine starting and generating power. Furthermore, existing aviation power generator or starter controllers are single-function controllers, often employing analog voltage-regulating generator controllers for generating power or brushed motor mechanical commutation starter controllers for starting, without digital control parameter tuning and maintenance. Existing single analog voltage-regulating generator controllers or single starter controllers have limited digital functions and use small memory capacities, sometimes even unable to record data for all operating states.

[0005] With the development of digital starter / generator integrated controller technology, research is needed on methods for recording starter / generator control parameters, normal starter / generator operation, fault and maintenance process data required by digital starter / generator integrated controllers.

[0006] Without requiring repeated code modifications, control parameters are simply sent from the communication host computer and stored in the memory, facilitating control parameter tuning and debugging. The control parameters required for the aircraft starting and generating system include the storage and retrieval of starting control parameters and generating control parameters. The stored starting control parameters include: segmented setpoint speed and acceleration for the speed loop, and PID parameter adjustments for the speed and current loops. The stored generating control parameters include: setpoint voltage and soft-start slope for the voltage loop, and PID parameter adjustments for the voltage and current loops.

[0007] In order to effectively record the entire startup process data, long-term power generation data, fault data, and maintenance self-test results data, the FLASH memory is partitioned for recording and data downloading.

[0008] In summary, research on data storage partitioning, recording, and downloading algorithms for digital starter-generator integrated controllers is crucial. Summary of the Invention

[0009] To address the aforementioned issues, this application provides a design method for data recording and downloading in an aircraft starting and generating system, which mainly includes memory partitioning function design, data recording function design, and data download function design.

[0010] The memory partitioning function is designed as follows: the FLASH memory is divided into control parameter sector, start-up data sector, normal power generation data sector, power generation fault data sector and maintenance BIT detection data sector, which are used to store the control parameters of the start-up power generation system, the running data of the entire start-up process, the normal power generation data, the power generation fault data and the maintenance BIT detection result data, respectively.

[0011] The data recording function is designed to record the corresponding operating data, fault data, or control parameters into the corresponding FLASH memory sector according to the different working modes of the system.

[0012] The data download function is designed to: respond to the data download command issued by the host computer, read data from the corresponding FLASH memory sector and upload it to the host computer.

[0013] Preferably, in the memory partitioning function design, the allocation of each sector size is determined by the following formula:

[0014] Control parameter: number of sectors = 1;

[0015] The number of data sectors to start, QD_Number, is:

[0016] ;

[0017] The number of data sectors for normal power generation operation is FDRun_Number:

[0018] ;

[0019] The number of power generation fault data sectors, FDError_Number, is:

[0020] ;

[0021] The number of sectors to maintain for BIT testing is MBIT_Number:

[0022] ;

[0023] Where Ceil is the floor function, Floor is the floor function, n is the number of records, Tq is the single start-up time, Td is the recording duration of normal power generation, Tn is the recording duration of power generation faults, Ts is the recording period, b is the number of 16-bit data in a single data packet, and SECTADDLEN is the length of a single sector. The number of records is adjusted to maximize the utilization of all sectors of the FLASH memory.

[0024] Preferably, the control parameter recording in the data recording function design includes:

[0025] When the DSP recognizes the control parameter sending command and control parameter data sent by the host computer, it erases the control parameter sector.

[0026] Write each control parameter data into two adjacent address bits of the control parameter sector;

[0027] When the system is powered on again, it reads and verifies the control parameters in adjacent address bits in sequence. If the data in the two address bits are consistent, the data is assigned to the corresponding control variable. If they are inconsistent, a fault is reported.

[0028] Preferably, the data recording function design includes recording the entire startup process operation data, including:

[0029] In response to the clear command issued by the host computer, initialize the starting sector and address of the start data record, and erase the starting sector and the next adjacent sector;

[0030] In startup mode, startup data packets are recorded to the current sector at fixed intervals;

[0031] When it is determined that the current sector is about to be full, switch to the next sector to record, and asynchronously erase the next sector;

[0032] During sector erasure, the generated runtime data is temporarily stored in the on-chip RAM cache array;

[0033] After the sector erasure is complete, the data in the cache array is written to the target sector, and real-time recording continues.

[0034] After recording to the last sector, return to the starting sector to perform a loop overwrite recording.

[0035] Preferably, the condition for determining that a sector record is about to be full is: the remaining address space of the sector is less than the length of a single packet of data; the method for determining that sector erasure is complete is: reading the value of a specific address bit in the erased sector to see if it is 0xFFFF.

[0036] Preferably, the data recording function design includes the recording of power generation operation data and power generation fault data, including:

[0037] Normal power generation data and power generation fault data are recorded separately.

[0038] The power generation operation data is recorded using a cyclical recording method with a relatively long recording period.

[0039] Power generation fault data recording begins when a fault is triggered, and the recording period is short to avoid fault data being overwritten by normal operating data.

[0040] Preferably, the data download operation in the data download function design is based on the state of the FLASH record full flag, starting from the current address of the current record sector, reading and uploading data in units of one packet from back to front;

[0041] When the record full flag is empty, data download stops at the beginning address of the starting sector;

[0042] When the record is full, the data download starts from the current sector, backtracks to the starting sector, and then jumps to the last sector to continue downloading until the next sector of the current record sector stops.

[0043] Preferably, during data download, the effective download tail address of each sector is determined using the following formula:

[0044] .

[0045] This application utilizes a hierarchical and layered approach to record and download operational or fault data in the FLASH memory under different operating modes of the starting and generating system. This facilitates monitoring and analysis of the system's operating status and improves its maintainability. Simultaneously, the memory stores starting / generating control parameters, enabling convenient debugging and tuning of the starting / generating algorithm parameters. Attached Figure Description

[0046] Figure 1This is a schematic diagram illustrating the functional partitioning of the FLASH storage space by the recording functions of each mode of the starting power generation system.

[0047] Figure 2 This is a schematic diagram of the starting and power generation control parameter recording process in an embodiment of the present invention.

[0048] Figure 3 This is a schematic diagram of the process of starting up all running data recording in an embodiment of the present invention.

[0049] Figure 4 This is a schematic diagram of the data recording process for normal power generation operation in an embodiment of the present invention.

[0050] Figure 5 This is a schematic diagram of the power generation fault data recording process in an embodiment of the present invention.

[0051] Figure 6 This is a schematic diagram of the process for maintaining BIT detection data recording in an embodiment of the present invention.

[0052] Figure 7 This is a schematic diagram of the data download process for starting normal operation in an embodiment of the present invention.

[0053] Figure 8 This is a schematic diagram illustrating the data download direction when the record full flag is "empty" in an embodiment of the present invention.

[0054] Figure 9 This is a schematic diagram illustrating the normal data download direction when the record full flag is "full" in an embodiment of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are only some, not all, of the embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0056] This application proposes a data recording and downloading design method for an aviation starting and power generation system. Specifically, an external FLASH memory is selected. In standby mode, a FLASH starting / power generation data download command and control variable values ​​are sent from a communication host computer to the corresponding control parameters and recorded in the control parameter sector of the FLASH memory. Upon power-up, the controller reads the recorded parameters from the FLASH memory and assigns them to the corresponding control parameters in the software. This satisfies the requirement of sending and recording starting / power generation control parameters via communication to the FLASH memory, thereby achieving parameter adjustability. In starting mode, starting operation data is recorded in the starting data sector of the FLASH memory, enabling data recording of the entire process of starting the engine under motor-driven conditions, including normal starting data and abnormal fault data. In power generation mode, power generation operation data is recorded in the power generation data sector of the FLASH memory, enabling data recording of the entire process of powering the load under motor-driven conditions, including normal power generation data and abnormal fault data. In maintenance mode, a maintenance BIT (Block Bit Interruption) test is performed, and the MBIT test results are recorded in the MBIT data sector of the FLASH memory. In standby or fault mode, a data download command is issued by the communication host computer to download the start-up / generation operation or fault data stored in the FLASH sector. In summary, this achieves the purpose of recording start-up and generation system control parameters, all start-up operation data, normal generation operation and fault data, and maintaining BIT test result data.

[0057] The design method of this application is characterized in that the method includes memory partitioning function design, data recording function design, and data download function design;

[0058] The memory partitioning function is designed as follows: the FLASH memory is divided into control parameter sector, start-up data sector, normal power generation data sector, power generation fault data sector and maintenance BIT detection data sector, which are used to store the control parameters of the start-up power generation system, the running data of the entire start-up process, the normal power generation data, the power generation fault data and the maintenance BIT detection result data, respectively.

[0059] The data recording function is designed to record the corresponding operating data, fault data, or control parameters into the corresponding FLASH memory sector according to the different working modes of the system.

[0060] The data download function is designed to: respond to the data download command issued by the host computer, read data from the corresponding FLASH memory sector and upload it to the host computer.

[0061] This invention uses a 512Mbit FLASH memory, divided into 512 1Mbit (1Mbit = 64K * 16bit) sectors for recording. The recorded content includes: start-up power generation system control parameters, all start-up operation data, normal power generation operation data, power generation fault data, and maintenance BIT detection data.

[0062] In some alternative implementations, the allocation of sector sizes in the memory partitioning design is determined by the following formula:

[0063] Control parameter: number of sectors = 1;

[0064] The number of data sectors to start, QD_Number, is:

[0065] ;

[0066] The number of data sectors for normal power generation operation is FDRun_Number:

[0067] ;

[0068] The number of power generation fault data sectors, FDError_Number, is:

[0069] ;

[0070] The number of sectors to maintain for BIT testing is MBIT_Number:

[0071] ;

[0072] Where Ceil is the floor function, Floor is the floor function, n is the number of records, Tq is the single start-up time, Td is the recording duration of normal power generation, Tn is the recording duration of power generation faults, Ts is the recording period, b is the number of 16-bit data in a single data packet, and SECTADDLEN is the length of a single sector. The number of records is adjusted to maximize the utilization of all sectors of the FLASH memory.

[0073] In this embodiment, since the control parameter storage information of the starting power generation system is relatively small (generally about 30 to 50 16-bit control quantities), the control parameter storage information is allocated to Control_Number=1 sector.

[0074] Since the engine starting process is relatively short, lasting about 20-40 seconds, the entire starting process and multiple operation data can be recorded, including normal data and fault data, without the need to record normal and fault data separately.

[0075] To record n ​​startup data cycles, with each startup lasting Tq seconds and a recording period of Ts milliseconds, and with one data packet containing b 16-bit data points, and one FLASH address bit capable of storing one 16-bit number, the number of allocated sectors QD_Number for the entire startup process can be calculated using the following formula 1):

[0076] (1)

[0077] It is a rounding function. This is the floor function. This indicates the number of packets that a sector can record. This represents the startup time (in milliseconds) for n startup attempts. Increasing the sector count by 1 is because during FLASH recording, one sector is always in an erase state; this sector is not used for startup data recording, and an extra sector needs to be reserved. (This refers to the calculation of the sector count.) Rounding up is necessary because the number of allocated sectors is not an integer. To ensure that complete startup data is recorded n times, the complete number of sectors needs to be stored.

[0078] Because the power generation operation time is long (each flight of an aircraft is about several hours, and it is always in power generation mode), the memory capacity is limited, and the overlay cyclic recording is used. It is impossible to record the entire process and multiple power generation operation data. Furthermore, when a power generation failure occurs, the fault data in the operation data cannot be directly detected. Therefore, the normal power generation process data and power generation failure data are recorded in separate partitions to avoid the recorded fault data being overwritten by the normal operation data.

[0079] To meet the requirements of recording normal power generation data for Td minutes, with a recording period of Ts milliseconds, one data packet contains b 16-bit data points, and one FLASH address bit records one 16-bit number. The number of sectors allocated when recording normal power generation data for Td minutes can be calculated using the following formula 2):

[0080] (2)

[0081] It is a rounding function. This is the floor function. This indicates the number of packets that a sector can record. This represents the total number of packets recorded in minutes Td. The increment of 1 is because during the FLASH recording process, one sector is always in an erase state; this sector is not recorded as normal power generation data and an extra sector needs to be reserved. This is used to calculate the number of sectors. Rounding up is necessary because the calculated number of allocated sectors is not an integer. To ensure that the complete power generation and normal operation data is recorded during the Td time period, the complete number of sectors needs to be stored.

[0082] To meet the requirements of recording power generation fault data for Tn minutes, with a recording period of Ts milliseconds, one data packet contains b 16-bit data points, and one FLASH address bit records one 16-bit number, the number of sectors allocated (FDError_Number) for recording power generation fault data for Tn minutes can be calculated using the following formula 3):

[0083] (3)

[0084] It is a rounding function. This is the floor function. This indicates the number of packets that a sector can record. This represents the total number of packets recorded over Tn minutes. The increment of 1 is because during the FLASH recording process, one sector is always in an erase state; this sector is not recorded as power generation fault data, and an extra sector needs to be reserved. This is used to calculate the number of sectors. Rounding up is necessary because the calculated number of allocated sectors is not an integer. To ensure that the recorded power generation fault data for time Tn is complete, the complete number of sectors needs to be stored.

[0085] While the aircraft is undergoing ground maintenance, a "Maintenance BIT Test Command" is issued via communication, requesting the start-up power generation system to perform a maintenance BIT function test. The maintenance BIT test results are then reported to the next-level RIU device via communication, and simultaneously stored in the FLASH memory. However, the maintenance BIT record contains relatively little information, and each time a "Maintenance BIT Test Command" is received, the maintenance BIT test data record only records the current test result once in a packet format (i.e., one packet of data).

[0086] To record the maintenance BIT test results data n times, one data packet contains b 16-bit data, and one FLASH address bit records one 16-bit number. The number of allocated sectors for maintaining the BIT test results data, MBIT_Number, can be calculated using the following formula 4):

[0087] (4)

[0088] It is a rounding function. This is the floor function. This indicates the number of packets a sector can record. Increasing by 1 is because during FLASH recording, one sector is always in an erase state; this sector is not used for maintaining BIT data records, and an extra sector needs to be reserved. This is used to calculate the number of sectors. Rounding up is necessary because the calculated number of allocated sectors is not an integer. To ensure that the recorded n complete maintenance of BIT data is stored, the complete number of sectors needs to be taken.

[0089] Since the FLASH memory has 512 sectors, and it is necessary to maximize the utilization of all FLASH sectors, the control parameter data, start-up operation data, normal power generation operation data, and power generation fault data are allocated according to sectors. This can be achieved by adjusting the appropriate number of recordings n to satisfy the following equation (5):

[0090] (5)

[0091] This FLASH memory adopts a parallel bus read and write operation mode, supports 16-bit data read and write, and each address bit occupies one 16-bit data. Therefore, the 16 data lines of the FLASH are accessed by the data bus of the DSP main control chip XD0~XD15.

[0092] The FLASH storage capacity is 512Mbit (512Mbit = 32M * 16bit = 2^25 * 16bit) address space, requiring 25 address buses. Therefore, the XA0~XA19 address buses of the DSP main control chip (DSP28335 only has 20 address buses) and 5 general I / O ports are used for control.

[0093] For example, the startup data log is set to record one data packet every 10 ms, with each packet containing 30 16-bit data points. One 16-bit number is recorded per FLASH address bit. Each startup takes 30 seconds, and the startup process data needs to be recorded 180 times. According to formula 1), 249 sectors are required for recording startup process data. The normal power generation data log is set to record one data packet every 100 ms, with each packet containing 30 16-bit data points. One 16-bit number is recorded per FLASH address bit. 740 minutes of normal power generation process data needs to be recorded. According to formula 2), 205 sectors are required for recording power generation operation data. The power generation fault data log is set to record one data packet every 10 ms, with each packet containing 30 16-bit data points. One 16-bit number is recorded per FLASH address bit. 20 minutes of power generation fault data needs to be recorded. According to formula 3), 55 sectors are required for recording power generation fault data. The maintenance BIT test data record only records the current test result once in a packet format. Each packet contains 20 16-bit data entries, and one 16-bit number is recorded per FLASH address. The requirement is to record and maintain BIT result data 200 times. Based on equation 4), calculate the 2 sectors required for recording and maintaining BIT result data.

[0094] like Figure 1As shown, the entire startup process operation data is recorded in sectors 1 to 249, normal power generation operation data is recorded in sectors 250 to 454, power generation fault data is recorded in sectors 455 to 509, and maintenance BIT detection data is recorded in sectors 510 to 511. A total of 25 startup / power generation control parameters are recorded in sector 0.

[0095] The data logging function includes five functions: recording start-up / generation control parameters, recording normal start-up data, recording normal generation data, recording generation fault data, and recording maintenance BIT test results data. These are explained in detail below.

[0096] In some optional implementations, the control parameter recording in the data logging function design includes:

[0097] When the DSP recognizes the control parameter sending command and control parameter data sent by the host computer, it erases the control parameter sector.

[0098] Write each control parameter data into two adjacent address bits of the control parameter sector;

[0099] When the system is powered on again, it reads and verifies the control parameters in adjacent address bits in sequence. If the data in the two address bits are consistent, the data is assigned to the corresponding control variable. If they are inconsistent, a fault is reported.

[0100] This embodiment describes the process of recording start-up / generation control parameters. In this embodiment, the host computer communication packet sends "control parameter 1", "control parameter 2", ... "control parameter n" data, and simultaneously issues a "control parameter sending command".

[0101] When the DSP recognizes the communication sending of "control parameter send command" and data information such as "control parameter 1", "control parameter 2", ... "control parameter n", it first erases the Control_SECTNO sector containing the FLASH control parameters. Then, it stores each control parameter in two adjacent address bits of that sector. The purpose is to perform data verification by checking whether the control parameters read from the FLASH only once during DSP power-up initialization (the FLASH reads control parameters only once upon DSP power-up) are equal. If the data read from the two address bits is inconsistent, a "FLASH control parameter read failure" is reported; if the data read from the two address bits is consistent, the FLASH read data is assigned to the corresponding control variable as the start / generator control parameter to ensure the correctness of the recorded control parameters.

[0102] For example, such as Figure 2 As shown, the recording steps are as follows:

[0103] Step 11: When the DSP recognizes the "control parameter sending command" sent by the communication, the DSP recognizes the command, erases sector 0 of the FLASH, completes the FLASH sector clearing operation, and sets the FLASH erase status flag to "erasure complete" before writing the parameters.

[0104] Step 12: Store the communication control parameter 1 in the address bits Addr0 and Addr1 of sector 0, store the control parameter 2 in the address bits Addr2 and Addr3 of sector 0, ... store the control parameter n in the address bits Addrn and Addrn+1 of sector 0.

[0105] Step 13: Power on the DSP again and sequentially read the adjacent addresses of sector 0 of the FLASH to store control parameter 1 (Addr0, Addr1), control parameter 2 (Addr2, Addr3), and so on, until the adjacent addresses (Addrn, Addrn+1) store control parameter n.

[0106] Step 4: Compare the control parameter n stored at adjacent address bits Addrn and Addrn+1 respectively. If they do not match, report "FLASH control parameter read failure"; if they match, assign the FLASH read control parameter to the corresponding control variable.

[0107] In some optional implementations, the data recording function design includes recording the entire startup process operation data, including:

[0108] In response to the clear command issued by the host computer, initialize the starting sector and address of the start data record, and erase the starting sector and the next adjacent sector;

[0109] In startup mode, startup data packets are recorded to the current sector at fixed intervals;

[0110] When it is determined that the current sector is about to be full, switch to the next sector to record, and asynchronously erase the next sector;

[0111] During sector erasure, the generated runtime data is temporarily stored in the on-chip RAM cache array;

[0112] After the sector erasure is complete, the data in the cache array is written to the target sector, and real-time recording continues.

[0113] After recording to the last sector, return to the starting sector to perform a loop overwrite recording.

[0114] In some alternative implementations, the condition for determining that a sector record is about to be full is: the remaining address space of the sector is less than the length of a single packet of data; the method for determining that sector erasure is complete is: reading the value of a specific address bit of the erased sector to see if it is 0xFFFF.

[0115] This embodiment describes the entire startup process and its data recording procedure. In this embodiment, when the host computer sends a "clear FLASH startup data command", the DSP recognizes the command and initializes the FLASH startup and normal operation data sector number QD_SECTNO to the starting QD_SECTNO_START sector for startup data recording. The starting address of the sector segment is initialized to 0x0000, and the starting QD_SECTNO_START sector and the adjacent QD_SECTNO_START+1 sector are erased simultaneously. When the sector erasure is complete, the FLASH erasure status flag is set to "erasure complete", and the FLASH sector record full flag is set to "empty".

[0116] When a start command is detected and the system enters start mode, the start mode data packet is recorded in the FLASH memory. When a start / stop command is received or a fault occurs, the system stops starting, disconnects the start contactor, and stops recording FLASH data.

[0117] In startup mode, FLASH starts recording from address 0x0000 of the starting QD_SECTNO_START sector. When the condition (SECTADDLEN - currently recorded sector address) < startup data packet length is met, where SECTADDLEN is the sector length = 0x10000, the sector is considered full, and the system switches to the next sector (QD_SECTNO_START+1 sector). Simultaneously, the sector after the next one (QD_SECTNO_START+2 sector) is erased, and the FLASH erase status flag is set to "erasing in progress". Since no data can be written to the FLASH memory during the erase process, the process data generated during the erase process is cached in the QD_BUFF_FLASH array of the on-chip RAM.

[0118] Since the address bits of the erased sector are all 0xFFFF after the FLASH memory is erased, the erase status judgment function reads the values ​​of address 0x0000, SECTADDLEN-1 (0x10000-1=0xFFFF), and SECTADDLEN / 2 (0x10000 / 2=0x8000) of the sector being erased in QD_SECTNO_START+2 and checks if they are 0xFFFF. If they are 0xFFFF, the FLASH erase status flag is set to "erasure complete" and the erasure is stopped.

[0119] In the "erase complete" state, within one recording cycle, the data cached in the QD_BUFF_FLASH array is immediately written to the starting address 0x0000 of the QD_SECTNO_START+1 sector of the FLASH memory. Then, the current running data is recorded in real time every 10ms to ensure that the information data recorded by the FLASH is not missing during the running process.

[0120] When recording from sector QD_SECTNO_START to sector QD_SECTNO_END in sequence according to the above steps, when switching from sector QD_SECTNO_START to the next sector (sector QD_SECTNO_START+1), the sector after that (sector QD_SECTNO_START+2) is erased, until sector QD_SECTNO_END is full. At this point, the FLASH memory full flag is set to "valid", and the cyclic overwriting recording starts again from sector QD_SECTNO_START.

[0121] For example, such as Figure 3 As shown, the steps for recording operational data throughout the startup process are as follows:

[0122] Step 21: When the host computer sends the "Clear FLASH Startup Data Command", the DSP recognizes the command, initializes the FLASH startup data sector number QD_SECTNO to the first sector of the startup data record, initializes the starting address of the sector segment to 0x0000, and erases the first sector and the two adjacent sectors. When the sector erasure is complete, the FLASH erasure status flag is set to "Erase Complete", and the FLASH sector record full flag is set to "Empty".

[0123] Step 22: When a start command is detected and the system enters start mode, the start mode data information packet is recorded in the FLASH memory. When a start / stop command is received or a fault occurs, the system stops starting and disconnects the start contactor, and then stops recording FLASH data.

[0124] Step 23: In startup mode, the FLASH starts recording from address 0x0000 of sector 1. When the condition (SECTADDLEN - currently recorded sector address) < startup data packet length, where SECTADDLEN is the sector length = 0x10000, the sector is considered full, and the process switches to the next sector (sector 2). Simultaneously, the sector after that (sector 3) is erased, and the FLASH erase status flag is set to "erasing in progress". Since the FLASH memory cannot write data during the erase process, the process data generated during the erase process is cached in the QD_BUFF_FLASH array of the on-chip RAM.

[0125] Step 24: Since the address bits of the erased sector are all 0xFFFF after the FLASH memory is erased, the erase status judgment function reads the values ​​of address 0x0000, SECTADDLEN-1 (0x10000-1=0xFFFF), and SECTADDLEN / 2 (0x10000 / 2=0x8000) of the sector being erased and checks if they are 0xFFFF. If they are 0xFFFF, the FLASH erase status flag is set to "erasure complete" and the erasure is stopped.

[0126] Step 25: In the "Erase Complete" state, within one recording cycle, the data cached in the QD_BUFF_FLASH array is immediately written to the starting address 0x0000 of the second sector of the FLASH memory. Then, the current running data is recorded in real time every 10ms to ensure that the information data recorded by the FLASH is not missing during the running process.

[0127] Step 26: While recording from sector 1 to sector 249 according to the above steps, when switching from sector 248 to the next sector (sector 249), erase the sector immediately after it (sector 1); when sector 249 is full, set the FLASH memory full record flag to "valid", and then start cyclically overwriting records from sector 1 again.

[0128] In some optional implementations, the recording of power generation operation data and power generation fault data in the data recording function design includes:

[0129] Normal power generation data and power generation fault data are recorded separately.

[0130] The power generation operation data is recorded using a cyclical recording method with a relatively long recording period.

[0131] Power generation fault data recording begins when a fault is triggered, and the recording period is short to avoid fault data being overwritten by normal operating data.

[0132] This embodiment illustrates the process of recording normal power generation data and power generation fault data.

[0133] First, regarding the normal operation data records of power generation, when the host computer sends the "Clear FLASH Power Generation Operation Data Command", the DSP recognizes the command and initializes the power generation FDRUN_SECTNO sector number of the FLASH to the starting FDRUN_SECTNO_START sector of the power generation operation data record, and initializes the starting address of the sector segment to 0x0000. Simultaneously, it erases the starting FDRUN_SECTNO_START sector and the adjacent FDRUN_SECTNO_START+1 sector. When the sector erasure is complete, the FLASH erasure status flag is set to "Erasing Complete", and the FLASH sector record full flag is set to "Empty".

[0134] When a power generation command is detected and the system switches to power generation mode, the power generation mode data information packet is recorded in the FLASH memory. When a power generation stop command is received or a fault occurs (when a fault occurs, normal operation data recording stops and the fault data area is entered for fault recording), the system stops power generation and disconnects the power generation contactor and excitation relay, and then stops the normal power generation data recording in the FLASH memory.

[0135] In power generation mode, FLASH starts recording from address 0x0000 of the starting FDRUN_SECTNO_START sector. When the condition (SECTADDLEN - currently recorded sector address) < power generation data packet length, where SECTADDLEN is the sector length = 0x10000, the sector is considered full, and the system switches to the next sector (FDRUN_SECTNO_START+1 sector). Simultaneously, the sector after the next one (FDRUN_SECTNO_START+2 sector) is erased, and the FLASH erase status flag is set to "erasing in progress". Since no data can be written to the FLASH memory during the erase process, the process data generated during the erase process is cached in the FD_RUN_BUFF_FLASH array of the on-chip RAM.

[0136] Since the address bits of the erased sector are all 0xFFFF after the FLASH memory is erased, the erase status judgment function reads the values ​​of address 0x0000, SECTADDLEN-1 (0x10000-1=0xFFFF), and SECTADDLEN / 2 (0x10000 / 2=0x8000) of the FDRUN_SECTNO_START+2 sector being erased. If they are 0xFFFF, the FLASH erase status flag is set to "erasure complete" and the erasure is stopped.

[0137] In the "erasure complete" state, within one recording cycle, the data cached in the FD_RUN_BUFF_FLASH array is immediately written to the starting address 0x0000 of the FDRUN_SECTNO_START+1 sector of the FLASH memory. Then, the current state running data is recorded in real time every 100ms to ensure that the information data recorded by the FLASH is not missing during the running process.

[0138] When recording from sector FDRUN_SECTNO_START to sector FDRUN_SECTNO_END in sequence according to the above steps, when switching from sector FDRUN_SECTNO_START to the next sector (sector FDRUN_SECTNO_START+1), the sector after that (sector FDRUN_SECTNO_START+2) is erased; when sector FDRUN_SECTNO_END is full, the FLASH memory full record flag is set to "valid", and the cyclic overwriting record starts again from sector FDRUN_SECTNO_START.

[0139] For example, such as Figure 4 As shown, the steps for recording normal power generation data are as follows:

[0140] Step 31: When the host computer sends the "Clear FLASH power generation normal operation data instruction", the DSP recognizes the instruction, initializes the power generation FDRUN_SECTNO sector number of the FLASH to the starting sector 250 of the power generation operation data record, initializes the starting address of the sector segment to 0x0000, and erases the starting sector 250 and the adjacent sector 251 at the same time, completing the clearing of the FLASH sector operation. The FLASH erase status flag is set to "erasure completed", and the FLASH sector record full flag is set to "empty".

[0141] Step 32: When a power generation command is detected and the system switches to power generation mode, the power generation mode data information packet is recorded in the FLASH memory. When a power generation stop command is received or a fault occurs (when a fault occurs, normal operation data recording is stopped and the fault data area is entered for fault recording), the system stops power generation and disconnects the power generation contactor and excitation relay, and stops the normal power generation data recording in FLASH memory.

[0142] Step 33: In power generation mode, the FLASH starts recording from address 0x0000 of the first 250 sectors. When the condition is met: (SECTADDLEN - currently recorded sector address) < power generation data packet length, where SECTADDLEN is the sector length = 0x10000, the sector is considered full, and the system switches to the next sector (sector 251). Simultaneously, the sector after that (sector 252) is erased, and the FLASH erase status flag is set to "erasing in progress". Since the FLASH memory cannot write data during the erase process, the process data generated during the erase process is cached in the FD_RUN_BUFF_FLASH array of the on-chip RAM.

[0143] Step 34: Since the address bits of the erased sector are all 0xFFFF after the FLASH memory is erased, the erase status judgment function reads the values ​​of address 0x0000, SECTADDLEN-1 (0x10000-1=0xFFFF), and SECTADDLEN / 2 (0x10000 / 2=0x8000) of the sector being erased in sector 252 to see if they are 0xFFFF. If they are 0xFFFF, the FLASH erase status flag is set to "erasure complete" and the erasure is stopped.

[0144] Step 35: In the "Erase Complete" state, within one recording cycle, the data cached in the FD_RUN_BUFF_FLASH array is immediately written to the starting address 0x0000 of sector 251 of the FLASH memory. Then, the current running data is recorded in real time every 100ms to ensure that the information data recorded by the FLASH is not missing during the running process.

[0145] Step 36: When recording from sector 250 to sector 454 in sequence according to the above steps, when switching from sector 453 to the next sector (sector 454), erase the sector after the next (sector 250); when sector 454 is full, set the FLASH memory full record flag to "valid", and then start cyclically overwriting records from sector 250.

[0146] Secondly, regarding the power generation fault data record, when the host computer sends the "Clear FLASH Power Generation Fault Data Command", the DSP recognizes the command and initializes the FLASH power generation FDERROR_SECTNO sector number to the starting FDERROR_SECTNO_START sector of the power generation fault data record, and initializes the starting address of the sector segment to 0x0000. Simultaneously, it erases the starting FDERROR_SECTNO_START sector and the adjacent FDERROR_SECTNO_START+1 sector. When the sector erasure is complete, the FLASH erasure status flag is set to "Erasing Complete", and the FLASH sector record full flag is set to "Empty".

[0147] When a power generation fault is triggered and the system enters fault mode, the power generation fault data packet is recorded in the FLASH memory until the power generation fault protection disconnects the main contactor, at which point the FLASH fault data recording stops.

[0148] In power generation failure mode, FLASH starts recording from address 0x0000 of the starting sector FDERROR_SECTNO_START. When the condition (SECTADDLEN - currently recorded sector address) < power generation failure data packet length, where SECTADDLEN is the sector length = 0x10000, the sector is considered full, and the system switches to the next sector (FDERROR_SECTNO_START+1). Simultaneously, the sector after the first sector (FDERROR_SECTNO_START+2) is erased, and the FLASH erase status flag is set to "erasing in progress". Since no data can be written to the FLASH memory during the erase process, the process data generated during the erase process is cached in the FD_ERROR_BUFF_FLASH array of the on-chip RAM.

[0149] Since the address bits of the erased sector are all 0xFFFF after the FLASH memory is erased, the erase status judgment function reads the values ​​of address 0x0000, SECTADDLEN-1 (0x10000-1=0xFFFF), and SECTADDLEN / 2 (0x10000 / 2=0x8000) of the sector being erased in FDERROR_SECTNO_START+2 and checks if they are 0xFFFF. If they are 0xFFFF, the FLASH erase status flag is set to "erasure complete" and the erasure is stopped.

[0150] In the "erase complete" state, within one recording cycle, the data cached in the FD_ERROR_BUFF_FLASH array is immediately written to the starting address 0x0000 of the FDERROR_SECTNO_START+1 sector of the FLASH memory. Then, the current fault data is recorded in real time every 10ms to ensure that the information data recorded by the FLASH is not missing during the operation.

[0151] When recording from sector FDERROR_SECTNO_START to sector FDERROR_SECTNO_END in sequence according to the above steps, when switching from sector FDERROR_SECTNO_START to the next sector (sector FDERROR_SECTNO_START+1), the sector after that (sector FDERROR_SECTNO_START+2) is erased; when sector FDERROR_SECTNO_END is full, the FLASH memory full flag is set to "valid", and the cyclic overwriting recording starts from sector FDERROR_SECTNO_START again.

[0152] For example, such as Figure 5 As shown, the steps for recording power generation fault data are as follows:

[0153] Step 41: When the host computer sends the "Clear FLASH power generation fault data command", the DSP recognizes the command, initializes the power generation FDERROR_SECTNO sector number of the FLASH to the starting sector 455 of the power generation fault data record, initializes the starting address of the sector segment to 0x0000, and simultaneously erases the starting sector 455 and the adjacent sector 456. When the sector erasure is complete, the FLASH erasure status flag is set to "Erase Complete", and the FLASH sector record full flag is set to "Empty".

[0154] Step 42: When a power generation fault is triggered and the system enters fault mode, the power generation fault data packet is recorded in the FLASH memory until the power generation fault protection disconnects the main contactor, at which point the FLASH fault data recording stops.

[0155] Step 43: In power generation failure mode, the FLASH starts recording from address 0x0000 of the starting sector 455. When the condition (SECTADDLEN - currently recorded sector address) < power generation failure data packet length is met, the sector is considered full, and the system switches to the next sector (sector 456). Simultaneously, the sector after that (sector 457) is erased, and the FLASH erase status flag is set to "erasing in progress". Since data cannot be written to the FLASH memory during the erase process, the process data generated during the erase process is cached in the FD_ERROR_BUFF_FLASH array of the on-chip RAM.

[0156] Step 44: Since the address bits of the erased sector are all 0xFFFF after the FLASH memory is erased, the erase status judgment function reads the values ​​of address 0x0000, SECTADDLEN-1 (0x10000-1=0xFFFF), and SECTADDLEN / 2 (0x10000 / 2=0x8000) of the sector being erased in sector 457 to see if they are 0xFFFF. If they are 0xFFFF, the FLASH erase status flag is set to "erasure complete" and the erasure is stopped.

[0157] Step 45: In the "Erase Complete" state, within one recording cycle, the data cached in the FD_ERROR_BUFF_FLASH array is immediately written to the starting address 0x0000 of sector 456 of the FLASH memory. Then, the current fault data is recorded in real time every 10ms to ensure that the information data recorded by the FLASH is not missing during the operation.

[0158] Step 46: While recording from sector 455 to sector 509 according to the above steps, when switching from sector 455 to the next sector (sector 456), erase the sector immediately after it (sector 457); when sector 509 is full, set the FLASH memory full record flag to "valid", and then start cyclically overwriting records from sector 455 again.

[0159] In addition, it also includes the maintenance of BIT test result data records. When the host computer sends the "clear maintenance BIT result data command", the DSP recognizes the command, initializes the MBIT_SECTNO sector number of FLASH to the starting MBIT_SECTNO_START sector of the maintenance BIT test result data record, initializes the starting address of the sector segment to 0x0000, and erases the starting MBIT_SECTNO_START sector and the adjacent MBIT_SECTNO_START+1 sector at the same time. When the sector erasure is completed, the FLASH erasure status flag is set to "erasure completed" and the FLASH sector record full status flag is set to "empty".

[0160] Upon receiving a maintenance BIT test command, the system switches to maintenance BIT mode and records the maintenance BIT test data results into the FLASH memory. The maintenance BIT test involves detecting the analog and discrete circuit excitations of the controller; only the test results are recorded into the FLASH memory.

[0161] In maintenance BIT mode, FLASH starts recording from address 0x0000 of the starting MBIT_SECTNO_START sector. When the condition (SECTADDLEN - currently recorded sector address) < maintenance BIT detection packet length, where SECTADDLEN is the sector length = 0x10000, the sector is considered full, and the system switches to the next sector (MBIT_SECTNO_START+1 sector). Simultaneously, the sector after the first sector (MBIT_SECTNO_START+2 sector) is erased, and the FLASH erase status flag is set to "erasing in progress". Since no data can be written to the FLASH memory during the erase process, the process data generated during the erase process is cached in the MBIT_BUFF_FLASH array of the on-chip RAM.

[0162] Since the address bits of the erased sector are all 0xFFFF after the FLASH memory is erased, the erase status judgment function reads the values ​​of address 0x0000, SECTADDLEN-1 (0x10000-1=0xFFFF), and SECTADDLEN / 2 (0x10000 / 2=0x8000) of the MBIT_SECTNO_START+2 sector being erased. If they are 0xFFFF, the FLASH erase status flag is set to "erasure complete" and the erasure is stopped.

[0163] In the "erase complete" state, within one recording cycle, the data cached in the MBIT_BUFF_FLASH array is immediately written to the starting address 0x0000 of the MBIT_SECTNO_START+1 sector of the FLASH memory. Then, when the next MBIT detection command is received, the detection result is recorded in real time to the current recording address of the corresponding sector to ensure that no information data is lost during operation.

[0164] When recording from sector MBIT_SECTNO_START to sector MBIT_SECTNO_END in sequence according to the above steps, when switching from sector MBIT_SECTNO_START to the next sector (sector MBIT_SECTNO_START+1), the sector after that (sector MBIT_SECTNO_START+2) is erased; when sector MBIT_SECTNO_END is full, the FLASH memory full record flag is set to "valid", and then the cyclic overwrite recording starts from sector MBIT_SECTNO_START.

[0165] For example, such as Figure 6 As shown, the steps for maintaining BIT test result data records are as follows:

[0166] Step 51: When the host computer sends the "Clear Maintenance BIT Result Data Command", the DSP recognizes the command, initializes the FLASH maintenance BIT SECTNO sector number to the starting sector 510 of the maintenance BIT detection data record, initializes the starting address of the sector segment to 0x0000, and simultaneously erases the starting sector 510 and the adjacent sector 511. When the sector erasure is complete, the FLASH erasure status flag is set to "Erasing Complete", and the FLASH sector record full status flag is set to "Empty".

[0167] Step 52: Upon receiving a maintenance BIT test command and entering maintenance BIT mode, the maintenance BIT test result data is recorded in the FLASH memory. The maintenance BIT test involves the detection of analog and discrete circuit excitations of the controller; only the test result data is recorded in the FLASH memory.

[0168] Step 53: In maintenance BIT mode, FLASH starts recording from address 0x0000 of sector 510. When the condition is met: (SECTADDLEN - currently recorded sector address) < maintenance BIT detection data packet length, where SECTADDLEN is the sector length = 0x10000, the sector is considered full, and the process switches to the next sector (sector 511). Simultaneously, the sector after that (sector 510) is erased, and the FLASH erase status flag is set to "erasing in progress." Since data cannot be written to the FLASH memory during the erase process, the process data generated during the erase process is cached in the MBIT_BUFF_FLASH array of the on-chip RAM.

[0169] Step 54: Since the address bits of the erased sector are all 0xFFFF after the FLASH memory is erased, the erase status judgment function reads the values ​​of address 0x0000, SECTADDLEN-1 (0x10000-1=0xFFFF), and SECTADDLEN / 2 (0x10000 / 2=0x8000) of the sector being erased in sector 510 to see if they are 0xFFFF. If they are 0xFFFF, the FLASH erase status flag is set to "erasure complete" and the erasure is stopped.

[0170] Step 55: In the "Erase Complete" state, within one recording cycle, immediately write the data cached in the MBIT_BUFF_FLASH array to the starting address 0x0000 of sector 511 of the FLASH memory. Then, when the next MBIT detection command is received, the detection result is recorded in real time to the current recording address of the sector to ensure that no information data is missing during operation.

[0171] Step 56: When recording from sector 510 to sector 511 in sequence according to the above steps, when switching from sector 510 to the next sector (sector 511), erase the sector after the next (sector 510); when sector 511 is full, set the FLASH memory full record flag to "valid", and then start cyclically overwriting records from sector 510.

[0172] In some optional implementations, the data download operation in the data download function design is to read and upload data in reverse order, starting from the current address of the current recording sector, based on the state of the FLASH record full flag;

[0173] When the record full flag is empty, data download stops at the beginning address of the starting sector;

[0174] When the record is full, the data download starts from the current sector, backtracks to the starting sector, and then jumps to the last sector to continue downloading until the next sector of the current record sector stops.

[0175] In some alternative implementations, the effective download tail address of each sector is determined by the following formula during data download:

[0176] .

[0177] The above embodiments illustrate the design process of the data download function, which includes four functions: startup and normal operation data download, power generation normal operation data download, power generation fault data download, and maintenance BIT detection result data download. Taking startup and normal operation data download as an example, when the host computer sends the "startup and normal operation data download command", the DSP recognizes the command and reads the current sector number QDRUN_SECTNO, sector address Addr, and FLASH full record flag recorded in the FLASH.

[0178] When the FLASH record is full and the flag is "empty", data is read from the current address (Addr) of the current sector number, one data packet at a time, and placed into the buffer array Rn_QD_FLASH. At the same time, the read data packet is uploaded to the host computer via communication until the current sector's starting address (0x0000) is downloaded. Then, the process switches to the previous sector (QDRUN_SECTNO-1) for data download.

[0179] Data is downloaded from the tail address of sector QDRUN_SECTNO-1 backwards until the current sector's starting address 0x0000 is reached. Then, the download continues to the previous sector QDRUN_SECTNO-2, and finally stops at the starting address 0x0000 of sector QDRUN_SECTNO_START.

[0180] When the FLASH record is full, data is read from the current address (Addr) of the current sector number, in units of one data packet, from back to front, and placed into the buffer array Rn_QD_FLASH. The current data packet is then uploaded to the host computer via communication until the current sector's starting address (0x0000) is reached, at which point the process switches to the previous sector (QDRUN_SECTNO-1) for data download.

[0181] Data is downloaded from the last address of sector QDRUN_SECTNO-1 backwards until the current sector's starting address 0x0000 is reached. Then, data is downloaded from the previous sector QDRUN_SECTNO-2 until the starting address of sector QDRUN_SECTNO_START is reached (0x0000). After that, data is downloaded from the last address of the last sector (starting data is from sector QDRUN_SECTNO_END) backwards until the current sector QDRUN_SECTNO+2 is reached. Since the data in sector QDRUN_SECTNO+1 is already erased, no further download is needed.

[0182] Because the FLASH data recording method proposed in this paper only records the complete data packet length in each sector, there may be cases where the recorded data is insufficient to form a complete data packet at the end address. Therefore, the process will move to the next sector to record the complete data packet. Thus, it is necessary to calculate the end address of the sector from which the data is downloaded. The calculation formula is as follows:

[0183] (6)

[0184] The sector length is 0x10000. This is the floor function. This indicates the number of packets that a sector can record. Subtracting 1 is because the sector starts recording from address 0x0000.

[0185] For example, such as Figure 7 As shown, the steps for downloading normal startup data are as follows:

[0186] When the data sector is not full, i.e., the FLASH record full flag is "empty", read the current sector number SECTNO=150 and sector address Add=0x3600 recorded in the FLASH, and record a packet of data b=30, such as Figure 8 As shown, the method includes:

[0187] Step 61: The host computer sends a "Start Normal Operation Data Download Command". When the DSP recognizes the command and the FLASH record full flag is "empty", it reads data from the address 0x3600 of the current 150th sector, with each data packet consisting of 30 16-bit numbers, from the end to the beginning, and puts the data into the buffer Rn_QD_FLASH array. The current data packet is then uploaded to the host computer via communication until the current sector's starting address 0x0000 is reached, at which point the DSP moves to the 149th sector for data download.

[0188] Step 62: Download data from the last address of sector 149 backwards until the current sector's starting address 0x0000 is reached. Then, switch to the previous sector 148 to download data. Finally, stop downloading at the starting address 0x0000 of sector 0.

[0189] When the data sector is full and begins to overwrite and cyclically record data (i.e., the FLASH record full flag is "full"), read the current sector number SECTNO=220 and sector address Add=0x4800 recorded in the FLASH, and record a data packet b=30. Figure 9 As shown, the method includes:

[0190] Step 71: The host computer sends a "Start Normal Operation Data Download Command". When the DSP recognizes the command and the FLASH record full flag is "full", it reads data from address 0x3600 of the current 220th sector, with each data packet consisting of 30 16-bit numbers, from the end to the beginning, and puts the data into the buffer Rn_QD_FLASH array. The current data packet is then uploaded to the host computer via communication until the current sector's starting address 0x0000 is reached, at which point the process switches to the 219th sector for data download.

[0191] Step 72: Download data from the last address bit of sector 219 backwards until the current sector's starting address 0x0000 is reached. Then, switch to the previous sector 218 to download data. After downloading to the starting address 0x0000 of sector 0, switch to the last address bit of sector 249 to download data backwards until the current sector 222 is reached. Since the data in sector 221 has been erased, it does not need to be downloaded.

[0192] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A design method for data recording and downloading in an aircraft starting and generating system, characterized in that, The method includes memory partitioning function design, data recording function design, and data download function design. The memory partitioning function is designed as follows: the FLASH memory is divided into control parameter sector, start-up data sector, normal power generation data sector, power generation fault data sector and maintenance BIT detection data sector, which are used to store the control parameters of the start-up power generation system, the running data of the entire start-up process, the normal power generation data, the power generation fault data and the maintenance BIT detection result data, respectively. The data recording function is designed to record the corresponding operating data, fault data, or control parameters into the corresponding FLASH memory sector according to the different working modes of the system. The data download function is designed to: respond to the data download command issued by the host computer, read data from the corresponding FLASH memory sector and upload it to the host computer.

2. The design method for data recording and downloading of an aircraft starting and generating system according to claim 1, characterized in that, In the memory partitioning function design, the allocation of each sector size is determined by the following formula: Control parameter: number of sectors = 1; The number of data sectors to start, QD_Number, is: ； The number of data sectors for normal power generation operation is FDRun_Number: ； The number of power generation fault data sectors, FDError_Number, is: ； The number of sectors to maintain for BIT testing is MBIT_Number: ； Where Ceil is the floor function, Floor is the floor function, n is the number of records, Tq is the single start-up time, Td is the recording duration of normal power generation, Tn is the recording duration of power generation faults, Ts is the recording period, b is the number of 16-bit data in a single data packet, and SECTADDLEN is the length of a single sector. The number of records is adjusted to maximize the utilization of all sectors of the FLASH memory.

3. The design method for data recording and downloading of an aircraft starting and generating system according to claim 1, characterized in that, The control parameter recording in the data logging function design includes: When the DSP recognizes the control parameter sending command and control parameter data sent by the host computer, it erases the control parameter sector. Write each control parameter data into two adjacent address bits of the control parameter sector; When the system is powered on again, it reads and verifies the control parameters in adjacent address bits in sequence. If the data in the two address bits are consistent, the data is assigned to the corresponding control variable. If they are inconsistent, a fault is reported.

4. The design method for data recording and downloading of an aircraft starting and generating system according to claim 1, characterized in that, The data recording function design includes recording the entire startup process data, including: In response to the clear command issued by the host computer, initialize the starting sector and address of the start data record, and erase the starting sector and the next adjacent sector; In startup mode, startup data packets are recorded to the current sector at fixed intervals; When it is determined that the current sector is about to be full, switch to the next sector to record, and asynchronously erase the next sector; During sector erasure, the generated runtime data is temporarily stored in the on-chip RAM cache array; After the sector erasure is complete, the data in the cache array is written to the target sector, and real-time recording continues. After recording to the last sector, return to the starting sector to perform a loop overwrite recording.

5. The design method for data recording and downloading of an aircraft starting and generating system according to claim 4, characterized in that, The condition for determining that a sector record is about to be full is: the remaining address space in the sector is less than the length of a single packet of data; the method for determining that sector erasure is complete is: read the value of a specific address bit in the erased sector to see if it is 0xFFFF.

6. The design method for data recording and downloading of an aircraft starting and generating system according to claim 1, characterized in that, The data recording function design includes the recording of power generation operation data and power generation fault data, including: Normal power generation data and power generation fault data are recorded separately. The data recording for normal power generation operation adopts a cyclical recording method with a relatively long recording cycle; Power generation fault data recording begins when a fault is triggered, and the recording period is short to avoid fault data being overwritten by normal operating data.

7. The design method for data recording and downloading of an aircraft starting and generating system according to claim 1, characterized in that, The data download function design involves reading and uploading data in reverse order, starting from the current address of the current record sector, based on the FLASH record full status, in units of one packet of data. When the record full flag is empty, data download stops at the beginning address of the starting sector; When the record is full, the data download starts from the current sector, backtracks to the starting sector, and then jumps to the last sector to continue downloading until the next sector of the current record sector stops.

8. The design method for data recording and downloading of an aircraft starting and generating system according to claim 7, characterized in that, During data download, the valid download tail address for each sector is determined using the following formula: 。

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