Graphics processor chip, reset system, reset method and electronic device

Abstract

This application discloses a graphics processing unit (GPU) chip, a reset system, a reset method, and an electronic device, belonging to the field of computer technology. The GPU chip includes a graphics processing module, a PCIe control module, and a reset control module, with the reset control module coupled to both the graphics processing module and the PCIe control module. The reset control module controls the graphics processing module to reset during the GPU chip reset process and controls the PCIe control module not to participate in the reset. The reset control module includes a PCIe link holding module and a watchdog module. Both the PCIe link holding module and the watchdog module are in operation during the GPU chip reset. The PCIe link holding module is communicatively connected to the PCIe control module and is used to: control the PCIe control module to remain powered on and not participate in the reset during the GPU chip reset process, ensuring the PCIe link is not interrupted.

Description

Technical Field

[0001] This application belongs to the field of computer science, and specifically relates to a graphics processor chip, a reset system, a reset method, and an electronic device. Background Technology

[0002] Currently, graphics processing unit (GPU) chips typically communicate with the host via the PCI Express (PCIe) bus. During the operation of a GPU chip, a chip-level reset may be triggered due to software malfunctions, firmware upgrades, internal logic errors, or watchdog timeouts.

[0003] The reset mechanism in related technologies usually adopts a global reset method, that is, when a reset is triggered, all functional modules in the graphics processor chip are reset uniformly.

[0004] However, this reset method in related technologies can cause PCIe link interruption. After the host detects that the PCIe link is disconnected, it will determine that the graphics processor chip is abnormally removed, which may lead to service interruption or system instability. Summary of the Invention

[0005] This application provides a graphics processor chip, a reset system, a reset method, and an electronic device, which can solve the problem of PCIe link interruption during the reset process of a graphics processor chip in related technologies.

[0006] In a first aspect, a graphics processor chip is provided, comprising: a graphics processing module, a PCIe control module, and a reset control module, wherein the reset control module is coupled to the graphics processing module and the PCIe control module respectively;

[0007] The reset control module is used to control the graphics processing module to reset during the reset process of the graphics processor chip, and to control the PCIe control module not to participate in the reset; wherein, the PCIe control module is a module used to control the PCIe link, and the PCIe link is not interrupted during the reset process of the graphics processor chip.

[0008] The reset control module includes a PCIe link holding module and a watchdog module; the PCIe link holding module and the watchdog module are in operation during the graphics processor chip reset.

[0009] The PCIe link holding module is communicatively connected to the PCIe control module. The PCIe link holding module is used to: control the PCIe control module to remain powered on during the graphics processor chip reset and keep the PCIe link uninterrupted.

[0010] In a second aspect, a reset system is provided, including a host and a graphics processor chip according to the first aspect, wherein the host and the graphics processor chip are connected via a PCIe link.

[0011] Thirdly, a reset method is provided for the graphics processor chip described in the first aspect, the reset method comprising:

[0012] During the graphics processor chip reset process, the watchdog module sends a reset signal to the graphics processing module;

[0013] During the graphics processor chip reset, the PCIe link holding module controls the PCIe control module to remain powered on and ensures that the PCIe link is not interrupted.

[0014] After the graphics processing module completes its reset, the PCIe link holding module coordinates the reconnection between the PCIe control module and the graphics processing module, enabling the graphics processor chip to resume normal communication.

[0015] Fourthly, an electronic device is provided, including a processor and a memory, the memory storing a program or instructions that, when executed by the processor, implement the method as described in the first aspect.

[0016] Fifthly, a readable storage medium is provided, on which a program or instructions are stored, which, when executed by a processor, implement the method as described in the first aspect.

[0017] A sixth aspect provides a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0018] In this embodiment, the graphics processing unit (GPU) chip includes a reset control module, which comprises a PCIe link holding module and a watchdog module. Both the PCIe link holding module and the watchdog module are operational during GPU chip reset. The PCIe link holding module is used to: control the PCIe control module to remain powered on and not participate in the reset during GPU chip reset, thus ensuring the PCIe link remains uninterrupted. Therefore, by controlling the PCIe control module to remain powered on and not participate in the reset during GPU chip reset, the PCIe link remains uninterrupted, thereby solving the problem of PCIe link interruption during GPU chip reset in related technologies. Attached Figure Description

[0019] Figure 1This is a schematic diagram of a graphics processor chip provided in an embodiment of this application;

[0020] Figure 2 This is a schematic diagram of a reset system provided in an embodiment of this application;

[0021] Figure 3 This is a flowchart of a reset method provided in an embodiment of this application;

[0022] Figure 4 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0024] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0025] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0026] To better understand this application, some terms involved in the embodiments of this application will be explained below.

[0027] A graphics processing unit (GPU) is a processor specifically designed for performing complex mathematical and geometric calculations. While its core task was originally to accelerate the rendering of computer graphics and images, its unique architecture has made it a key engine driving the artificial intelligence (AI) and high-performance computing (HPC) revolutions.

[0028] PCI Express (PCIe) is one of the most important internal connectivity technologies in modern computer systems. It can be understood as the computer's "neural network," with PCIe responsible for high-speed data transfer between key components such as the CPU, memory, graphics card, solid-state drive (SSD), and network card.

[0029] A watchdog timer (WDT) is a hardware circuit or software timer used in embedded systems to monitor the system's operating status. The core function of a watchdog timer is to automatically trigger a reset signal and force a system restart when the system becomes unresponsive due to software failures (such as program crashes or infinite loops) or external interference, thereby restoring it to a normal state. When the watchdog timer is a hardware circuit, it can be a dedicated module integrated within the graphics processing unit (GPU) chip and can have its own independent clock source.

[0030] The watchdog's workflow can be summarized as a clear closed loop as follows:

[0031] Start-up timing: After the system starts up, the watchdog timer begins to count down from a preset value (or increment from 0).

[0032] Normal watchdog feeding: In a normally running program, a "watchdog feeding" operation will be performed periodically before the watchdog timer overflows (decreases to 0 or increases to the upper limit) to reset the counter back to its initial value.

[0033] Abnormal timeout: If the program fails to feed the dog on time due to reasons such as infinite loop or freezing, the counter will continue to count until it overflows (timeout).

[0034] Triggered Reset: After the counter overflows, the watchdog module will immediately send a reset signal to the system, forcing a restart and giving the system a chance to recover from the fault.

[0035] Because the PCIe controller and its physical and link layer logic on the GPU chip are reset simultaneously during the reset process, the PCIe link is forced to be interrupted. Upon detecting the link disconnection, the host-side PCIe root complex typically determines the device as abnormally removed and triggers corresponding error handling mechanisms, such as re-enumerating the PCIe bus, reporting a serious error, or directly removing the device from the system. In server and data center applications, this behavior often manifests as device "card drop," service interruption, or even decreased system stability.

[0036] To address the aforementioned issues, some related technologies attempt to restore the device through host-side software intervention. Examples include driver-driven device re-initialization, triggering a PCIe bus hot reset, or relying on a system-level reboot to restore the device's operational state. However, these solutions typically have long recovery times, heavily rely on the host operating system and driver environment, cannot guarantee the continuity of the PCIe link at the moment of device reset, and still carry the risk of the device being mistakenly identified as removed by the host.

[0037] Other related technologies have proposed solutions to restore communication by retraining the PCIe link after the device is reset. However, this method requires going through the entire link training and enumeration process, which not only increases the system recovery latency but may also cause the device to fail to come back online due to link training failure. This makes it difficult to meet the continuous operation requirements of high reliability and high availability systems.

[0038] Therefore, related technologies generally suffer from the following shortcomings: they cannot effectively maintain a continuous PCIe link connection when a device experiences an abnormal reset or restart, which can easily lead to problems such as device loss, card drop, and system instability on the host side. How to prevent the PCIe link from being disconnected when PCIe devices such as GPU chips are reset, and ensure that the host side always maintains effective recognition of the device, has become an urgent technical problem to be solved.

[0039] To address the issue that existing PCIe devices such as GPU chips are prone to PCIe link interruption and host-side device loss during abnormal reset or restart, this application proposes a graphics processor chip, reset system, and reset method for PCIe link maintenance, which can maintain PCIe link stability during device reset.

[0040] This application embodiment improves the internal reset architecture of the GPU chip so that during the GPU chip reset process, the PCIe link-related functional modules, namely the PCIe control module, do not participate in the reset, thereby achieving continuous maintenance of the PCIe link.

[0041] Figure 1 This is a schematic diagram of a graphics processor chip provided in an embodiment of this application. (Refer to...) Figure 1 The graphics processor chip 100 provided in this embodiment includes a graphics processing module 110, a PCIe control module 120, and a reset control module 130. The reset control module 130 is coupled to both the graphics processing module 110 and the PCIe control module 120. The reset control module 130 controls the reset of each module within the graphics processor chip 100 and can provide reset signals to the modules within the graphics processor chip 100.

[0042] The reset control module 130 is used to control the graphics processing module 110 to reset during the graphics processor chip reset process, and to control the PCIe control module 120 not to participate in the reset. The PCIe control module 120 is a module for controlling the PCIe link, and the PCIe link is not interrupted during the graphics processor chip reset process. The PCIe control module 120 may include a PCIe controller, and may also include physical layer logic and link layer logic of the PCIe controller. The graphics processing module 110 may include GPU core logic, which may include at least one of a GPU core computing module, an internal interconnect module, and a storage control module. The PCIe link being uninterrupted during the graphics processor chip reset process means that the PCIe link is in a continuously connected state during the graphics processor chip reset process; that is, the PCIe link between the host and the PCIe device (e.g., graphics processor chip 100) remains connected and is not disconnected during the graphics processor chip reset process.

[0043] The reset control module 130 includes a PCIe link holding module and a watchdog module; the PCIe link holding module and the watchdog module are in operation during the reset of the graphics processor chip 100.

[0044] The PCIe link holding module is communicatively connected to the PCIe control module 120. The PCIe link holding module is used to control the PCIe control module 120 to remain powered on and not participate in the reset during the reset of the graphics processor chip 100, so that the PCIe link is not interrupted.

[0045] In this embodiment, the graphics processing unit (GPU) chip includes a reset control module, which comprises a PCIe link holding module and a watchdog module. Both the PCIe link holding module and the watchdog module are operational during GPU chip reset. The PCIe link holding module is used to: control the PCIe control module to remain powered on and not participate in the reset during GPU chip reset, thus ensuring the PCIe link remains uninterrupted. Therefore, by controlling the PCIe control module to remain powered on and not participate in the reset during GPU chip reset, the PCIe link remains uninterrupted, thereby solving the problem of PCIe link interruption during GPU chip reset in related technologies.

[0046] In some embodiments of this application, the watchdog module is used to send a reset signal to the graphics processing module within the graphics processor chip, without applying a reset operation to the PCIe link holding module. The watchdog module can also be used to send a reset signal to the PCIe control module within the graphics processor chip. In other embodiments of this application, the watchdog module can be used to send reset signals to all modules within the graphics processor chip except for the reset control module.

[0047] It should be noted that in some embodiments of this application, the PCIe link holding module and the watchdog module may be located in the same reset holding domain of the graphics processor chip. The reset holding domain is an area that remains powered on and retains data during the graphics processor chip reset. In other embodiments of this application, the PCIe link holding module may be located inside the watchdog module. Thus, since the watchdog module remains operational during the graphics processor chip reset and is not reset, this method allows the PCIe link holding module to continue operating during the graphics processor chip reset without being reset.

[0048] In this embodiment, the PCIe link can be a PCIe link between the graphics processor chip and the host. The host is a device external to the graphics processor chip. In a specific implementation where the PCIe link holding module controls the PCIe control module not to participate in the reset, the PCIe link holding module is used to: shield the PCIe control module from the impact of the reset signal from inside the graphics processor chip, preventing the PCIe control module from sending target indication information to the host, the target indication information indicating that the PCIe link is disconnected or the PCIe device is unreachable. The PCIe device may include the graphics processor chip. This ensures that the PCIe control module does not participate in the reset and allows the host to always maintain effective recognition of the PCIe device.

[0049] In some embodiments of this application, the PCIe link persistence module can also be used to: after the graphics processing module reset is completed, coordinate the re-interface between the PCIe control module and the graphics processing module, enabling the graphics processor chip to resume normal communication. Specifically, the PCIe link persistence module can be used to: after the graphics processing module reset is completed, coordinate the re-interface between the PCIe control module and the graphics processing module, enabling the graphics processor chip to resume normal communication without retraining the PCIe link and without triggering the host to re-enumerate. Thus, throughout the entire reset and recovery process, the host side maintains effective identification of the PCIe device, thereby preventing device loss or system anomalies. Device loss refers to the phenomenon where, during normal system operation, the operating system suddenly loses a PCIe device, and the device logically disappears from the system.

[0050] In this embodiment, PCIe link training essentially refers to a complex handshake and negotiation process automatically executed by the physical layer after a PCIe device is powered on or reset. The entire process is managed entirely by the Link Training and Status State Machine (LTSSM) in the hardware, without any software intervention. The core objective of PCIe link training is to ensure that both communicating parties reach an agreement on link bandwidth, transmission rate, and signal quality, preparing for subsequent data transmission.

[0051] PCIe link training can involve the following states: detect, polling, configuration, L0, and recovery. The detect state is used to detect the presence of a device at the other end of the link; the polling state is used to establish a basic communication link; the configuration state is used to write and determine the link's operating parameters; the L0 state is the normal operating state of the link; and the recovery state is used to reconfigure the link.

[0052] The ultimate goal of link training is to stabilize the LTSSM in the L0 state. At this point, the physical layer link establishment is complete, paving the way for data interaction at the upper layers. Only then will the system perform software-level tasks such as device enumeration and resource allocation.

[0053] In this embodiment, host re-enumeration, simply put, is the process by which the operating system or Basic Input / Output System (BIOS) forces the PCIe subsystem to rediscover, identify, and configure all devices on the bus. Normal enumeration occurs during system startup. After the system is already running (Post-Boot), re-enumeration will be triggered if hot-plugging, link error recovery, or reset occurs.

[0054] Link training occurs at the physical layer and aims to enable two ports to successfully "handshake" physically, confirming transmission rate and bandwidth. This is a prerequisite for re-enumeration. Re-enumeration occurs at the bus driver / operating system layer and aims to allocate logical resources (addresses, interrupts) to physically existing devices, making them accessible to the processor.

[0055] The graphics processor chip and its reset process provided in the embodiments of this application will be further explained below.

[0056] In existing technologies, GPU chips typically employ a total reset when an anomaly occurs. When the watchdog module triggers a reset, it simultaneously resets the GPU core logic and the PCIe controller, resulting in the clearing of the PCIe physical layer and data link layer states. The host then detects the disconnected link and determines the device to be removed. To address these issues, this application redesigns the reset mechanism from the perspective of dividing the chip's internal reset domain.

[0057] More specifically, in embodiments of this application, the PCIe link holding function module can be located inside the watchdog module within the GPU chip, or within the same reset holding domain as the watchdog module. Since the watchdog module typically remains operational during GPU chip reset and is not reset, this method ensures that the PCIe link holding module continues to run during GPU reset.

[0058] In its implementation, when the GPU chip is operating normally, the PCIe link holding module is in a monitoring or standby state, monitoring the PCIe link status in real time. When an anomaly is detected and the GPU chip is reset by the watchdog module, the watchdog module only sends a reset signal to the GPU core logic and does not apply a reset operation to the PCIe link holding module. The GPU core logic may include at least one of the following: a GPU core computing module, an internal interconnect module, and a storage control module.

[0059] During GPU core logic reset, the PCIe link holding module applies holding control to the PCIe control module, keeping the PCIe physical layer powered on and preventing the link layer state machine from entering a disconnected or retrained state. Simultaneously, the link holding module shields the PCIe link registers (such as some critical registers) and state machine from the effects of internal GPU reset signals, preventing the PCIe control module from sending indications of link disconnection or device unreachability to the host.

[0060] After the GPU core logic is reset, the PCIe link maintenance module coordinates the reconnection of the PCIe controller and graphics processing modules, such as the GPU core logic, enabling the GPU chip to resume normal communication without retraining the PCIe link or triggering host re-enumeration. Throughout the reset and recovery process, the host side maintains effective recognition of the PCIe device, thereby preventing device loss or system malfunctions.

[0061] Through the above technical solution, the embodiments of this application effectively solve the problem of PCIe link interruption when the GPU chip is abnormally reset in related technologies. Compared with the solution that relies on host-side re-enumeration or restart, the embodiments of this application significantly reduce system recovery latency and improve the continuity and reliability of system operation. At the same time, the solution provided by the embodiments of this application is implemented entirely inside the GPU chip, transparent to the host system and drivers, and has good versatility and engineering feasibility, making it suitable for server and data center application scenarios with high requirements for stability and availability.

[0062] Figure 2 This is a schematic diagram of a reset system provided in an embodiment of this application. (Refer to...) Figure 2 The reset system provided in this application includes a host 200 and a graphics processor chip 100 according to any of the above embodiments. The host 200 and the graphics processor chip 100 are connected via a PCIe link. The graphics processor chip 100 provided in this application includes a graphics processing module 110, a PCIe control module 120, and a reset control module 130. The relevant details of the graphics processing module 110, the PCIe control module 120, and the reset control module 130 can be found in the foregoing description.

[0063] exist Figure 2 In the reset system shown, the graphics processing unit (GPU) chip can complete the reset process internally, without relying on the host computer. After the GPU chip is reset, it can communicate with the host computer.

[0064] Figure 3 This is a flowchart of a reset method provided in an embodiment of this application. (Refer to...) Figure 3The reset method provided in this application embodiment can be applied to the graphics processing unit (GPU) chip provided in any of the above embodiments, such as... Figure 1 The graphics processor chip shown. The reset method provided in this application embodiment may include:

[0065] Step 310: During the graphics processor chip reset process, the watchdog module sends a reset signal to the graphics processing module.

[0066] Step 320: During the graphics processor chip reset, the PCIe link holding module controls the PCIe control module to remain powered on and ensures that the PCIe link is not interrupted.

[0067] Step 330: After the graphics processing module reset is completed, the PCIe link holding module coordinates the re-interface between the PCIe control module and the graphics processing module, so that the graphics processor chip can resume normal communication.

[0068] In step 310, the watchdog module can also send reset signals to all modules within the graphics processor chip except for the reset control module.

[0069] In step 320, the PCIe link holding module can shield the PCIe control module from the reset signal from inside the GPU chip, preventing the PCIe control module from sending target indication information to the host, which indicates that the PCIe link is disconnected or the PCIe device is unreachable.

[0070] In step 330, after the graphics processing module reset is completed, the PCIe link holding module can coordinate the re-interface between the PCIe control module and the graphics processing module, so that the GPU chip can resume normal communication without retraining the PCIe link or triggering the host to re-enumerate.

[0071] In this embodiment, the graphics processing unit (GPU) chip includes a reset control module, which comprises a PCIe link holding module and a watchdog module. Both the PCIe link holding module and the watchdog module are operational during GPU chip reset. The PCIe link holding module is used to: control the PCIe control module to remain powered on and not participate in the reset during GPU chip reset, thus ensuring the PCIe link remains uninterrupted. Therefore, by controlling the PCIe control module to remain powered on and not participate in the reset during GPU chip reset, the PCIe link remains uninterrupted, thereby solving the problem of PCIe link interruption during GPU chip reset in related technologies.

[0072] It should be understood that the relevant content of the reset method provided in the embodiments of this application can be referred to the above text, and will not be repeated here.

[0073] Figure 4 This is a structural block diagram of an electronic device provided in an embodiment of this application. For example... Figure 4 As shown in the illustration, this application also provides an electronic device 400. The electronic device 400 includes a processor 410 and a memory 420. The memory 420 stores programs or instructions, which, when executed by the processor 410, implement the steps of any of the methods described above. For example, when the program is executed by the processor 410, it implements the following process: during the graphics processor chip reset process, the watchdog module sends a reset signal to the graphics processing module; during the graphics processor chip reset, the PCIe link holding module controls the PCIe control module to remain powered on and maintains the PCIe link without interruption; after the graphics processing module reset is completed, the PCIe link holding module coordinates the re-interface between the PCIe control module and the graphics processing module, enabling the graphics processor chip to resume normal communication.

[0074] In this embodiment, the graphics processing unit (GPU) chip includes a reset control module, which comprises a PCIe link holding module and a watchdog module. Both the PCIe link holding module and the watchdog module are operational during GPU chip reset. The PCIe link holding module is used to: control the PCIe control module to remain powered on and not participate in the reset during GPU chip reset, thus ensuring the PCIe link remains uninterrupted. Therefore, by controlling the PCIe control module to remain powered on and not participate in the reset during GPU chip reset, the PCIe link remains uninterrupted, thereby solving the problem of PCIe link interruption during GPU chip reset in related technologies.

[0075] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the steps in the reset method provided in the above embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0076] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0077] This application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the above method embodiments and achieve the same technical effects. To avoid repetition, it will not be described again here.

[0078] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0079] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0080] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A graphics processing unit chip, characterized in that, include: The system includes a graphics processing module, a PCIe rapid peripheral interconnect (PCIe) control module, and a reset control module, wherein the reset control module is coupled to the graphics processing module and the PCIe control module, respectively. The reset control module is used to control the graphics processing module to reset during the reset process of the graphics processor chip, and to control the PCIe control module not to participate in the reset; wherein, the PCIe control module is a module used to control the PCIe link, and the PCIe link is not interrupted during the reset process of the graphics processor chip. The reset control module includes a PCIe link holding module and a watchdog module; the PCIe link holding module and the watchdog module are in operation during the graphics processor chip reset. The PCIe link holding module is communicatively connected to the PCIe control module. The PCIe link holding module is used to control the PCIe control module to remain powered on and not participate in the reset during the graphics processor chip reset, so that the PCIe link is not interrupted.

2. The graphics processor chip according to claim 1, characterized in that, The PCIe link holding module and the watchdog module are located in the same reset holding domain of the graphics processor chip. The reset holding domain is an area that remains powered on and can retain data during the reset of the graphics processor chip; or, the PCIe link holding module is located inside the watchdog module.

3. The graphics processor chip according to claim 2, characterized in that, The PCIe link is the PCIe link between the graphics processor chip and the host; the PCIe link holding module is also used to: shield the PCIe control module from the reset signal from inside the graphics processor chip, and prevent the PCIe control module from sending target indication information to the host, the target indication information indicating that the PCIe link is disconnected or the PCIe device is unreachable.

4. The graphics processor chip according to claim 3, characterized in that, The PCIe link holding module is also used to: after the graphics processing module has been reset, coordinate the re-interface between the PCIe control module and the graphics processing module, so that the graphics processor chip can resume normal communication without retraining the PCIe link and without triggering the host to re-enumerate.

5. The graphics processor chip according to claim 1, characterized in that, The watchdog module is used to send a reset signal to the graphics processing module without applying a reset operation to the PCIe link holding module.

6. A reset system, characterized in that, It includes a host computer and a graphics processing unit (GPU) chip according to any one of claims 1-5, wherein the host computer and the GPU chip are connected via a PCIe link.

7. A reset method, characterized in that, The reset method, applied to the graphics processor chip according to claim 1, includes: During the graphics processor chip reset process, the watchdog module sends a reset signal to the graphics processing module; During the graphics processor chip reset, the PCIe link holding module controls the PCIe control module to remain powered on and ensures that the PCIe link is not interrupted. After the graphics processing module completes its reset, the PCIe link holding module coordinates the reconnection between the PCIe control module and the graphics processing module, enabling the graphics processor chip to resume normal communication.

8. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that, when executed by the processor, implement the method as described in claim 7.

9. A readable storage medium, characterized in that, A program or instructions are stored on the readable storage medium, which, when executed by a processor, implement the method as described in claim 7.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method as described in claim 7.

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