Radio frequency power amplifier module and power protection method thereof

Abstract

This invention discloses an RF power amplifier module and its power protection method. The module includes a controller chip, an RF power amplifier chip, and a filter connected in sequence. The controller chip is connected to a power supply voltage VCC that powers the RF power amplifier chip. The controller chip detects the power supply voltage VCC and outputs a limiting bias voltage that increases with the increase of the power supply voltage VCC when VCC exceeds a set threshold. The RF power amplifier chip includes a limiting circuit and a power amplifier unit. The limiting circuit limits and attenuates the RF input signal according to the limiting bias voltage to obtain an attenuated RF signal. The power amplifier unit amplifies the attenuated RF signal before outputting it. The filter filters the amplified RF signal to output an RF signal in the target frequency band. This invention can adaptively change the limiting degree according to the power level and improve the speed of power detection.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more specifically, to a radio frequency power amplifier module and its power protection method. Background Technology

[0002] Currently, mainstream 5G mobile terminal RF front-end solutions have evolved to Phase 8, with solutions continuously moving towards higher integration and miniaturization. The most integrated L-PAMiD solution modularizes power amplifiers (PAs), RF switches, controllers, low-noise amplifiers (LNAs), and filters into a single RF power amplifier module to support the RF communication functions of mobile terminals. However, when the input power is high, the power amplifier's output power approaches saturation, especially during module robustness testing. At this point, the amplifier transistors experience significant voltage swings and current surges, leading to severe overheating and potentially irreversible damage such as transistor burnout. Therefore, improving the reliability of RF power amplifier modules under high input power conditions by adding protection circuitry is a crucial and meaningful task.

[0003] In the existing technology, there are some solutions designed to protect power amplifiers, but they all have certain limitations:

[0004] Existing technology 1 discloses an RF front-end module with input limiting protection. Each amplifier stage of this RF front-end module includes at least one limiting circuit and its bias circuit, input matching circuit, and amplifier transistor. The limiting circuit is used to limit the input signal power and output a lower power signal. When the input power of the transmit path exceeds a set threshold, the limiting circuit activates its limiting function, reducing the input power to protect the amplifier transistor. The drawback of this solution is its poor linkage with power; it cannot adaptively change the limiting degree according to the power level, lacking flexibility and limiting its practical application.

[0005] Prior art 2 discloses an RF front-end module with input power protection, comprising a signal input terminal, a bias circuit, an amplifier, and a signal output terminal connected in sequence. The bias circuit detects the power of the input amplifier and, based on the detected average power of the input signal, actively reduces the bias current of the input power amplifier to protect it. The drawback of this solution is that, because power detection requires a certain amount of time, the real-time performance of the protected amplifier is poor, and the response speed is slow. It is easy for the amplifier to burn out before high power is successfully detected, resulting in unsatisfactory practical performance. Summary of the Invention

[0006] The purpose of this invention is to propose an RF power amplifier module and its power protection method, which can adaptively change the limiting degree according to the power level and improve the power detection speed.

[0007] To achieve the above objectives, the present invention proposes an RF power amplifier module, comprising a controller chip (101), an RF power amplifier chip (102), and a filter (109) connected in sequence.

[0008] The controller chip (101) is connected to the power supply voltage VCC that supplies power to the radio frequency power amplifier chip (102). The controller chip (101) is used to detect the power supply voltage VCC and output a limiting bias voltage (VDIODE) that increases with the increase of the power supply voltage VCC when the power supply voltage VCC exceeds a set threshold.

[0009] The radio frequency power amplifier chip (102) includes a limiting circuit (107) and a power amplifier unit (108); the limiting circuit (107) is used to limit and attenuate the radio frequency input signal (RFIN) according to the limiting bias voltage (VDIODE) to obtain the attenuated radio frequency signal (RFIN_Limit); the power amplifier unit (108) is used to amplify the attenuated radio frequency signal (RFIN_Limit) and output it.

[0010] The filter (109) is used to filter the amplified radio frequency signal to output the radio frequency signal (RFOUT) of the target frequency band.

[0011] Optionally, the controller chip (101) includes a voltage detection and comparison unit (103) and a limiting bias LDO circuit (104).

[0012] The voltage detection and comparison unit (103) includes a VCC voltage divider circuit (105) and a voltage comparison current generation circuit (106).

[0013] The VCC voltage divider circuit (105) is used to divide the power supply voltage VCC that supplies power to the RF power amplifier chip (102) to generate a voltage divider signal;

[0014] The voltage comparison current generation circuit (106) is used to compare the voltage divider signal with the first reference voltage (VREF2), and after the power supply voltage VCC reaches the set threshold (VCC_VTH), it generates and outputs a pull-up current (Isource) that gradually increases with the increase of the power supply voltage VCC.

[0015] The limiting bias LDO circuit (104) is used to generate the limiting bias voltage (VDIODE), and after receiving the source current (Isource), the limiting bias voltage (VDIODE) gradually increases as the power supply voltage VCC increases.

[0016] Optionally, the VCC voltage divider circuit (105) includes: a first voltage divider resistor (R1), a second voltage divider resistor (R2), and a voltage buffer (310).

[0017] The first voltage divider resistor (R1) and the second voltage divider resistor (R2) are connected in series between the power supply voltage VCC and ground to divide the power supply voltage VCC, and output the first voltage divider voltage (VDIV1) at the connection node of the first voltage divider resistor (R1) and the second voltage divider resistor (R2).

[0018] The voltage buffer (310) is composed of an operational amplifier connected in unity gain. The positive input terminal of the voltage buffer (310) is connected to the first voltage divider (VDIV1). The inverting input terminal of the voltage buffer (310) is shorted to its output terminal. The output terminal of the voltage buffer (310) outputs a second voltage divider (VDIV2) with driving capability. The second voltage divider (VDIV2) is the voltage divider signal. The power supply terminal of the voltage buffer (310) is connected to the power supply VBAT of the controller chip (101).

[0019] Optionally, the voltage comparison current generation circuit (106) includes: a bias current source (IBIAS), a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), and a fourth NMOS transistor (MN4).

[0020] One end of the bias current source (IBIAS) is connected to the power supply VBAT, and the other end of the bias current source (IBIAS) is connected to the drain of the first NMOS transistor (MN1).

[0021] The drain and gate of the first NMOS transistor (MN1) are connected to each other, and the source of the first NMOS transistor (MN1) is grounded;

[0022] The gate of the second NMOS transistor (MN2) is connected to the gate of the first NMOS transistor (MN1), the drain of the second NMOS transistor (MN2) is connected to the drain of the first PMOS transistor (MP1), and the source of the second NMOS transistor (MN2) is grounded.

[0023] The gate and drain of the first PMOS transistor (MP1) are connected to each other, and the source of the first PMOS transistor (MP1) is connected to the first reference voltage (VREF2).

[0024] The gate of the second PMOS transistor (MP2) is connected to the gate of the first PMOS transistor (MP1), the source of the second PMOS transistor (MP2) is connected to the second voltage divider (VDIV2), and the drain of the second PMOS transistor (MP2) is connected to the drain of the third NMOS transistor (MN3).

[0025] The gate and drain of the third NMOS transistor (MN3) are connected to each other, and the source of the third NMOS transistor (MN3) is grounded;

[0026] The gate of the fourth NMOS transistor (MN4) is connected to the gate of the third NMOS transistor (MN3), the source of the fourth NMOS transistor (MN4) is grounded, and the drain of the fourth NMOS transistor (MN4) serves as the circuit output terminal, outputting the source current (Isource).

[0027] The first PMOS transistor (MP1) and the second PMOS transistor (MP2), the first NMOS transistor (MN1) and the second NMOS transistor (MN2), and the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) respectively form current mirrors.

[0028] Optionally, the VCC voltage divider circuit (105) includes a voltage divider resistor network, a voltage divider point selection network, and a voltage buffer (310).

[0029] The voltage divider resistor network includes multiple voltage divider resistors connected in series between the power supply voltage VCC and ground, and voltage divider taps are respectively provided at the series nodes between the multiple voltage divider resistors.

[0030] The voltage divider selection network includes multiple transmission gates. The input of each transmission gate is connected to a voltage divider tap. The outputs of the multiple transmission gates are interconnected and connected to the positive input of the voltage buffer (310). Each transmission gate is controlled by a corresponding logic control signal to select one of the voltages from the multiple voltage divider taps as the first voltage divider voltage (VDIV1) and output it to the voltage buffer (310).

[0031] The input terminal of the voltage buffer (310) is connected to the common output terminal of the voltage divider selection circuit. The output terminal of the voltage buffer (310) outputs a second voltage divider voltage (VDIV2) with driving capability. The second voltage divider voltage (VDIV2) is the voltage divider signal. The inverting input terminal of the voltage buffer (310) is short-circuited with its output terminal. The power supply terminal of the voltage buffer (310) is connected to the power supply VBAT of the controller chip (101).

[0032] Optionally, the voltage comparison current generation circuit (106) includes: a first bias current source (IBIAS), a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), a plurality of auxiliary NMOS transistors, and a plurality of transmission gates;

[0033] One end of the bias current source (IBIAS) is connected to the power supply VBAT, and the other end of the bias current source (IBIAS) is connected to the drain of the first NMOS transistor (MN1).

[0034] The drain and gate of the first NMOS transistor (MN1) are connected to each other, and the source of the first NMOS transistor (MN1) is grounded;

[0035] The gate of the second NMOS transistor (MN2) is connected to the gate of the first NMOS transistor (MN1), the drain of the second NMOS transistor (MN2) is connected to the drain of the first PMOS transistor (MP1), and the source of the second NMOS transistor (MN2) is grounded.

[0036] The gate and drain of the first PMOS transistor (MP1) are connected to each other, and the source of the first PMOS transistor (MP1) is connected to the first reference voltage (VREF2).

[0037] The gate of the second PMOS transistor (MP2) is connected to the gate of the first PMOS transistor (MP1), the source of the second PMOS transistor (MP2) is connected to the second voltage divider (VDIV2), and the drain of the second PMOS transistor (MP2) is connected to the drain of the third NMOS transistor (MN3).

[0038] The gate and drain of the third NMOS transistor (MN3) are connected to each other, and the source of the third NMOS transistor (MN3) is grounded;

[0039] The sources of the multiple auxiliary NMOS transistors are all grounded, and their gates are all connected to the gate of the third NMOS transistor (MN3). The third NMOS transistor (MN3) and the multiple auxiliary NMOS transistors respectively form current mirrors with different scaling factors.

[0040] The input terminals of the multiple transmission gates are all connected to the gate of the third NMOS transistor (MN3), and the output terminal of each transmission gate is connected to the gate of an auxiliary NMOS transistor.

[0041] The drains of all the auxiliary NMOS transistors are connected together to serve as the output terminal of the source current (Isource);

[0042] The control terminal of each transmission gate receives the corresponding logic control signal to selectively turn on the corresponding transmission gate and turn on the current mirror composed of the corresponding auxiliary NMOS transistor and the third NMOS transistor (MN3) to adjust the mirror ratio of the source current (Isource).

[0043] Optionally, the voltage detection and comparison unit (103) further includes a second set of VCC voltage divider circuits and a second set of voltage comparison current generation circuits; the second set of VCC voltage divider circuits has the same circuit structure as the VCC voltage divider circuits, and the second set of voltage comparison current generation circuits has the same circuit structure as the voltage comparison current generation circuits.

[0044] The second voltage divider circuit is used to divide the power supply voltage VCC and output a third voltage divider voltage (VDIV62).

[0045] The second set of voltage comparison current generation circuits is used to compare the third voltage divider (VDIV62) with the third reference voltage (VREF3), and output the second sourcing current (Isource_2) when the power supply voltage VCC reaches the second threshold (VCC_VTH_2).

[0046] The second pull current (Isource_2) output by the second voltage comparison current generation circuit is superimposed with the pull current (Isource) output by the voltage comparison current generation circuit (106) and then input to the limiting bias LDO circuit (104).

[0047] Optionally, the limiting bias LDO circuit (104) includes a bandgap reference circuit (301), an error amplifier (302), a power transistor (303), and a resistor network (304).

[0048] The input terminal of the bandgap reference circuit (301) is connected to the power supply VBAT. The first output terminal of the bandgap reference circuit (301) is used to output the first reference voltage (VREF2). The first output terminal of the bandgap reference circuit (301) is used to output the second reference voltage (VREF1).

[0049] The non-inverting input terminal of the error amplifier (302) is connected to the second reference voltage (VREF1), the output terminal of the error amplifier (302) is connected to the gate of the power transistor (303), and the power supply terminal of the error amplifier (302) is connected to the power supply VBAT.

[0050] The source of the power transistor (303) is connected to the power supply VBAT, and the drain of the power transistor (303) outputs the limiting bias voltage (VDIODE).

[0051] The resistor network (304) includes a third resistor (R3), a fourth resistor (R4), and a fifth resistor (R5). One end of the third resistor (R3) is grounded, and the other end of the third resistor (R3) is connected to one end of the fourth resistor (R4). The other end of the fourth resistor (R4) is connected to one end of the fifth resistor (R5), and the other end of the fifth resistor (R5) is connected to the drain of the power transistor (303). The connection node between the third resistor (R3) and the fourth resistor (R4) serves as a feedback node (VFB) connected to the inverting input of the error amplifier (302).

[0052] The source current (Isource) is injected into the connection node between the fourth resistor (R4) and the fifth resistor (R5).

[0053] Optionally, the limiting circuit (107) includes at least one diode, which is used to limit and attenuate the radio frequency input signal (RFIN).

[0054] This invention also proposes a power protection method for an RF power amplifier module, applied to the RF power amplifier module described above, the method comprising:

[0055] Based on the upper and lower limits of the performance of the power amplifier unit (108) and the filter (109) in the RF power amplifier chip (102) in different frequency bands, a control curve is configured for the limiting bias voltage (VDIODE) to change with the power supply voltage VCC in different frequency bands. The control curve defines the corresponding relationship that the limiting bias voltage (VDIODE) increases as the power supply voltage VCC increases after the power supply voltage VCC exceeds a set threshold (VCC_VTH).

[0056] The controller chip (101) detects the power supply voltage VCC in real time and generates and outputs a limiting bias voltage (VDIODE) corresponding to the current power supply voltage VCC value when the power supply voltage VCC exceeds the set threshold (VCC_VTH) according to the control curve.

[0057] The limiting bias voltage (VDIODE) is received by the limiting circuit (107) in the RF power amplifier chip (102), and the input RF signal (RFIN) is attenuated to a corresponding degree according to the magnitude of the limiting bias voltage (VDIODE). The attenuated RF signal is then amplified by the power amplifier unit (108) and filtered by the filter (109) before being output.

[0058] Adjust the limiting circuit (107) to optimize the performance of the power amplifier unit (108) and the filter (109).

[0059] The beneficial effects of this invention are as follows:

[0060] (1) Compared with the prior art, the RF power amplifier module based on voltage detection for power protection of the present invention abandons the slow path of traditional detection of the average power of the input signal, and instead directly and in real time detects the supply voltage (VCC) of the power amplifier unit through the controller chip. The response speed of the voltage detection circuit can reach the microsecond (µs) level, and can start protection immediately when the power amplifier faces the risk of overload due to high VCC. This completely solves the problem of poor protection real-time performance and slow response speed in the prior art because the power detection takes a certain amount of time. It effectively prevents the amplifier tube from being burned out before the protection circuit takes effect.

[0061] (2) The core of this invention is that the limiting bias voltage (VDIODE) is configured to increase with the increase of VCC, thereby driving the limiting circuit to continuously attenuate the input signal accordingly, realizing continuous and accurate matching between the protection strength and the actual working state of the power amplifier, thus realizing the adaptive "the greater the output power potential, the stronger the input attenuation", overcoming the shortcomings of the prior art that cannot adaptively change the limiting degree according to the power size and lacks flexibility, and can minimize unnecessary impact on the RF performance under normal power conditions while ensuring the safety of the amplifier.

[0062] (3) Based on the circuit architecture of this invention, different protection start-up thresholds (VCC_VTH) can be easily set by adjusting the ratio of the voltage divider resistors in the VCC voltage divider circuit, or the slope of the protection curve can be changed by adjusting the ratio of the current mirror. Furthermore, by introducing logic control or adding detection branches, dynamic switching of thresholds or slopes, and even multi-segment protection curves, can be achieved. This configurability allows the same hardware design to flexibly adapt to amplifiers or filters of different frequency bands and power levels, improving the practicality and applicability of the solution.

[0063] The system of the present invention has other features and advantages that will be apparent from or will be set forth in detail in the accompanying drawings and following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description

[0064] The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0065] Figure 1 This is a schematic block diagram of a radio frequency power amplifier module according to Embodiment 1 of the present invention.

[0066] Figure 2 This is a circuit diagram of the voltage detection and comparison unit and the limiting bias LDO circuit in Embodiment 1 of the present invention.

[0067] Figure 3 The waveform of the limiting bias voltage VDIODE output by the limiting bias LDO circuit in Embodiment 1 of the present invention is shown.

[0068] Figure 4 This is a circuit diagram of the VCC voltage divider circuit in Embodiment 2 of the present invention.

[0069] Figure 5 The waveform of the limiting bias voltage VDIODE output by the limiting bias LDO circuit in Embodiment 2 of the present invention is shown.

[0070] Figure 6 This is a circuit diagram of the voltage comparison and current generation circuit in Embodiment 3 of the present invention.

[0071] Figure 7 The waveform of the limiting bias voltage VDIODE output by the limiting bias LDO circuit in Embodiment 3 of the present invention is shown.

[0072] Figure 8 This is a circuit diagram of the voltage detection and comparison unit in Embodiment 4 of the present invention.

[0073] Figure 9 The waveform of the limiting bias voltage VDIODE output by the limiting bias LDO circuit in Embodiment 4 of the present invention is shown.

[0074] Figure 10 This is a flowchart of a power protection method for an RF power amplifier module according to Embodiment 5 of the present invention. Detailed Implementation

[0075] The invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0076] Example 1

[0077] like Figure 1 As shown, this embodiment provides an RF power amplifier module, including a controller chip 101, an RF power amplifier chip 102, and a filter 109 connected in sequence. The controller chip provides a limiting bias voltage VDIODE for the limiting circuit in the RF power amplifier chip. The RF power amplifier chip amplifies the RF signal power and outputs it to the filter. The filter filters the amplified RF signal to obtain the desired RF signal RFOUT in a specific frequency band.

[0078] The controller chip 101 is connected to the power supply voltage VCC that supplies power to the RF power amplifier chip 102. The controller chip 101 is used to detect the power supply voltage VCC and output a limiting bias voltage VDIODE that increases with the increase of the power supply voltage VCC when the power supply voltage VCC exceeds a set threshold.

[0079] The RF power amplifier chip 102 includes a limiting circuit 107 and a power amplifier unit 108. The limiting circuit 107 is used to limit and attenuate the RF input signal RFIN according to the limiting bias voltage VDIODE to obtain the attenuated RF signal RFIN_Limit. The power amplifier unit 108 is used to amplify the attenuated RF signal RFIN_Limit and output the amplified RF signal RFOUT_Limit. Optionally, the limiting circuit 107 includes at least one diode, which has a bias terminal and an RF terminal. The bias terminal of the diode receives the limiting bias voltage VDIODE, and the RF terminal of the diode is coupled to the path of the RF input signal RFIN. The limiting circuit 107 uses the diode to limit and attenuate the RF input signal RFIN.

[0080] Filter 109 is used to filter the amplified radio frequency signal to output the target frequency band radio frequency signal RFOUT.

[0081] refer to Figure 1In this embodiment, the controller chip 101 includes a voltage detection and comparison unit 103 and a limiting bias LDO circuit 104. The voltage detection and comparison unit detects the power supply voltage VCC of the power amplifier unit. When VCC reaches the set threshold VCC_VTH, it starts to provide a gradually increasing pull-up current Isource to the limiting bias LDO circuit as VCC increases. The limiting bias LDO circuit generates a bias voltage VDIODE. When VCC reaches the set threshold VCC_VTH, it starts to gradually increase the output voltage VDIODE as VCC increases.

[0082] The voltage detection and comparison unit 103 includes a VCC voltage divider circuit 105 and a voltage comparison current generation circuit 106. The function of the VCC voltage divider circuit is to divide the power supply voltage VCC proportionally to obtain a divided voltage VDIV2, which is provided to the voltage comparison current generation circuit for comparison. The function of the voltage comparison current generation circuit is to compare the divided voltage VDIV2 with the reference voltage VREF2. When the power supply voltage VCC reaches the set threshold VCC_VTH, that is, when the second divided voltage VDIV2 reaches the set threshold, a current Isource is generated. The current Isource gradually increases as VCC increases.

[0083] VCC voltage divider circuit 105 is used to divide the power supply voltage VCC that supplies power to the RF power amplifier chip 102 proportionally to generate a voltage divider signal, second voltage divider voltage VDIV2, which is provided to the voltage comparison generating current circuit for comparison.

[0084] The voltage comparison current generation circuit 106 is used to compare the voltage divider signal with the first reference voltage VREF2, and when the power supply voltage VCC reaches the set threshold VCC_VTH, that is, when the second voltage divider voltage VDIV2 reaches the set threshold, it starts to generate and output the pull-up current Isource, which gradually increases with the increase of the power supply voltage VCC.

[0085] The limiting bias LDO circuit 104 is used to generate the limiting bias voltage VDIODE, and after receiving the pull current Isource, the limiting bias voltage VDIODE gradually increases as the power supply voltage VCC increases.

[0086] Furthermore, such as Figure 2 As shown, the VCC voltage divider circuit 105 in this embodiment specifically includes: a first voltage divider resistor R1, a second voltage divider resistor R2, and a voltage buffer 310;

[0087] The first voltage divider resistor R1 and the second voltage divider resistor R2 are connected in series between the power supply voltage VCC and ground to divide the power supply voltage VCC, and output the first voltage divider voltage VDIV1 at the connection node of the first voltage divider resistor R1 and the second voltage divider resistor R2.

[0088] The voltage buffer 310 is composed of a unity-gain operational amplifier. The positive input terminal of the voltage buffer 310 is connected to the first voltage divider voltage VDIV1, and the inverting input terminal of the voltage buffer 310 is shorted to its output terminal. The output terminal of the voltage buffer 310 outputs a second voltage divider voltage VDIV2 with driving capability. The second voltage divider voltage VDIV2 is a voltage divider signal. The power supply terminal of the voltage buffer 310 is connected to the power supply VBAT of the controller chip 101.

[0089] The voltage comparison current generation circuit 106 includes: a bias current source IBIAS, a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4;

[0090] One end of the bias current source IBIAS is connected to the power supply VBAT, and the other end of the bias current source IBIAS is connected to the drain of the first NMOS transistor MN1.

[0091] The drain and gate of the first NMOS transistor MN1 are connected to each other, and the source of the first NMOS transistor MN1 is grounded.

[0092] The gate of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1, the drain of the second NMOS transistor MN2 is connected to the drain of the first PMOS transistor MP1, and the source of the second NMOS transistor MN2 is grounded.

[0093] The gate and drain of the first PMOS transistor MP1 are connected to each other, and the source of the first PMOS transistor MP1 is connected to the first reference voltage VREF2.

[0094] The gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1, the source of the second PMOS transistor MP2 is connected to the second voltage divider voltage VDIV2, and the drain of the second PMOS transistor MP2 is connected to the drain of the third NMOS transistor MN3.

[0095] The gate and drain of the third NMOS transistor MN3 are connected to each other, and the source of the third NMOS transistor MN3 is grounded.

[0096] The gate of the fourth NMOS transistor MN4 is connected to the gate of the third NMOS transistor MN3. The source of the fourth NMOS transistor MN4 is grounded. The drain of the fourth NMOS transistor MN4 serves as the circuit output terminal, outputting the pull-up current Isource.

[0097] Among them, the first PMOS transistor MP1 and the second PMOS transistor MP2, the first NMOS transistor MN1 and the second NMOS transistor MN2, and the third NMOS transistor MN3 and the fourth NMOS transistor MN4 respectively form current mirrors.

[0098] The limiting bias LDO circuit 104 includes a bandgap reference circuit 301, an error amplifier 302, a power transistor 303, and a resistor network 304;

[0099] The input terminal of the bandgap reference circuit 301 is connected to the power supply VBAT. The first output terminal of the bandgap reference circuit 301 is used to output the first reference voltage VREF2, and the first output terminal of the bandgap reference circuit 301 is used to output the second reference voltage VREF1.

[0100] The non-inverting input terminal of the error amplifier 302 is connected to the second reference voltage VREF1, the output terminal of the error amplifier 302 is connected to the gate of the power transistor 303, and the power supply terminal of the error amplifier 302 is connected to the power supply VBAT.

[0101] The source of power transistor 303 is connected to the power supply VBAT, and the drain of power transistor 303 outputs a limiting bias voltage VDIODE.

[0102] Resistor network 304 includes a third resistor R3, a fourth resistor R4, and a fifth resistor R5. One end of the third resistor R3 is grounded, and the other end of the third resistor R3 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the drain of the power transistor 303. The connection node between the third resistor R3 and the fourth resistor R4 serves as the feedback node VFB, which is connected to the inverting input of the error amplifier 302.

[0103] The sourcing current Isource is injected into the connection node between the fourth resistor R4 and the fifth resistor R5.

[0104] Specifically, the controller chip 101 includes a limiting bias LDO circuit 104, a VCC voltage divider circuit 105, and a voltage comparison current generation circuit 106. The limiting bias LDO circuit consists of a bandgap reference circuit 301, an error amplifier 302, a power transistor 303, and a resistor network 304. The bandgap reference circuit 301 provides the second reference voltage VREF1 and the first reference voltage VREF2. The error amplifier clamps the voltage at the two input terminals of the operational amplifier, making the feedback node voltage equal to the input reference voltage, i.e., VFB = VREF1. The resistor network, composed of resistors R3, R4, and R5, determines the feedback coefficient of the LDO. The power transistor provides the driving capability of the output voltage VDIODE; the larger the power transistor, the greater the driving capability. The expression for the output voltage VDIODE in the case of only the main LDO circuit is as follows: .

[0105] The function of the VCC voltage divider circuit is to proportionally divide the voltage VCC to obtain voltage VDIV2, which is then provided to the voltage comparison and current generation circuit for comparison. First, resistors R1 and R2 divide the voltage VCC to obtain voltage VDIV1. Then, VDIV1 passes through voltage buffer 310 to obtain VDIV2. The function of the voltage buffer is to enable the divided voltage VDIV2 to have driving capability, so that it can be provided to the voltage comparison and current generation circuit for comparison. The expression for voltage VDIV2 is as follows: The voltage buffer consists of an operational amplifier connected with unity gain.

[0106] The voltage comparison current generation circuit compares the divided voltage VDIV2 with the reference voltage VREF2. When VCC reaches the set threshold VCC_VTH, i.e., when VDIV2 reaches the set comparison threshold, a source current Isource is generated. Isource is then fed into the resistor network of the main LDO circuit, causing the LDO output voltage VDIODE to gradually increase as VCC increases. IBIAS is the bias current. NMOS transistors MN1, MN2, MN3, and MN4 form current mirrors, as do PMOS transistors MP1 and MP2. According to Kirchhoff's current law, the current flowing into node A is equal to the current flowing out of node A. That is, the current I5 flowing through resistor R5 is equal to the sum of the current I4 flowing through resistor R4 and the source current Isource, i.e., I5 = I4 + Isource. Due to the clamping effect of the error amplifier, the reference voltage at the input is equal to the feedback node voltage, i.e., VREF1 = VFB. Thus, with voltage VREF1 and voltage VFB remaining constant, the current I3 flowing through resistor R3 remains constant, the current I4 flowing through resistor R4 remains constant, and the voltage VA at node A remains constant. Therefore, the expression for the output voltage VDIODE is:

[0107] ,

[0108] When VCC is less than the set threshold VCC_VTH, that is, when the voltage divider voltage VDIV2 is less than the reference voltage VREF2, the current mirrors of PMOS transistors MP1 and MP2 are cut off, and the source current Isource is 0. In this case, the voltage comparison current generation circuit will not affect the operation of the main LDO circuit. That is, at this time, the voltage comparison current generation circuit does not affect the output voltage VDIODE. At this time, VDIODE outputs the initial voltage value, I5 = I4. .

[0109] When VCC reaches the set threshold VCC_VTH, meaning the voltage divider voltage VDIV2 begins to exceed the reference voltage VREF2, the current mirrors of PMOS transistors MP1 and MP2 gradually turn on, and the source current Isource gradually increases from 0. The current I5 flowing through resistor R5 also gradually increases. At this point, VDIODE's output voltage begins to gradually increase as VCC increases, and I5 = I4 + Isource. The scaling factor achieved by current mirrors MN1 and MN2, MP1 and MP2, and MN3 and MN4 is N, i.e., Isource = IBIAS. N, once the current mirrors of PMOS transistors MP1 and MP2 are fully turned on, the VDIODE voltage will stabilize, and I5 = I4 + IBIAS. N, .

[0110] By adjusting the scaling factor N of the current mirror, different current sourcing rates, i.e., different rising slopes of VDIODE as VCC changes, can be achieved. By adjusting the voltage division ratio of resistors R1 and R2, different VCC trigger voltages can be used to initiate the increase of VDIODE.

[0111] The higher the VCC voltage, the stronger the amplification capability of the power amplifier and the larger the output power RFOUT_Limit. However, the amplifying tubes and filters of the power amplifier unit are more prone to overheating and irreversible damage. Therefore, the voltage VCC is first detected to identify scenarios where the amplifying tubes and filters are prone to damage. Then, a limiting bias voltage VDIODE that varies with VCC is generated and provided to the limiting circuit. Different limiting bias voltages VDIODE correspond to different attenuation levels of the RF input signal RFIN. Ultimately, when VCC reaches the set threshold VCC_VTH, the higher the VCC voltage, the larger the limiting bias voltage VDIODE, and the more severe the attenuation of the RF input signal RFIN. This achieves an adaptive protection effect where the higher the output power, the more severe the attenuation.

[0112] Figure 3The waveform of the limiting bias voltage VDIODE output by the limiting bias LDO circuit in this embodiment shows the dynamic relationship between the power supply voltage VCC and the limiting bias voltage VDIODE. When VCC is lower than the set voltage VCC_VTH, VDIODE remains at a constant initial level. At this time, the protection circuit does not activate, and the limiting circuit is in a minimum attenuation state. Once VCC reaches and exceeds VCC_VTH, VDIODE immediately begins to rise linearly from the initial level, and its voltage value is proportional to the amount of VCC exceeding the threshold. This waveform intuitively demonstrates the rapid response (VDIODE changes immediately after VCC exceeds the threshold) and continuous adaptability (VDIODE increases continuously with VCC, rather than a step jump) of the protection mechanism in this embodiment. This means that the input attenuation of the power amplifier will smoothly and in real time increase with its supply voltage (i.e., output power potential), thereby providing immediate and precise progressive protection in the event of overload risk, achieving the optimal dynamic balance between RF performance and reliability.

[0113] Based on the above, the RF power amplifier module of this embodiment can adaptively and dynamically adjust the limiting bias voltage VDIODE according to the VCC voltage, so as to achieve precise matching of the attenuation degree of the output power RFOUT_Limit and the input signal RFIN_Limit. Moreover, the voltage detection and comparison unit responds quickly to the changes in VCC voltage and can adjust the limiting bias voltage VDIODE within microseconds after reaching the voltage threshold, so as to attenuate the RF input signal in time and protect the amplifier tube from irreversible damage caused by overheating. In addition, the voltage detection and comparison unit circuit is simple to implement and has the characteristics of flexible adjustment.

[0114] Example 2

[0115] This embodiment provides an RF power amplifier module. Based on Embodiment 1, this embodiment further improves the VCC voltage divider circuit 105 in the controller chip 101, such as... Figure 4 As shown, the VCC voltage divider circuit 105 in this embodiment includes a voltage divider resistor network, a voltage divider point selection network, and a voltage buffer 310.

[0116] The voltage divider resistor network includes multiple voltage divider resistors R11-R55 connected in series between the power supply voltage VCC and ground. Voltage divider taps VDIV11-VDIV14 are respectively provided at the series nodes between the multiple voltage divider resistors R11-R55.

[0117] The voltage divider selection network includes multiple transmission gates 406-409. The input of each transmission gate is connected to a voltage divider tap. The outputs of the multiple transmission gates are interconnected and then connected to the positive input of the voltage buffer 310. Each transmission gate is controlled by a corresponding logic control signal to select one of the voltages from the multiple voltage divider taps as the first voltage divider voltage VDIV1 and output it to the voltage buffer 310.

[0118] The input terminal of voltage buffer 310 is connected to the common output terminal of the voltage divider point selection circuit. The output terminal of voltage buffer 310 outputs a voltage divider signal with driving capability, namely the second voltage divider voltage VDIV2. The inverting input terminal of voltage buffer 310 is shorted to its output terminal. The power supply terminal of voltage buffer 310 is connected to the power supply VBAT of controller chip 101.

[0119] Specifically, in this embodiment, different voltage divider taps VDIV11-VDIV14 are first extracted from the series node of multiple voltage divider resistors in the VCC voltage divider circuit. Then, the logic levels VC11-VC14 are used to control the enable transmission gates 406-409 respectively, which in turn control the voltage divider taps VDIV11-VDIV14 to determine which voltage divider voltage is used as the first voltage divider voltage VDIV1 and transmitted to the voltage buffer 310, so as to correspond to different threshold voltages VTH11-VTH14 of VCC.

[0120] Figure 5 The waveform of the limiting bias voltage VDIODE output by the limiting bias LDO circuit in this embodiment is shown. The figure illustrates multiple VDIODE-VCC relationship curves achieved by selecting different voltage divider taps through logic control signals under the same circuit structure. These curves have the same rising slope but originate from different VCC threshold voltage points (e.g., VTH1, VTH2, VTH3, VTH4). This waveform clearly demonstrates the high configurability of the module in this embodiment. Users can flexibly set the most suitable protection trigger point through digital logic based on the specific tolerance characteristics of different frequency band power amplifiers or filters. For example, for more vulnerable devices, a lower trigger threshold (e.g., VTH1) can be selected to provide earlier protection intervention; while for more tolerant devices, a higher threshold (e.g., VTH4) can be selected to avoid unnecessary performance limitations within the normal operating voltage range. This flexibility greatly expands the application range of the module in this embodiment.

[0121] Example 3

[0122] This embodiment provides an RF power amplifier module. Based on Embodiment 1 or 2, this embodiment further improves the voltage comparison and current generation circuit 106 in the controller chip 101, such as... Figure 6As shown, the voltage comparison current generation circuit 106 in this embodiment includes: a first bias current source IBIAS, a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, multiple auxiliary NMOS transistors MN21-MN24, and multiple transmission gates 505-508.

[0123] One end of the bias current source IBIAS is connected to the power supply VBAT, and the other end of the bias current source IBIAS is connected to the drain of the first NMOS transistor MN1.

[0124] The drain and gate of the first NMOS transistor MN1 are connected to each other, and the source of the first NMOS transistor MN1 is grounded.

[0125] The gate of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1, the drain of the second NMOS transistor MN2 is connected to the drain of the first PMOS transistor MP1, and the source of the second NMOS transistor MN2 is grounded.

[0126] The gate and drain of the first PMOS transistor MP1 are connected to each other, and the source of the first PMOS transistor MP1 is connected to the first reference voltage VREF2.

[0127] The gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1, the source of the second PMOS transistor MP2 is connected to the second voltage divider voltage VDIV2, and the drain of the second PMOS transistor MP2 is connected to the drain of the third NMOS transistor MN3.

[0128] The gate and drain of the third NMOS transistor MN3 are connected to each other, and the source of the third NMOS transistor MN3 is grounded.

[0129] The sources of multiple auxiliary NMOS transistors MN21-MN24 are all grounded, and their gates are all connected to the gate of the third NMOS transistor MN3. The third NMOS transistor MN3 and the multiple auxiliary NMOS transistors form current mirrors with different scaling factors.

[0130] The input terminals of multiple transmission gates 505-508 are all connected to the gate of the third NMOS transistor MN3, and the output terminal of each transmission gate is connected to the gate of an auxiliary NMOS transistor.

[0131] The drains of each auxiliary NMOS transistor MN21-MN24 are connected together to serve as the output terminal of the pull-up current Isource;

[0132] The control terminals of each transmission gate 505-508 receive the corresponding logic control signals to selectively turn on the corresponding transmission gate, and turn on the current mirror composed of the corresponding auxiliary NMOS transistor and the third NMOS transistor MN3 to adjust the mirror ratio of the pull-up current Isource.

[0133] Specifically, in this embodiment, multiple NMOS transistor current mirrors are added to the voltage comparison current generation circuit to control the different magnitudes of the pull-up current Isource. The third NMOS transistor MN3 and the auxiliary NMOS transistors MN21-MN24 form current mirrors with different scaling factors. Then, the logic levels VC21-VC24 are used to control the enable transmission gates 505-508 respectively, which in turn control the current mirrors formed by MN21-MN24 to determine which current mirror is turned on, so as to correspond to the different rising slopes of VDIODE after VCC reaches the threshold voltage.

[0134] Figure 7 The figure shows the waveform of the limiting bias voltage VDIODE output by the limiting bias LDO circuit in this embodiment. It illustrates multiple VDIODE-VCC relationship curves generated by selecting different current mirror ratios through logic control under the same trigger threshold VCC_VTH. These curves start from the same point but rise with significantly different slopes. A larger slope means that after VCC exceeds the threshold, VDIODE increases faster with VCC, resulting in stronger attenuation of the input signal. This waveform visually demonstrates the precise control capability of this embodiment over the protection strength (i.e., attenuation rate). In practical applications, the slope can be configured according to the system's different requirements for the "aggressive" or "mild" degree of protection response. For example, a high-slope curve can be selected in applications requiring extreme protection, while a low-slope curve can be selected in applications where a smooth transition and reduced impact on signal abrupt changes are desired.

[0135] In addition, the voltage comparison current generation circuit of this embodiment can be combined with the VCC voltage divider circuit of embodiment 2. The two work together to adjust the threshold voltage of VCC trigger and the voltage rise slope of VDIODE after triggering, further improving the flexibility of VDIODE adjustment.

[0136] Example 4

[0137] This embodiment provides an RF power amplifier module, such as... Figure 8 As shown, based on Embodiment 1, this embodiment adds another set of VCC voltage divider circuits and voltage comparison current generation circuits to the controller chip 101. That is, the voltage detection and comparison unit 103 in this embodiment includes two sets of VCC voltage divider circuits with the same structure and two sets of voltage comparison current generation circuits with the same structure.

[0138] like Figure 8 As shown, the first voltage divider resistor R1, the second voltage divider resistor R2, and the voltage buffer 310 form the first VCC voltage divider circuit. The connection relationship between the various components is as described in Example 1, and will not be repeated here.

[0139] The second voltage divider circuit is used to divide the power supply voltage VCC and output the third voltage divider voltage VDIV62.

[0140] The second voltage divider circuit specifically includes: a sixth voltage divider resistor R61, a seventh voltage divider resistor R62, and a second voltage buffer 603. The sixth voltage divider resistor R61 and the seventh voltage divider resistor R62 are connected in series between the power supply voltage VCC and ground to divide the power supply voltage VCC, and output the fourth voltage divider voltage VDIV61 at the connection node of the sixth voltage divider resistor R61 and the seventh voltage divider resistor R62.

[0141] The positive input terminal of the second voltage buffer 603 is connected to the fourth voltage divider voltage VDIV61. The inverting input terminal of the second voltage buffer 603 is shorted to its output terminal. The output terminal of the second voltage buffer 603 outputs a third voltage divider voltage VDIV62 with driving capability. The third voltage divider voltage VDIV62 is a voltage divider signal. The power supply terminal of the second voltage buffer 603 is connected to the power supply VBAT of the controller chip 101.

[0142] The first voltage comparison current generation circuit includes a bias current source IBIAS, a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4; the connection relationship between the various devices is as described in Example 1, and will not be repeated here.

[0143] The second voltage comparison current generation circuit includes a bias current source IBIAS, a third PMOS transistor MP63, a fourth PMOS transistor MP64, a fifth NMOS transistor MN61, a sixth NMOS transistor MN62, a seventh NMOS transistor MN65, and an eighth NMOS transistor MN66.

[0144] One end of the bias current source IBIAS is connected to the power supply VBAT, and the other end of the bias current source IBIAS is connected to the drain of the fifth NMOS transistor MN61.

[0145] The drain and gate of the fifth NMOS transistor MN61 are connected to each other, and the source of the fifth NMOS transistor MN61 is grounded;

[0146] The gate of the sixth NMOS transistor MN62 is connected to the gate of the fifth NMOS transistor MN61, the drain of the sixth NMOS transistor MN62 is connected to the drain of the third PMOS transistor MP63, and the source of the sixth NMOS transistor MN62 is grounded.

[0147] The gate and drain of the third PMOS transistor MP63 are connected to each other, and the source of the third PMOS transistor MP63 is connected to the first reference voltage VREF2.

[0148] The gate of the fourth PMOS transistor MP64 is connected to the gate of the third PMOS transistor MP63, the source of the fourth PMOS transistor MP64 is connected to the second voltage divider voltage VDIV2, and the drain of the fourth PMOS transistor MP64 is connected to the drain of the seventh NMOS transistor MN65.

[0149] The gate and drain of the seventh NMOS transistor MN65 are connected to each other, and the source of the seventh NMOS transistor MN65 is grounded;

[0150] The gate of the eighth NMOS transistor MN66 is connected to the gate of the seventh NMOS transistor MN65. The source of the eighth NMOS transistor MN66 is grounded, and the drain of the eighth NMOS transistor MN66 serves as the circuit output terminal, outputting the pull-up current Isource.

[0151] Among them, the third PMOS transistor MP63 and the fourth PMOS transistor MP64, the fifth NMOS transistor MN61 and the sixth NMOS transistor MN62, and the seventh NMOS transistor MN65 and the eighth NMOS transistor MN66 respectively form current mirrors.

[0152] The second voltage comparison current generation circuit is used to compare the third voltage divider voltage VDIV62 with the third reference voltage VREF3, and output the second pull-up current Isource_2 when the power supply voltage VCC reaches the second threshold VCC_VTH_2.

[0153] The second pull-up current Isource_2 output by the second voltage comparison current generation circuit and the pull-up current Isource_1 output by the first voltage comparison current generation circuit are superimposed and input together to the limiting bias LDO circuit 104.

[0154] This embodiment adds another VCC voltage divider circuit and a voltage comparison current generation circuit to the control chip 101. First, the power supply voltage VCC is divided using the sixth voltage divider resistor R61 and the seventh voltage divider resistor R62 to obtain voltage VDIV61. Then, after passing through a voltage buffer, voltage VDIV62 is obtained. The expression for voltage VDIV62 is as follows: ,

[0155] Then, the voltage divider voltage VDIV62 is compared with the reference voltage VREF3. When VCC reaches the set threshold VCC_VTH_2, a source current Isource_2 is generated. Isource_2 is then fed into the resistor network of the main LDO circuit, causing the LDO output voltage VDIODE to gradually increase as VCC increases. According to Kirchhoff's current law, the source current Isource is equal to the sum of Isource_1 and Isource_2, i.e., Isource = Isource_1 + Isource_2. Therefore, the expression for the output voltage VDIODE at this time is:

[0156] ,

[0157] When VCC reaches the set threshold VCC_VTH, the source current Isource_1 gradually increases from 0. At this time, VDIODE's output voltage gradually increases as VCC increases. When VCC reaches the set threshold VCC_VTH_2, the source current Isource_2 gradually increases from 0. At this time, VDIODE's output voltage gradually increases with a larger slope as VCC increases, so as to achieve VDIODE rising at different slopes in different threshold voltage ranges of VCC.

[0158] Figure 9 The waveform of the limiting bias voltage VDIODE output by the limiting bias LDO circuit in this embodiment is shown. The figure illustrates a more complex VDIODE-VCC relationship curve with two distinct inflection points. When VCC is below the first threshold VCC_VTH, VDIODE maintains its initial level; when VCC is between VCC_VTH and the second threshold VCC_VTH_2, VDIODE rises linearly with a first slope; when VCC exceeds the higher second threshold VCC_VTH_2, the rate of increase of VDIODE increases sharply, climbing with a larger second slope. This waveform reveals an advanced, piecewise adaptive protection strategy: mild protection is used for moderate overvoltages, while strong protection is activated for severe overvoltages. This "piecewise linear approximation" approach enables a near-nonlinear optimal protection curve with relatively simple circuitry, providing more intelligent and realistic protection across a wider operating voltage range.

[0159] Example 5

[0160] This embodiment provides a power protection method for an RF power amplifier module, applicable to any of the RF power amplifier modules in embodiments 1-4 above. The method flow of this embodiment is as follows: Figure 10 As shown, it specifically includes:

[0161] First, the upper and lower limits of the performance of power amplifier units and filters in different frequency bands were determined through testing;

[0162] Then, based on the performance upper and lower limits of the power amplifier unit 108 and filter 109 in the RF power amplifier chip 102 in different frequency bands, control curves of the limiting bias voltage VDIODE changing with the power supply voltage VCC are configured in different frequency bands. The control curves define the corresponding relationship that the limiting bias voltage VDIODE increases with the increase of the power supply voltage VCC after the power supply voltage VCC exceeds the set threshold VCC_VTH.

[0163] Then, the controller chip 101 detects the power supply voltage VCC in real time, and according to the control curve, when the power supply voltage VCC exceeds the set threshold VCC_VTH, it generates and outputs a limiting bias voltage VDIODE corresponding to the current power supply voltage VCC value.

[0164] Then, the limiting bias voltage VDIODE is received by the limiting circuit 107 in the RF power amplifier chip 102, and the input RF signal RFIN is attenuated to a corresponding degree according to the magnitude of the limiting bias voltage VDIODE. The attenuated RF signal is then amplified by the power amplifier unit 108 and filtered by the filter 109 before being output.

[0165] Finally, the limiting circuit 107 is adjusted to optimize the performance of the power amplifier unit 108 and the filter 109.

[0166] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A radio frequency power amplifier module, characterized in that, It includes a controller chip (101), an RF power amplifier chip (102), and a filter (109) connected in sequence. The controller chip (101) is connected to the power supply voltage VCC that supplies power to the radio frequency power amplifier chip (102). The controller chip (101) is used to detect the power supply voltage VCC and output a limiting bias voltage (VDIODE) that increases with the increase of the power supply voltage VCC when the power supply voltage VCC exceeds a set threshold. The radio frequency power amplifier chip (102) includes a limiting circuit (107) and a power amplifier unit (108); the limiting circuit (107) is used to limit and attenuate the radio frequency input signal (RFIN) according to the limiting bias voltage (VDIODE) to obtain the attenuated radio frequency signal (RFIN_Limit); the power amplifier unit (108) is used to amplify the attenuated radio frequency signal (RFIN_Limit) and output it. The filter (109) is used to filter the amplified radio frequency signal to output the radio frequency signal (RFOUT) of the target frequency band. The controller chip (101) includes a voltage detection and comparison unit (103) and a limiting bias LDO circuit (104). The voltage detection and comparison unit (103) includes a VCC voltage divider circuit (105) and a voltage comparison current generation circuit (106). The VCC voltage divider circuit (105) is used to divide the power supply voltage VCC that supplies power to the RF power amplifier chip (102) to generate a voltage divider signal; The voltage comparison current generation circuit (106) is used to compare the voltage divider signal with the first reference voltage (VREF2), and after the power supply voltage VCC reaches the set threshold (VCC_VTH), it generates and outputs a pull-up current (Isource) that gradually increases with the increase of the power supply voltage VCC. The limiting bias LDO circuit (104) is used to generate the limiting bias voltage (VDIODE), and after receiving the source current (Isource), the limiting bias voltage (VDIODE) gradually increases as the power supply voltage VCC increases.

2. The RF power amplifier module of claim 1, wherein, The VCC voltage divider circuit (105) includes: a first voltage divider resistor (R1), a second voltage divider resistor (R2), and a voltage buffer (310). The first voltage divider resistor (R1) and the second voltage divider resistor (R2) are connected in series between the power supply voltage VCC and ground to divide the power supply voltage VCC, and output the first voltage divider voltage (VDIV1) at the connection node of the first voltage divider resistor (R1) and the second voltage divider resistor (R2). The voltage buffer (310) is composed of an operational amplifier connected in unity gain. The positive input terminal of the voltage buffer (310) is connected to the first voltage divider (VDIV1). The inverting input terminal of the voltage buffer (310) is shorted to its output terminal. The output terminal of the voltage buffer (310) outputs a second voltage divider (VDIV2) with driving capability. The second voltage divider (VDIV2) is the voltage divider signal. The power supply terminal of the voltage buffer (310) is connected to the power supply VBAT of the controller chip (101).

3. The RF power amplifier module of claim 2, wherein, The voltage comparison current generation circuit (106) includes: a bias current source (IBIAS), a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), and a fourth NMOS transistor (MN4). One end of the bias current source (IBIAS) is connected to the power supply VBAT, and the other end of the bias current source (IBIAS) is connected to the drain of the first NMOS transistor (MN1). The drain and gate of the first NMOS transistor (MN1) are connected to each other, and the source of the first NMOS transistor (MN1) is grounded; The gate of the second NMOS transistor (MN2) is connected to the gate of the first NMOS transistor (MN1), the drain of the second NMOS transistor (MN2) is connected to the drain of the first PMOS transistor (MP1), and the source of the second NMOS transistor (MN2) is grounded. The gate and drain of the first PMOS transistor (MP1) are connected to each other, and the source of the first PMOS transistor (MP1) is connected to the first reference voltage (VREF2). The gate of the second PMOS transistor (MP2) is connected to the gate of the first PMOS transistor (MP1), the source of the second PMOS transistor (MP2) is connected to the second voltage divider (VDIV2), and the drain of the second PMOS transistor (MP2) is connected to the drain of the third NMOS transistor (MN3). The gate and drain of the third NMOS transistor (MN3) are connected to each other, and the source of the third NMOS transistor (MN3) is grounded; The gate of the fourth NMOS transistor (MN4) is connected to the gate of the third NMOS transistor (MN3), the source of the fourth NMOS transistor (MN4) is grounded, and the drain of the fourth NMOS transistor (MN4) serves as the circuit output terminal, outputting the source current (Isource). The first PMOS transistor (MP1) and the second PMOS transistor (MP2), the first NMOS transistor (MN1) and the second NMOS transistor (MN2), and the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) respectively form current mirrors.

4. The RF power amplifier module of claim 1, wherein, The VCC voltage divider circuit (105) includes a voltage divider resistor network, a voltage divider point selection network, and a voltage buffer (310). The voltage divider resistor network includes multiple voltage divider resistors connected in series between the power supply voltage VCC and ground, and voltage divider taps are respectively provided at the series nodes between the multiple voltage divider resistors. The voltage divider selection network includes multiple transmission gates. The input of each transmission gate is connected to a voltage divider tap. The outputs of the multiple transmission gates are interconnected and connected to the positive input of the voltage buffer (310). Each transmission gate is controlled by a corresponding logic control signal to select one of the voltages from the multiple voltage divider taps as the first voltage divider voltage (VDIV1) and output it to the voltage buffer (310). The input terminal of the voltage buffer (310) is connected to the common output terminal of the voltage divider selection circuit. The output terminal of the voltage buffer (310) outputs a second voltage divider voltage (VDIV2) with driving capability. The second voltage divider voltage (VDIV2) is the voltage divider signal. The inverting input terminal of the voltage buffer (310) is short-circuited with its output terminal. The power supply terminal of the voltage buffer (310) is connected to the power supply VBAT of the controller chip (101).

5. The RF power amplifier module of claim 1, wherein, The voltage comparison current generation circuit (106) includes: a first bias current source (IBIAS), a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), multiple auxiliary NMOS transistors, and multiple transmission gates; One end of the bias current source (IBIAS) is connected to the power supply VBAT of the controller chip (101), and the other end of the bias current source (IBIAS) is connected to the drain of the first NMOS transistor (MN1). The drain and gate of the first NMOS transistor (MN1) are connected to each other, and the source of the first NMOS transistor (MN1) is grounded; The gate of the second NMOS transistor (MN2) is connected to the gate of the first NMOS transistor (MN1), the drain of the second NMOS transistor (MN2) is connected to the drain of the first PMOS transistor (MP1), and the source of the second NMOS transistor (MN2) is grounded. The gate and drain of the first PMOS transistor (MP1) are connected to each other, and the source of the first PMOS transistor (MP1) is connected to the first reference voltage (VREF2). The gate of the second PMOS transistor (MP2) is connected to the gate of the first PMOS transistor (MP1), the source of the second PMOS transistor (MP2) is connected to the second voltage divider (VDIV2), and the drain of the second PMOS transistor (MP2) is connected to the drain of the third NMOS transistor (MN3). The gate and drain of the third NMOS transistor (MN3) are connected to each other, and the source of the third NMOS transistor (MN3) is grounded; The sources of the multiple auxiliary NMOS transistors are all grounded, and their gates are all connected to the gate of the third NMOS transistor (MN3). The third NMOS transistor (MN3) and the multiple auxiliary NMOS transistors respectively form current mirrors with different scaling factors. The input terminals of the multiple transmission gates are all connected to the gate of the third NMOS transistor (MN3), and the output terminal of each transmission gate is correspondingly connected to the gate of an auxiliary NMOS transistor. The drains of all the auxiliary NMOS transistors are connected together to serve as the output terminal of the source current (Isource); The control terminal of each transmission gate receives the corresponding logic control signal to selectively turn on the corresponding transmission gate and turn on the current mirror composed of the corresponding auxiliary NMOS transistor and the third NMOS transistor (MN3) to adjust the mirror ratio of the source current (Isource).

6. The RF power amplifier module of claim 3, wherein, The voltage detection and comparison unit (103) further includes a second set of VCC voltage divider circuits and a second set of voltage comparison current generation circuits; the second set of VCC voltage divider circuits has the same circuit structure as the VCC voltage divider circuits, and the second set of voltage comparison current generation circuits has the same circuit structure as the voltage comparison current generation circuits. The second VCC voltage divider circuit is used to divide the power supply voltage VCC and output a third voltage divider (VDIV62). The second set of voltage comparison current generation circuits is used to compare the third voltage divider (VDIV62) with the third reference voltage (VREF3), and output the second sourcing current (Isource_2) when the power supply voltage VCC reaches the second threshold (VCC_VTH_2). The second pull current (Isource_2) output by the second voltage comparison current generation circuit is superimposed with the pull current (Isource) output by the voltage comparison current generation circuit (106) and then input to the limiting bias LDO circuit (104).

7. The radio frequency power amplifier module of any of claims 1-6, wherein, The limiting bias LDO circuit (104) includes a bandgap reference circuit (301), an error amplifier (302), a power transistor (303), and a resistor network (304). The input terminal of the bandgap reference circuit (301) is connected to the power supply VBAT of the controller chip (101). The first output terminal of the bandgap reference circuit (301) is used to output the first reference voltage (VREF2). The first output terminal of the bandgap reference circuit (301) is used to output the second reference voltage (VREF1). The non-inverting input terminal of the error amplifier (302) is connected to the second reference voltage (VREF1), the output terminal of the error amplifier (302) is connected to the gate of the power transistor (303), and the power supply terminal of the error amplifier (302) is connected to the power supply VBAT. The source of the power transistor (303) is connected to the power supply VBAT, and the drain of the power transistor (303) outputs the limiting bias voltage (VDIODE). The resistor network (304) includes a third resistor (R3), a fourth resistor (R4), and a fifth resistor (R5). One end of the third resistor (R3) is grounded, and the other end of the third resistor (R3) is connected to one end of the fourth resistor (R4). The other end of the fourth resistor (R4) is connected to one end of the fifth resistor (R5), and the other end of the fifth resistor (R5) is connected to the drain of the power transistor (303). The connection node between the third resistor (R3) and the fourth resistor (R4) serves as a feedback node (VFB) connected to the inverting input of the error amplifier (302). The source current is injected into the connection node between the fourth resistor (R4) and the fifth resistor (R5).

8. The radio frequency power amplifier module of any of claims 1-6, wherein, The limiting circuit (107) includes at least one diode, which is used to limit and attenuate the radio frequency input signal (RFIN).

9. A power protection method for an RF power amplifier module, applied to the RF power amplifier module according to any one of claims 1 to 8, characterized in that, The method includes: Based on the upper and lower limits of the performance of the power amplifier unit (108) and the filter (109) in the RF power amplifier chip (102) in different frequency bands, a control curve is configured for the limiting bias voltage (VDIODE) to change with the power supply voltage VCC in different frequency bands. The control curve defines the corresponding relationship that the limiting bias voltage (VDIODE) increases as the power supply voltage VCC increases after the power supply voltage VCC exceeds a set threshold (VCC_VTH). The controller chip (101) detects the power supply voltage VCC in real time and generates and outputs a limiting bias voltage (VDIODE) corresponding to the current power supply voltage VCC value when the power supply voltage VCC exceeds the set threshold (VCC_VTH) according to the control curve. The limiting bias voltage (VDIODE) is received by the limiting circuit (107) in the RF power amplifier chip (102), and the input RF signal (RFIN) is attenuated to a corresponding degree according to the magnitude of the limiting bias voltage (VDIODE). The attenuated RF signal is then amplified by the power amplifier unit (108) and filtered by the filter (109) before being output. Adjust the limiting circuit (107) to optimize the performance of the power amplifier unit (108) and the filter (109).

Images