Pulse width modulation (PWM) signal output device and pulse width modulation (PWM) signal output method

Abstract

The invention discloses a pulse width modulation (PWM) signal output device and method, and the device comprises a frequency division processing module which outputs frequency division clock pulses under a plurality of target PWM frequencies according to a plurality of frequency division coefficients and a main clock signal, the frequency division coefficients are obtained based on the normalization processing of a plurality of linear models, and the main clock signal is obtained based on the normalization processing of a plurality of linear models; the linear model is a linear relationship between the output data and the PWM duty ratio under the target PWM frequency; the signal output module responds to the frequency division clock pulse to count and outputs a PWM signal according to a count value, a corresponding normalized count threshold value and a total clock number, the normalized count threshold value is obtained based on a normalization model, the normalization model is a relation between the normalized count threshold value and the output data, and the total clock number is obtained based on the relation between the normalized count threshold value and the output data. The total clock number is the total number of reference clock pulses required by a complete period of the target PWM frequency. The technical scheme can reduce processing logic and reduce power consumption.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a pulse width modulation (PWM) signal output device and a PWM signal output method. Background Technology

[0002] Pulse width modulation (PWM) is a commonly used technique in industrial control technology. PWM signals can be used as drive signals to control the on / off state of power switching devices. In integrated circuit design, digital pins (such as OUT) typically only support two states: high level (1) and low level (0). When multiple data streams need to be output through a single pin, existing technologies use PWM duty cycles to represent data values ​​(such as ADC sample values) and distinguish data types by frequency. Generally, each type of data requires multiple comparators and multiple adders, and different frequencies of PWM use independent control logic, resulting in complex logic and high power consumption. Summary of the Invention

[0003] The main objective of this invention is to provide a pulse width modulation (PWM) signal output device and a PWM signal output method, which aim to reduce processing logic and lower power consumption.

[0004] To achieve the above objectives, the present invention proposes a pulse width modulation (PWM) signal output device, comprising: a frequency division processing module, which outputs multiple frequency division clock pulses at multiple target PWM frequencies based on multiple frequency division coefficients and a master clock signal, wherein the frequency division coefficients are obtained by normalizing multiple linear models, and the linear models are linear relationships between the output data and the PWM duty cycle at the target PWM frequency; and a signal output module, which counts in response to the frequency division clock pulses and outputs a PWM signal based on the count value, the corresponding normalized count threshold, and the total number of clock pulses, wherein the normalized count threshold is obtained based on a normalized model, and the normalized model is the relationship between the normalized count threshold and the output data, and the total number of clock pulses is the total number of reference clock pulses required for one complete cycle of the target PWM frequency.

[0005] Optionally, the linear model is: Where X is the output data, representing the duty cycle control quantity; Y is the clock count value corresponding to the PWM duty cycle; a is the slope corresponding to the target PWM frequency; and Ymax is the total number of clock cycles corresponding to the target PWM frequency.

[0006] Optionally, the frequency division coefficients are common factors of the multiple linear models; the normalization model is: Where X is the output data and Y' is the normalized count threshold.

[0007] Optionally, the frequency division processing module includes: a frequency division counter for counting the master clock signal to generate a first current count value; a frequency division processor for comparing the first current count value with the frequency division threshold corresponding to the frequency division coefficient and outputting a comparison result signal; and an integrated clock gating unit for outputting the corresponding frequency division clock pulse according to the comparison result signal.

[0008] Optionally, the frequency divider processor includes multiple frequency divider comparators, wherein the frequency divider comparators are 4-bit comparators; or, the frequency divider processor is a multiplexer.

[0009] Optionally, the frequency divider counter is a 4-bit counter, the counting range of the 4-bit counter is 0 to 15, and the bit width of the frequency divider counter is determined according to the maximum value of the frequency division coefficient.

[0010] Optionally, the signal output module includes: a calculation unit for obtaining the normalized count threshold based on the output data and the normalization model; a main counter for counting in response to the frequency division clock pulse at the target PWM frequency to obtain a second current count value; a first comparator for comparing the second current count value with the normalized count threshold to obtain a first comparison result; a second comparator for comparing the second current count value with the corresponding total clock count to obtain a second comparison result; and a signal generation unit for outputting a PWM signal at a high level or switching the PWM signal to a low level based on the first comparison result, and outputting a PWM signal at a low level or resetting based on the second comparison result.

[0011] Optionally, the calculation unit is an adder, the main counter is an 11-bit main counter, and the first comparator and the second comparator are 11-bit comparators.

[0012] This invention also proposes a pulse width modulation (PWM) signal output method, comprising: outputting multiple frequency division clock pulses at a target PWM frequency based on multiple frequency division coefficients and a master clock signal, wherein the frequency division coefficients are obtained by normalizing multiple linear models, and the linear models are linear relationships between the output data and the PWM duty cycle at the target PWM frequency; counting in response to the frequency division clock pulses, and outputting a PWM signal based on the count value, the corresponding normalized count threshold, and the total number of clock pulses, wherein the normalized count threshold is obtained based on a normalized model, and the normalized model is the relationship between the normalized count threshold and the output data, and the total number of clock pulses is the total number of reference clock pulses required for one complete cycle of the target PWM frequency.

[0013] Optionally, the linear model is: Where X is the output data, representing the duty cycle control quantity; Y is the clock count value corresponding to the PWM duty cycle; a is the slope corresponding to the target PWM frequency; Y max This represents the total number of clock cycles corresponding to the target PWM frequency.

[0014] Optionally, the normalization model is: Where X is the output data and Y' is the normalized count threshold.

[0015] Optionally, the normalization model is: Where X is the output data, Y' is the normalized counting threshold, and b is the precision multiplier.

[0016] Optionally, the step of outputting a plurality of frequency-divided clock pulses at the target PWM frequency based on the plurality of frequency division coefficients and the master clock signal includes: counting the master clock signal to generate a first current count value; outputting a corresponding comparison result signal when the first current count value reaches a plurality of frequency division thresholds corresponding to the plurality of frequency division coefficients; and outputting the corresponding frequency-divided clock pulse based on the comparison result signal.

[0017] Optionally, the step of counting in response to the frequency-divided clock pulse and outputting a PWM signal based on the count value, the corresponding normalized count threshold, and the total number of clock cycles includes: obtaining the normalized count threshold based on the output data and the normalization model; counting in response to the frequency-divided clock pulse at the target PWM frequency to obtain a second current count value; comparing the second current count value with the normalized count threshold to obtain a first comparison result; comparing the second current count value with the corresponding total number of clock cycles to obtain a second comparison result; outputting a PWM signal at a high level or switching the PWM signal to a low level based on the first comparison result; and outputting a PWM signal at a low level or resetting based on the second comparison result.

[0018] Optionally, the PWM signal is kept high during the period from 0 to the normalized count threshold of the second current count value; the PWM signal is switched to low when the second current count value reaches the normalized count threshold; the PWM signal is kept low during the period from the normalized count threshold to the total number of clock cycles of the second current count value; and the cycle counting ends when the second current count value reaches the total number of clock cycles.

[0019] The technical solution of this invention sets up a frequency division processing module and a signal output module. Through a linear model of the output data and PWM duty cycle at the target PWM frequency, and normalization processing, it unifies multi-frequency PWM control into a single parameter space. Through frequency division processing, it outputs PWM signals through count values, the corresponding normalized count threshold, and the total number of clock cycles. By outputting various output data corresponding to different PWM duty cycles at different frequencies, it achieves the reuse of processing logic and hardware, reduces processing logic, saves hardware resources through frequency division processing, and greatly reduces power consumption. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0021] Figure 1 A schematic diagram of a pulse width modulation (PWM) signal output device according to an embodiment of the present invention is provided; Figure 2 A graph showing the linear relationship between the PWM duty cycle and the ADC value is provided. Figure 3 A schematic diagram of the frequency division processing module of a pulse width modulation (PWM) signal output device according to an embodiment of the present invention is provided; Figure 4 A schematic diagram of the signal output module of a pulse width modulation (PWM) signal output device according to an embodiment of the present invention is provided; Figure 5 A schematic flowchart of a pulse width modulation (PWM) signal output method according to an embodiment of the present invention is provided; Figure 6 A flowchart illustrating step S10 of a pulse width modulation (PWM) signal output method according to an embodiment of the present invention is provided. Figure 7 A flowchart illustrating step S20 of a pulse width modulation (PWM) signal output method according to an embodiment of the present invention is provided; Explanation of icon numbers: 1. Pulse Width Modulation (PWM) signal output device; 10. Frequency division processing module; 20. Signal output module; 110. Frequency divider counter; 120. Frequency divider comparator; 130. Integrated clock gating unit; 210, Main counter; 220, Calculation unit; 230, First comparator; 240, Second comparator; 250, Signal generation unit.

[0022] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0024] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0025] This invention proposes a pulse width modulation (PWM) signal output device 1.

[0026] Reference Figure 1 , Figure 1 A schematic diagram of a pulse width modulation (PWM) signal output device according to an embodiment of the present invention is provided. In this embodiment, the PWM signal output device 1 includes a frequency division processing module 10 and a signal output module 20.

[0027] Digital pins typically only support two states: high (1) and low (0). When multiple data streams need to be output through a single pin, the specific data value needs to be represented by the PWM duty cycle. The data value can be, for example, an ADC (Analog-to-Digital Converter) sample value, and different data types are distinguished by the PWM frequency. Multiple output data need to be output through multiple PWM duty cycles at different PWM frequencies. Based on multiple output data and corresponding target PWM frequencies, multiple linear models and multiple total clock counts are obtained. The linear model represents the linear relationship between the output data and the PWM duty cycle at the target PWM frequency. The multiple linear models are normalized to obtain corresponding multiple frequency division coefficients and a normalized model. The normalized model represents the relationship between the normalized count threshold and the output data. The frequency division processing module 10 outputs multiple frequency division clock pulses at the target PWM frequency based on the multiple frequency division coefficients and the master clock signal. The frequency division coefficients are obtained based on the normalization of multiple linear models, and the linear model is the linear relationship between the output data and the PWM duty cycle at the target PWM frequency. The signal output module 20 counts in response to the frequency division clock pulse and outputs a PWM signal based on the count value, the corresponding normalized count threshold, and the total number of clocks. The normalized count threshold is obtained based on a normalization model, which is the relationship between the normalized count threshold and the output data. The total number of clocks is the total number of reference clock pulses required for one complete cycle of the target PWM frequency.

[0028] The technical solution of this invention sets up a frequency division processing module 10 and a signal output module 20. By using a linear model of the output data and PWM duty cycle at the target PWM frequency, and normalization processing, it unifies the control of multi-frequency PWM into a single parameter space. Then, through frequency division processing, it outputs PWM signals using the count value, the corresponding normalized count threshold, and the total number of clock cycles. By outputting various output data corresponding to different PWM duty cycles at different frequencies, it achieves the reuse of processing logic and hardware, reduces processing logic, saves hardware resources through frequency division processing, and greatly reduces power consumption.

[0029] Furthermore, such as Figure 2 As shown, Figure 2 This is a graph showing the linear relationship between the PWM duty cycle and the ADC value. Figure 2 The diagram illustrates the linear relationship of the linear model, assuming a 10% duty cycle when the output data is 0, and a 90% duty cycle when the output data is 1023; the vertical axis Y represents the PWM duty cycle, and the horizontal axis X represents the ADC value (i.e., the output data). (The diagram is presented in the original text.) Figure 2 The linear relationship diagram shown can yield a linear model, for example: Where X is the output data, representing the duty cycle control quantity; Y is the clock count value corresponding to the PWM duty cycle; a is the slope corresponding to the target PWM frequency; Y max This represents the total number of clock cycles corresponding to the target PWM frequency.

[0030] Taking the output data as ADC values ​​(range 0~1023), with two sets of output data and two PWM frequencies of 3.9kHz and 2.6kHz as an example, the output data range can be scaled proportionally. The output PWM signal uses a high-frequency digital signal, and the master clock signal frequency is 50MHz. Assuming the PWM duty cycle is 10% when the output data is 0, and 90% when the output data is 1023, the complete 0~100% range is not used. Of course, this embodiment is not limited to this.

[0031] The first PWM frequency is 3.9kHz, with a period T = 1 / 3.9kHz ≈ 256μs, corresponding to a total clock count Y. max =50MHz T / 1 = 50000 / 3.9 ≈ 12820; the second PWM frequency is 2.6kHz, the period T = 1 / 2.6kHz ≈ 385μs, corresponding to a total clock count Y. max =50MHz T / 1 = 50000 / 2.6 ≈ 19230.

[0032] Substituting X=1023 (maximum ADC value), and assuming the duty cycle upper limit is 80% (0.8... Y max ); First type of PWM: 1023 a=0.8 12820 a = 10.02 ≈ 10, resulting in equation (1): X * 10 + 0.1 * 12820 = Y; Second type of PWM: 1023 a=0.8 19230 a = 15.04 ≈ 15, resulting in equation (2): X * 15 + 0.1 * 19230 = Y.

[0033] Multiple frequency division coefficients are obtained by extracting common factors from multiple linear models. A normalized model is then derived based on the linear models and corresponding frequency division coefficients at different PWM frequencies. The normalized model is as follows: Where X is the output data and Y' is the normalized count threshold.

[0034] Specifically, by extracting common factors from equations (1) and (2), the corresponding frequency division coefficients 10 and 15 are obtained. Equations (1) and (2) are then normalized. Equation (1) is simplified and its common factors are extracted to obtain equation (3): Y = 10X + 1280 = 10(X + 128). Equation (2) is simplified and its common factors are extracted to obtain equation (4): Y = 15X + 1923 = 15(X + 128.2) ≈ 15(X + 128). Thus, the normalized model is obtained. .

[0035] See Figure 3 , Figure 3 A schematic diagram of the frequency division processing module of a pulse width modulation (PWM) signal output device according to an embodiment of the present invention is provided. The frequency division processing module 10 includes a frequency divider counter 110, a frequency divider processor, and an integrated clock gating unit 130. The frequency divider processor may include, for example, multiple frequency divider comparators 120, which may be 4-bit comparators or, for example, multiplexers. The number of frequency divider comparators 120 is the same as the number of types of output data, and different frequency divisions are compared and controlled by different frequency divider comparators 120. The frequency divider counter 110 counts the master clock signal to generate a first current count value. The frequency divider processor compares the first current count value with the frequency division threshold corresponding to the frequency division coefficient and outputs a comparison result signal. The integrated clock gating unit 130 outputs the corresponding frequency-divided clock pulse according to the comparison result signal. By using the frequency divider counter 110, the frequency divider processor, and the integrated clock gating unit 130 for frequency division output, compared with the prior art, clock gating (ICG) technology is used to turn on the clock only when needed, avoiding continuous counter toggling and reducing dynamic power consumption.

[0036] For a target PWM frequency of 3.9kHz, one LSB (Least Significant Bit) consists of 10 cycles; for a target PWM frequency of 2.6kHz, one LSB consists of 15 cycles. The frequency divider counter 110 counts the master clock signal to generate the first current count value. Each count increments by 1 every 10 or 15 cycles, representing the addition of one LSB. Through frequency division, each count with a 10 or 15 division represents the addition of one LSB. This frequency division method can be implemented using ICG (integrated clock gating) to subtract the clock frequency, saving resources. In this example, the frequency divider counter 110 can be a 4-bit counter with a counting range of 0 to 15. The bit width of the frequency divider counter 110 is determined by the maximum value of the division factor.

[0037] Taking a division factor of 10 as an example, the division counter 110 starts counting from 0 and increments by 1 every 50MHz clock cycle. When it counts to 9 (the division threshold corresponding to the division factor of 10), the counter is reset to 0 in the next clock cycle. The comparison value of the division comparator 120 is the division threshold. The division comparator 120 compares the first current count value output by the division counter 110 with the division threshold (9) and outputs the comparison result signal. The comparison result signal can be, for example, a high-level signal. When the first current count value output by the division comparator 120 is 9, the division comparator 120 outputs clk_en10 = 1, indicating that 10 clock cycles have been counted. When the integrated clock gating unit 130 receives the comparison result signal, the clock gating is turned on and outputs the corresponding division clock pulse. Then the clock path is turned off and the next trigger is waited for. Similarly, when the frequency division factor is 15, the count starts from 0 and increments by 1 every 50MHz clock cycle. When the count reaches 14 (the frequency division threshold corresponding to the frequency division factor 15), the counter is reset to 0 in the next clock cycle. The comparison value of the frequency divider comparator 120 is the frequency division threshold. The frequency divider comparator 120 compares the first current count value output by the frequency divider counter 110 with the frequency division threshold (14) and outputs the comparison result signal. When the first current count value output by the frequency divider comparator 120 is 14, the frequency divider comparator 120 outputs clk_en15 = 1, indicating that 15 clock cycles have been counted. When the integrated clock gating unit 130 receives the comparison result signal, the clock gating is turned on and outputs the corresponding frequency-divided clock pulse. By using integrated clock gating (ICG) technology, the clock can be turned off when the clock signal is not needed, which can reduce dynamic power consumption. When the frequency divider counter 110 counts before reaching the frequency division threshold, the frequency-divided clock signal is turned off, so that the circuit of the subsequent signal output module 20 is in a static state, reducing power consumption. The threshold of the frequency divider comparator 120 directly corresponds to the frequency division coefficient minus 1 (e.g., a 10-fold division corresponds to a threshold of 9), achieving cycle control through simple numerical comparison and saving logic resources. Furthermore, after normalization design, the control logic for different frequencies is unified into a combination of "frequency divider counter 110, frequency divider comparator 120, and integrated clock gating unit 130", reducing redundant hardware resources.

[0038] See Figure 4 , Figure 4A schematic diagram of the signal output module of a pulse width modulation (PWM) signal output device according to an embodiment of the present invention is provided. The signal output module 20 includes: a main counter 210, a calculation unit 220, a first comparator 230, a second comparator 240, and a signal generation unit 250. The calculation unit 220 obtains a normalized counting threshold based on the output data and a normalization model; the main counter 210 counts in response to the frequency-divided clock pulse at the target PWM frequency to obtain a second current count value; the first comparator 230 compares the second current count value with the normalized counting threshold to obtain a first comparison result; the second comparator 240 compares the second current count value with the corresponding total clock count to obtain a second comparison result; the signal generation unit 250 outputs a PWM signal at a high level or switches the PWM signal to a low level according to the first comparison result, and outputs a PWM signal at a low level or resets it according to the second comparison result. Compared with the prior art, the pulse width modulation (PWM) signal output device provided in this embodiment reduces one 14-bit addition logic, reduces the number of comparators from 4 (14-bit or 15-bit) to 2 (11-bit), adds two 4-bit comparators, and also reduces the bit width of the adder to a certain extent. Therefore, the digital circuit area is reduced and hardware resources are reduced.

[0039] The calculation unit 220 can be an adder to perform the X+128 operation and generate a normalized count threshold. Since 128 = 0x80, this can be achieved through fixed offset addition, narrowing the adder's bit width (requiring only 10 bits), and the two frequencies only need to correspond to different division ratios. The main counter 210 can be an 11-bit main counter. The main counter 210 receives the divided clock pulse at the target PWM frequency and counts to obtain the second current count value. The first comparator 230 and the second comparator 240 can also be 11-bit comparators. The first comparator 230 compares the second current count value with the normalized count threshold. When the second current count value has not reached the normalized count threshold, the signal generation unit 250 outputs a high-level PWM signal; when the second current count value reaches the normalized count threshold, the signal generation unit 250 switches the PWM signal to a low level. The second comparator 240 compares the second current count value with the total clock count. When the second current count value has not reached the total clock count, the signal generation unit 250 outputs a PWM signal that remains low, and the cycle has not ended. When the second current count value reaches the total clock count, the next cycle count begins, triggering the main counter 210 to reset to 0. Simultaneously, the pulse width modulation (PWM) signal output goes high, starting a new cycle. This ensures that the total duration of each cycle is fixed, maintaining the target PWM frequency. During the period from 0 to the normalized count threshold, the PWM signal remains high; when the second current count value reaches the normalized count threshold, the PWM signal is switched to low; during the period from the normalized count threshold to the total clock count, the PWM signal remains low; and when the second current count value reaches the total clock count, the cycle count ends.

[0040] In another embodiment of the present invention, the normalization model may be: Where X is the output data, Y' is the normalized counting threshold, and b is the precision multiplier. It can adapt to a high-frequency master clock signal (e.g., a 40MHz clock). The PWM reference frequency is 31.25kHz (40000 / 1280), which is 3.1kHz after a 10 division. To maintain a similar output frequency (e.g., 3.9kHz), the threshold can be increased, and then a 10 division yields 15.625kHz / 10≈1.56kHz. In this case, the division ratio needs to be adjusted to 4, resulting in 15.625kHz / 4≈3.9kHz. By setting the precision multiplier, the period corresponding to each LSB is increased by a corresponding multiple; that is, each LSB is represented by the number of sampling points of the precision multiplier. Since the threshold is doubled, the total number of clock cycles is also doubled, expanding the counting range of the second comparator 240 to 2560, increasing the number of effective bits, thus providing finer duty cycle adjustment at the same frequency.

[0041] This invention also proposes a pulse width modulation (PWM) signal output method, which is applied to the PWM signal output device as described in the above embodiments. See also Figure 5 , Figure 5 A flowchart illustrating a pulse width modulation (PWM) signal output method according to an embodiment of the present invention is provided. The PWM signal output method includes the following steps: S10, output multiple frequency division clock pulses at multiple target PWM frequencies based on multiple frequency division coefficients and the master clock signal, wherein the frequency division coefficients are obtained by normalizing multiple linear models, and the linear models are the linear relationship between the output data at the target PWM frequency and the PWM duty cycle; S20, in response to the frequency division clock pulse, count is performed, and a PWM signal is output according to the count value, the corresponding normalized count threshold and the total number of clocks. The normalized count threshold is obtained based on a normalization model, which is the relationship between the normalized count threshold and the output data. The total number of clocks is the total number of reference clock pulses required for one complete cycle of the target PWM frequency.

[0042] The linear model is, for example: Where X is the output data, representing the duty cycle control quantity; Y is the clock count value corresponding to the PWM duty cycle; a is the slope corresponding to the target PWM frequency; Y max This represents the total number of clock cycles corresponding to the target PWM frequency.

[0043] Taking the output data as ADC values ​​(range 0~1023), with two sets of output data and two PWM frequencies of 3.9kHz and 2.6kHz as an example, the output data range can be scaled proportionally. The output PWM signal uses a high-frequency digital signal, and the master clock signal frequency is 50MHz. Assuming the PWM duty cycle is 10% when the output data is 0, and 90% when the output data is 1023, the complete 0~100% range is not used. Of course, this embodiment is not limited to this.

[0044] The first PWM frequency is 3.9kHz, with a period T = 1 / 3.9kHz ≈ 256μs, corresponding to a total clock count Y. max =50MHz T / 1 = 50000 / 3.9 ≈ 12820; the second PWM frequency is 2.6kHz, the period T = 1 / 2.6kHz ≈ 385μs, corresponding to a total clock count Y. max =50MHz T / 1 = 50000 / 2.6 ≈ 19230.

[0045] Substituting X=1023 (maximum ADC value), and assuming the duty cycle upper limit is 80% (0.8... Y max ); First type of PWM: 1023 a=0.8 12820 a = 10.02 ≈ 10, resulting in equation (1): X * 10 + 0.1 * 12820 = Y; Second type of PWM: 1023 a=0.8 19230 a = 15.04 ≈ 15, resulting in equation (2): X * 15 + 0.1 * 19230 = Y.

[0046] In one embodiment of the present invention, the normalization model is: Where X is the output data and Y' is the normalized counting threshold. Specifically, the corresponding frequency division systems 10 and 15 are obtained by extracting common factors according to equations (1) and (2). Equations (1) and (2) are normalized, and equation (1) is simplified and common factors are extracted to obtain equation (3): Y=10X+1280=10(X+128). Equation (2) is simplified and common factors are extracted to obtain equation (4): Y=15X+1923=15(X+128.2)≈15(X+128), thus obtaining the normalized model. .

[0047] In another embodiment of the present invention, the normalization model may be: Where X is the output data, Y' is the normalized counting threshold, and b is the precision multiplier. By setting the precision multiplier, the period corresponding to each LSB is also increased by a corresponding multiple, that is, each LSB is represented by the number of sampling points of the precision multiplier. Since the threshold is doubled, the total number of clock cycles is also doubled, the counting value range of the second comparator 240 is expanded to 2560, the number of effective bits is increased, thereby providing finer duty cycle adjustment at the same frequency.

[0048] See Figure 6 , Figure 6 A flowchart illustrating step S10 of a pulse width modulation (PWM) signal output method according to an embodiment of the present invention is provided. Step S10 includes: S110, Count the master clock signal to generate a first current count value; S120, when the first current count value reaches the multiple frequency division thresholds corresponding to the multiple frequency division coefficients, output the corresponding comparison result signal; S110, output the corresponding frequency division clock pulse according to the comparison result signal.

[0049] For a target PWM frequency of 3.9kHz, one LSB (Least Significant Bit) consists of 10 cycles; for a target PWM frequency of 2.6kHz, one LSB consists of 15 cycles. The frequency divider counter 110 counts the master clock signal to generate the first current count value. Each count increments by 1 every 10 or 15 cycles, representing the addition of one LSB. Through frequency division, each count with a 10 or 15 division represents the addition of one LSB. This frequency division method can be implemented using ICG (integrated clock gating) to subtract the clock frequency, saving resources. In this example, the frequency divider counter 110 can be a 4-bit counter with a counting range of 0 to 15. The bit width of the frequency divider counter 110 is determined by the maximum value of the division factor.

[0050] Taking a division factor of 10 as an example, the division counter 110 starts counting from 0 and increments by 1 every 50MHz clock cycle. When it counts to 9 (the division threshold corresponding to the division factor of 10), the counter is reset to 0 in the next clock cycle. The comparison value of the division comparator 120 is the division threshold. The division comparator 120 compares the first current count value output by the division counter 110 with the division threshold (9) and outputs the comparison result signal. The comparison result signal can be, for example, a high-level signal. When the first current count value output by the division comparator 120 is 9, the division comparator 120 outputs clk_en10 = 1, indicating that 10 clock cycles have been counted. When the integrated clock gating unit 130 receives the comparison result signal, the clock gating is turned on and outputs the corresponding division clock pulse. Then the clock path is turned off and the next trigger is waited for. Similarly, when the division factor is 15, the count starts from 0 and increments by 1 every 50MHz clock cycle. When the count reaches 14 (the division threshold corresponding to the division factor 15), the counter is reset to 0 in the next clock cycle. The comparison value of the frequency divider comparator 120 is the division threshold. The frequency divider comparator 120 compares the first current count value output by the frequency divider counter 110 with the division threshold (14) and outputs the comparison result signal. When the first current count value output by the frequency divider comparator 120 is 14, the frequency divider comparator 120 outputs clk_en15 = 1, indicating that 15 clock cycles have been counted. When the integrated clock gating unit 130 receives the comparison result signal, the clock gating is turned on and outputs the corresponding divided clock pulse. The number of frequency divider comparators 120 is the same as the number of types of output data. Different divisions are compared and controlled by different frequency divider comparators 120. By using integrated clock gating (ICG) technology, the clock can be turned off when the clock signal is not needed, which can reduce dynamic power consumption. When the frequency divider counter 110 has not reached the frequency division threshold, the divided clock signal is turned off, keeping the subsequent signal output module 20 in a static state and reducing power consumption. The threshold of the frequency divider comparator 120 directly corresponds to the frequency division coefficient minus 1 (e.g., a 10-fold division corresponds to a threshold of 9), achieving cycle control through simple numerical comparison and saving logic resources. Furthermore, through normalization design, the control logic for different frequencies is unified into a combination of "frequency divider counter 110, frequency divider comparator 120, and integrated clock gating unit 130", reducing redundant hardware resources.

[0051] See Figure 7 , Figure 7 A flowchart illustrating step S20 of a pulse width modulation (PWM) signal output method according to an embodiment of the present invention is provided. Step S20 includes: S210, the normalized count threshold is obtained based on the output data and the normalization model; S220, in response to the frequency division clock pulse at the target PWM frequency, count to obtain a second current count value; S230, compare the second current count value and the normalized count threshold to obtain a first comparison result; S240, compare the second current count value with the corresponding total clock count to obtain a second comparison result; S250: Based on the first comparison result, output a PWM signal at a high level or switch the PWM signal to a low level; based on the second comparison result, output a PWM signal at a low level or reset.

[0052] Specifically, the PWM signal is kept high during the period from 0 to the normalized count threshold of the second current count value; the PWM signal is switched to low when the second current count value reaches the normalized count threshold; the PWM signal is kept low during the period from the normalized count threshold to the total number of clock cycles of the second current count value; and the cycle counting ends when the second current count value reaches the total number of clock cycles.

[0053] The pseudocode corresponding to the pulse width modulation (PWM) signal output method described in this application is shown below: input [9:0] adc_val; input clk; input rst_n; input chn_sel; wire [10:0] num_duty; wire [10:0] num_cycle; reg [10:0]cnt1; reg [3:0]cnt2; reg dout; always @(*) begin num_duty = adc_val[9:0] + 128; num_cycle = 1280; if(cnt <num_duty) dout = 1; / / High-level phase else dout = 0; / / Low level phase if(chn_sel) clk_div_num = 14; else clk_div_num = 9; end always @(posedge clk or negedge rst_n) if (!rst_n) cnt2<= 0; else if(!(cnt2 == clk_div_num)) cnt2 <= cnt2 + 1; else cnt2<= 0; reg latch_out; reg clk_en; wire clk_gated1; always @(*) begin clk_en = cnt2 == clk_div_num; / / Triggered when the frequency divider counter reaches the frequency divider threshold if(!clk) latch_out = clk_en; end assign clk_gated1 = clk&latch_out; / / Output a clock pulse after the frequency division cycle ends. always @(posedge clk_gated1 or negedge rst_n) if(!rst_n) cnt1<= 0; else if (cnt1 != num_cycle) cnt1 <= cnt1 + 1; else cnt1<= 0; Among them, adc_val [9:0] is a 10-bit ADC value with a range of 0 to 1023; chn_sel is a channel selection signal (0 / 1) that determines the division factor (10 or 15); clk is a 50 MHz high-frequency clock. num_duty = adc_val + 128, and the normalized count threshold, i.e., the high-level duration threshold, is calculated through an adder. The ADC value is mapped to the PWM count value through a fixed offset (128); um_cycle = 1280 is the total number of clocks, i.e., the total length of the PWM period. cnt2 [3:0] is a 4-bit division counter 110 used to control clock gating; cnt1 [10:0] is an 11-bit main counter 210 that determines the PWM signal waveform. cnt2 generates a clk_gated1 pulse every 10 clock cycles. cnt1 counts under the drive of clk_gated1. When cnt1 < num_duty, dout is high level, otherwise it outputs low level. When cnt1 = num_cycle, the counter is reset to start a new cycle. Similarly, cnt2 generates a clk_gated2 pulse every 15 clock cycles. cnt1 counts under the drive of clk_gated2. When cnt1 < num_duty, dout is high level, otherwise it outputs low level. When cnt1 = num_cycle, the counter is reset to start a new cycle. <X

[0054] The technical solution of the present invention establishes a linear model between the output data and the PWM duty cycle at the target PWM frequency. Through normalization processing, multi-frequency PWM control is unified into a single parameter space, and through frequency division processing, a PWM signal is output through the count value, the corresponding normalized count threshold, and the total number of clocks. Multiple output data corresponding to the PWM duty cycle at different frequencies are output. Due to the adoption of normalization processing, the reuse of processing logic and hardware is achieved, the processing logic is reduced, and the reduction of logic also brings a reduction in power consumption. Through frequency division processing, hardware resources are saved and power consumption is also greatly reduced; and some addition logic and multiplexers are also reduced, and the bit width of the adder is also reduced to a certain extent, so the digital circuit area is also reduced. Moreover, when the number of types of PWM frequencies output is more, more resources and power consumption are saved.

[0055] The above are only optional embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structural transformation made under the inventive concept of the present invention by using the content of the specification and drawings of the present invention, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A pulse width modulation (PWM) signal output device, characterized in that, include: The frequency division processing module outputs frequency-divided clock pulses at multiple target PWM frequencies based on multiple frequency division coefficients and the master clock signal. The frequency division coefficients are obtained by normalizing multiple linear models, and the linear models are the linear relationship between the output data at the target PWM frequency and the PWM duty cycle. The signal output module counts in response to the frequency division clock pulse and outputs a PWM signal based on the count value, the corresponding normalized count threshold, and the total number of clocks. The normalized count threshold is obtained based on a normalization model, which is the relationship between the normalized count threshold and the output data. The total number of clocks is the total number of reference clock pulses required for one complete cycle of the target PWM frequency.

2. The pulse width modulation (PWM) signal output device as described in claim 1, characterized in that, The linear model is as follows: ； Where X is the output data, representing the duty cycle control quantity; Y is the clock count value corresponding to the PWM duty cycle; a is the slope corresponding to the target PWM frequency; Y max This represents the total number of clock cycles corresponding to the target PWM frequency.

3. The pulse width modulation (PWM) signal output device as described in claim 2, characterized in that, The frequency division coefficient is a common factor of the multiple linear models; The normalization model is as follows: ； Where X is the output data and Y' is the normalized count threshold.

4. The pulse width modulation (PWM) signal output device as described in claim 1, characterized in that, The frequency division processing module includes: A frequency divider counter is used to count the master clock signal and generate a first current count value. The frequency divider processor compares the first current count value with the frequency division threshold corresponding to the frequency division coefficient and outputs a comparison result signal; and An integrated clock gating unit outputs the corresponding frequency-divided clock pulse based on the comparison result signal.

5. The pulse width modulation (PWM) signal output device as described in claim 4, characterized in that, The frequency divider processor includes multiple frequency divider comparators, wherein each frequency divider comparator is a 4-bit comparator; or, the frequency divider processor is a multiplexer.

6. The pulse width modulation (PWM) signal output device as described in claim 4, characterized in that, The frequency divider counter is a 4-bit counter with a counting range of 0 to 15. The bit width of the frequency divider counter is determined based on the maximum value of the frequency division coefficient.

7. The pulse width modulation (PWM) signal output device as described in claim 1, characterized in that, The signal output module includes: The calculation unit obtains the normalized count threshold based on the output data and the normalization model; The master counter counts in response to the frequency-divided clock pulse at the target PWM frequency to obtain a second current count value; A first comparator compares the second current count value with the normalized count threshold to obtain a first comparison result; A second comparator compares the second current count value with the corresponding total clock count to obtain a second comparison result; and The signal generation unit outputs a PWM signal at a high level or switches the PWM signal to a low level based on the first comparison result, and outputs a PWM signal at a low level or resets based on the second comparison result.

8. The pulse width modulation (PWM) signal output device as described in claim 7, characterized in that, The calculation unit is an adder, the main counter is an 11-bit main counter, and the first comparator and the second comparator are 11-bit comparators.

9. A method for outputting a pulse width modulation (PWM) signal, characterized in that, include: Based on multiple frequency division coefficients and the master clock signal, multiple frequency division clock pulses at target PWM frequencies are output. The frequency division coefficients are obtained by normalizing multiple linear models, and the linear models are the linear relationship between the output data at the target PWM frequency and the PWM duty cycle. The system counts in response to the frequency division clock pulse and outputs a PWM signal based on the count value, the corresponding normalized count threshold, and the total number of clock pulses. The normalized count threshold is obtained based on a normalization model, which is the relationship between the normalized count threshold and the output data. The total number of clock pulses is the total number of reference clock pulses required for one complete cycle of the target PWM frequency.

10. The pulse width modulation (PWM) signal output method as described in claim 9, characterized in that, The linear model is as follows: ； Where X is the output data, representing the duty cycle control quantity; Y is the clock count value corresponding to the PWM duty cycle; a is the slope corresponding to the target PWM frequency; Y max This represents the total number of clock cycles corresponding to the target PWM frequency.

11. The pulse width modulation (PWM) signal output method as described in claim 10, characterized in that, The normalization model is as follows: ； Where X is the output data and Y' is the normalized count threshold.

12. The pulse width modulation (PWM) signal output method as described in claim 10, characterized in that, The normalization model is as follows: ； Where X is the output data, Y' is the normalized count threshold, and b is the precision multiplier.

13. The pulse width modulation (PWM) signal output method as described in claim 9, characterized in that, The step of outputting multiple frequency-divided clock pulses at multiple target PWM frequencies based on multiple frequency division coefficients and the master clock signal includes: The master clock signal is counted to generate a first current count value; When the first current count value reaches the multiple frequency division thresholds corresponding to the multiple frequency division coefficients, the corresponding comparison result signal is output; The corresponding frequency-divided clock pulse is output based on the comparison result signal.

14. The pulse width modulation (PWM) signal output method as described in claim 9, characterized in that, The step of counting in response to the frequency-divided clock pulse and outputting a PWM signal based on the count value, the corresponding normalized count threshold, and the total number of clock cycles includes: The normalized count threshold is obtained based on the output data and the normalization model; A second current count value is obtained by counting in response to the frequency division clock pulse at the target PWM frequency; A first comparison result is obtained by comparing the second current count value with the normalized count threshold; A second comparison result is obtained by comparing the second current count value with the corresponding total number of clock cycles. Based on the first comparison result, the output PWM signal is either high or the PWM signal is switched to low. Based on the second comparison result, the output PWM signal is either low or reset.

15. The pulse width modulation (PWM) signal output method as described in claim 14, characterized in that, During the period from 0 to the normalized count threshold, the PWM signal is kept high; when the second current count value reaches the normalized count threshold, the PWM signal is switched to low; during the period from the normalized count threshold to the total clock count, the PWM signal is kept low; when the second current count value reaches the total clock count, the cycle counting ends.

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