A PCIe message aggregation switching method and device

Abstract

This invention belongs to the field of PCIe switching chips and relates to a PCIe packet aggregation and switching method and apparatus. The apparatus includes a PCIe ingress port, an ingress aggregation module, a crossbar switch, an egress deaggregation module, and a PCIe egress port. The ingress aggregation module is used to filter and match multiple received TLPs according to preset aggregation conditions to determine whether they meet the aggregation requirements. The crossbar switch is used to receive CTLPs or independent TLPs sent by the ingress aggregation module and forward them to the corresponding egress deaggregation module according to the destination port of the packet. The egress deaggregation module is used to receive packets forwarded by the crossbar switch and determine whether they are CTLPs or independent TLPs. This invention significantly improves bandwidth utilization, significantly reduces transmission latency, has excellent compatibility, low implementation cost, high reliability, and strong universality.

Description

Technical Field

[0001] This invention relates to a PCIe packet aggregation and switching method and apparatus, belonging to the field of PCIe switching chip technology. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial bus protocol widely used in data centers, servers, and high-performance computing scenarios. Its core characteristics are a point-to-point topology and a hierarchical data transmission mechanism, achieving data exchange through Transaction Layer Packets (TLPs). With the rapid development of high-performance computing (HPC) and artificial intelligence (AI) technologies, the demand for interconnect bandwidth within data centers is growing exponentially. As the core bus standard for interconnection within and between servers, the performance of PCIe switches directly determines the overall system throughput.

[0003] In the internal architecture of PCIe switching chips, to handle high-speed data streams, fixed-size flasks are typically used for internal transmission and switching of packets. For example, in a typical PCIe 5.0 (Peripheral Component Interconnect Express 5.0; the fifth-generation PCI Express interface standard) protocol switching chip, the internal data bus width is designed to be 512 bits, and the size of each flask corresponding to the system clock is fixed at 512 bits. Externally input PCIe transaction layer packets (TLPs) are divided into multiple flasks and exchanged within the internal crossbar after entering the switching chip.

[0004] In existing technologies, PCIe packets need to be transmitted in fixed-size shards within the switching chip, dividing the TLP into multiple shards, with each shard occupying one clock cycle during switching. However, this fixed-shard mechanism has significant drawbacks:

[0005] 1) Low bandwidth utilization: When the payload of a TLP is small, the proportion of the header increases significantly, leading to wasted micro-slice resources. For example, a TLP with a payload of 128 bytes requires 3 micro-slices, of which 1 micro-slice is used only for transmitting the header, resulting in a bandwidth utilization of only 66.7%. When the payload is 256 bytes, the bandwidth utilization drops to 80%, and when the payload is 512 bytes, the bandwidth utilization is 88.9%. The higher the proportion of small payload packets, the more serious the bandwidth waste, making it impossible to meet the needs of high-throughput scenarios.

[0006] 2) Limited transmission efficiency: The fixed size of the microchips means that small packets need to be exchanged multiple times, which increases latency and reduces the throughput of PCIe switching chips.

[0007] 3) High transmission latency: Each TLP is cut and transmitted independently, and needs to be scheduled by arbitration of the cross switch separately. When there are many small-load TLPs, the number of arbitrations of the cross switch increases significantly, resulting in an increase in overall transmission latency, which cannot meet the low latency requirements of high-performance computing, AI training and other scenarios.

[0008] 4) Rigid resource allocation: Existing PCIe switching chips require separate allocation of buffer and arbitration resources for each microchip, resulting in high hardware complexity and increased costs.

[0009] In AI training collective communication or frequent small-block data read / write scenarios in databases, there are a large number of messages of 128 bytes or even smaller. According to existing technology, the smaller the message payload, the larger the proportion of clock cycles occupied by the message header. This leads to a significant decrease in the effective bandwidth utilization of the PCIe switching chip, making it impossible to fully utilize the theoretical bandwidth of the physical link, increasing transmission latency, and limiting the overall computing power of high-performance computing clusters.

[0010] Existing optimization solutions have limitations: Current optimization solutions for the above problems either rely on the software layer for packet aggregation and decomposition (such as the patent technology in publication number CN113542148B), which requires the cooperation of drivers or applications, has poor compatibility, and introduces additional software latency; or focus on optimizing queue scheduling strategies (such as the patent technology in publication number CN102905311A), which can only improve the fairness of packet transmission and cannot solve the core problem of low bandwidth utilization caused by wasted packet header fragments.

[0011] The "Method, Apparatus, Network Interface Card and Readable Storage Medium for Message Aggregation" disclosed in Publication No. CN113542148B involves determining the target aggregation length based on a preset bandwidth utilization threshold when the number of small-byte messages transmitted within a set time period exceeds a preset proportion threshold; acquiring messages to be transmitted in real time and adding them to the aggregated message set, and accumulating the total message length of each message in the aggregated message set; and when the total message length accumulates to meet the trigger condition of the target aggregation length, aggregating each message in the aggregated message set according to a preset aggregation format to generate an aggregated message.

[0012] The "Data Packet Aggregation Device and Data Packet Aggregation Method" disclosed in Publication No. CN102905311A includes a caching module for caching packets sent to each user station. The caching module sets up a caching queue for each user station, storing packets sent to the same user station in the same queue. An aggregation module aggregates and sends the packets in each user station's caching queue. The caching module queues all packets cached in the user station's caching queue based on the user station and sends the queued packets to the aggregation module.

[0013] Therefore, how to break through the limitations of the existing fixed microchip transmission mechanism, and solve the problems of bandwidth waste and high latency in small-load TLP transmission without modifying the PCIe standard or affecting system compatibility, and improve the transmission efficiency of PCIe switching chips, has become an urgent technical problem to be solved in the field of PCIe switching technology. Summary of the Invention

[0014] The purpose of this invention:

[0015] To address the problems of low bandwidth utilization in small-load PCIe packets, high splitting latency due to coarse packet aggregation logic, poor aggregation reliability, and insufficient compatibility in existing PCIe switching chips, the present invention aims to solve the following problems:

[0016] 1) Optimize the message header transmission method to reduce the header fragment occupation of small-load transaction layer groups and improve bandwidth utilization;

[0017] 2) By using the TLP aggregation method, the number of micro-chip transmissions is reduced, thus reducing switching latency;

[0018] 3) Establish reasonable aggregation conditions to ensure a regular aggregated message structure, reducing decomposition difficulty and latency. Simultaneously, limit the number of aggregations to balance transmission efficiency and reliability.

[0019] 4) Implement aggregation and decomposition logic without modifying the existing PCIe standard to ensure compatibility.

[0020] The specific technical solution of the present invention is as follows:

[0021] In a first aspect, a PCIe packet aggregation and switching device includes a PCIe ingress port, an ingress aggregation module, a crossbar switch, an egress deaggregation module, and a PCIe egress port;

[0022] The PCIe ingress port is used to receive multiple TLPs sent by external devices, parse each TLP, extract the message parameters of the TLP, and send the parsed TLP to the ingress aggregation module;

[0023] The ingress aggregation module is connected to the PCIe ingress port and is used to filter and match multiple received TLPs according to preset aggregation conditions to determine whether they meet the aggregation requirements.

[0024] If the aggregation conditions are met, multiple TLPs are aggregated to generate a CTLP;

[0025] If the aggregation conditions are not met, the TLP will be sent to the cross switch as an independent message;

[0026] The cross switch is connected to the inlet aggregation module and the outlet deaggregation module respectively, and is used to receive CTLP or independent TLP sent by the inlet aggregation module, and forward them to the corresponding outlet deaggregation module according to the destination port of the message;

[0027] The exit de-aggregation module is connected to the cross switch and the PCIe exit port, and is used to receive the messages forwarded by the cross switch and determine whether they are CTLP or independent TLP.

[0028] If it is a CTLP, then it is depolymerized and restored to multiple original TLPs;

[0029] If it is a standalone TLP, it will be sent directly to the PCIe egress port;

[0030] The PCIe export port is used to receive the original TLP or independent TLP sent by the export de-aggregation module and send it to the corresponding external device.

[0031] In a further improvement, the inlet aggregation module includes an aggregation judgment unit and a CTLP construction unit;

[0032] The aggregation judgment unit is used to filter and match multiple TLPs to determine whether they meet the aggregation requirements;

[0033] The CTLP building unit is used to aggregate multiple TLPs that meet the aggregation conditions to generate a CTLP.

[0034] In a further improvement, the export de-aggregation module includes a message identification unit and a TLP restoration unit;

[0035] The message identification unit is used to determine whether the received message is a CTLP or an independent TLP;

[0036] The TLP reduction unit is used to depolymerize CTLP and restore it to multiple original TLPs.

[0037] In a further improvement, the PCIe packet aggregation and switching device also includes a storage module for temporarily storing the TLP parsed by the PCIe ingress port, the CTLP generated by the ingress aggregation module, and the original TLP restored by the egress deaggregation module; ensuring the stability of packet transmission and avoiding data loss.

[0038] Both the inlet aggregation module and the outlet deaggregation module are implemented through hardware logic, without the involvement of a software layer.

[0039] Secondly, a PCIe packet aggregation and switching method, implemented using the aforementioned PCIe packet aggregation and switching device, includes the following steps:

[0040] Step S1: Message reception;

[0041] The PCIe switching chip's PCIe ingress port receives multiple TLPs sent by external devices, parses each TLP, and extracts the TLP's message parameters.

[0042] Step S2: Aggregation judgment;

[0043] The ingress aggregation module filters and matches multiple received TLPs according to preset aggregation conditions to determine whether they meet the aggregation requirements.

[0044] Step S3: Message aggregation;

[0045] If multiple TLPs meet the aggregation conditions, the entry aggregation module performs aggregation processing to generate a single CTLP.

[0046] Step S4: In-chip swapping;

[0047] The crossbar switch of the PCIe switching chip forwards CTLPs or non-aggregated TLPs to the corresponding PCIe egress ports according to their destination ports.

[0048] Step S5: Message de-aggregation;

[0049] The export de-aggregation module receives messages forwarded by the cross switch and determines whether they are CTLP or independent TLP;

[0050] If it is a standalone TLP, it will be forwarded directly to the corresponding external device;

[0051] If it is a CTLP, then it is depolymerized and restored to multiple original TLPs;

[0052] Step S6: Message transmission;

[0053] The PCIe egress port will send the deaggregated original TLPs, or the unaggregated independent TLPs, to the corresponding external devices to complete the aggregation and exchange of PCIe messages.

[0054] In a further improvement, in step S1, the message parameters include destination port, payload size, message type, Fmt field, Type field, and message timing information.

[0055] In a further improvement, in step S2, the polymerization conditions include:

[0056] Multiple TLPs are transmitted in close proximity without bubbles, with the same destination port, the same payload size, the same message type / Fmt field / Type field, and the number of aggregations ≤ a preset threshold (e.g., 4).

[0057] In the internal data transmission link of a PCIe switching chip, the subsequent TLP arrives at the designated module (such as the ingress aggregation module) immediately following the previous TLP. The time interval between two adjacent TLPs is 0 clock cycles, and no idle cycles (bubbles) without effective data transmission are inserted. This transmission method is called adjacent bubble-free transmission.

[0058] In a further improvement, in step S3, the polymerization process includes:

[0059] The headers of multiple TLPs are compressed into a single micro-piece. The lower two bits of the Type field indicate the number of aggregations. The payloads of multiple TLPs are concatenated sequentially to generate several payload micro-pieces. The header micro-pieces are combined with all payload micro-pieces to form a CTLP. If a single TLP or multiple TLPs do not meet the aggregation conditions, they are not aggregated and are transmitted directly as independent messages.

[0060] In a further improvement, in step S3, when the message headers of multiple TLPs are compressed into a micro-piece, the key information of each TLP message header is retained, and redundant and duplicate information is eliminated to ensure that the message header of each TLP can be accurately restored during de-aggregation.

[0061] The aforementioned key information includes, but is not limited to, destination address, source address, length, and attribute fields.

[0062] In step S4, the cross switch treats CTLP as a regular long data packet, without needing to modify the original arbitration scheduling logic.

[0063] In a further improvement, in step S5, the depolymerization process of the outlet depolymerization module and the polymerization process of the inlet polymerization module are designed symmetrically, and the TLP after depolymerization is completely consistent with the original TLP before polymerization; there is no data loss and no formatting errors.

[0064] The present invention differs from the patent technology disclosed in CN113542148B as follows:

[0065] 1) Different aggregation triggering conditions:

[0066] The aggregation of the present invention is triggered by fixed logic: consecutive TLPs with the same payload size, the same destination port, the same message format and type meet a number threshold (e.g., 4) or there is a transmission interval (bubble) between messages.

[0067] The aggregation of the patent technology published in CN113542148B is triggered by dynamic performance:

[0068] ① The number of small byte messages detected exceeds the preset threshold.

[0069] ② The total message length is accumulated to meet the target aggregation length (determined by the preset bandwidth utilization threshold);

[0070] ③ The total number of messages and the transmission waiting time (timeout) are used as auxiliary triggering conditions.

[0071] This invention employs deterministic, low-latency hardware flow control aggregation, which is suitable for high-speed switching within a chip.

[0072] The patent technology published under CN113542148B uses dynamic aggregation based on bandwidth utilization and traffic statistics, which is more suitable for making decisions at the upper layer of smart network cards to adapt to changing network loads.

[0073] 2) Different aggregation methods:

[0074] This invention uses message header aggregation (CTLP aggregated message header) to compress multiple TLP message headers into a single microchip, and indicates the aggregation quantity by modifying the low-order bits of the Type field in the aggregated message header.

[0075] The patent technology published in CN113542148B concatenates message information (metadata) independently, and concatenates each message information (such as total message length, relative timestamp, verification information, etc.) to occupy the preset length of the aggregated message (e.g., 256 bytes).

[0076] The "header aggregation" of this invention is key to the efficiency improvement. It directly reduces the header microchip cycle allocated to each TLP during internal chip switching, achieving "zero-overhead" header transmission.

[0077] The patent technology published in CN113542148B treats message information as a "new message tail" or "new message header" of a new message, which still occupies additional fixed length space.

[0078] 3) Different de-aggregation methods:

[0079] This invention implements deaggregation at the output port of the switching chip, decomposing the CTLP into regular TLPs before sending them out, which is transparent to the driver layer and the application end.

[0080] The decomposition of the patent technology published in CN113542148B is carried out on the application side (App). The aggregated message and the completion message (containing decomposition information) need to be uploaded to the driver layer, and the driver layer instructs the application side to perform decomposition processing.

[0081] This invention achieves full hardware acceleration, is unaware of the software stack, and has extremely low latency.

[0082] The patent technology published under CN113542148B requires the cooperation of a software stack (driver layer / application end) to complete message decomposition.

[0083] The present invention differs from the patent technology disclosed in CN102905311A as follows:

[0084] 1) Different aggregation triggering conditions:

[0085] The aggregation of the present invention is triggered by fixed logic: consecutive TLPs with the same payload size, the same destination port, the same message format and type meet a number threshold (e.g., 4) or there is a transmission interval (bubble) between messages.

[0086] The aggregation of patent technology published in CN102905311A is based on user queue-driven scheduling triggering: based on the cache queue set for each user station, it is triggered when the number of packets in the queue reaches the maximum packet sending threshold, or when an interrupt trigger signal (timer) is issued.

[0087] This invention emphasizes the continuity of TLP transmission and the consistency of message types to ensure the effectiveness of message aggregation.

[0088] The patent technology published under CN102905311A emphasizes grouping and queue scheduling by user station to ensure fairness and timely transmission.

[0089] 2) Different aggregation methods:

[0090] This invention uses the CTLP structure and message header compression to compress multiple TLP message headers into a single micro-piece (aggregated message header), and uses the low-order bits of the aggregated message header field to identify the aggregation quantity.

[0091] The patent technology published under CN102905311A focuses on queue management and batch sending, queuing and aggregation by user station, emphasizing the collaboration between the caching module and the aggregation module, and performing aggregation based on the maximum packet sending threshold of the queue or timed interrupts. It does not involve packet header compression or micro-level optimization.

[0092] The beneficial effects of this invention are:

[0093] 1. Significantly improved bandwidth utilization: Through the aggregation mechanism, this invention compresses the headers of multiple small payload TLPs that meet the conditions into a single micro-piece, reducing the number of header micro-pieces and lowering the bandwidth overhead occupied by the headers. For example, existing technologies require 12 micro-pieces (4 header micro-pieces + 8 payload micro-pieces) for 4 128-byte TLPs, while this invention only requires 9 micro-pieces (1 header micro-piece + 8 payload micro-pieces) after aggregation, increasing bandwidth utilization from 66.7% to 88.9% and reducing bandwidth overhead by 25%.

[0094] 2. Significantly Reduced Transmission Latency: In cross-connect switches, arbitrators typically schedule packets. Aggregating multiple small payload packets (TLPs) into a single cross-connect packet (CTLP) means the arbitrator only needs to perform one scheduling operation to transmit multiple packets. This reduces the number of arbitrations, switching overhead, and packet forwarding operations in the cross-connect switch, lowering the switching arbitration overhead and improving overall switching efficiency during multi-port concurrency. Furthermore, aggregation and deaggregation are implemented through hardware logic, eliminating software latency and effectively reducing overall transmission latency, making it suitable for low-latency scenarios such as high-performance computing and AI training.

[0095] 3. Excellent compatibility: The aggregation and deaggregation process of this invention is implemented entirely in hardware within the PCIe switching chip, without modifying external devices, drivers, or the PCIe protocol. The CTLP format design conforms to the PCIe standard (using the reserved bit of the Type field to identify the aggregation status). External devices do not need to make any adaptations to receive and send messages normally, and the compatibility is better than existing software layer aggregation schemes.

[0096] 4. Low cost and high reliability: This invention utilizes reserved bits in the PCIe packet Type field to mark the aggregation quantity, eliminating the need for complex additional sideband signals. Both the ingress aggregation module and the egress deaggregation module employ lightweight hardware logic design. Aggregation condition judgment and CTLP construction / parsing can be implemented through pipelines, without introducing complex hardware structures, thus not increasing power consumption or chip complexity excessively. Simultaneously, the aggregation conditions limit the aggregation quantity, packet type, and other rules, ensuring a regular CTLP structure, low deaggregation latency, and avoiding conflicts with existing PCIe standards, making the technical solution stable and reliable.

[0097] 5. High versatility: This invention can be widely applied to high-speed switching chips of PCIe 5.0 and above, and is suitable for various scenarios with a high proportion of small-load TLP transmission (such as HPC, AI training, server interconnection, etc.). It does not require large-scale modification of existing PCIe systems and is easy to promote and apply. Attached Figure Description

[0098] Figure 1 This is an architecture diagram of a PCIe switching chip that includes an ingress aggregation module and an egress deaggregation module.

[0099] Figure 2 This is the architecture diagram of the export depolymerization module;

[0100] Figure 3 This is a timing diagram comparing the present invention with existing technologies when transmitting four small payloads (TLPs). Detailed Implementation

[0101] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0102] Definitions of abbreviations and key terms:

[0103] XBAR: Crossbar, a fully interconnected switching structure consisting of multiple input ports and multiple output ports, which enables point-to-point connections from any input to any output through a switch matrix.

[0104] FLIT: Flow Control Unit. Data is divided into fixed-size data packets, called Flow Control Units (FLITs), each of which is of a fixed size.

[0105] Fmt: Format, used to indicate the message format of the TLP.

[0106] Type: Indicates the message type of the TLP.

[0107] CTLP: Converged Transaction Layer Packet.

[0108] Example 1

[0109] This invention provides a PCIe packet aggregation and switching method. By aggregating qualified TLPs at the input port of the PCIe switching chip to generate an aggregated TLP (Converged TLP), the CTLP is deaggregated at the output port to restore the original TLP, thereby reducing the proportion of chip transmission occupied by the packet header, reducing the number of chips, and improving bandwidth utilization.

[0110] like Figure 1As shown, an ingress aggregation module is added after each PCIe ingress port and before the crossbar (XBAR) of the PCIe switching chip, and an egress deaggregation module is added before each PCIe egress port and after the crossbar. Utilizing the large bit width of the transmission microchip inside the crossbar (e.g., 512 bits in PCIe 5.0), the headers of multiple small payload TLPs are compressed into a single microchip, and their data payloads are compactly arranged to form an aggregated transaction layer data packet for transmission and exchange within the chip.

[0111] Ingress aggregation module: Located at each PCIe ingress port of the PCIe switching chip, it is used to buffer incoming TLPs, check aggregation conditions, perform header merging and payload splicing, and create CTLPs.

[0112] Crossbar switch (XBAR): Responsible for routing and switching CTLP packets from the PCIe ingress port to the designated PCIe egress port. For the crossbar switch, CTLP is treated as a regular, long data packet.

[0113] Egress De-aggregation Module: Located at each egress port of the PCIe switching chip. It identifies CTLPs, parses the aggregated packet header, restores the CTLPs to multiple original TLPs (TLP reconstruction), and sends them sequentially to the link.

[0114] exist Figure 1 In this module, TLP caching and checking is a pre-module of the entry aggregation module, which realizes temporary caching of TLPs to be aggregated, time synchronization, and real-time detection of aggregation conditions; CTLP creation is the core execution sub-module of the entry aggregation module, which realizes packet header compression, aggregation identifier writing, and payload concatenation of TLPs that meet the conditions, and finally generates CTLP.

[0115] like Figure 2 As shown, the CTLP aggregation method and process describe in detail the logical flow of the entry aggregation module determining aggregation conditions and creating CTLP:

[0116] Step 1: The PCIe switch chip receives the TLP from the PCIe ingress port;

[0117] Step 2: Aggregation condition detection. The ingress aggregation module detects consecutively arriving TLPs and triggers the aggregation operation if and only if the subsequent TLP and the current cached TLP satisfy all of the following conditions:

[0118] Condition A: Adjacent relationship, that is, the next TLP arrives immediately after the previous TLP, with no bubbles in between (interval ≥ 1 clock cycle).

[0119] Condition B: The destination ports are the same, ensuring that the aggregated packets go to the same exit.

[0120] Condition C: The loads are the same size, which facilitates the calculation of offset and deaggregation;

[0121] Condition D: The TLP message type must be MWr (Memory Write) or CplD (Completion with Data), and the Fmt field (Format, used to indicate the message format) and Type field (used to indicate the message type) of all TLPs aggregated in a single instance must be exactly the same;

[0122] Condition E: Aggregation quantity limit, the number of TLPs in a single aggregation shall not exceed 4;

[0123] Step 3: If the above aggregation conditions are met, proceed to step 4; otherwise, send the received TLP as a regular TLP to XBAR.

[0124] Step 4: Construct the aggregated message header using the first microchip of CTLP, and place the received TLP message headers in the corresponding positions of the aggregated message header in sequence;

[0125] Step 5: Use the lower 2 bits of the Type field (default value 0 in PCIe protocol) in the CTLP aggregation header to identify the aggregation status. Increment the Type field by 1 each time a TLP is aggregated. For example:

[0126] Type[1:0] = 11: This indicates that 4 TLPs were aggregated;

[0127] Type[1:0] = 10: This indicates that 3 TLPs have been aggregated;

[0128] Type[1:0] = 01: This indicates that two TLPs have been aggregated;

[0129] Type[1:0] = 00: Indicates a regular TLP, not aggregated;

[0130] Step 6: Construct CTLP aggregation loads by cascading and splicing the original TLP loads to be aggregated in sequence; for example:

[0131] The TLP consists of four 128-byte payloads: TLP0 payload (128 bytes) + TLP1 payload (128 bytes) + TLP2 payload (128 bytes) + TLP3 payload (128 bytes) = 512 bytes of total payload. These 512 bytes of data are sequentially filled into the micro-pieces following the CTLP aggregate header. Since each micro-piece is 512 bits (64 bytes), the 512-byte payload occupies exactly 8 micro-pieces.

[0132] Send the CTLP; for example: the total length of the generated CTLP is: 1 aggregate head micropie + 8 payload micropie = 9 micropieces, and the CTLP is sent to XBAR.

[0133] Message decompression:

[0134] like Figure 2 As shown, the exit de-aggregation module is responsible for receiving packets forwarded by the cross switch. It first determines whether the packet is a CTLP or an independent TLP. The specific determination logic is as follows:

[0135] Parse the message header fragments and identify them based on the lower two bits of the Type field in the aggregated message header:

[0136] 1) If the lower two bits of the Type field are zero, it will be processed as a normal TLP and directly forwarded to the PCIe egress port;

[0137] 2) If the lower two bits of the Type field are not zero, it is determined to be CTLP and CTLP decomposition processing is required.

[0138] If the received message is an independent TLP, it can be directly forwarded to the corresponding external device;

[0139] If it is a CTLP, it is depolymerized and restored to multiple original TLPs.

[0140] The depolymerization process specifically includes:

[0141] Parsing the CTLP message header micro-piece (i.e. Figure 2 The "CTLP header (Type=aggregation count)" uses the lower two bits of the Type field to obtain the aggregation count (the core function of the Type field in the "CTLP header" is to identify the total number of aggregated TLPs). It then extracts the header information of each original TLP and further breaks down the concatenated payload fragments (i.e.,...). Figure 2 The phrase "cascaded load 0 + load 1 + ..." corresponds to the result of cascading and splicing multiple TLP loads during aggregation. It also corresponds to the load of each original TLP, which is ultimately combined to form multiple original TLPs.

[0142] The specific methods for load splitting and restoration are as follows:

[0143] Based on the number of identified TLP aggregations, separate the independent headers of TLP0, TLP1, TLP2, and TLP3 from the CTLP aggregation header (i.e., the first micro-piece). Figure 2The "reconstructed TLP TLP header 0, reconstructed TLP TLP header 1, reconstructed TLP TLP header n" in the header, where n is the aggregation quantity - 1 (n ≤ 3 in this invention), are then processed according to the known TLP payload size (e.g., 128 bytes) in the header, through payload slicing logic (i.e. Figure 2 The “load slicing logic” is the hardware logic built into the export depolymerization module, which is used to slice the hierarchical loads according to preset rules. It sequentially slices the data stream in the subsequent micro-slices of CTLP to complete the load 0 slice, load 1 slice, and load n slice (corresponding to the loads of the original TLP0, TLP1, and TLPn respectively, where n is the number of aggregations - 1).

[0144] Bytes 0-127 are segmented into TLP0, bytes 128-255 into TLP1, and the remaining bytes are segmented accordingly; the entire de-aggregation process relies on header parsing and reconstruction logic (i.e. Figure 2 The "header parsing and reconstruction logic" is a built-in hardware logic of the outgoing de-aggregation module, used to parse the CTLP message header, extract the original TLP message header and complete the reconstruction.

[0145] Message transmission:

[0146] The egress port will send the deaggregated original TLPs (where the restored TLP0, TLP1, TLP2, and TLP3 are sequentially sent from the PCIe egress port) or the unaggregated independent TLPs to the corresponding external devices, completing the aggregation and exchange of PCIe messages. This sending process fully complies with the PCIe specification, remains transparent to the PCIe devices at the other end of the port, and requires no adaptation from external devices; the deaggregated original TLPs need to be assembled and serialized (i.e., Figure 2 The "TLP assembly and serialization" is a hardware logic built into the egress port module, used to assemble the reconstructed TLP header and the corresponding slice payload into a standard TLP and convert it into the serial format required by the PCIe protocol. The TLPs are assembled into TLP0 (header 0 + payload 0), TLP1 (header 1 + payload 1), and TLPn (header n + payload n) (n is the aggregation quantity - 1, corresponding to the combination of the reconstructed TLP header and the corresponding slice payload), and then sent to PCIe (i.e. sent to the corresponding external PCIe device).

[0147] Figure 2 The header parsing and reconstruction logic is the core hardware logic of the exit de-aggregation module. It realizes the parsing of the CTLP aggregated message header, the identification of the number of aggregates, and the complete reconstruction of the original TLP message header, providing accurate message header data for TLP restoration.

[0148] Example 2

[0149] Examples of transmission efficiency comparisons, such as Figure 3As shown, Figure 3 The horizontal axis represents the TLP load size, and the vertical axis represents the bandwidth utilization.

[0150] See Figure 3 It includes a timing diagram comparing transmission efficiency, clearly showing two core parts:

[0151] 1. Structural level:

[0152] The process of compressing the message headers of 4 TLPs into a single message header micro-piece (CTLP header (Type=aggregation count)), the process of cascading and splicing payloads to form cascaded payloads (load 0 + load 1 + ...), and the design of the lower 2 bits of the Type field indicating the aggregation quantity, intuitively demonstrate the structural characteristics of CTLP.

[0153] 2. Comparison of transmission efficiency:

[0154] The timing diagram uses "time (clock cycle / chip)" as the time dimension to compare the efficiency difference between the prior art (without aggregation) and the present invention (with aggregation) when transmitting 4 small payload TLPs (4×128B=512B).

[0155] Among them, the existing technology uses independent TLP transmission, which requires the sequential transmission of "header + payload (128B)" of 4 TLPs, with each TLP occupying a separate header micropie and payload micropie;

[0156] This invention completes the process with a single CTLP transmission, requiring only the transmission of one "CTLP header (aggregating 4 TLP headers)" and the corresponding cascaded payload (4×128B=512B). The timing clearly shows that a single CTLP transmission saves clock cycles compared to 4 independent TLP transmissions, achieving a significant bandwidth gain.

[0157] Combined with a transmission efficiency comparison example, in a 128-byte payload scenario, when transmitting 4 small payload TLPs, the existing technology (without aggregation) has 12 internal transmission shards (4 header shards + 8 payload shards); the present invention (with aggregation) reduces the number of internal transmission shards to 9 (1 CTLP header shard + 8 payload shards). The intuitive presentation of the timing diagram further highlights the bandwidth gain brought by the present invention, confirming the technical advantage of increasing bandwidth utilization from 66.7% to 88.9%.

[0158] In other words, the present invention has a significantly higher bandwidth utilization rate than existing technologies in low-load TLP transmission scenarios, demonstrating clear technical advantages.

[0159] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A PCIe packet aggregation and switching device, characterized in that: Includes PCIe ingress port, ingress aggregation module, cross switch, egress deaggregation module, and PCIe egress port; The PCIe ingress port is used to receive multiple TLPs sent by external devices, parse each TLP, extract the message parameters of the TLP, and send the parsed TLP to the ingress aggregation module; The ingress aggregation module is connected to the PCIe ingress port and is used to filter and match multiple received TLPs according to preset aggregation conditions to determine whether they meet the aggregation requirements. If the aggregation conditions are met, multiple TLPs are aggregated to generate a CTLP; If the aggregation conditions are not met, the TLP will be sent to the cross switch as an independent message; The cross switch is connected to the inlet aggregation module and the outlet deaggregation module respectively, and is used to receive CTLP or independent TLP sent by the inlet aggregation module, and forward them to the corresponding outlet deaggregation module according to the destination port of the message; The exit de-aggregation module is connected to the cross switch and the PCIe exit port, and is used to receive the messages forwarded by the cross switch and determine whether they are CTLP or independent TLP. If it is a CTLP, then it is depolymerized and restored to multiple original TLPs; If it is a standalone TLP, it will be sent directly to the PCIe egress port; The PCIe export port is used to receive the original TLP or independent TLP sent by the export de-aggregation module and send it to the corresponding external device. The polymerization process includes: The headers of multiple TLPs are compressed into a single micro-piece. The lower two bits of the Type field indicate the number of aggregations. The payloads of multiple TLPs are concatenated sequentially to generate several payload micro-pieces. The header micro-pieces are combined with all payload micro-pieces to form a CTLP. If a single TLP or multiple TLPs do not meet the aggregation conditions, they are not aggregated and are transmitted directly as independent messages.

2. The PCIe packet aggregation and switching device according to claim 1, characterized in that: The inlet aggregation module includes an aggregation judgment unit and a CTLP construction unit; The aggregation judgment unit is used to filter and match multiple TLPs to determine whether they meet the aggregation requirements; The CTLP building unit is used to aggregate multiple TLPs that meet the aggregation conditions to generate a CTLP.

3. A PCIe packet aggregation and switching device according to claim 1, characterized in that: The export depolymerization module includes a message recognition unit and a TLP restoration unit; The message identification unit is used to determine whether the received message is a CTLP or an independent TLP; The TLP reduction unit is used to depolymerize CTLP and restore it to multiple original TLPs.

4. A PCIe packet aggregation and switching device according to claim 1, characterized in that: It also includes a storage module for temporarily storing the TLP parsed from the PCIe ingress port, the CTLP generated by the ingress aggregation module, and the original TLP restored by the egress deaggregation module.

5. A PCIe packet aggregation and switching method, characterized in that, Implemented using a PCIe packet aggregation switching device as described in any one of claims 1 to 4, comprising the following steps: Step S1, Message Reception The PCIe switching chip's PCIe ingress port receives multiple TLPs sent by external devices, parses each TLP, and extracts the TLP's message parameters. Step S2, Aggregation Judgment The ingress aggregation module filters and matches multiple received TLPs according to preset aggregation conditions to determine whether they meet the aggregation requirements. Step S3, Message Aggregation If multiple TLPs meet the aggregation conditions, the entry aggregation module performs aggregation processing to generate a single CTLP. Step S4, In-chip switching The crossbar switch of the PCIe switching chip forwards CTLPs or non-aggregated TLPs to the corresponding PCIe egress ports according to their destination ports. Step S5, message de-aggregation The export de-aggregation module receives messages forwarded by the cross switch and determines whether they are CTLP or independent TLP; If it is a standalone TLP, it will be forwarded directly to the corresponding external device; If it is a CTLP, then it is depolymerized and restored to multiple original TLPs; Step S6: Message Sending The PCIe egress port will send the deaggregated original TLPs, or the unaggregated independent TLPs, to the corresponding external devices to complete the aggregation and exchange of PCIe messages. In step S3, the polymerization process includes: The headers of multiple TLPs are compressed into a single micro-piece. The lower two bits of the Type field indicate the number of aggregations. The payloads of multiple TLPs are concatenated sequentially to generate several payload micro-pieces. The header micro-pieces are combined with all payload micro-pieces to form a CTLP. If a single TLP or multiple TLPs do not meet the aggregation conditions, they are not aggregated and are transmitted directly as independent messages.

6. The PCIe packet aggregation and switching method according to claim 5, characterized in that: In step S1, the message parameters include destination port, payload size, message type, Fmt field, Type field, and message timing information.

7. A PCIe packet aggregation and switching method according to claim 5, characterized in that: In step S2, the polymerization conditions include: Multiple TLPs are transmitted in close proximity without bubbles, with the same destination port, the same payload size, the same message type / Fmt field / Type field, and the number of aggregations ≤ a preset threshold.

8. The PCIe packet aggregation and switching method according to claim 5, characterized in that: In step S3, when the headers of multiple TLPs are compressed into a single micro-piece, the key information of each TLP header is retained, and redundant and duplicate information is removed.

9. A PCIe packet aggregation and switching method according to claim 5, characterized in that: In step S5, the depolymerization process of the outlet depolymerization module and the polymerization process of the inlet polymerization module are designed symmetrically, and the TLP after depolymerization is completely consistent with the original TLP before polymerization.

Images