Method and system for automatically generating programmable optical delay line network architecture based on graph search and combinatorial optimization

Abstract

The invention discloses a programmable optical delay line network architecture automatic generation method based on graph search and combinatorial optimization, and aims to solve the problem that the design of an optical delay line network architecture depends on artificial experience and is high in redundancy. According to the method, four types of nodes A, B, C and D and a graph model of a strict connection rule are established, topology is coded by an adjacent matrix, acyclic paths from Ai to Di of all channels are searched by utilizing DFS, and resource conflict-free cross-channel combination is carried out; under multiple checks of node degree, 0 delay path, target matching de-duplication and B node advanced constraint, a coverage target delay combination number is defined as fitness, and maximum combination coverage is realized by adopting a GA evolutionary algorithm. According to the method, the automatic search and optimization of the network topology can be realized under the given resource limitation, the delay combination coverage capability and the design efficiency are remarkably improved, and the method is suitable for the scenes of optical communication, beam forming, programmable photon processing and the like.

Description

Technical Field

[0001] This invention relates to the fields of optical signal processing and photonic integration technology, and in particular to a method and system for automatically generating programmable optical delay line network architecture based on graph search and combinatorial optimization. Background Technology

[0002] With the development of optical communication and microwave photonics technologies, optical delay line networks play a crucial role in applications such as programmable delay, beamforming, and optical computing. However, when faced with the need for multi-channel, multi-target delay combinations, manually designing network topologies is not only inefficient and error-prone, but also makes it difficult to guarantee high coverage of the target delay combinations. Existing solutions mostly rely on empirically preset topologies and manual drawing, making it difficult to obtain near-optimal or optimal network structures under resource constraints.

[0003] In existing technologies, most solutions employ predefined fixed topologies or rule-based heuristic layouts, lacking the ability to systematically optimize multi-channel joint delay combinations. Especially under resource-constrained conditions (such as limited optical switch ports and delay lines), manual design often struggles to achieve high coverage of the target delay combination table while meeting physical constraints. Furthermore, traditional methods typically ignore resource conflicts between cross-channel paths (such as shared delay lines or connection edges), resulting in a significantly lower actual achievable delay combinations than theoretically expected, thus limiting network performance.

[0004] Therefore, there is an urgent need for a method that can automatically and efficiently generate optical delay line network architectures that meet the delay requirements of multiple targets. This method should be able to achieve full or near-full coverage of target delay combinations under given resource and topology constraints, and have good scalability and optimization capabilities to meet the increasingly complex photonic signal processing application requirements. Summary of the Invention

[0005] The purpose of this invention is to overcome the problems of strong reliance on human experience, low design efficiency, and insufficient combinatorial coverage in the prior art. It provides a method and system for automatically generating programmable optical delay line network architecture based on graph search and combinatorial optimization. Under the condition of given node resources and target delay combination, it can automatically generate a network topology that meets the constraints and has the best or near-optimal coverage.

[0006] The technical solution of the present invention is as follows: An automatic generation method for programmable optical delay line network architecture based on graph search and combinatorial optimization is characterized by the following steps: S1. Construct a network diagram model of optical delay lines with physical constraints, abstracting optical components into four types of functional nodes: input node A, optical switch node B, delay line node C, and output node D, and setting node connection rules according to actual physical implementation constraints: nodes A / C / D can only be connected to node B, and nodes B are allowed to be interconnected. S2. The network topology is encoded using an adjacency matrix. The upper triangular elements of the symmetric 0 / 1 adjacency matrix are sequentially expanded into chromosome strings and then expanded into chromosomes. An initial population is generated using a hybrid strategy that combines random generation and heuristic generation. S3. For each candidate network architecture, use depth-first search (DFS) to search all acyclic paths from each input node A to the corresponding output node D. Generate cross-channel candidate delay combinations through channel-by-channel iterative combination, and detect and avoid resource conflicts between different paths during the combination process. S4. Perform multiple validity checks on the candidate delay combinations generated in step S3, including the following sequential checks: - Node degree limit check: Verify that node degree A ≤ 1, node degree D ≤ 1, node degree C ≤ 2, and node degree B ≤ 4; - Zero-delay path check: Ensure that each channel has at least one A-B-D path that does not pass through any C nodes; - Target matching and deduplication: Map each candidate combination to an N-time delay vector, match it with the preset target time delay combination table validTable, and deduplicate it by vector; -B node advanced constraint check: In any combination, the number of different predecessor node types and successor node types connected to each node B does not exceed 2, and the total of the two does not exceed 4. If any one of the checks fails, the candidate combination is eliminated. S5. Based on the verification results of step S4, the number of target delay combinations covered is used as the fitness, and a genetic algorithm (GA) is used for iterative optimization until the termination condition is met and the optimal network topology is output, thereby maximizing the coverage of the target delay combination table.

[0007] Furthermore, the heuristic generation in step S2 includes: connecting each node A to a node B, selecting 1-2 nodes C for node B according to the delay value from smallest to largest, and then randomly connecting each node C to a node D.

[0008] Furthermore, the resource conflict detection in step S3 includes: during the combination generation process, if a newly added path shares the same side or the same C node with an existing path in the combination, the combination is discarded.

[0009] Furthermore, in the advanced constraint check of node B in step S4, the preceding nodes include nodes connected to node B from the direction of node A, and the succeeding nodes include nodes connected to node C or node D from node B.

[0010] Furthermore, the genetic algorithm in step S5 includes fitness-based tournament selection and elite retention, two-point crossover, probabilistic mutation, and a repair mechanism for violations of node degree constraints.

[0011] Furthermore, the repair mechanism refers to: decoding chromosomes that violate node degree constraints after crossover or mutation into adjacency matrices, identifying nodes with excessive degree and randomly removing some of their edges until all node degrees meet the constraints, and then re-encoding them into chromosomes to continue participating in the evolutionary process.

[0012] Furthermore, the termination condition in step S5 includes any of the following situations: Reach the preset maximum number of iterations; Find the individual that covers all M rows of delay combinations in the target combination table; This termination condition ensures that the algorithm outputs a feasible solution within a finite amount of time.

[0013] Second, the present invention also provides an automatic generation system for programmable optical delay line network architecture based on graph search and combinatorial optimization, characterized in that it includes: The graph modeling module is used to construct a graph model containing four types of nodes: A, B, C, and D, as well as connection rules. The encoding initialization module is used to encode the topology using an adjacency matrix and generate an initial population. The path combination module is used to perform path search and generate conflict-free combinations; The validation and evaluation module is used to perform multiple validity checks and fitness assessments; The optimization output module is used to perform genetic algorithm optimization and output the optimal topology.

[0014] Third, the present invention also provides a computer-readable storage medium having a computer program stored thereon, characterized in that the program, when executed by a processor, implements the steps of the method described above.

[0015] Compared with the prior art, the present invention has the following advantages: 1. By organically combining graph modeling, path search, combinatorial generation, and evolutionary optimization, end-to-end automatic generation of network topology from latency requirements is achieved, completely eliminating the reliance on human experience.

[0016] 2. This algorithm does not rely on human experience to set up and draw the network architecture. Instead, it intelligently finds the optimal network topology under given node resource conditions through automatic search and optimization. This greatly improves the efficiency and accuracy of network design.

[0017] 3. The algorithm cleverly utilizes the global search capability and heuristic search advantages of genetic algorithms (GA). Through hybrid initialization (heuristic and random), elite retention strategy, tournament selection, bi-point crossover, probabilistic mutation, and fast repair strategy, it achieves efficient and comprehensive solution space search.

[0018] 4. Using the target delay combination table (validTable) as the core evaluation criterion, the fitness function is used to explicitly measure the coverage of the network topology to the target combination. Throughout the iterative optimization process, the goal is continuously to "maximize coverage requirements," ensuring that the generated network architecture effectively meets the needs of practical applications. Attached Figure Description

[0019] Figure 1 This is a flowchart of the automatic generation method for programmable optical delay line network architecture based on graph search and combinatorial optimization according to the present invention.

[0020] Figure 2 The graph showing the running results of the method of this invention is: GA coverage progress curve (validTable coverage row count vs. iteration number).

[0021] Figure 3 This is a schematic diagram of the optical delay line network architecture automatically generated by the method of the present invention. The diagram shows a scheduling module 200 composed of an input node module 100 (A), an optical switch node (B), and a delay line node module (C), as well as an output node module 300 (D). The input module 100 flexibly schedules the optical delay line module 200 using an optical switch to transmit data to the output module 300. Nodes A, B, C, and D represent the input, optical switch, delay line, and output nodes, respectively. Each channel connects from node A through nodes B and C to the corresponding node D. Detailed Implementation

[0022] The following description, in conjunction with the accompanying drawings and specific examples, further illustrates the automatic generation method for programmable optical delay line network architecture based on graph search and combinatorial optimization according to the present invention.

[0023] An automatic generation method for programmable optical delay line network architecture based on graph search and combinatorial optimization includes the following steps: Step 1: Construct a graphical model of the optical delay line network. Abstract the optical physical components into mathematical representations, describing their actual physical behavior using mathematical language. In this graphical model: specific component types are represented by different numbered nodes, such as four types of nodes (A, B, C, D) representing input, 2x2 optical switches (two inputs, two outputs), fiber delay lines, and outputs, respectively. Edges describe the connection relationships between devices. It is stipulated that nodes A, C, and D can only connect to nodes B, while nodes B can connect to each other. This stipulation is based on actual physical implementation relationships: inputs, outputs, and fiber delay lines can only be directly connected to optical switches, while optical switches can connect to each other. The results of this step: first, "defining specifications"—clarifying the number of channels and their one-to-one correspondence with inputs / outputs, available delay lines and their values, and a target delay combination table; simultaneously, providing the connection limit for each type of node as a hard constraint threshold for subsequent screening. Any candidate network that exceeds the connection limit for any type of node will be directly eliminated and will not proceed to the next step. This yields a batch of feasible candidate network blueprints that meet the physical limits, laying the foundation for subsequent search and evaluation.

[0024] Step 2: Adjacency Matrix Encoding. The optical delay line network architecture is represented using an adjacency matrix, encoding possible node connections as chromosomes. Network nodes are divided into four categories: input nodes (A), optical switch nodes (B), delay line nodes (C), and output nodes (D). Each A node corresponds to an input channel, each D node corresponds to the output of that channel, each C node represents an optical delay line resource with a specific delay value, and B nodes act as intermediate switching nodes connecting nodes A, C, and D. The initial population's network architecture can be encoded using adjacency matrices randomly or heuristically. The result of this step is a large number of diverse candidate networks obtained at once. Subsequently, obviously unreasonable connections are automatically corrected to ensure all candidates remain within resource limits. This ultimately forms a substantial set of feasible blueprints with diverse structures that do not exceed limits, serving as input for subsequent path and combination calculations.

[0025] Step 3: Path Search and Combination Generation. Using a graph search algorithm (e.g., Depth-First Search (DFS), for each generated adjacency matrix (candidate solution), search for all possible paths from each input node A to the corresponding output node D. Then, combine the paths of each channel to generate delay combination schemes across multiple channels. During the combination process, ensure that the paths within each combination do not use the same optical delay lines or links to avoid resource conflicts. The results of this step are: a basket of candidate paths collected for each channel, including both "straight-through paths without delay lines" and paths "passing through some delay lines"; at the cross-channel level, multiple sets of candidate combinations are formed that "do not preempt the same connection / same delay resource". If a network blueprint contains channels with no straight-through paths that have "zero additional latency", the entire blueprint is deemed invalid and discarded. Each remaining combination clearly indicates which optical switches each channel passes through and which delay lines are used.

[0026] Step 4: Legality Verification and Fitness Evaluation. Each generated candidate architecture undergoes legality verification, including checks on node resource constraints (node ​​degree constraints), path uniqueness, and advanced constraints used by B nodes. A fitness function is defined to evaluate the extent to which the generated architecture covers the target latency combinations—that is, the degree to which the number of latency combinations implemented by the architecture matches the requirements in the preset target combination table. The fitness value is taken as the number of target combinations covered; the more coverage, the higher the fitness. The results of this step include: a "coverage score" (the number of rows in the target table hit) for each candidate network, and a "list of feasible combinations"—where each combination corresponds one-to-one with a row in the target table; it also provides a "latency and value vector" for each combination (e.g., for a combination hitting (0,1,2), it will clearly show one channel as 0, another as 1, and the third as 2).

[0027] Step 5: Evolutionary Iterative Optimization. A genetic algorithm is used to iteratively optimize the architecture. Each generation of the population is selected based on fitness, and a new architecture is generated through genetic operations (tournament selection of parents), ensuring that the new architecture meets resource constraints such as node degree. Each generation, the algorithm evaluates the coverage (fitness) of the current population architecture to the preset delay combination requirements, retaining superior individuals and continuously searching for better architectures until the termination condition is met (e.g., finding an architecture that covers all target combinations or reaching the maximum number of iterations). The results of this step include: a "coverage progress curve" that increases with the number of generations, clearly showing how the number of hit target rows increases with iteration; once a network that can simultaneously hit all rows of the target table appears, the system will clearly indicate the iteration generation in which it occurred. The final output includes: a blueprint of the network topology with the strongest coverage capability; all valid combinations supported by this blueprint and their corresponding channel delays and values. If the current search has not yet achieved full coverage, the current number of hit rows will be clearly stated, and it will be suggested to continue approaching a full-coverage solution by expanding the search scale or adjusting the initial structural preferences.

[0028] Example 1. Parameter Initialization: First, determine the network scale and target requirements. Taking a three-channel programmable optical delay line network as an example, i.e., the number of channels N=3, set the number of A nodes numA = N and the number of D nodes numD = N (each channel corresponds to a pair of A and D nodes). Set the number of B nodes numB and the number of C nodes numC according to actual needs. Simultaneously, pre-define a list of delay values ​​CValues ​​for each C node, and a target delay combination table validTable (size is M rows × N columns, the number of columns N equals the number of channels, each row is a set of delay combinations to be covered). Node resource constraints are as follows: each A node can connect to a maximum of 1 edge, each D node can connect to a maximum of 1 edge, each B node can connect to a maximum of 4 edges, and each C node can connect to a maximum of 2 edges. Nodes A, C, and D can only connect to B nodes, and B nodes can interconnect with each other. These constraints reflect the physical port limitations and resource capacity of various types of nodes in a real optical delay network.

[0029] 2. Population Initialization: The network topology is represented by an adjacency matrix, where a 1 indicates a connection between corresponding node pairs, and a 0 indicates no connection. The adjacency matrix is ​​a symmetric matrix (undirected graph). To apply the evolutionary algorithm, the adjacency matrix needs to be expanded and encoded into chromosomes, which are strings of 0s and 1s arranged in an upper triangular order. Several feasible adjacency matrix chromosomes can be randomly generated for the initial population. During random generation, it is necessary to ensure that the node degree constraint is not violated: one implementation is to randomly attempt to connect each node B to 1 to 4 other nodes (which could be nodes A, C, or D). Each time a random target node is selected, the following checks are made: (a) whether the current degree of the node B has not reached the upper limit of 4 and the degree of the target node has not exceeded the limit, and (b) whether the connection does not yet exist. If these conditions are met, the connection is added. If multiple attempts fail to find a suitable connection, the connection process for the node B is stopped. Similarly, each node C can be randomly connected to no more than 2 nodes, and each node A and D can be connected to no more than 1 node. Through the above process, a random topology that satisfies the constraints can be generated.

[0030] To improve the quality of the initial solution and accelerate convergence, this invention also employs a heuristic initialization method to generate a portion of the population: for example, each node A is randomly connected to a node B; then, in ascending order of delay values, 1-2 nodes C with shorter delays are selected and connected to each node B (while ensuring that the degree of node B does not exceed 4 and the degree of node C does not exceed 2); next, a node D is randomly selected and connected to each node C (ensuring that the degree of node C ≤ 2 and the degree of node D ≤ 1). This heuristic strategy makes the initial architecture tend to prioritize the use of shorter delay lines, which helps to meet the basic delay combination requirements. After generating the required number of initial architecture individuals using random or heuristic methods, the initial population of the evolutionary algorithm is obtained.

[0031] 3. Calculate the fitness of individuals in the population: (1) Path Search and Combination Generation: For each candidate architecture (adjacency matrix representation) in the population, it is necessary to evaluate the time-delay combinations that it can achieve. First, perform a path search from A to D for a given architecture. Within a single architecture, for the starting node A of each channel, use depth-first search (DFS) to traverse all possible paths to the corresponding ending node D. During the search, avoid repeatedly traversing the same edge to prevent path loops. Let the set of all paths found for each channel i be Pathsi.

[0032] Then, the paths of each channel are combined: one path is selected from each Pathsi to form a candidate delay combination scheme spanning N channels. An important constraint must be satisfied during combination: paths from different channels cannot share the same physical edge or delay line resource. That is, for any two channels, if their paths involve the same C node or the same connecting edge, these two paths cannot appear in the same combination simultaneously; otherwise, a "side conflict" of resource contention will occur. This invention ensures this constraint by iteratively constructing combinations and detecting conflicts channel by channel: initially, each path of the first channel is treated as an initial combination, then paths from the second channel are added sequentially, paired with existing combinations. If the newly added path does not share edges with existing paths in the combination, a new combination is formed; if a sharing conflict exists, the combination is discarded. This process iterates until all paths of N channels are considered, ultimately generating a candidate combination list. During this process, duplicate combination schemes are automatically filtered out (e.g., combinations with the same path set due to different order of addition are retained only once).

[0033] (2) Legality verification: Each generated channel path combination must undergo multi-level legality verification to ensure that the architecture meets all resource and functional constraints: (3) Node degree constraint check: First, check whether the adjacency matrix of the architecture satisfies the constraint conditions for the number of connections of various types of nodes (A≤1, B≤4, C≤2, D≤1). If a candidate architecture violates these conditions, it is considered infeasible and will not be considered in subsequent evaluations (fitness is considered invalid).

[0034] (4) Basic Functionality Check: Each channel must have at least one path that enables zero-latency transmission (i.e., without passing through any C-delay lines). This usually means that a path exists that connects A directly to D via node B, so that the channel can be transmitted without introducing additional latency. If there is no path with a total latency of 0 in the path set of a certain channel, the architecture cannot provide a zero-latency option for that channel and is considered incomplete, therefore the architecture is deemed invalid.

[0035] (5) Target matching and deduplication: Each candidate combination scheme is mapped to a delay value vector (length N, corresponding to the sum of the cumulative delay values ​​of each channel path). Then, it is filtered against the preset target delay combination table validTable: only when the delay vector of the combination completely matches a target row in validTable is the combination considered to meet the requirements and retained; unmatched combinations are meaningless and are eliminated. Furthermore, to avoid duplicate combinations, the matched combinations are deduplicated according to their delay value vectors (if multiple combinations achieve the same set of delay values, only one example is retained).

[0036] (6) Advanced Constraints on B Nodes: For each retained combination scheme, further examine the usage of B nodes in its network topology. For each B node in the combination, count the size of the different sets of preceding and succeeding nodes connected to the B node in the combination. For example, if a B node appears on a path of channel 1 in the combination, and the nodes connected to both sides of the B node are A1 and Cx respectively, then the preceding node includes A1, and the succeeding node includes Cx; if the B node in the same combination also appears on a path of channel 2, and the nodes connected to both sides are A2 and Cy, then the set of preceding nodes is A1, A2, and the set of succeeding nodes is Cx, Cy. This invention stipulates that the number of different preceding nodes and different succeeding nodes connected to each B node in any combination scheme shall not exceed 2, and the total number of types of preceding and succeeding nodes shall not exceed 4 (corresponding to the upper limit of 4 physical degree of B node optical switching). If it is found that a B node in a combination is connected to more than 2 different A nodes or more than 2 different C / D nodes (or the total exceeds 4), then the combination is determined not to meet the advanced constraint conditions and is eliminated. After the above multiple screening processes, the remaining combinations represent the effective delay combinations that this architecture can actually achieve. The specific algorithm execution results are shown in Table 1 below:

[0037] Table 1: Three-channel path combination and value mapping With the three-channel configuration of parameters A=D=3, B=9, and C=4, the algorithm generates four combinations, which correspond to the four rows of validTable: [0 0 0], [0 1 2], [0 2 4], and [0 3 6]. Each combination consists of three paths from A to D (corresponding to the three channels). The node numbering rule is as follows: 1–3 are A, 4–12 are B, 13–16 are C (weights are 1, 2, 3, 3 respectively), and 17–19 are D. The path value is equal to the sum of the weights of all C nodes on the path. Therefore, the path that does not pass through C has a value of 0. For example, the first path [1,4,17] goes from A1 through B4 to D17, which does not contain C, so it takes the value 0. The value vector of each combination can be obtained by analogy for the other paths.

[0038] (7) Fitness Function Definition: This invention uses the number of target delay combinations that the architecture can cover as the fitness evaluation index. Specifically, for a candidate network architecture, its fitness value is defined as the size of the above-mentioned effective delay combination set, that is, the number of delay combinations that the architecture can achieve and that meet the validTable requirements. If the architecture can cover all M sets of target combinations, the fitness reaches the maximum value M; if it can only cover a part of them or even cannot cover any target combinations, the fitness decreases accordingly. Through such a fitness function, the algorithm clearly defines the optimization direction as covering as many target delay combinations as possible. Figure 2 The corresponding coverage progress curve is shown, with the number of covered rows increasing in a stepwise manner from 1→2→3, and jumping to 4 in the 130th generation.

[0039] 4. Evolutionary Algorithm Iterative Optimization: A Genetic Algorithm (GA) is used to perform an evolutionary search on the architecture encoding. The main process is as follows: (1) Evaluate the initial population: Use the population generated in step 2 as the initial solution set, including several randomly generated individuals and high-quality individuals generated heuristically. Set parameters such as population size and maximum number of iterations for the genetic algorithm. For each individual (network architecture chromosome) in the current population, calculate its fitness value (the number of target combinations covered). Record the best individual in the current population and its fitness value.

[0040] (2) Selecting a superior adjacency matrix: A tournament selection method is used to select some superior individuals from the current population as parents to generate the next generation. Preferably, an elite retention strategy is introduced, directly copying one or more architecture individuals with the highest current fitness to the next generation to ensure that excellent solutions are not lost.

[0041] (3) Crossover: Perform a two-point crossover genetic operation on the selected parent individuals. That is, randomly select two crossover points and exchange some gene segments of the corresponding chromosomes, that is, perform partial row and column exchanges on the adjacency matrix, thereby generating new offspring chromosomes. The crossover operation can promote the diversity of solutions and explore new topological structures.

[0042] (5) Mutation: Apply mutation operation to the offspring individuals after crossover. Scan the chromosome bit by bit with a certain mutation probability Pm, compare with the random number, and if mutation is triggered, the gene at that position is reversed (i.e., 01 mutation, adding the connection if there was no connection before, and breaking the connection if there was a connection before). Mutation operation helps to introduce new topological structure components and prevents the population from converging to a local optimum too early.

[0043] (6) Repair: Crossover and mutation may produce invalid chromosomes that do not meet the node degree constraints. To address this, this invention introduces an adjacency matrix repair algorithm: the mutated chromosome is converted back to an adjacency matrix representation, and the degree of each type of node is checked for exceeding the limit. If the degree of a node exceeds the allowed upper limit, some edges of that node are randomly removed until the constraints are met. After repair, the matrix is ​​encoded back into the chromosome. After the repair process, it can be ensured that the new individual meets the basic topological constraints, improving the efficiency of evolutionary search in the feasible solution space.

[0044] (7) Iteration and Termination: The old population is replaced by a new population generated by the above selection, crossover, mutation, and repair operations, and the next generation of iterations begins. In each generation, the fitness of the population is re-evaluated and the current best solution is updated. The algorithm terminates when one of the following conditions is met: the preset maximum number of generations is reached, or an individual with fitness equal to M (i.e., covering all target combinations) is found. Upon termination, the recorded optimal network architecture is output as the result.

[0045] 5. Results and Examples: The algorithm output includes the adjacency matrix of the optimal network architecture and metrics such as the delay combination coverage achieved by this architecture. For example, in an example implementation, the number of channels N is set to 3, each delay line C node has a different delay value, and the target combination table validTable contains several sets of delay combination requirements for 3 channels. After the above evolutionary optimization, the algorithm finally obtains a network architecture scheme. The number of coverage combinations of this scheme is denoted as Z. Figure 2 This paper illustrates a schematic diagram of an architecture automatically generated by the algorithm of this invention, in which each channel Ai is connected to the corresponding Di via several B and C nodes. This architecture achieves high coverage of the target latency combination through the sharing and optimized configuration of latency resources.

Claims

1. A method for automatically generating programmable optical delay line network architecture based on graph search and combinatorial optimization, characterized in that, Includes the following steps: S1. Construct a network diagram model of optical delay lines with physical constraints, abstracting optical components into four types of functional nodes: input node A, optical switch node B, delay line node C, and output node D, and setting node connection rules according to actual physical implementation constraints: nodes A / C / D can only be connected to node B, and nodes B are allowed to be interconnected. S2. The network topology is encoded using an adjacency matrix. The upper triangular elements of the symmetric 0 / 1 adjacency matrix are sequentially expanded into chromosome strings and then expanded into chromosomes. An initial population is generated using a hybrid strategy that combines random generation and heuristic generation. S3. For each candidate network architecture, use depth-first search (DFS) to search all acyclic paths from each input node A to the corresponding output node D. Generate cross-channel candidate delay combinations through channel-by-channel iterative combination, and detect and avoid resource conflicts between different paths during the combination process. S4. Perform multiple validity checks on the candidate delay combinations generated in step S3, including the following sequential checks: - Node degree limit check: Verify that node degree A ≤ 1, node degree D ≤ 1, node degree C ≤ 2, and node degree B ≤ 4; - Zero-delay path check: Ensure that each channel has at least one A-B-D path that does not pass through any C nodes; - Target matching and deduplication: Map each candidate combination to an N-time delay vector, match it with the preset target time delay combination table validTable, and deduplicate it by vector; -B node advanced constraint check: In any combination, the number of different predecessor node types and successor node types connected to each node B does not exceed 2, and the total of the two does not exceed 4. If any one of the checks fails, the candidate combination is eliminated. S5. Based on the verification results of step S4, the number of covered target delay combinations is used as the fitness, and a genetic algorithm (GA) is used for iterative optimization until the termination condition is met and the optimal network topology is output, thereby maximizing the coverage of the target delay combination table.

2. The method for automatically generating programmable optical delay line network architecture based on graph search and combinatorial optimization according to claim 1, characterized in that, The heuristic generation in step S2 includes: connecting each node A to a node B, selecting 1-2 nodes C for node B according to the delay value from smallest to largest, and then randomly connecting each node C to a node D.

3. The method for automatically generating programmable optical delay line network architecture based on graph search and combinatorial optimization according to claim 1, characterized in that, The resource conflict detection in step S3 includes: during the combination generation process, if a newly added path shares the same side or the same C node with an existing path in the combination, the combination is discarded.

4. The method for automatically generating programmable optical delay line network architecture based on graph search and combinatorial optimization according to claim 1, characterized in that, In the advanced constraint check of node B in step S4, the preceding nodes include nodes connected to node B from the direction of node A, and the succeeding nodes include nodes connected to node C or node D from node B.

5. The method for automatically generating programmable optical delay line network architecture based on graph search and combinatorial optimization according to claim 1, characterized in that, The genetic algorithm in step S5 includes fitness-based tournament selection and elite retention, two-point crossover, probabilistic mutation, and a repair mechanism for violations of node degree constraints.

6. The method for automatically generating programmable optical delay line network architecture based on graph search and combinatorial optimization according to claim 5, characterized in that, The repair mechanism refers to: decoding chromosomes that violate node degree constraints after crossover or mutation into an adjacency matrix, identifying nodes with excessive degree and randomly removing some of their edges until all node degrees meet the constraints, and then re-encoding them into chromosomes to continue participating in the evolutionary process.

7. The method for automatically generating programmable optical delay line network architecture based on graph search and combinatorial optimization according to claim 1, characterized in that, The termination condition in step S5 includes any of the following situations: Reach the preset maximum number of iterations; Find the individual that covers all M rows of delay combinations in the target combination table; This termination condition ensures that the algorithm outputs a feasible solution within a finite amount of time.

8. A system for automatically generating programmable optical delay line network architectures based on graph search and combinatorial optimization, characterized in that, include: The graph modeling module is used to construct a graph model containing four types of nodes: A, B, C, and D, as well as connection rules. The encoding initialization module is used to encode the topology using an adjacency matrix and generate an initial population. The path combination module is used to perform path search and generate conflict-free combinations; The validation and evaluation module is used to perform multiple validity checks and fitness assessments; The optimization output module is used to perform genetic algorithm optimization and output the optimal topology.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the method as described in any one of claims 1-7.

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