Low on-resistance LDMOS (Laterally Diffused Metal Oxide Semiconductor) structure and preparation method thereof

Abstract

The invention discloses a low-on-resistance LDMOS structure and a preparation method thereof. According to the structure, a composite structure is arranged on an N-type drift region and comprises a thick oxide layer, a floating field plate is arranged on the upper surface of the thick oxide layer, an N-type heavily-doped doping region is arranged on the lower surface of the thick oxide layer, and the N-type heavily-doped doping region and the floating field plate are arranged in a staggered mode. A segmented P-type top layer is arranged below the N-type heavily-doped doping region, and the N-type heavily-doped doping region and the segmented P-type top layer are arranged in a staggered manner; the thick oxide layer is arranged on the surface of the N-type drift region, and the N-type heavily-doped doping region and the segmented P-type top layer are located in the N-type drift region. The preparation method comprises the following steps: injecting P-type impurities into the surface of the N-type drift region to form a segmented P-type top layer; forming thick oxide layers on the surfaces of the P-type body region and the N-type drift region; forming a grid electrode, a floating field plate and a side wall on the surfaces of the P-type body region and the thick oxide layer; and doping the P-type body region and the N-type drift region to form an N-type heavily doped region, a body electrode, a source electrode and a drain electrode.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device design and manufacturing, specifically a low on-resistance LDMOS structure and its fabrication method. Background Technology

[0002] Compared to traditional CMOS devices, LDMOS (Lateral Double-Diffused Metal Oxide Semiconductor) offers advantages such as higher reliability and faster switching speeds. Furthermore, because its source, drain, and gate are all located on the device surface, it is easy to integrate and is therefore widely used in power integrated circuits, becoming a core device in BCD (Bipolar-CMOS-DMOS) process technology.

[0003] With the continuous development of power semiconductor technology, LDMOS structures based on shallow trench isolation (STI) have been proposed and widely used. The introduction of STI technology further enhances the breakdown voltage capability of LDMOS, while significantly reducing device area and improving integration density. By introducing the STI structure into the drift region, the effective surface path from the body region to the drain can be extended without increasing the vertical dimension, thereby improving the electric field distribution and increasing the breakdown voltage.

[0004] However, the traditional STI structure also has certain limitations: First, compared with traditional LDMOS, the current path is longer in the on state, and current congestion is prone to occur at the corner of the STI, resulting in an increase in the specific on-resistance (Ron,sp); Second, the edge of the STI is usually deep, which restricts the performance optimization of high-voltage devices to achieve low specific on-resistance; Third, the current concentration at the bottom edge of the STI will cause a local high electric field, which will lead to increased collision ionization and hot carrier effects, affecting the long-term reliability and stability of the device.

[0005] In summary, suppressing the current path congestion and local high electric field effects caused by the STI structure has become a key issue for the further development of LDMOS technology. Summary of the Invention

[0006] To address the aforementioned problems, this invention proposes a low on-resistance LDMOS structure and its fabrication method. By introducing a composite structure consisting of a thick oxide layer, a floating field plate, a segmented P-type top layer, and a heavily doped N-type doped region formed by source / drain ion implantation, the electric field distribution is effectively modulated and the conduction current path is shortened, thereby significantly reducing the specific on-resistance and improving the electrical performance and reliability of the device. The fabrication process of this invention is consistent with the conventional BCD process.

[0007] The technical solution of the present invention is as follows: The present invention discloses a low on-resistance LDMOS structure, comprising a P-type substrate, a P-type body region and an N-type drift region on the P-type substrate, a body electrode and a source electrode on the P-type body region, a drain electrode on the N-type drift region, a gate electrode on the P-type body region and the N-type drift region, and a composite structure on the N-type drift region. The composite structure includes a thick oxide layer, a plurality of floating field plates on the upper surface of the thick oxide layer, a heavily doped N-type region on the lower surface of the thick oxide layer with the heavily doped N-type region and the floating field plates staggered, and a segmented P-type top layer below the heavily doped N-type region with the heavily doped N-type region and the segmented P-type top layer staggered. The thick oxide layer is disposed on the surface of the N-type drift region, and the heavily doped N-type region and the segmented P-type top layer are located within the N-type drift region.

[0008] The present invention discloses a method for fabricating a low on-resistance LDMOS, comprising the following steps: Determine the substrate; P-type impurities are implanted into the substrate surface to form a P-type buried layer; then, a P-type body region and an N-type drift region are formed on the substrate surface, respectively. P-type impurities are injected into the surface of the N-type drift region to form a segmented P-type top layer; A thick oxide layer is formed on the surface of the P-type body region and the N-type drift region; A gate, a floating field plate, and a sidewall are formed in the P-type body region and on the surface of the thick oxide layer. The P-type body region and the N-type drift region are doped to form an N-type heavily doped region, a body electrode, a source electrode, and a drain electrode.

[0009] Compared with the prior art, the present invention has the following beneficial effects: This invention employs a unique composite structure that effectively modulates the electric field distribution and shortens the conduction current path, thereby significantly reducing specific on-resistance and improving the electrical performance and reliability of the device. This composite structure, through the synergistic effect of a thick oxide layer, a floating field plate, a segmented P-type top layer, and a heavily doped N-type region between the field plates, achieves a substantial reduction in specific on-resistance while maintaining the breakdown voltage. The floating field plate, covering the thick oxide layer, is not directly connected to any electrode and is in a potential-floating state, effectively modulating the electric field distribution on the drift region surface and improving electric field concentration. Source / drain ion implantation into the heavily doped N-type region at the gap of the floating field plate increases the surface doping concentration of the drift region, thereby effectively reducing the parasitic resistance of the N-type drift region surface, providing a low-resistance path for the conduction current, and significantly reducing the specific on-resistance of the device. In addition, the segmented P-type top layer located in the gap below the heavily doped N-type region employs a segmented implantation method to reduce the concentration of the P-type top layer. This prevents incomplete depletion and premature breakdown due to excessive concentration. Together with the heavily doped N-type region, it optimizes the electric field distribution in the drift region, aiding in depletion and simultaneously increasing the surface doping concentration, thus reducing on-resistance. The surface mechanism (floating field plate and thick oxide layer) and the bulk mechanism (segmented P-type top layer and heavily doped N-type region) of this composite structure are coupled, uniformly distributing the electric field peaks originally concentrated in a localized area of ​​the device across the entire drift region. This achieves a higher doping concentration on the drift region surface while maintaining breakdown voltage, enabling a low-resistance current path during conduction and ultimately significantly reducing the specific on-resistance of the device.

[0010] The process flow of this invention is completely consistent with the conventional BCD process. Without introducing any additional process steps, it integrates a thick oxide layer, a floating field plate, a segmented P-type top layer, and an N-type heavily doped region in the field plate gap. The thick oxide layer is embedded in the surface of the drift region, and the floating field plate covers the thick oxide layer, extending laterally along the surface of the drift region. During source / drain ion implantation, the floating field plate itself acts as part of a mask, blocking doping below its covered area, ensuring that impurity ions are implanted only into the exposed portion of the field plate gap. This process requires no additional process steps; by controlling the implantation energy and dose, an N-type heavily doped region with a specific junction depth and doping concentration distribution can be formed in the field plate gap. The segmented P-type top layer is located in the gap below this N-type heavily doped region. Attached Figure Description

[0011] Figure 1 The figure shown is a cross-sectional view of an LDMOS device with a composite structure of a thick oxide layer, a floating field plate, a segmented P-type top layer, and an N-type heavily doped doped region formed by ion implantation in the field plate gap, as proposed in this invention.

[0012] Figure 2 The diagram shown is a schematic of the LDMOS structure with the composite structure proposed in this invention.

[0013] Figure 3 The diagram shown is a schematic of a traditional LDMOS structure.

[0014] Figure 4 This is a process flow diagram of the structure described in this invention.

[0015] Figure 5 The diagram shows a flowchart of the method for preparing the composite structure of a thick oxide layer, a floating field plate, a segmented P-type top layer, and an N-type heavily doped doped region in the field plate gap formed by ion implantation.

[0016] Figure 6 The diagram shown is a schematic diagram of the conductive path of the structure described in this invention.

[0017] Figure 7 The diagram shows the current path of two traditional structures.

[0018] Figure 8 The figure shows a comparison of the transfer characteristic curves of the traditional STI structure and the LDMOS of this invention.

[0019] Figure 9 The figure shows a comparison of the surface electric field distribution curves of the traditional STI structure and the LDMOS of this invention. Detailed Implementation

[0020] The present invention will now be described in detail with reference to the accompanying drawings. Example 1

[0021] A low on-resistance LDMOS structure includes a P-type substrate 1, a P-type body region 2 and an N-type drift region 3 on the P-type substrate 1, a body electrode 6 and a source electrode 7 on the P-type body region 2, a drain electrode 8 on the N-type drift region 3, a gate electrode 9 on the P-type body region 2 and the N-type drift region 3, and a composite structure on the N-type drift region 3. The composite structure includes a thick oxide layer 4, a plurality of floating field plates 10 on the upper surface of the thick oxide layer 4, a heavily doped N-type region 5 on the lower surface of the thick oxide layer 4, the heavily doped N-type region 5 being staggered with the floating field plates 10, and a segmented P-type top layer 12 below the heavily doped N-type region 5, the heavily doped N-type region 5 being staggered with the segmented P-type top layer 12. For example: Figure 1 The positional relationship between the floating field plate 10 and the heavily doped N-type region 5 is a staggered arrangement, as is the positional relationship between the heavily doped N-type region 5 and the segmented P-type top layer 12. The thick oxide layer 4 is disposed on the surface of the N-type drift region 3, and the heavily doped N-type region 5 and the segmented P-type top layer 12 are located within the N-type drift region 3. The multiple floating field plates refer to at least two floating field plates, and the floating field plate 10 is in an electrically floating state and is not directly connected to any electrode. In this embodiment, The floating field plates 10 are evenly distributed, with a length of 0.3~0.6μm and a spacing of 0.2~0.5μm between them. The floating field plates 10 are made of polycrystalline silicon. Sidewalls 11 are provided on both sides of the floating field plates 10, and the sidewalls 11 are made of silicon nitride.

[0022] The N-type heavily doped region 5 is phosphorus doped with a doping concentration of 1e15~2e15cm. -3 .

[0023] The length of the segmented P-type top layer 12 is 0.6~0.8 μm, and the spacing between adjacent segments of the P-type top layer 12 is 0.3~0.6 μm. The segmented P-type top layer 12 is boron doped with a doping concentration of 2.7e12~3e12cm. -3 .

[0024] The bottom apex angle of the thick oxide layer 4 is 30 degrees, and the thickness of the thick oxide layer 4 is 0.08~0.15μm.

[0025] The body electrode 6 is located outside the source electrode 7, and the two are short-circuited; the gate electrode 9 is made of polycrystalline silicon. Example 2

[0026] A method for fabricating a low on-resistance LDMOS includes the following steps: Substrate 1 is defined with the following crystal orientation: <100> The orientation is P-type, and the resistivity is 10 Ω·cm. Boron was implanted onto the surface of the substrate 1 at a dose of 1e13 cm⁻¹. -2 The injection energy was 50 keV to form a P-type buried layer 13; the injection dose was changed to 6e13 cm -2 Boron was implanted onto the surface of substrate 1 at an implantation energy of 180 keV to form a P-type body region 2; then phosphorus was implanted onto the surface of substrate 1 at an implantation dose of 4.9e12 cm⁻¹. -2 An energy of 200 keV is injected to form an N-type drift region 3; Boron was implanted into the surface of the N-type drift region 3 at a dose of 5e12 cm⁻¹. -2 An energy of 100keV is injected to form a segmented P-type top layer 12; A thick oxide layer 4 is formed on the surface of the P-type body region 2 and the N-type drift region 3, and the thickness of the thick oxide layer 4 is 0.12 μm. A gate 9, a floating field plate 10, and a sidewall 11 are formed on the surface of the P-type body region 2 and the thick oxide layer 4, wherein the gate 9 and the floating field plate 10 are both made of polysilicon, and the sidewall 11 is made of silicon nitride. The P-type body region 2 and the N-type drift region 3 are doped to form an N-type heavily doped region 5, a body electrode 6, a source electrode 7, and a drain electrode 8.

[0027] The invention will now be further described with reference to the accompanying drawings.

[0028] Working principle of the invention: Figure 1 This is a cross-sectional view of the LDMOS device with a composite structure of a thick oxide layer, a floating field plate, a segmented P-type top layer, and an N-type heavily doped doped region formed by ion implantation in the field plate gap, as proposed in this invention. Figure 2 This is a schematic diagram of the composite LDMOS structure proposed in this invention. Compared to the traditional STI structure LDMOS, this invention introduces a composite structure of a thick oxide layer and a floating field plate above the drift region. The thick oxide layer is embedded in the surface of the drift region, and the floating field plate covers the thick oxide layer and extends laterally along the surface of the drift region. An N-type heavily doped region is formed in the gap between the floating field plates through source / drain ion implantation. This N-type heavily doped region effectively reduces the parasitic resistance from the edge of the field plate to the drain by increasing the doping concentration on the surface of the drift region, providing a low-resistance path for the conduction current, thereby significantly reducing the specific on-resistance of the device. The floating field plate in this structure is not directly connected to any electrode and is in a floating potential state. In addition, the segmented P-type top layer located in the gap below the N-type heavily doped region can optimize the electric field distribution of the drift region and assist in the depletion of the drift region. Figure 3 The diagram shown is a schematic of a traditional LDMOS structure. Figure 4 This is a process flow diagram of the structure described in this invention. The process flow is completely consistent with the conventional BCD process, and it achieves the integration of a thick oxide layer, a floating field plate, a segmented P-type top layer, and a heavily doped N-type doped region between the field plates without introducing any additional process steps. Figure 5 A flowchart illustrating the fabrication method of the composite structure of a thick oxide layer, a floating field plate, a segmented P-type top layer, and an N-type heavily doped region in the field plate gap formed by ion implantation is presented. As shown in the figure, during the implantation process, the floating field plate itself acts as part of a mask, blocking the doping below its covered area, thus allowing impurity ions to be implanted only into the exposed portion of the field plate gap. By controlling the implantation energy and dose, an N-type heavily doped region with a specific junction depth and doping concentration distribution can be formed in this area, and this process requires no additional photolithography step. Figure 6 This is a schematic diagram of the conductive path of the structure described in this invention, compared with the conductive path of a traditional STI structure (e.g., Figure 7 Compared to (b), it significantly shortens the current path, greatly reduces the power loss of the same current, and alleviates the current congestion effect at the STI corner. Figure 7 The diagram shows the current path of two traditional structures.

[0029] The influence of the structure of the present invention on the electrical characteristics of LDMOS is explained below with reference to the accompanying drawings. Figure 8Furthermore, a comparison of the transfer characteristic curves (Vds=0.1V, Vgs=5V) for the two structures is presented. Simulation results show that, under the same gate voltage conditions, the on-current of the structure proposed in this invention is increased by 50% compared to the traditional structure, which intuitively verifies its reduction in specific on-resistance. Figure 9 The simulation results of the electric field distribution of the conventional structure and the present invention at Vgs=5V are presented. As can be seen from the figure, the peak electric field in the drift region below the field plate of the present invention is significantly reduced, and the high electric field region is more dispersed, effectively suppressing the phenomenon of local electric field concentration.

Claims

1. A low on-resistance LDMOS structure, comprising a P-type substrate (1), a P-type body region (2) and an N-type drift region (3) disposed on the P-type substrate (1), a body electrode (6) and a source electrode (7) disposed on the P-type body region (2), a drain electrode (8) disposed on the N-type drift region (3), and a gate electrode (9) disposed on the P-type body region (2) and the N-type drift region (3), characterized in that, A composite structure is provided on the N-type drift region (3). The composite structure includes a thick oxide layer (4). Multiple floating field plates (10) are provided on the upper surface of the thick oxide layer (4). An N-type heavily doped region (5) is provided on the lower surface of the thick oxide layer (4) and the N-type heavily doped region (5) and the floating field plates (10) are staggered. A segmented P-type top layer (12) is provided below the N-type heavily doped region (5) and the N-type heavily doped region (5) and the segmented P-type top layer (12) are staggered. The thick oxide layer (4) is provided on the surface of the N-type drift region (3). The N-type heavily doped region (5) and the segmented P-type top layer (12) are located in the N-type drift region (3).

2. The low on-resistance LDMOS structure according to claim 1, characterized in that, Side walls (11) are provided on both sides of the floating field plate (10).

3. The low on-resistance LDMOS structure according to claim 1 or 2, characterized in that, The N-type heavily doped region (5) is doped with phosphorus, with a doping concentration of 1e15~2e15cm. -3 .

4. The low on-resistance LDMOS structure according to claim 1 or 2, characterized in that, The segmented P-type top layer (12) is boron doped with a doping concentration of 2.7e12~3e12cm. -3 .

5. The low on-resistance LDMOS structure according to claim 1, characterized in that, The floating field plates (10) are evenly distributed.

6. The low on-resistance LDMOS structure according to claim 5, characterized in that, The length of the floating field plate (10) is 0.3~0.6μm, and the spacing between the floating field plates (10) is 0.2~0.5μm.

7. The low on-resistance LDMOS structure according to claim 1, characterized in that, The length of the segmented P-type top layer (12) is 0.6~0.8μm, and the interval between adjacent segmented P-type top layers (12) is 0.3~0.6μm.

8. A method for fabricating a low on-resistance LDMOS, characterized in that, Includes the following steps: Determine the substrate (1); P-type impurities are implanted into the surface of the substrate (1) to form a P-type buried layer (13); then a P-type body region (2) and an N-type drift region (3) are formed on the surface of the substrate (1). P-type impurities are injected into the surface of the N-type drift region (3) to form a segmented P-type top layer (12). A thick oxide layer (4) is formed on the surface of the P-type body region (2) and the N-type drift region (3); A gate (9), a floating field plate (10), and a sidewall (11) are formed on the surface of the P-type body region (2) and the thick oxide layer (4). The P-type body region (2) and the N-type drift region (3) are doped to form an N-type heavily doped region (5), a body electrode (6), a source electrode (7), and a drain electrode (8).

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