An operand prefetch method, system, apparatus, device, and storage medium

Abstract

The application discloses an operand prefetch method, system, device, equipment and storage medium. The method is applied to an operand prefetch system, and comprises an instruction emission queue, a cache unit, a register stack, an instruction scheduling device and an execution unit. The cache unit corresponds to one or more instruction emission queues. The method comprises the following steps: the cache unit scans instructions in the corresponding one or more instruction emission queues to determine a prefetch instruction; the instruction emission queue sends a prefetch request of the prefetch instruction to the cache unit; the cache unit reads an operand and a corresponding physical register tag from the register stack based on the prefetch request, and stores the read operand and the corresponding physical register tag in the cache unit; and the cache unit broadcasts the physical register tag to the corresponding one or more instruction emission queues. The read port conflict is significantly reduced, and the effective instruction emission bandwidth is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an operand prefetching system, method, apparatus, device and storage medium. Background Technology

[0002] In existing technologies, the instruction scheduler interacts directly with a shared, centralized register file to obtain operands. After decoding and renaming at the pipeline front end, micro-operations are dispatched to the instruction issue queue to wait. At this time, the instruction monitors whether its source operands are ready. When all source operands of an instruction are ready, it is "wake up." In each clock cycle, the instruction issue queue selects M instructions from all woken instructions according to priority for issuance. Traditional implementations initiate register file read requests at a fixed cycle and obtain operands in the fixed cycle + 1 cycle. In processor design, register file read ports are valuable resources, closely related to area and frequency; therefore, read port resources cannot be increased indefinitely, meaning they are finite. Of the M selected instructions for issuance, all instructions that need to read operands from the register file must compete for the limited N read ports of the general-purpose registers. Therefore, existing technologies have the following drawbacks: reduced actual issue bandwidth due to register file read port resource conflicts; and a lack of flexibility in critical resource access paths, leading to uneven resource utilization. Summary of the Invention

[0003] This invention provides an operand prefetching method, system, apparatus, device, and storage medium, which solves the problem of reduced instruction issuance bandwidth caused by register stack read port resource contention in the prior art by prefetching and caching operands.

[0004] In a first aspect, embodiments of the present invention provide an operand prefetching method, the method being applied to an operand prefetching system, the system comprising: an instruction issuance queue, a cache unit, a register file, an instruction scheduling device, and an execution unit; the cache unit corresponds to one or more of the instruction issuance queues, and the method comprising:

[0005] The cache unit scans one or more instructions in the corresponding instruction issuance queue to determine the prefetch instruction;

[0006] The instruction issuance queue sends the prefetch request of the prefetch instruction to the cache unit;

[0007] The cache unit reads operands and corresponding physical register tags from the register file based on the prefetch request, and stores the read operands and corresponding physical register tags in the cache unit;

[0008] The cache unit broadcasts the physical register tag to one or more corresponding instruction issue queues.

[0009] Secondly, embodiments of the present invention also provide an operand prefetching system, the system comprising: an instruction issuance queue, a cache unit, a register file, an instruction scheduling device, and an execution unit; the cache unit corresponds to one or more of the instruction issuance queues;

[0010] The instruction issuance queue is connected to the instruction scheduling device and the corresponding cache unit; the cache unit is connected to the instruction scheduling device and the register file; the instruction scheduling device is connected to the execution unit; and the execution unit is connected to the instruction scheduling device.

[0011] The system is used to execute the operand prefetching method described in the embodiments of the present invention.

[0012] Thirdly, embodiments of the present invention also provide an operand prefetching apparatus, the apparatus being disposed in an operand prefetching system, the system comprising: an instruction issuance queue, a cache unit, a register file, an instruction scheduling device, and an execution unit; the cache unit corresponding to one or more of the instruction issuance queues, and the apparatus comprising:

[0013] A prefetch instruction determination module is used by the cache unit to scan one or more instructions in the corresponding instruction issuance queue to determine the prefetch instruction;

[0014] A prefetch request sending module is used for the instruction issuance queue to send the prefetch request of the prefetch instruction to the cache unit;

[0015] An operand prefetch module is used by the cache unit to read operands and corresponding physical register tags from the register file based on the prefetch request, and to store the read operands and corresponding physical register tags in the cache unit;

[0016] The physical register tag broadcasting module is used by the cache unit to broadcast the physical register tag to one or more corresponding instruction issue queues.

[0017] Fourthly, embodiments of the present invention also provide an electronic device, the electronic device comprising:

[0018] At least one processor; and

[0019] A memory communicatively connected to the at least one processor; wherein,

[0020] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the operand prefetching method described in the embodiments of the present invention.

[0021] Fifthly, embodiments of the present invention also provide a computer-readable storage medium storing computer instructions that are used to cause a processor to execute the operand prefetching method described in the embodiments of the present invention.

[0022] This invention discloses an operand prefetching method, system, apparatus, device, and storage medium. The method is applied to an operand prefetching system, which includes: an instruction issuance queue, a cache unit, a register file, an instruction scheduling device, and an execution unit. The cache unit corresponds to one or more instruction issuance queues. The method includes: the cache unit scanning the instructions in the corresponding one or more instruction issuance queues to determine the prefetching instructions; the instruction issuance queue sending a prefetch request for the prefetch instruction to the cache unit; the cache unit reading the operand and its corresponding physical register tag from the register file based on the prefetch request, and storing the read operand and its corresponding physical register tag in the cache unit; and the cache unit broadcasting the physical register tag to the corresponding one or more instruction issuance queues. The operand prefetching method provided by this invention prefetches the operand corresponding to the instruction into the cache unit, allowing the instruction scheduling device to directly read the operand from the cache unit when receiving an instruction, without needing to read the operand from the register file through a read port, significantly reducing read port conflicts and improving the effective instruction issuance bandwidth. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of an operand prefetching system according to Embodiment 1 of the present invention;

[0024] Figure 2 This is a flowchart of an operand prefetching method according to Embodiment 2 of the present invention;

[0025] Figure 3 This is a schematic diagram of an operand prefetching device according to Embodiment 3 of the present invention;

[0026] Figure 4 This is a schematic diagram of the structure of an electronic device according to Embodiment 4 of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] It is understood that before using the technical solutions disclosed in the various embodiments of this disclosure, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this disclosure in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained.

[0030] In existing technologies, all instructions that need to fetch operands from the general-purpose register file must compete for a limited number of N read ports within the same cycle selected by the issue selection logic. When the issue width M is greater than the number of read ports N, if more than N of the selected instructions need to read a port, port conflicts will inevitably occur, causing some instructions to fail to be issued and to be replayed. This results in idle slots in the pipeline, reducing the actual instruction issue bandwidth achieved.

[0031] The use of general-purpose register read ports is tightly coupled with instruction issuance behavior. Read ports can only be used during issue cycles; outside of issue cycles, or when the operands of the issued instructions all come from the forwarding network, the general-purpose register read port resources are completely idle. This "extremely busy during busy times, extremely idle during idle times" pattern leads to low utilization of hardware resources over time.

[0032] Example 1

[0033] Figure 1 This is a schematic diagram of an operand prefetching system provided in Embodiment 1 of the present invention, as shown below. Figure 1As shown, the system includes: an instruction issuance queue 10, a cache unit 20, a register file 30, an instruction scheduling device 40, and an execution unit 50.

[0034] Each cache unit 20 corresponds to one or more instruction issue queues 10. That is, the cache unit 20 is privately paired with one or more instruction issue queues 10.

[0035] Specifically, the instruction issuance queue 10 is connected to the instruction scheduling device 40 and the corresponding cache unit 20; the cache unit 20 is connected to the instruction scheduling device 40 and the register file 30; the instruction scheduling device 40 is connected to the execution unit 50; and the execution unit 50 is connected to the instruction scheduling device 40. Optionally, such as... Figure 1 As shown, the system also includes an arbitration unit 60.

[0036] The instruction issue queue 10 is used to cache instructions to be executed; the cache unit 20 is used to prefetch operands from the register file 30 and cache them; the register file 30 is used to store the operands required by the instruction; the instruction scheduling device 40 is used to retrieve operands from the cache unit 20, the network, or the register file 30 based on the issued instruction, and send the instruction and operands to the execution unit 50 for execution. The execution unit 50 sends the generated operands to the register file 30 to be used as source operands for subsequent instructions. The arbitration unit 60 is used to determine which prefetch request to allocate an idle read port when multiple prefetch requests are received.

[0037] In this embodiment, the idle read port period of the register file refers to the period during which the read port of the register file is idle and can be used for operand prefetching if the instruction to be issued in this period does not need to access the register file and can be obtained through the forwarding network.

[0038] Specifically, the detailed process of operand prefetching performed by the operand prefetching system in this embodiment is described in the following embodiments, and will not be elaborated here.

[0039] The operand prefetching system provided in this embodiment includes: an instruction issue queue, a cache unit, a register file, an instruction scheduler, and an execution unit. The cache unit corresponds to one or more instruction issue queues. Each instruction issue queue is connected to both the instruction scheduler and its corresponding cache unit. The cache unit is connected to both the instruction scheduler and the register file. The instruction scheduler is connected to the execution unit. The execution unit is connected to the instruction scheduler. The system is used to execute the operand prefetching method of this embodiment. By prefetching from the register file through the cache unit, instructions do not need to be fetched from the register file during issuance, which reduces the bandwidth pressure of accessing the register file during issuance, increases issuance bandwidth, and increases instruction parallelism.

[0040] Example 2

[0041] Figure 2 This is a flowchart of an operand prefetching method provided in Embodiment 2 of the present invention. The method is applied to an operand prefetching system, which includes: an instruction issuance queue, a cache unit, a register file, an instruction scheduling device, and an execution unit; the cache unit corresponds to one or more instruction issuance queues. Figure 1 As shown, the method includes the following steps:

[0042] S210, the cache unit scans the instructions in one or more corresponding instruction issue queues to determine the prefetch instruction.

[0043] In this context, prefetching instructions can be understood as instructions that prefetch operands. The cache unit scans its corresponding one or more instruction issue queues either every clock cycle or based on certain rules. The correspondence between a cache unit and one or more instruction issue queues can be understood as a one-to-one or one-to-many relationship. That is, one or more instruction issue queues are privately paired with one cache unit.

[0044] Optionally, the cache unit may scan the instructions in one or more corresponding instruction issuance queues in the following ways: when the number of operand-ready instructions in one or more corresponding instruction issuance queues scanned by the cache unit exceeds a first set threshold, the cache unit scans the instructions in one or more corresponding instruction issuance queues; or, when the number of repeated prefetches of prefetch instructions in one or more instruction issuance queues exceeds a second set threshold, the scanning frequency is increased; and the instructions in one or more corresponding instruction issuance queues are scanned based on the increased scanning frequency.

[0045] Operand readiness can be understood as the data or objects required by the instruction being ready. The first and second threshold settings can be preset and are not limited here. The number of times a prefetch instruction is repeated can be understood as the sum of the number of times all prefetch instructions are repeated over a period of time.

[0046] In this embodiment, when the number of ready instructions in one or more instruction issuance queues scanned by the cache unit exceeds a first set threshold, the cache unit scans the instructions in one or more instruction issuance queues. This avoids frequent scanning and scanning failures due to unread instructions, thus avoiding the situation where prefetched instructions are not obtained and avoiding the waste of computing resources.

[0047] In this embodiment, when the number of repeated prefetches of prefetch instructions in one or more instruction issuance queues exceeds a second set threshold, it indicates that the probability of the corresponding cache unit being allocated to the read port is low. Here, it is necessary to increase the scanning frequency to increase the probability of the corresponding cache unit being allocated to the read port, and further improve the success rate of prefetching operands.

[0048] Specifically, the process of the cache unit scanning the instructions in one or more corresponding instruction issuance queues to determine the prefetch instructions can be as follows: selecting instructions that meet the set conditions from the instructions in one or more corresponding instruction issuance queues as candidate instructions; and determining the candidate instructions that have been stored in the cache queue for the longest time as the prefetch instruction.

[0049] The condition is that the operands required by the instruction are stored in the register file, meaning the operands needed by the instruction must be fetched from the register file. There can be one or more candidate instructions. The instruction with the longest cache queue storage time can be understood as the oldest instruction. Specifically, the cache unit scans the instructions in its corresponding instruction issue queue, extracts the instructions whose operands need to be fetched from the register file as candidate instructions, and finally determines the candidate instruction with the longest cache queue storage time as the prefetch instruction.

[0050] S220, the instruction issuance queue sends the prefetch request for the prefetch instruction to the buffer unit.

[0051] In this embodiment, after the prefetch instruction is determined, the instruction issuing unit generates a prefetch request based on the prefetch instruction and sends the prefetch request to the cache unit, so that the cache unit can obtain the operand corresponding to the prefetch instruction from the register file based on the prefetch request.

[0052] S230, the cache unit reads the operands and corresponding physical register tags from the register file based on the prefetch request, and stores the read operands and corresponding physical register tags in the cache unit.

[0053] The number of operand entries that the cache unit can store can be preset and is not limited here. The associativity of the cache units can be fully associative, direct mapping, or higher-path set-associative. In this embodiment, the cache unit sends a prefetch request to the register file, which obtains the operands and their corresponding physical register tags based on the prefetch request, and then sends the obtained operands and their corresponding physical register tags to the cache unit for storage.

[0054] Specifically, the cache unit can read operands and corresponding physical register tags from the register file based on a prefetch request in the following ways: the cache unit requests a read port from the register file based on the prefetch request and sends the prefetch request to the register file through the requested read port; the register file obtains the operands and corresponding physical register tags based on the prefetch request and sends the obtained operands and corresponding physical register tags to the cache unit through the read port.

[0055] The register file includes multiple read ports, and the cache unit needs to request an idle read port from the register file within the current clock cycle. Specifically, after the cache unit obtains a read port from the register file, it sends a prefetch request to the register file through the obtained read port. The register file obtains the operands and their corresponding physical register tags based on the prefetch request, and then sends the obtained operands and their corresponding physical register tags to the cache unit through the read port.

[0056] Optionally, the system also includes an arbitration unit; correspondingly, the cache unit may request a read port from the register file based on the prefetch request in the following way: the cache unit sends the prefetch request to the arbitration unit, and the arbitration unit allocates a read port to the cache unit based on the prefetch request.

[0057] Optionally, if the arbitration unit receives multiple prefetch requests, a read port is allocated based on the priority of the prefetch requests.

[0058] The priority of a prefetch request is determined by the length of time the corresponding prefetch instruction has been stored in the instruction issuance queue. Specifically, the longer the prefetch instruction has been stored in the instruction issuance queue, the higher its priority. That is, the arbitration unit allocates the read port to the cache unit corresponding to the prefetch instruction that has been stored in the instruction issuance queue for the longest time.

[0059] The cache prefetching operand scheme introduced in this invention fundamentally separates the "operand fetching" behavior from the critical "instruction issue" cycle. As described in the technical solution, during multiple waiting cycles before an instruction is officially issued, idle read ports in the system are proactively used to prefetch operands into cache units privately paired with the instruction issue queue. When these prefetched instructions are finally selected in the issue cycle, they can directly obtain data from the zero-conflict, low-latency cache units without participating in the competition for shared read ports. This directly reduces the number of instructions that need to access read ports during the critical issue cycle. Compared to the existing technology where M instructions compete for N ports, this invention may only require Mk instructions (k being the cache hit count) to compete for N ports, significantly reducing the probability of port conflicts. Ultimately, the number of instruction replays due to port conflicts is significantly reduced, and the processor's effective instruction issue bandwidth is effectively improved.

[0060] S240, the cache unit broadcasts the physical register tag to one or more corresponding instruction issue queues.

[0061] In this embodiment, the cache unit broadcasts the physical register tag to one or more corresponding instruction issue queues, so that the cache unit adjusts the information about the operand storage location in the corresponding instruction to "operands are stored in the cache unit", so that after the instruction is issued to the instruction scheduler, the instruction scheduler obtains the operand from the cache unit according to the information.

[0062] Optionally, the following steps are also included: the instruction issuance queue sends the prefetch instruction to the instruction scheduling device; the instruction scheduling device generates an operand read request for the prefetch instruction, reads the operand corresponding to the prefetch instruction from the cache unit based on the operand read request, and sends the operand and the prefetch instruction to the execution unit for execution.

[0063] In this embodiment, when a prefetch instruction meets the issuance conditions (operands are ready and have been stored in the instruction issuance queue for the longest time), the instruction issuance queue sends the prefetch instruction to the instruction scheduling device. Upon receiving the prefetch instruction, the instruction scheduling device generates an operand read request for the prefetch instruction, reads the operands corresponding to the prefetch instruction from the cache unit based on the operand read request, and finally sends the operands and the prefetch instruction to the execution unit for execution. The execution unit sends the generated operands to the register file as operands for subsequent instructions.

[0064] The cache unit prefetching operand scheme of this invention breaks the tight coupling between register read port usage and instruction issuance behavior. As described in the technical solution steps, it enables the system to proactively initiate operand prefetching in any cycle with an idle general-purpose register read port (even in cycles where no instruction needs to read general-purpose registers), preparing operands in advance for instructions that may be issued in the future. This mechanism achieves "peak shaving and valley filling" of general-purpose register read port resources. It distributes and evens out the bursty port access pressure that was originally concentrated in the issue cycle across multiple waiting cycles before instruction issuance, utilizing previously wasted idle time. This not only makes the overall utilization rate of general-purpose registers higher but also makes the system design more flexible. From another perspective, it allows designers to support a wider processor issue width by adding relatively low-cost cache units without increasing the number of expensive general-purpose register read ports, thereby achieving performance improvements at a higher cost-effectiveness ratio.

[0065] In this embodiment, the cache unit scans the instructions in one or more corresponding instruction issuance queues to determine the prefetch instructions. The instruction issuance queue sends a prefetch request for the prefetch instruction to the cache unit. Based on the prefetch request, the cache unit reads the operands and corresponding physical register tags from the register file and stores the read operands and corresponding physical register tags in the cache unit. The cache unit broadcasts the physical register tags to one or more corresponding instruction issuance queues. The operand prefetching method provided by this embodiment prefetches the operands corresponding to the instruction into the cache unit, enabling the instruction scheduling device to directly read the operands from the cache unit when receiving an instruction, without needing to read the operands from the register file through a read port. This significantly reduces read port conflicts and improves the effective instruction issuance bandwidth.

[0066] Example 3

[0067] Figure 3 This is a schematic diagram of an operand prefetching device according to Embodiment 3 of the present invention. The device is disposed in an operand prefetching system, which includes: an instruction issuance queue, a cache unit, a register file, an instruction scheduling device, and an execution unit; the cache unit corresponds to one or more of the instruction issuance queues, and the device includes:

[0068] The prefetch instruction determination module 310 is used by the cache unit to scan one or more instructions in the corresponding instruction issuance queue to determine the prefetch instruction;

[0069] The prefetch request sending module 320 is used to send the prefetch request of the prefetch instruction to the cache unit from the instruction sending queue;

[0070] The operand prefetch module 330 is used for the cache unit to read operands and corresponding physical register tags from the register file based on the prefetch request, and to store the read operands and corresponding physical register tags in the cache unit;

[0071] The physical register tag broadcasting module 340 is used by the cache unit to broadcast the physical register tag to one or more corresponding instruction issuance queues.

[0072] Optionally, the prefetch instruction determination module 310 is also used for:

[0073] Instructions that meet set conditions are selected from one or more corresponding instruction issue queues and used as candidate instructions; wherein, the set conditions are that the operands required by the instruction are stored in the register file;

[0074] The candidate instruction that has been stored in the cache queue for the longest time is determined as the prefetch instruction.

[0075] Optionally, the operand prefetch module 330 is also used for:

[0076] The cache unit requests a read port from the register file based on the prefetch request, and sends the prefetch request to the register file through the obtained read port; the register file obtains the operands and corresponding physical register tags based on the prefetch request, and sends the obtained operands and corresponding physical register tags to the cache unit through the read port.

[0077] Optionally, the operand prefetch module 330 is also used for:

[0078] The caching unit sends the prefetch request to the arbitration unit, and the arbitration unit allocates a read port to the caching unit based on the prefetch request.

[0079] Optionally, if the arbitration unit receives multiple prefetch requests, it allocates a read port based on the priority of the prefetch requests; wherein the priority of the prefetch request is determined by the duration for which the corresponding prefetch instruction is stored in the instruction issuance queue.

[0080] Optionally, the prefetch instruction determination module 310 is also used for:

[0081] When the number of ready instructions with operands in one or more corresponding instruction issuance queues scanned by the cache unit exceeds a first preset threshold, the cache unit scans the instructions in one or more corresponding instruction issuance queues; or...

[0082] If the number of repeated prefetches of prefetched instructions in one or more of the instruction issuance queues exceeds a second preset threshold, the scanning frequency is increased; and the instructions in one or more of the corresponding instruction issuance queues are scanned based on the increased scanning frequency.

[0083] Optionally, it may also include: an instruction execution module, used for:

[0084] The instruction issuance queue sends the prefetch instruction to the instruction scheduling device; the instruction scheduling device generates an operand read request for the prefetch instruction, reads the operand corresponding to the prefetch instruction from the cache unit based on the operand read request, and sends the operand and the prefetch instruction to the execution unit for execution.

[0085] The above-described apparatus can execute the methods provided in all the foregoing embodiments of the present invention, and has the corresponding functional modules and beneficial effects for executing the above methods. Technical details not described in detail in this embodiment can be found in the operand prefetching methods provided in all the foregoing embodiments of the present invention.

[0086] Example 4

[0087] Figure 4 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components, connections and relationships between components, and their functions shown herein are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0088] like Figure 4 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0089] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0090] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as operand prefetching methods.

[0091] In some embodiments, the operand prefetching method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the operand prefetching method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the operand prefetching method by any other suitable means (e.g., by means of firmware).

[0092] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0093] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0094] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0095] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0096] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0097] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0098] This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the operand prefetching method as provided in any embodiment of this application.

[0099] In implementing the computer program product, computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0100] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0101] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An operand prefetching method, characterized in that, The method is applied to an operand prefetching system, the system comprising: an instruction issuance queue, a cache unit, a register file, an instruction scheduling device, and an execution unit; the cache unit corresponds to one or more of the instruction issuance queues, and the method comprises: The cache unit scans one or more instructions in the corresponding instruction issuance queue to determine the prefetch instruction; The instruction issuance queue sends the prefetch request of the prefetch instruction to the cache unit; The cache unit reads operands and corresponding physical register tags from the register file based on the prefetch request, and stores the read operands and corresponding physical register tags in the cache unit; The cache unit broadcasts the physical register tag to one or more corresponding instruction issue queues; The cache unit scans one or more instructions in the corresponding instruction issuance queue to determine the prefetch instruction, including: Instructions that meet set conditions are selected from one or more corresponding instruction issue queues and used as candidate instructions; wherein, the set conditions are that the operands required by the instruction are stored in the register file; The candidate instruction that has been stored in the cache queue for the longest time is determined as the prefetch instruction.

2. The method according to claim 1, characterized in that, The cache unit reads operands and corresponding physical register tags from the register file based on the prefetch request, including: The cache unit requests a read port from the register file based on the prefetch request, and sends the prefetch request to the register file through the obtained read port; the register file obtains the operands and corresponding physical register tags based on the prefetch request, and sends the obtained operands and corresponding physical register tags to the cache unit through the read port.

3. The method according to claim 2, characterized in that, The system also includes an arbitration unit; the cache unit requests a read port from the register file based on the prefetch request, including: The caching unit sends the prefetch request to the arbitration unit, and the arbitration unit allocates a read port to the caching unit based on the prefetch request.

4. The method according to claim 3, characterized in that, If the arbitration unit receives multiple prefetch requests, it allocates a read port based on the priority of the prefetch requests; wherein the priority of the prefetch request is determined by the duration for which the corresponding prefetch instruction is stored in the instruction issuance queue.

5. The method according to claim 1, characterized in that, The cache unit scans one or more instructions in the corresponding instruction issuance queue, including: When the number of ready instructions with operands in one or more corresponding instruction issuance queues scanned by the cache unit exceeds a first preset threshold, the cache unit scans the instructions in one or more corresponding instruction issuance queues; or... If the number of repeated prefetches of prefetched instructions in one or more of the instruction issuance queues exceeds a second preset threshold, the scanning frequency is increased; and the instructions in one or more of the corresponding instruction issuance queues are scanned based on the increased scanning frequency.

6. The method according to claim 1, characterized in that, Also includes: The instruction issuance queue sends the prefetched instruction to the instruction scheduling device; The instruction scheduling device generates an operand read request for the prefetch instruction, reads the operand corresponding to the prefetch instruction from the cache unit based on the operand read request, and sends the operand and the prefetch instruction to the execution unit for execution.

7. An operand prefetching system, characterized in that, The system includes: an instruction issuance queue, a cache unit, a register file, an instruction scheduling device, and an execution unit; the cache unit corresponds to one or more of the instruction issuance queues. The instruction issuance queue is connected to the instruction scheduling device and the corresponding cache unit; the cache unit is connected to the instruction scheduling device and the register file; the instruction scheduling device is connected to the execution unit; and the execution unit is connected to the instruction scheduling device. The system is used to execute the operand prefetching method according to any one of claims 1-6.

8. An operand prefetching device, characterized in that, The device is configured in an operand prefetching system, which includes: an instruction issuance queue, a cache unit, a register file, an instruction scheduling device, and an execution unit; the cache unit corresponds to one or more of the instruction issuance queues, and the device includes: A prefetch instruction determination module is used by the cache unit to scan one or more instructions in the corresponding instruction issuance queue to determine the prefetch instruction; A prefetch request sending module is used for the instruction issuance queue to send the prefetch request of the prefetch instruction to the cache unit; An operand prefetch module is used by the cache unit to read operands and corresponding physical register tags from the register file based on the prefetch request, and to store the read operands and corresponding physical register tags in the cache unit; A physical register tag broadcasting module is used by the cache unit to broadcast the physical register tag to one or more corresponding instruction issue queues; The instruction prefetching determination module is further configured to: select instructions that meet set conditions from one or more corresponding instruction issue queues as candidate instructions; wherein the set conditions are that the operands required by the instruction are stored in the register file; The candidate instruction that has been stored in the cache queue for the longest time is determined as the prefetch instruction.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the operand prefetching method according to any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the operand prefetching method according to any one of claims 1-6.

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