Signal processing method and signal processing device

Abstract

The invention provides a signal processing method and a signal processing device. The signal processing method comprises the following steps: receiving and analyzing debugging data from at least one external computer through a unified data interface, and outputting a debugging instruction or capturing a network data signal to corresponding target equipment through a corresponding channel according to an analysis result; receiving heterogeneous signals from a plurality of different types of target devices, and performing preliminary conversion on at least part of the heterogeneous signals; adding channel identification information into the signal processed in the above step and performing protocol conversion to form an aggregated data stream; and outputting the aggregated data stream through the unified data interface. According to the method, multiple external target devices can be debugged at the same time, the debugging result can be output to the external computer through a unified data interface, the problems that in a traditional debugging scheme, tool switching is tedious, and the cooperation efficiency is low are solved, and the debugging efficiency and convenience of a complex system are remarkably improved.

Description

Technical Field

[0001] This application relates to, but is not limited to, integrated circuit technology, and specifically to a signal processing method and a signal processing device. Background Technology

[0002] In embedded system development, traditional debugging methods face significant challenges: to achieve collaborative debugging of heterogeneous hardware platforms, developers need to deploy multiple independent devices simultaneously—for System-on-a-Chip (SoC), a J-LinkPro emulator and a USB-to-UART tool are required to achieve JTAG boundary scan and serial communication; for microcontroller units (such as the Infineon TC397), the Aurix dedicated debugger must be used to execute SWD protocol communication; and for automotive Ethernet devices (such as the Marvell 88Q5152 switch), a physical network port must be connected to a PC for packet capture analysis. This distributed debugging architecture not only leads to tangled cables and redundant physical interfaces, but also forces developers to frequently switch between multiple independent tools, severely disrupting the continuity of analysis. Furthermore, the high cost of dedicated debugging equipment and platform compatibility limitations further exacerbate the reduction in development efficiency and resource consumption. Summary of the Invention

[0003] To address the shortcomings of the prior art, this application provides a signal processing method and signal processing apparatus that can improve debugging efficiency.

[0004] A signal processing method includes the following steps: S1, receiving and parsing debugging data from at least one external computer through a unified data interface, and outputting debugging commands or capturing network data signals to the corresponding target device through the corresponding channel based on the parsing results; S2, receiving heterogeneous signals from multiple different types of target devices, and performing preliminary conversion on at least some of the heterogeneous signals; S3, adding channel identification information and performing protocol conversion on the signal processed in step S2 to form an aggregated data stream; and S4, outputting the aggregated data stream through the unified data interface. During the formation of the aggregated data stream, the data stream is scheduled and bandwidth is allocated based on a preset priority rule corresponding to the channel identifier.

[0005] Preferably, in step S1, when outputting a debugging command to the corresponding target device, the debugging command is converted, including: performing level conversion processing on access protocol type debugging commands that do not meet the level requirements, and / or converting universal serial bus protocol type debugging commands into serial communication signals.

[0006] Preferably, in step S1, when outputting debugging instructions to the corresponding target device, the method further includes: routing the access protocol type debugging instructions to the corresponding target device.

[0007] Preferably, in step S2, the preliminary conversion of at least some heterogeneous signals includes: performing level conversion processing on access protocol signals that do not meet the level requirements, and / or converting serial communication signals into universal serial bus protocol signals, and converting network data signals into universal control bus signals; step S2 also includes selecting a unique path for transmission from the received access protocol signals.

[0008] Preferably, in step S3, the channel identification information includes channel ID, data length, and timestamp, which are added in the form of a data header.

[0009] Preferably, the target device includes an in-vehicle MCU, an in-vehicle SOC, and an in-vehicle Ethernet device. The scheduling and bandwidth allocation of debugging data and data streams based on the preset priority rules corresponding to the channel identifier includes: the priority of debugging data for the in-vehicle SOC is higher than the priority of debugging data for the in-vehicle MCU, and the priority of data streams from the in-vehicle Ethernet device is higher than the priority of data streams from the in-vehicle SOC and the in-vehicle MCU; relative to the bandwidth allocated to the data streams of the in-vehicle SOC and the in-vehicle MCU, the bandwidth allocated to the data streams of the in-vehicle Ethernet device is 1.8 to 2.2 times.

[0010] A signal processing apparatus includes: a unified data interface for connecting and communicating with at least one external computer; a signal interface module for connecting and communicating with multiple different types of target devices, and for performing preliminary conversion on at least a portion of the received signals; and a programmable logic chip for receiving and parsing debugging data from at least one external computer through the unified data interface, outputting debugging commands or capturing network data signals to corresponding target devices through corresponding channels of the signal interface module based on the parsing results, receiving heterogeneous signals from the multiple different types of target devices through the signal interface module, adding channel identification information and performing protocol conversion on the signals processed by the signal interface module to form an aggregated data stream, and outputting it through the unified data interface. During the formation of the aggregated data stream, the programmable logic chip is also used to schedule and allocate bandwidth for the data stream based on preset priority rules corresponding to the channel identifiers.

[0011] Preferably, the signal interface module includes: a level conversion circuit for level conversion of access protocol signals transmitted between the target device and the programmable logic chip; a serial port conversion circuit for receiving serial communication signals from the target device and converting them into USB protocol signals for output, or receiving USB protocol signals from the programmable logic chip and converting them into serial communication signals; a multiplexer for opening a communication channel between the debug access protocol interface of one of the different target devices and the programmable logic chip according to the control instructions of the programmable logic chip; and a first protocol conversion circuit and a second protocol conversion circuit for realizing signal conversion between network device management bus protocols.

[0012] Preferably, the target device includes an in-vehicle MCU, an in-vehicle SOC, and an in-vehicle Ethernet device; the programmable logic chip is configured to include a GPIO Bank, an SWD controller, a DMA controller, BANK A, and BANK B; the GPIO Bank is used to interact with the UART interface of the in-vehicle SOC and the in-vehicle MCU, as well as the JTAG interface of the in-vehicle SOC; the SWD controller is used to interact with the JTAG interface of the in-vehicle MCU; and the DMA controller is used to interact with the in-vehicle Ethernet device; BANK A serves as a channel between the GPIO Bank and the SWD controller and the unified data interface; BANK B serves as a channel between the DMA controller and the unified data interface; and the programmable logic chip is configured to implement the logic of the unified data interface controller.

[0013] Preferably, the programmable logic chip is configured to include a parsing module for parsing debugging data from an external computer, determining the target device, operation type, and specific content in the debugging data, and debugging the vehicle-mounted SOC, vehicle-mounted MCU, and / or vehicle-mounted Ethernet device in parallel or in time-sharing based on the parsing results.

[0014] This application effectively solves the inherent defects of traditional multi-device debugging through an integrated architecture and intelligent processing mechanism: it integrates scattered dedicated debugging tools into a single device, uses dynamic protocol adaptation technology to realize the automatic conversion and unified encapsulation of heterogeneous signals, eliminates the physical environment clutter caused by multiple cable connections, improves debugging efficiency, and simplifies the debugging process. Attached Figure Description

[0015] Figure 1 This is a schematic diagram illustrating the working principle of a signal processing method according to an embodiment of this application.

[0016] Figure 2 This is a schematic diagram of the system architecture of a signal processing device according to an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions will be clearly and completely described below in conjunction with the embodiments of this application. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0018] Example 1: A signal processing method, applied as per the instruction manual. Figure 2 The signal processing device shown is connected between the target device to be debugged and the computer. It is used to debug the target device (such as, but not limited to, System-on-a-Chip (SoC), Microcontroller (MCU), and Ethernet devices) based on debugging data from the computer. This involves exchanging various signals and data (for convenience, these various types of signals and data are collectively referred to as heterogeneous signals), parsing these heterogeneous signals, adding identification information, performing protocol conversion, data routing, logic control, and other processing. The signal processing device connects to the debugging ports of each target device and is connected to the computer through a unified data interface.

[0019] The target device is preferably, but not limited to, in-vehicle electronic equipment, such as, but not limited to, the SOC and MCU of an in-vehicle infotainment system, an assisted / autonomous driving domain controller, etc. Ethernet devices in the target device include, but are not limited to, in-vehicle Ethernet switches (ETH switches) and in-vehicle Ethernet physical interface transceivers (ETH PHYs). This signal processing device can connect to multiple computers simultaneously, each running different debugging programs to enable simultaneous debugging of various SOCs, MCUs, and Ethernet devices.

[0020] Debugging interfaces commonly used in automotive SoCs include serial communication interfaces (such as, but not limited to, UART interfaces) and access protocol interfaces (such as, but not limited to, JTAG interfaces). Debugging interfaces commonly used in automotive MCUs include serial communication interfaces (such as, but not limited to, UART, SPI, and I2C interfaces) and access protocol interfaces (such as, but not limited to, JTAG and DAP interfaces). Network data interfaces commonly used in ETH switches include SMI and T1 interfaces. ETH typically uses an SMI interface as its network data interface. Thus, heterogeneous signals can include access protocol signals (JTAG signals, DAP signals), serial communication signals (UART signals, SPI signals, I2C signals), and network data signals (SMI signals, T1 signals). The full names and Chinese names of the above protocols are listed below: UART, Universal Asynchronous Receiver / Transmitter; JTAG, Joint Test Action Group; SPI, Serial Peripheral Interface; I2C, Inter-Integrated Circuit; DAP, Directory Access Protocol; SMI, Serial Management Interface; T1, a digital transmission standard originating from North American telecommunications standards.

[0021] In this embodiment, the signal processing circuit mainly includes a signal interface module, a programmable logic chip, and a unified data interface. The programmable logic chip is preferably an FPGA (Field-Programmable Gate Array) chip. The unified data interface is preferably a multi-port USB hub, where one port connects to the FPGA chip, and the remaining ports can be used to connect to a computer. This allows for the debugging of multiple SOCs, MCUs, and Ethernet devices using two or more computers. The USB hub is preferably a USB 3.2 multi-port hub.

[0022] like Figure 1 As shown, the signal processing method mainly includes steps S1 to S4.

[0023] Step S1 involves receiving and parsing debugging data from at least one external computer via a unified data interface, and outputting debugging commands or capturing network data signals to the corresponding target device through the corresponding channel based on the parsing results. The debugging data includes access protocol debugging data, serial communication signal debugging data, and network data debugging data.

[0024] Step S2: Receive heterogeneous signals from multiple different types of target devices and perform preliminary conversion on at least some of the heterogeneous signals.

[0025] Step S3: After adding channel identification information and protocol conversion to the signal processed in step S2, an aggregated data stream is formed.

[0026] Step S4: Output the aggregated data stream through a unified data interface.

[0027] In step S1, when outputting debugging instructions to the corresponding target device, the debugging instructions are also converted, including: performing level conversion processing on access protocol type debugging instructions that do not meet the level requirements, and / or converting universal serial bus protocol type debugging instructions into serial communication signals.

[0028] Step S1 also includes routing the access protocol-type debug command to a corresponding SOC or MCU in the target device, that is, switching signals in the multiple access protocol-type debug commands. In this way, it is possible to debug only one SOC or MCU at the same time.

[0029] In step S2, the preliminary conversion of at least some heterogeneous signals includes: performing level conversion processing on access protocol signals that do not meet the level requirements, and / or converting serial communication signals into universal serial bus protocol signals, and converting network data signals into universal control bus signals.

[0030] Furthermore, step S2 also includes selecting a single output from the received access protocol signals, i.e., switching between multiple access protocol signals. This allows for debugging of only one SOC or MCU at a time.

[0031] More specifically, signal switching includes: after receiving debugging data from the computer, parsing the data to determine if the debugging instructions included in the debugging data are debugging instructions for one of the SOCs or MCUs, then routing the instructions to the corresponding SOC or MCU, and then receiving the debugging data fed back by the corresponding SOC or MCU.

[0032] The signal interface module of the signal processing device can realize the conversion in step S1 and the preliminary conversion in step S2. That is, the signal interface module is used to connect and communicate with various types of target devices and to perform preliminary conversion on at least a portion of the received signals. More specifically, it is used to receive heterogeneous signals from various types of target devices and perform preliminary conversion on at least a portion of the heterogeneous signals, or to send signals from the FPGA chip directly or after conversion to the corresponding SOC and / or MCU and / or Ethernet device. The signal interface module is also used to select a unique output to the FPGA from the received access protocol signals according to the instructions of the FPGA chip, or to select and output the corresponding debugging instructions to one of the SOCs or MCUs.

[0033] The signal interface module may include a level conversion circuit, a serial port adapter circuit, a multiplexer, multiple protocol conversion circuits, and an analog-to-digital conversion circuit. Figure 1 In the diagram, the number of each circuit in the signal interface module is one. Understandably, this number can be adjusted according to the number of target devices to be debugged as needed.

[0034] The signal level output by the JTAG interface of the automotive SOC is usually lower than the level range required by the FPGA chip. The level conversion circuit is used to receive the access protocol signal (JTAG signal) of the SOC, convert the access protocol signal to a level, and output a signal that conforms to the level standard of the FPGA chip (such as the CMOS standard signal), or convert the level of the JTAG-type debugging command from the FPGA chip to output a signal that conforms to the JTAG interface of the automotive SOC.

[0035] The serial port conversion circuit mainly includes a multi-serial-to-USB chip. Its multiple serial ports are respectively connected to the serial communication signal interface of the SOC and the serial communication signal interface of the MCU. Its USB output interface is connected to the FPGA chip. It is used to receive the serial communication signal of the SOC or the MCU and convert it into a USB protocol signal. For example, but not limited to, converting the serial communication signal (UART / SPI / I2C) output by the SOC or the MCU into a standard USB 2.0 protocol differential signal. It is also used to receive the USB protocol signal of the FPGA chip and convert it into a serial communication signal (UART / SPI / I2C) and output it to the serial communication signal interface of the corresponding target device.

[0036] Multiplexers are used to connect debug access protocol interfaces of different target devices to the FPGA under the control of the FPGA chip. For example, multiplexers can be used to dynamically select access protocol signals (JTAG) from or sent to the SOC and access protocol signals (DAP / JTAG) from or sent to the MCU under the control of the FPGA chip, and switch signal paths in real time to realize the switching of data paths.

[0037] The first and second protocol conversion circuits are connected at one end to the network data signal interface of the ETH Switch and the network data signal interface of the ETH PHY, respectively, and at the other end to an FPGA chip. They are used to convert signals between network device management bus protocols, such as, but not limited to, converting the network data signals (e.g., SMI or T1) of the ETH Switch and ETH PHY into general control bus signals (e.g., I2C signals or MII / RGMII / SGMII signals). In this embodiment, both the first and second protocol conversion circuits are SMI to I2C chips. The analog-to-digital converter is mainly used to convert the DS1 / T1 line signals (also called analog digital signals) output from the T1 port of the ETH Switch into signals that can be recognized and processed by the DMA module inside the FPGA chip; preferably, it is a PHY chip.

[0038] The signal interface module also processes signals from the FPGA chip, specifically by sending them directly (via multiplexer and serial port conversion circuit) or by converting them (level conversion circuit and / or serial port conversion circuit and / or first protocol conversion circuit and / or second protocol conversion circuit) to the corresponding SOC and / or MCU and / or Ethernet device.

[0039] The FPGA chip is used to receive and parse debugging data from at least one external computer through a unified data interface. Based on the parsing results, it outputs debugging commands or captures network data signals to the corresponding target device through the corresponding channel of the signal interface module. The signal interface module receives heterogeneous signals from various types of target devices, adds channel identification information and performs protocol conversion on the processed signals to form an aggregated data stream, which is then output through the unified data interface. In other words, the main steps of the signal processing method in this application are implemented by the FPGA chip.

[0040] To this end, the FPGA chip is configured to receive and parse debug data from at least one external computer, and based on the parsing results, output debug commands or capture network data signals to the corresponding target device through the corresponding channel of the signal interface module. The FPGA chip is also configured to parse signals directly transmitted through the signal interface module or after preliminary conversion, add channel identification information, and perform protocol conversion to form an aggregated data stream, which is then output through a unified data interface. The FPGA chip is further configured to switch between data from the MCU and SOC based on preset priority rules corresponding to the channel identification information. The FPGA chip is also configured to allocate bandwidth to different data streams within the aggregated data stream based on the channel identification information.

[0041] To achieve the above functions, the FPGA chip is configured to include at least a GPIO Bank (General Purpose Input / Output Pin Group), an SWD (Serial Wire Debug) controller, a DMA (Direct Memory Access) controller, memory cells BRAM1 and BRAM2, a parsing module, and BANK A and BANK B.

[0042] The GPIO Bank is used to interact with the UART interface of the SOC and MCU, as well as the JTAG interface of the SOC. The SWD controller is used to interact with the JTAG interface of the MCU. The DMA controller is used to interact with the automotive Ethernet device ETH Switch and ETH PHY. In this embodiment, the FPGA chip has a built-in USB IP core (such as Xilinx USB3.0 PHY), which can implement the logic of the USB 3.2 device controller and can directly establish a high-speed communication link with the computer through a unified data interface.

[0043] Debugging data from the computer is encapsulated in a unified data encapsulation protocol (e.g., but not limited to USB 3.2) as a debug instruction packet (i.e., debug data). This packet is output to the FPGA via a unified data interface and then reaches different parsing modules via BANK A or BANK B. The parsing module parses the debug instruction packet to determine the target device (vehicle SOC / vehicle MCU / vehicle Ethernet device), operation type (read / write / control), and specific content (such as memory address, register address, network data, etc.). Based on the parsing results, the vehicle SOC, vehicle MCU, and / or vehicle Ethernet device are debugged in parallel or in a time-sharing manner.

[0044] For example, an FPGA chip can simulate JTAG timings (TMS, TCK, TDI, TDO) via its GPIO Bank, outputting the signals to the SOC's JTAG interface via a multiplexer and level conversion circuit. This allows for direct low-level JTAG debugging, programming, and memory access of the automotive SOC. The FPGA chip can also simulate SWD timings via an SWD controller, outputting the signals to the MCU's JTAG interface via a multiplexer, enabling MCU debugging. Furthermore, the FPGA chip can forward character data between the computer and the SOC / MCU via its GPIO Bank and serial port adapter circuit, facilitating communication.

[0045] The FPGA chip can also configure port mirroring of the ETH Switch via the DMA controller, allowing the actual data from the vehicular network to be copied to the FPGA chip's BRAM2 memory unit via the first protocol conversion circuit, the second protocol conversion circuit, or the analog-to-digital conversion circuit of the signal processing device, and then output to the unified data interface via BANK B. The FPGA chip may also simulate the management interface of the ETH Switch and ETH PHY connected via the first protocol conversion circuit, the second protocol conversion circuit, or the analog-to-digital conversion circuit through the DMA controller, reading and writing their registers to perform link control, status monitoring, port mirroring configuration, etc.

[0046] To enable comprehensive Ethernet device debugging capabilities, the DMA controller can internally deploy Ethernet MAC logic, packet filters, protocol analyzers, and statistical counters. The results (or raw data) processed by the DMA controller can be output to a unified data interface via BANK B, and ultimately transmitted back to the computer at high speed for network analysis. The computer can also send test data packets to BANK B via the unified data interface. After being parsed by the parsing module, the DMA controller constructs and ultimately sends the data to the in-vehicle network equipment, enabling bus interference testing, fault injection, and simulation testing.

[0047] During high-volume data interactions (such as network packet capture and memory image download), the DMA controller uses the BRAM2 memory unit as a high-speed buffer to efficiently transfer data between the BANK B interface, the network interface (referring to the network interface on the FPGA side), and BRAM2. Reading output from BRAM2 requires meeting preset conditions. These conditions are: when the data in the corresponding buffer area within BRAM2 equals or exceeds a threshold (e.g., 50% of the buffer capacity), the DMA controller is triggered to read the data. The read data is encapsulated by the USB RNDIS engine within BANK B according to the USB RNDIS protocol and finally transmitted to the unified data interface. In this way, the ISO transmission mode of the unified data interface can be used to output to the computer, achieving high-speed data transmission.

[0048] To ensure stable operation of the equipment, an independent power supply is configured for the FPGA chip.

[0049] During the debugging process, the GPIO Bank, SWD controller, and DMA controller collect, convert, and encapsulate the generated debugging results (such as JTAG responses, serial port printouts, network statistics, memory data, etc.), and output them through BANKA and B via a unified data interface (such as USB 3.2). The computer can then further display and analyze these debugging results.

[0050] In this embodiment, data from the SOC, MCU, and Ethernet devices must be classified and tagged by the GPIO Bank, SWD controller, and DMA controller. Specifically, a multi-byte header is added to each data stream, including a channel identifier, data length, and timestamp. This allows the computer to easily identify the data source and classify and process debugging results from various channels. Channel identifiers include, for example, channel IDs such as 0x01=JTAG, 0x02=UART, 0x03=ETH packet capture, etc. When the same debugging interface is used, identification is achieved by adding the corresponding channel ID.

[0051] The preferred storage unit is Block Random Access Memory (BRAM). Storage unit BRAM1 buffers data streams from the SOC and MCU processed by the GPIO Bank and SWD controller, as well as debug data from the computer. Storage unit BRAM2 buffers data streams from Ethernet devices processed by the DMA controller, as well as debug data from the computer. This buffering process allows signals from different lines with varying rates and latency requirements to be stably stored in independent storage areas, providing a buffer for subsequent unified scheduling and transmission, and ensuring the continuity and overall stability of system processing.

[0052] Specifically, the FPGA chip can schedule and allocate bandwidth for cached debug data and data streams based on preset priority rules corresponding to the channel identifier. These preset priority rules include: debug data for the automotive SOC has a higher priority than debug data for the automotive MCU; data streams from automotive Ethernet devices have a higher priority than data streams from both the automotive SOC and the automotive MCU; and the bandwidth allocated to data streams from automotive Ethernet devices is 1.8 to 2.2 times that allocated to data streams from the automotive SOC / automotive MCU. For example, but not limited to, the allocation ratio can be 5:5:10 Gbps.

[0053] Specifically, the FPGA chip queries the preset priority rules based on the channel identifier in the data frame header to determine its priority, and strictly schedules data frames into the transmission queue in descending order of priority. For data streams with the same priority, the FPGA chip uses a polling mechanism to allocate transmission bandwidth. The FPGA chip's default route (through a multiplexer and serial port adapter circuit) is to the vehicle-mounted SOC. When the parsing module parses debugging instructions for the vehicle-mounted MCU, it switches the route to the vehicle-mounted MCU and enables the SWD controller. The transmission speed of BANK B is higher than that of BANK A, achieving high-speed data transmission of network data.

[0054] Thus, the signal processing apparatus and signal processing method of this application can achieve physical and protocol layer unification of the full-function debugging interface of the vehicle domain controller, integrating the following functions through a single unified data interface (e.g., USB 3.2): Heterogeneous chip debugging: covering the differentiated interface requirements of high-performance SOCs, high-security MCUs, Ethernet switches, and Ethernet PHYs.

[0055] Multi-protocol parallel support: Simultaneously handles protocols such as JTAG (SOC / MCU), UART, SPI, MDIO / SMI, and Ethernet packet capture, avoiding the cumbersome tool switching operations in traditional solutions.

[0056] Dynamic allocation of debugging resources: JTAG signal multiplexing and unified data interface bandwidth intelligent allocation are achieved through FPGA chips to ensure the priority of critical tasks (such as debugging of autonomous driving algorithms).

[0057] This significantly improves debugging efficiency. In a real-world debugging case, Orin-X (SOC device) kernel crash analysis and MCU register checks can be performed in a time-sharing manner, while Ethernet packet loss diagnosis can be performed simultaneously. Traditionally, switching between three tools takes 15 minutes, but this device can complete the process in 5 minutes with a single USB cable when using the USB 3.2 data interface.

[0058] The use of an independent power supply avoids level conflicts between the SOC and MCU, improving device reliability. Furthermore, the unified data interface supports hot-swapping, reducing the risk of unexpected interruptions during debugging.

[0059] Example 2: This embodiment provides a signal processing apparatus for implementing the signal processing method described in Embodiment 1. The specific structure and connection relationships of the signal processing apparatus have been described in detail in Embodiment 1, and will not be repeated here.

[0060] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0061] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0062] Although the description of this application has been given in conjunction with the specific embodiments described above, it will be apparent to those skilled in the art that many substitutions, modifications, and variations can be made based on the foregoing. Therefore, all such substitutions, modifications, and variations are included within the spirit and scope of the appended claims.

Claims

1. A signal processing method, characterized in that, Including the following steps: S1 receives and parses debugging data from at least one external computer through a unified data interface, and outputs debugging instructions or captures network data signals to the corresponding target device through the corresponding channel based on the parsing results. S2 receives heterogeneous signals from multiple different types of target devices and performs preliminary conversion on at least some of the heterogeneous signals; S3, After adding channel identification information and protocol conversion to the signal processed in step S2, an aggregated data stream is formed; as well as S4, output the aggregated data stream through the unified data interface; In the process of forming the aggregated data stream, the data stream is scheduled and bandwidth is allocated based on the preset priority rules corresponding to the channel identifier.

2. The signal processing method according to claim 1, characterized in that, In step S1, when outputting a debugging command to the corresponding target device, the debugging command is converted, including: performing level conversion processing on access protocol type debugging commands that do not meet the level requirements, and / or converting universal serial bus protocol type debugging commands into serial communication signals.

3. The signal processing method according to claim 2, characterized in that, In step S1, when outputting debugging instructions to the corresponding target device, the method further includes: routing the access protocol type debugging instructions to the corresponding target device.

4. The signal processing method according to claim 3, characterized in that, In step S2, the preliminary conversion of at least some heterogeneous signals includes: performing level conversion processing on access protocol signals that do not meet the level requirements, and / or converting serial communication signals into universal serial bus protocol signals, and converting network data signals into universal control bus signals; step S2 also includes selecting a unique path for transmission from the received access protocol signals.

5. The signal processing method according to claim 4, characterized in that, In step S3, the channel identification information, including channel ID, data length, and timestamp, is added in the form of a data header.

6. The signal processing method according to claim 5, characterized in that, The target devices include an in-vehicle MCU, an in-vehicle SOC, and an in-vehicle Ethernet device. The scheduling and bandwidth allocation of debug data and data streams based on preset priority rules corresponding to the channel identifier includes: Debug data for the vehicle SoC has a higher priority than debug data for the vehicle MCU, and data streams from vehicle Ethernet devices have a higher priority than data streams from both the vehicle SoC and the vehicle MCU. The bandwidth allocated to the data streams of in-vehicle SOCs and in-vehicle MCUs is 1.8 to 2.2 times that allocated to the data streams of in-vehicle Ethernet devices.

7. A signal processing apparatus, characterized in that, include: A unified data interface for connecting and communicating with at least one external computer; A signal interface module for connecting and communicating with various types of target devices, and for performing preliminary conversion on at least a portion of the received signal; as well as A programmable logic chip is used to receive and parse debugging data from at least one external computer through a unified data interface. Based on the parsing results, it outputs debugging instructions or captures network data signals to the corresponding target device through the corresponding channel of the signal interface module. It receives heterogeneous signals from various types of target devices through the signal interface module, adds channel identification information and protocol conversion to the signal after processing by the signal interface module to form an aggregated data stream, and outputs it through the unified data interface. In the process of forming the aggregated data stream, the programmable logic chip is also used to schedule and allocate bandwidth for the data stream based on a preset priority rule corresponding to the channel identifier.

8. The signal processing apparatus according to claim 7, characterized in that, The signal interface module includes: Level conversion circuits are used to convert the levels of access protocol signals transmitted between the target device and the programmable logic chip; A serial port adapter circuit is used to receive serial communication signals from the target device and convert them into USB protocol signals before outputting them, or to receive USB protocol signals from a programmable logic chip and convert them into serial communication signals. A multiplexer is used to establish a communication channel between a debug access protocol interface of a programmable logic chip and a programmable logic chip in different target devices, based on the control instructions of the programmable logic chip; and The first protocol conversion circuit and the second protocol conversion circuit are used to realize signal conversion between network device management bus protocols.

9. The signal processing apparatus according to claim 8, characterized in that, The target device includes an in-vehicle MCU, an in-vehicle SOC, and an in-vehicle Ethernet device; the programmable logic chip is configured to include a GPIO Bank, an SWD controller, a DMA controller, BANK A, and BANK B; the GPIO Bank is used to interact with the UART interface of the in-vehicle SOC and the in-vehicle MCU, as well as the JTAG interface of the in-vehicle SOC; the SWD controller is used to interact with the JTAG interface of the in-vehicle MCU; and the DMA controller is used to interact with the in-vehicle Ethernet device; BANK A serves as a channel between the GPIO Bank and the SWD controller and the unified data interface; BANK B serves as a channel between the DMA controller and the unified data interface; and the programmable logic chip is configured to implement the logic of the unified data interface controller.

10. The signal processing apparatus according to claim 9, characterized in that, The programmable logic chip is configured to include a parsing module for parsing debugging data from an external computer, determining the target device, operation type, and specific content in the debugging data, and debugging the vehicle-mounted SOC, vehicle-mounted MCU, and / or vehicle-mounted Ethernet device in parallel or in time-sharing based on the parsing results.

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