Signal transmission method, time schedule controller, display device and storage medium
By configuring dedicated skew correction parameters for each display driver chip, the timing matching of clock and data signals is corrected, solving the timing deviation problem in the mini-LVDS standard and realizing high-speed signal transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING ESWIN COMPUTING TECH CO LTD
- Filing Date
- 2026-03-20
- Publication Date
- 2026-04-24
AI Technical Summary
The setup/hold time limitations between the data and clock channels in the mini-LVDS standard affect the timing matching between the data and clock signals, making it impossible to meet high transmission rate requirements.
The timing controller configures dedicated skew correction parameters for each display driver chip to correct the transmission delay of clock and data signals, making their timing matched, and samples the data signal based on the timing-matched clock signal.
Ensuring timing matching of clock and data signals received by each display driver chip improves the reliability of signal sampling and supports the requirements of high transmission rates.
Smart Images
Figure CN121922086A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a signal transmission method, a timing controller, a display device, and a storage medium. Background Technology
[0002] With the development of display technology, various high-speed data transmission interfaces have emerged. Among them, the interface using the Miniature Low-Voltage Differential Signaling (mini-LVDS) standard has been widely used in various display devices due to its advantages such as low power consumption and no need to add clock recovery circuits. It is especially suitable for the miniaturization design requirements of display driver ICs (DDI) that serve as receivers (Rx).
[0003] Currently, the mini-LVDS standard typically employs a bus architecture. This means that multiple DDIs share the same set of data and clock channels, thereby minimizing the required hardware resources and improving circuit integration. This shared transmission method allows multiple DDIs to receive data and clock signals in a time-sharing or parallel manner on the same shared bus.
[0004] However, the mini-LVDS standard has limitations on the setup / hold time between the data and clock channels. This limitation affects the timing matching between the data and clock signals, posing a challenge to high transmission rates. Therefore, a reliable method for skew correction of the data / clock signals is urgently needed to support high transmission rate requirements. Summary of the Invention
[0005] A signal transmission method, timing controller, display device, and storage medium are provided, which can reliably correct the skew of data signals / clock signals to support high transmission rate requirements. The technical solution is as follows: On one hand, a signal transmission method is provided, applied to a timing controller, which is used to establish a connection with multiple display driver chips through a shared bus of shared data channel and clock channel; the method includes: Clock signals and data signals are transmitted to the plurality of display driver chips via the shared bus; Configure skew correction parameters for each of the plurality of display driver chips in a one-to-one manner; Specifically, for each of the display driver chips, the skew correction parameter is used to instruct the display driver chip to correct the transmission delay of at least one of the received clock signal and data signal, so that the timing of the clock signal and the data signal is matched, and the data signal is sampled based on the timing-matched clock signal.
[0006] Optionally, the clock signal includes a plurality of consecutive clock windows corresponding one-to-one with the plurality of display driver chips; the configuration of skew correction parameters corresponding one-to-one with each of the plurality of display driver chips includes: During the interval between two adjacent clock windows, a corresponding skew correction parameter is configured for the display driver chip corresponding to the next clock window adjacent to the interval, so that the display driver chip compensates for the transmission delay of the at least one signal based on the skew correction parameter within the corresponding clock window, and samples the data signal in response to the start transition edge of the clock signal.
[0007] Optionally, during the interval period, the potential of the clock signal remains at an invalid potential; Within the clock window, the potential of the clock signal periodically jumps between an active potential and an inactive potential.
[0008] Optionally, configuring skew correction parameters corresponding to each of the plurality of display driver chips includes: For each display driver chip, before the first clock signal arrives in the corresponding clock window, the potential of the clock signal is controlled to remain at an invalid potential. During the period of maintaining the invalid potential, the corresponding skew correction parameter is configured for the display driver chip, so that the display driver chip applies the configured skew correction parameter. After the display driver chip applies the configured skew correction parameter, the configured skew correction parameter is maintained until the last clock signal in the corresponding clock window ends.
[0009] Optionally, configuring skew correction parameters corresponding to each of the plurality of display driver chips includes: For each of the display driver chips, a corresponding skew correction parameter is configured for the display driver chip based on the transmission skew between the clock signal and the data signal sent to the display driver chip.
[0010] Optionally, the at least one signal is the clock signal.
[0011] Optionally, the timing controller is further configured to establish a connection with the plurality of display driver chips via a control bus; the method further includes: Control signals are sent to the plurality of display driver chips via the control bus; The control signal includes at least one of a polarity control signal and a timing control signal.
[0012] On the other hand, a timing controller is provided, which is used to establish a connection with multiple display driver chips through a shared bus of shared data channel and clock channel; the timing controller includes: The transmission module transmits clock signals and data signals to the plurality of display driver chips via the shared bus; The configuration module configures skew correction parameters for each of the plurality of display driver chips. Specifically, for each of the display driver chips, the skew correction parameter is used to instruct the display driver chip to correct the transmission delay of at least one of the received clock signal and data signal, so that the timing of the clock signal and the data signal is matched, and the data signal is sampled based on the timing-matched clock signal.
[0013] In another aspect, a display device is provided, the display device comprising: a display panel, a plurality of display driver chips, and a timing controller as described in the other aspect above.
[0014] In another aspect, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when executed by a computer, the computer program implements the signal transmission method as described in the preceding aspect.
[0015] In summary, the technical solution provided in this application can bring at least the following beneficial effects: A signal transmission method, a timing controller, a display device, and a storage medium are provided. In this method, the timing controller not only transmits clock and data signals to multiple display driver chips via a shared bus, but also configures specific skew correction parameters for each display driver chip. Therefore, each display driver chip can reliably compensate for the transmission delay of the received clock and / or data signals based on the corresponding skew correction parameters, ensuring that the timing of the clock and data signals received by each display driver chip is matched without any offset. This ensures good reliability of the sampling signals from each display driver chip, thus better supporting the requirements of high transmission rates. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a schematic flowchart of a signal transmission method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a display driving circuit provided in an embodiment of this application; Figure 3 This is a signal schematic diagram of a display driving circuit provided in an embodiment of this application; Figure 4 This is a timing diagram of a display driving circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a display driver chip provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a timing controller provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0019] As mentioned in the background, the commonly used standard in high-speed interface technology is the mini-LVDS standard. That is, in display driver circuits, the connection between the transmitter (Tx) and receiver (Rx) is often established using an interface based on the mini-LVDS standard. The transmitter (Tx) can be, for example, a timing controller (TCON), and the receiver (Rx) can be, for example, a display driver chip (DDI).
[0020] Because the timing controller TCON in the mini-LVDS standard can transmit clock signals to the display driver chip DDI via a dedicated clock channel and data signals to the display driver chip DDI via a dedicated data channel, there is no need to set up a clock recovery circuit on the display driver chip DDI side to recover the clock signal from the data signal, thus making it suitable for the miniaturization design of DDI. Furthermore, since mini-LVDS typically uses a bus architecture, where multiple display driver chips DDI share the same set of data and clock channels, and the connection length, material, impedance, etc., between different display driver chips DDI and the same timing controller TCON differ at the physical level, as do the wiring length and bending degree, the setup / hold time between the data and clock channels is constrained and limited. This causes a timing deviation between the data and clock signals transmitted to the display driver chip DDI, resulting in a significant difference in the arrival time of the data and clock signals at the display driver chip DDI.
[0021] Therefore, a method is urgently needed to correct the timing deviation between data signals and clock signals (also known as skew correction or skew compensation) to ensure high-speed data transmission. For example, in some embodiments, the timing controller TCON can uniformly configure a skew correction parameter for all display driver chips (DDIs) for global skew correction. However, since it is impossible to perform skew correction individually for each display driver chip (DDI), the skew correction effect is poor and still cannot meet the requirements of high-speed data transmission. In other embodiments, skew correction is also considered for a specific display driver chip (DDI). However, the remaining display driver chips (DDIs) cannot achieve skew correction, and the setup / hold time between the data channel and clock channel still cannot guarantee that it meets the requirements of high-speed data transmission.
[0022] To address the aforementioned technical challenges, this application provides a novel signal transmission method. This method performs independent skew correction for each display driver chip (DDI), ensuring consistent setup / hold times for each DDI and thus enabling faster data transmission to meet the demands of high-speed data transmission. Consequently, higher performance operation can be achieved in the display system without incurring additional costs or risks.
[0023] Figure 1 This is a schematic flowchart of a signal transmission method provided in an embodiment of this application. Combined with... Figure 2This method can be applied to a timing controller (TCON), which can establish connections with multiple display driver chips (DDIs) via a shared bus (BUS1) sharing data and clock channels. That is, as described above, the timing controller TCON and multiple display driver chips (DDIs) can establish connections via a bus architecture, eliminating the need for additional clock recovery circuits on the DDI side, thus making it suitable for miniaturized DDI designs. Optionally, the shared bus (BUS1) can be the mini-low-voltage differential bus (MLVDS) described above. Of course, it is not limited to this. Furthermore, combined with... Figure 1 As can be seen, the method includes: Step 101: Transmit clock signals and data signals to multiple display driver chips via a mini low-voltage differential bus.
[0024] Step 102: Configure skew correction parameters for each of the multiple display driver chips.
[0025] That is, combining Figure 1 and Figure 2 In this embodiment, the timing controller TCON can not only transmit clock signals (CLK) and data signals Data to multiple connected display driver chips (DDI) via the shared bus BUS1, but also configure special skew correction parameters S for each display driver chip (DDI) individually and specifically.
[0026] Specifically, for each display driver chip DDI, the skew correction parameter S is used to instruct the display driver chip DDI to correct the transmission delay of at least one of the clock signal CLK and the data signal Data, so that the timing of the clock signal CLK and the data signal Data is matched, and the data signal Data is sampled based on the timing-matched clock signal CLK.
[0027] Optionally, the skew correction parameter S can be, for example, a time delay value, with units such as picoseconds (ps) or nanoseconds (ns), used to characterize the magnitude of compensation for the transmission delay of clock signals and / or data signals.
[0028] That is, for each display driver chip (DDI), the skew correction parameter S can be used to indicate the timing deviation of the clock signal CLK transmitted to the display driver chip DDI, or the skew correction parameter S can be used to indicate the timing deviation of the data signal Data transmitted to the display driver chip DDI, or the skew correction parameter S can be used to indicate the timing deviation of the clock signal CLK transmitted to the display driver chip DDI, and can also be used to indicate the timing deviation of the data signal Data transmitted to the display driver chip DDI.
[0029] Based on this, when each display driver chip (DDI) receives the clock signal CLK and data signal Data transmitted by the timing controller (TCON), it first compensates for the transmission delay of the clock signal CLK and / or data signal Data based on the skew correction parameter S specially configured for it by the timing controller (TCON). This corrects the timing deviation or offset between the clock signal CLK and the data signal Data, thereby aligning and matching the timing of the clock signal CLK and the data signal Data, eliminating the timing deviation between them, and providing a timing-matched clock reference for sampling. Then, it performs accurate and reliable sampling processing on the data signal Data based on the timing-matched clock signal CLK to ensure good reliability of the data signal Data sampling.
[0030] For example, in one embodiment, each display driver chip (DDI) can first compensate for the transmission delay of the received clock signal CLK to obtain a clock signal that is timing-matched and unbiased with the data signal Data. Then, based on the compensated clock signal CLK, the data signal Data is sampled accurately and reliably. This effectively optimizes and corrects the timing offset that occurs when the clock signal CLK and the data signal Data are corrected, thereby ensuring that the data signal Data sampling has good reliability.
[0031] And / or, in another embodiment, each display driver chip (DDI) can first compensate for the transmission delay of the received data signal Data to obtain a data signal Data that is timing-matched and unbiased with the clock signal CLK. Then, based on the clock signal CLK, the compensated data signal Data is subjected to accurate and reliable sampling processing, thereby effectively optimizing and correcting the timing offset that occurs when the clock signal CLK and the data signal Data are corrected, thus ensuring that the data signal Data sampling has good reliability.
[0032] Optionally, each display driver chip (DDI) can also be used to connect to pixels in the display panel to drive the pixels to emit light based on the sampled data signal (Data), i.e., to light up the pixels, and ultimately drive the display panel to display the image.
[0033] In summary, the embodiments of this application provide a signal transmission method. Because the timing controller in this method can not only transmit clock and data signals to multiple display driver chips via a shared bus, but also configure specific skew correction parameters for each display driver chip individually, each display driver chip can reliably compensate for the transmission delay of the received clock and / or data signals based on the corresponding skew correction parameters. This ensures that the timing of the clock and data signals received by each display driver chip is matched without any offset. Thus, the reliability of the sampling signals of each display driver chip is well ensured, thereby better supporting the requirements of high transmission rates.
[0034] Optionally, combined Figure 2 It can also be seen that n display driver chips (DDI) can be set on each side of the timing controller TCON, where n is an integer greater than 1.
[0035] In this design, the n display driver chips (DDIs) on the left are labeled DDI-L0, DDI-L1…DDI-Ln; and the n display driver chips (DDIs) on the right are labeled DDI-R0, DDI-R1…DDI-Rn. Similarly, the shared bus BUS1 can be divided into two segments, labeled BUS1-L and BUS1-R. The timing controller TCON can connect to DDI-R0, DDI-R1…DDI-Rn via the shared bus BUS1-R, and can also connect to DDI-L0, DDI-L1…DDI-Ln via the shared bus BUS1-L. This design is often used in large-size display panels with a large number of display driver chips (DDIs) and a wide layout, to provide stable signals to all the DDIs. Generally, the left-side display driver chip (DDI) is positioned close to the left side of the display panel and connects to multiple columns of pixels within that left area; the right-side display driver chip (DDI) is positioned close to the right side of the display panel and connects to multiple columns of pixels within that right area; and adjacent display driver chips (DDIs) also have adjacent columns of pixels for connection. For example, combining... Figure 2 Assuming that the display driver chip DDI in DDI-L0 is used to connect pixels in columns 1 to 5, then the display driver chip DDI in DDI-L1 is used to connect pixels in columns 6 to 10, and so on. This facilitates layout. Of course, it is not limited to this layout method.
[0036] Optionally, combined Figure 2 It can also be seen that the timing controller TCON described in the embodiments of this application can also establish a connection with multiple display driver chips DDI via the control bus BUS2. The method may further include: sending control signals to multiple display driver chips DDI via the control bus BUS2.
[0037] The control signal may include at least one of a polarity control signal (POL) and a timing control signal (TP).
[0038] Understandably, the polarity control signal POL can be used to control the polarity reversal of liquid crystal molecules in the pixel, preventing liquid crystal molecule polarization. The timing control signal TP can be used to synchronize the internal timing of the display driver chip DDI. These control signals all ensure that the display driver chip DDI reliably drives the pixels to emit light, resulting in a better display effect on the display panel.
[0039] In addition, taking the shared bus BUS1-L on the left as an example, refer to... Figure 2 It can also be seen that the clock signal CLK transmitted via the shared bus BUS1-L can include clock differential pairs LVCLKN / LVCLKP, and the data signal Data can include data differential pairs LVP0 / LVM0, LVP1 / LVM1...LVPn / LVMn. LVP1 / LVM1 is used to transmit to display driver chip DDI-L0, LVP1 / LVM1 is used to transmit to display driver chip DDI-L1, and so on, with LVPn / LVMn used to transmit to display driver chip DDI-Ln. The signals transmitted on the shared bus BUS1-R on the right are similar and will not be repeated. It can be understood that a differential pair is a pair of differential signals with equal amplitude and opposite polarity. Differential signals have stronger anti-interference capabilities and are more suitable for high-speed, long-distance transmission.
[0040] exist Figure 2 Based on this, taking the clock differential pair LVCLKN / LVCLKP, LVPi / LVMi (where i is an integer greater than 0 and less than n, referring to the data differential pair transmitted to the i-th display driver chip DDI-Li) as an example, Figure 3 A schematic diagram of a mini-LVDS signal is also shown. Figure 3 middle: TM refers to the clock cycle, which is the time it takes for the clock signal CLK to complete one cycle from high to low and back to high. The unit is typically picoseconds (ps). Optionally, the high potential can be an active potential, and the low potential can be an inactive potential, but this is not a limitation. The transition from high to low potential is also called a rising edge; the transition from low to high potential is also called a falling edge.
[0041] Tsu refers to the setup time of the data signal Data, which is the minimum time that the data signal Data must remain stable before the sampling transition edge of the clock signal CLK arrives. In the diagram, it is defined as 0.225 times the clock cycle TM. Th refers to the hold time of the data signal Data, which is the minimum time that the data signal Data must remain stable after the sampling transition edge of the clock signal CLK arrives. It is also defined as 0.225 times the clock cycle TM in the diagram. It can be understood that the sampling transition edge is the trigger edge for the display driver chip DDI to sample the data signal Data, generally the initial transition edge of the valid potential (e.g., the rising edge from high to low potential). Thus, it can be seen that, using a bus architecture, the mini-LVDS standard has strict limitations on the setup / hold time between the data channel and the clock channel.
[0042] The diagram also shows the clock duty cycle of the clock signal CLK. The minimum (MIN) is defined as 45%, and the maximum (MAX) as 55%. That is, within one clock cycle TM, the ratio of the effective potential duration of the clock signal CLK to the total duration of that clock cycle can be between 45% and 55%.
[0043] Tf refers to the falling edge time, which is the time required for the clock signal CLK to transition from a high level to a low level. It reflects the falling speed of the clock signal; the smaller the Tf, the faster the signal falls. The diagram uses the example of the clock signal CLK falling from 80% to 20% of its amplitude, defining Tf as 500ps.
[0044] Tr refers to the rise time, which is the time required for the clock signal CLK to transition from a low level to a high level. It reflects the rise speed of the clock signal; the smaller the Tf, the faster the signal rises. In the figure, taking the clock signal CLK rising from 20% to 80% of its amplitude as an example, the Tf is defined as 500ps.
[0045] In satisfying Figure 3 Based on the parameters shown, reliable sampling of the data signal Data can be ensured. Of course, it is not limited to... Figure 3 The specific parameters of the example.
[0046] Optionally, in Figure 2 and Figure 3 On this basis, Figure 4 A timing diagram of a mini-LVDS is schematically shown. Combined with... Figure 4 As can be seen, the clock signal CLK can include multiple consecutive clock windows, each corresponding one-to-one with a display driver chip (DDI). That is, the clock signal CLK transmitted via a shared bus BUS1 can include multiple clock windows, the number of which matches the number of display driver chips (DDI). For example, Figure 3The diagram illustrates the clock signal CLK transmitted to each display driver chip DDI in DDI-L0, DDI-L1...DDI-Ln, with the clock windows labeled CLK-L0, CLK-L1...CLK-Ln respectively.
[0047] Based on this, it can be seen that configuring skew correction parameters one-to-one for each of the multiple display driver chips, i.e., step 102, may include: During the interval between two adjacent clock windows, a corresponding skew correction parameter S is configured for the display driver chip DDI corresponding to the next clock window adjacent to the interval, so that the display driver chip DDI compensates for the transmission delay of at least one signal based on the skew correction parameter S within the corresponding clock window, and samples the data signal Data in response to the sampling transition edge of the clock signal CLK.
[0048] In other words, as described above, the data signal transmission required by each display driver chip (DDI) can be utilized by dividing the time frame. Each display driver chip (DDI) can reliably sample the data signal Data transmitted by the timing controller (TCON) when the sampling transition edge (or clock edge) of the clock signal CLK arrives within its corresponding clock window. The sampling transition edge can be, for example, a rising edge transitioning from a low level to a high level. For instance, the i-th display driver chip DDI-Li can reliably sample the data differential pair LVPi / LVMi when the sampling transition edge of the clock signal CLK arrives within its corresponding clock window. Correspondingly, the clock window can also be called the sampling window.
[0049] Furthermore, combined Figure 4 For each display driver chip (DDI), the timing controller (TCON) can configure a dedicated skew correction parameter S specifically for that DDI within the time interval between its corresponding clock window and the adjacent previous clock window. Furthermore, the skew correction parameter S configured by the timing controller TCON before the clock window can be maintained within the clock window, allowing the DDI to compensate for the transmission delay of the received clock signal CLK and / or data signal based on the skew correction parameter S before performing the sampling operation. Therefore, for each display driver chip (DDI), signal delay can be adjusted independently in a time-division manner to compensate for skew and ensure timing synchronization.
[0050] Understandably, during the interval, the clock signal CLK can remain at an invalid potential. Within the clock window, the clock signal CLK can periodically transition between an active and invalid potential. The invalid potential can be low relative to the active potential. That is, during the interval, the clock signal CLK can remain at a low potential.
[0051] Therefore, it can also be considered that in the embodiment of this application, during the stage of configuring the skew correction parameter S, the clock signal CLK does not change, and once the clock signal CLK changes, it can be considered that the data signal Data needs to be sampled at this time. Thus, it is possible to avoid affecting the sampling operation and to reliably configure the skew correction parameter S.
[0052] Based on this, configuring skew correction parameters for each display driver chip DDI among the multiple display driver chips (i.e., step 102) may include: For each display driver chip, before the first clock signal arrives in the corresponding clock window, the potential of the control clock signal is kept at an invalid potential. During the period of maintaining the invalid potential, the corresponding skew correction parameters are configured to the display driver chip, causing the display driver chip to apply the configured skew correction parameters. After the display driver chip applies the configured skew correction parameters, the configured skew correction parameters are maintained until the end of the last clock signal in the corresponding clock window. For example, combined with Figure 2 Taking the first display driver chip (e.g., DDI-L0) to the last display driver chip (e.g., DDI-Ln) as an example: Before the first clock signal arrives, the timing controller TCON can configure the corresponding skew correction parameter S to the first display driver chip DDI, so that the first display driver chip DDI applies the configured skew correction parameter S and maintains the configured skew correction parameter S until the end of the m-th clock signal. Here, the first clock signal to the m-th clock signal belong to the first clock window of the corresponding first display driver chip DDI.
[0053] During the interval between the end of the m-th clock signal and the arrival of the (m+1)-th clock signal, the timing controller TCON can maintain the clock signal potential at an invalid level. During this invalid level maintenance period, the corresponding skew correction parameter S is configured for the second display driver chip DDI, causing the second display driver chip DDI to apply the configured skew correction parameter S. After the second display driver chip DDI applies the configured skew correction parameter S, the configured skew correction parameter S is maintained until the end of the 2m-th clock signal. The (m+1)-2m-th clock signals belong to the second clock window of the corresponding second display driver chip DDI.
[0054] According to the arrangement order of the multiple display driver chips (DDI), the corresponding skew correction parameters S are configured for each subsequent display driver chip (DDI).
[0055] Specifically, for the nth display driver chip (DDI), during the period before the first clock signal arrives in the corresponding nth clock window and while the control clock signal's potential remains invalid, a corresponding skew correction parameter S is configured for the nth display driver chip (DDI). This ensures that the nth display driver chip (DDI) applies the configured skew correction parameter S and maintains the configured skew correction parameter S until the last clock signal in the nth clock window ends. m is an integer greater than 0, and n is an integer greater than 2 and less than the total number of display driver chips (DDI).
[0056] That is, for example, taking at least one signal mentioned above as the clock signal CLK, and the first display driver chip as DDI-L0, and the last display driver chip as DDI-Ln as an example, combined with... Figure 4 In the embodiments of this application: Before the arrival of the first clock signal (i.e., the 1st clock signal 1st CLK) in the first clock window CLK-L0, the timing controller TCON can configure a dedicated skew correction parameter S-L0 for the corresponding first display driver chip DDI-L0, and maintain this skew correction parameter S-L0 until the end of the last clock signal (i.e., the m-th clock signal m CLK) in the clock window CLK-L0. In other words, the timing controller TCON can configure a dedicated skew correction parameter S-L0 for the first display driver chip DDI-L0 during the period before the arrival of the 1st clock signal 1st CLK and while the potential of the clock signal CLK remains low. This allows the first display driver chip DDI-L0 to adjust the delay of the received clock signal CLK based on the skew correction parameter S-L0, compensating for the transmission delay of the received clock signal CLK, and maintain this skew correction parameter S-L0 until the m-th clock signal m CLK.
[0057] During the interval between the first clock window CLK-L0 and the second clock window CLK-L1, that is, from the end of the m-th clock signal in the first clock window CLK-L0 to the arrival of the first clock signal in the second clock window CLK-L1 (i.e., the (m+1)-th clock signal m+1 CLK), the potential of the clock signal CLK can be kept low again. During this low potential period, the timing controller TCON can configure a dedicated skew correction parameter S-L1 for the corresponding second display driver chip DDI-L1, and keep the skew correction parameter S-L1 until the end of the last clock signal in the second clock window CLK-L1 (i.e., the 2m-th clock signal 2m CLK). In other words, the timing controller TCON can configure a dedicated skew correction parameter S-L1 for the second display driver chip DDI-L1 during the period before the arrival of the (m+1)th clock signal m+1 CLK and while the potential of the clock signal CLK remains low. The second display driver chip DDI-L1 can then adjust the delay of the received clock signal CLK based on the skew correction parameter S-L1 to compensate for the transmission delay of the received clock signal CLK, and maintain the skew correction parameter S-L1 until the 2mth clock signal 2m CLK.
[0058] Following the above method, and so on. For example, similarly, before the first clock signal arrives in the nth clock window CLK-Ln, the potential of the clock signal CLK can be kept low. During this low potential period, the timing controller TCON can configure a dedicated skew correction parameter S-Ln for the corresponding nth display driver chip DDI-Ln. The nth display driver chip DDI-Ln adjusts the delay of the received clock signal CLK based on the skew correction parameter S-Ln to compensate for the transmission delay of the received clock signal CLK, and maintains the skew correction parameter S-Ln until the last clock signal in the clock window CLK-Ln ends.
[0059] For another example, suppose the 1st to 100th transitions of the clock signal CLK correspond to the operating timing of the first display driver chip DDI-L0, which is the clock window CLK-L0 of the first display driver chip DDI-L0, and the 101st to 200th transitions of the clock signal CLK correspond to the operating timing of the second display driver chip DDI-L1, which is the clock window CLK-L1 of the second display driver chip DDI-L1. Then, if a dedicated skew correction parameter S-L1 is to be configured for the second display driver chip DDI-L1, in this embodiment, the timing controller TCON can complete the configuration and activate the skew correction parameter S-L1 during the period after the 100th transition of the clock signal CLK and before the 101st transition, when the potential of the clock signal CLK remains at an invalid potential (e.g., a low potential).
[0060] It is understandable that, as described above, in some embodiments, a global skew correction parameter S can be configured before the clock window CLK-L0 of the first display driver chip DDI-L0, and this skew correction parameter S can be applied to all display driver chips DDI. However, in this case, all display driver chips DDI will be affected by the global skew correction parameter S, making it impossible to perform optimized skew correction for each display driver chip DDI. The method provided in this application, however, configures a corresponding skew correction parameter S for each display driver chip DDI, thus allowing the skew correction parameter to be applied specifically to the signal receiving channel of each display driver chip DDI, thereby achieving faster data transmission.
[0061] Optionally, in the embodiments of this application, combined with Figure 2 Step 102 may include configuring skew correction parameters for each of the multiple display driver chips, one-to-one. Specifically, step 102 may include configuring a corresponding skew correction parameter S for each display driver chip DDI based on the transmission skew between the clock signal CLK and the data signal Data sent to the display driver chip DDI.
[0062] In other words, for each display driver chip (DDI), the timing controller (TCON) can reliably and specifically configure a corresponding skew correction parameter S for that display driver chip (DDI) based on the transmission skew, or timing offset, between the clock signal (CLK) and the data signal (Data) transmitted to that display driver chip (DDI). Furthermore, this skew correction parameter S can generally be calibrated during the pre-production testing phase, and the skew correction parameter S configured for each display driver chip (DDI) can be different.
[0063] Optionally, combined Figure 5 As can be seen, each display driver chip (DDI) can include: a receiving circuit, a skew compensation circuit, and a sampling circuit.
[0064] The receiving circuit can be used to receive the clock signal CLK and the data signal Data.
[0065] The skew compensation circuit can be used to compensate for the transmission delay of clock signal CLK and / or data signal Data based on the skew correction parameter S, so as to match the timing of clock signal CLK and data signal Data.
[0066] The sampling circuit can be used to sample the data signal Data based on the timing-matched clock signal CLK.
[0067] In other words, a dedicated receiver can be set up in the display driver chip DDI to receive the data signal Data and clock signal CLK from the timing controller TCON. A dedicated skew compensation circuit can be set up to compensate for the skew of the clock signal CLK and / or the data signal Data from the timing controller TCON. A sampling circuit can also be set up to reliably sample the data signal Data based on the compensated timing-matched clock signal CLK. The entire circuit structure is simple, low-cost, and applicable to a wide range of scenarios.
[0068] As can be understood, as mentioned earlier, when the display driver chip DDI receives the clock signal CLK and data signal Data transmitted by the timing controller TCON, it first compensates for the transmission delay of the clock signal CLK and / or data signal Data based on the skew correction parameter S specially configured for it by the timing controller TCON. This corrects the timing deviation or offset between the clock signal CLK and the data signal Data, thereby aligning and matching the timing of the clock signal CLK and the data signal Data, eliminating the timing deviation between them, and providing a timing-matched clock reference for sampling. Then, it performs accurate and reliable sampling processing on the data signal Data based on the timing-matched clock signal CLK to ensure good reliability of the data signal Data sampling.
[0069] Based on this, for example, taking the timing controller TCON's compensation of the clock signal CLK based on the skew correction parameter S as an example, the skew correction parameter S may include the delay length of the clock signal CLK or a signal used to calculate the delay length of the clock signal. Ideally, the rising edge of the clock signal CLK should be aligned with the midpoint of the data signal Data's effective potential. However, in reality, due to delays in either the clock signal CLK or the data signal Data, the rising edge of the clock signal CLK and the midpoint of the data signal Data's effective potential are not aligned. Therefore, the timing controller TCON can refer to the skew correction parameter S to compensate for, for example, the transmission delay of the clock signal CLK. The skew correction parameter S can, for example, be used to align the rising edge of the clock signal CLK with the midpoint of the data signal Data's effective potential.
[0070] In summary, the embodiments of this application provide a signal transmission method. Because the timing controller in this method can not only transmit clock and data signals to multiple display driver chips via a shared bus, but also configure specific skew correction parameters for each display driver chip individually, each display driver chip can reliably compensate for the transmission delay of the received clock and / or data signals based on the corresponding skew correction parameters. This ensures that the timing of the clock and data signals received by each display driver chip is matched without any offset. Thus, the reliability of the sampling signals of each display driver chip is well ensured, thereby better supporting the requirements of high transmission rates.
[0071] This application also provides a timing controller TCON. Combined with... Figure 2 The timing controller TCON is used to establish connections with multiple display driver chips (DDI) via a shared bus BUS1 that shares data and clock channels. Furthermore, combined with... Figure 6 The timing controller TCON includes: The transmission module transmits clock signal CLK and data signal Data to multiple display driver chips (DDI) via the shared bus BUS1.
[0072] The configuration module configures the skew correction parameter S to each of the multiple display driver chips (DDIs).
[0073] Specifically, for each display driver chip DDI, the skew correction parameter S is used to instruct the display driver chip DDI to correct the transmission delay of at least one of the received clock signal CLK and data signal Data, so that the timing of the clock signal CLK and the data signal Data is matched, and the data signal Data is sampled based on the timing-matched clock signal CLK.
[0074] It is understandable that, since the timing controller and the signal transmission method described above have essentially the same technical effect, for the sake of brevity, the technical effect of the timing controller will not be described again here.
[0075] This application also provides a display device. For example... Figure 7 As shown, the display device includes: a display panel, multiple display driver chips (DDI), and a timing controller (TCON) as described above.
[0076] As described above, the timing controller TCON can establish connections with multiple display driver chips (DDIs) via a shared bus BUS1 (e.g., mini-LVDS) that shares data and clock channels, to transmit clock and data signals to the DDIs. Each DDI can also connect to a pixel in the display panel to sample data signals based on the clock signal and use these data signals to drive the pixel to emit light, thus illuminating the pixel and ultimately driving the display panel to display the image.
[0077] Optionally, the display device described in the embodiments of this application may include, but is not limited to, organic light-emitting diode (OLED) display devices and liquid crystal displays (LCDs). Furthermore, the display device may be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-books, and any other products or components with display functions.
[0078] It is understandable that, since the display device has essentially the same technical effect as the timing controller described above, for the sake of brevity, the technical effect of the display device will not be described again here.
[0079] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a computer, implements the signal transmission method described above.
[0080] This application also provides a computer program product containing instructions that, when run on a computer, enables the computer to execute the signal transmission method provided in the above embodiments.
[0081] It is understood that the terminology used in the embodiments section of this application is for explaining the embodiments of this application only, and is not intended to limit this application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.
[0082] For example, the terms "first," "second," or "third," and similar words used in the patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "an" or "a," and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" covers the element or object listed after "comprising" or "including," and does not exclude other elements or objects. "Above," "below," "left," or "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection. "And / or" indicates that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0083] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A signal transmission method, characterized in that, The method is applied to a timing controller, which establishes connections with multiple display driver chips via a shared bus sharing a data channel and a clock channel; the method includes: Clock signals and data signals are transmitted to the plurality of display driver chips via the shared bus; Configure skew correction parameters for each of the plurality of display driver chips in a one-to-one manner; Specifically, for each of the display driver chips, the skew correction parameter is used to instruct the display driver chip to correct the transmission delay of at least one of the received clock signal and data signal, so that the timing of the clock signal and the data signal is matched, and the data signal is sampled based on the timing-matched clock signal.
2. The method according to claim 1, characterized in that, The clock signal includes multiple consecutive clock windows corresponding one-to-one with the plurality of display driver chips; the configuration of skew correction parameters corresponding one-to-one with each of the plurality of display driver chips includes: During the interval between two adjacent clock windows, a corresponding skew correction parameter is configured for the display driver chip corresponding to the next clock window adjacent to the interval, so that the display driver chip compensates for the transmission delay of the at least one signal based on the skew correction parameter within the corresponding clock window, and samples the data signal in response to the start transition edge of the clock signal.
3. The method according to claim 2, characterized in that, During the specified interval, the potential of the clock signal remains at an invalid potential; Within the clock window, the potential of the clock signal periodically jumps between an active potential and an inactive potential.
4. The method according to claim 2, characterized in that, The configuration of skew correction parameters corresponding to each of the plurality of display driver chips includes: For each display driver chip, before the first clock signal arrives in the corresponding clock window, the potential of the clock signal is controlled to remain at an invalid potential. During the period of maintaining the invalid potential, the corresponding skew correction parameter is configured for the display driver chip, so that the display driver chip applies the configured skew correction parameter. After the display driver chip applies the configured skew correction parameter, the configured skew correction parameter is maintained until the last clock signal in the corresponding clock window ends.
5. The method according to any one of claims 1 to 4, characterized in that, The configuration of skew correction parameters corresponding to each of the plurality of display driver chips includes: For each of the display driver chips, a corresponding skew correction parameter is configured for the display driver chip based on the transmission skew between the clock signal and the data signal sent to the display driver chip.
6. The method according to any one of claims 1 to 4, characterized in that, The at least one signal is the clock signal.
7. The method according to any one of claims 1 to 4, characterized in that, The timing controller is also used to establish a connection with the plurality of display driver chips via a control bus; the method further includes: Control signals are sent to the plurality of display driver chips via the control bus; The control signal includes at least one of a polarity control signal and a timing control signal.
8. A timing controller, characterized in that, The timing controller is used to establish connections with multiple display driver chips via a shared bus of shared data and clock channels; the timing controller includes: The transmission module transmits clock signals and data signals to the plurality of display driver chips via the shared bus; The configuration module configures skew correction parameters for each of the plurality of display driver chips. Specifically, for each of the display driver chips, the skew correction parameter is used to instruct the display driver chip to correct the transmission delay of at least one of the received clock signal and data signal, so that the timing of the clock signal and the data signal is matched, and the data signal is sampled based on the timing-matched clock signal.
9. A display device, characterized in that, The display device includes: a display panel, a plurality of display driver chips, and a timing controller as described in claim 8.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a computer, implements the signal transmission method as described in any one of claims 1 to 7.