Bigate transistor and display device including same

Abstract

The invention provides a dual-gate transistor and a display device including the same. The dual gate transistor includes a first gate electrode disposed in an inverted tapered shape on a first gate insulating layer, a buffer layer disposed to cover the first gate electrode, an active layer disposed on the buffer layer, a second gate insulating layer disposed to cover the active layer, and a second gate electrode disposed in a tapered shape on the second gate insulating layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0145460, filed on October 23, 2024, with the Korean Intellectual Property Office, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] This disclosure relates to a dual-gate transistor and a display device including the dual-gate transistor, and more specifically, to a dual-gate transistor having improved switching characteristics and a display device including the dual-gate transistor. Background Technology

[0004] In today's information society, display devices used to present images or visual information to users are becoming increasingly important. The demand for such display devices has led to the rapid development of display technology, resulting in the development and widespread use of various types of display devices, such as liquid crystal displays (LCDs), plasma displays, quantum dot displays, organic light-emitting displays (e.g., OLEDs), and inorganic light-emitting displays.

[0005] Among these display devices, organic light-emitting display devices have advantages in contrast, luminous efficiency, brightness, and viewing angle by using organic light-emitting diodes (OLEDs) as self-emissive elements.

[0006] An organic light-emitting display device may include organic light-emitting diodes in a plurality of sub-pixels disposed in a display panel, and may display an image by means of light emitted from each sub-pixel via a drive current flowing to each organic light-emitting diode controlled by a corresponding drive transistor.

[0007] For example, one or more of the transistors included in at least one sub-pixel can be oxide transistors. In this implementation, oxide transistors can provide the advantages of reduced leakage current and prevention of image artifacts such as flicker.

[0008] In addition, oxide transistors can be configured with a dual-gate structure including an upper gate electrode and a lower gate electrode to improve current characteristics and ensure reliability.

[0009] However, when the interlayer insulating layer has a small thickness, transistors with such a dual-gate structure may suffer from seam defects that occur in the boundary region of the upper gate electrode of the transistor, and the switching characteristics deteriorate as the channel width of the active layer decreases. Summary of the Invention

[0010] To address these issues, the inventors of this disclosure have invented a dual-gate transistor with improved switching characteristics and a display device including the dual-gate transistor.

[0011] One or more aspects of this disclosure may provide a dual-gate transistor and a display device including the dual-gate transistor, the dual-gate transistor having a structure in which the active layer has an increased channel width to provide improved switching characteristics.

[0012] One or more aspects of this disclosure may provide a dual-gate transistor and a display device including the dual-gate transistor, the dual-gate transistor having an upper gate electrode with a first tapered shape and a lower gate electrode with a second tapered shape, thereby providing an active layer with increased channel width and improved switching characteristics.

[0013] One or more aspects of this disclosure may provide a dual-gate transistor and a display device including the dual-gate transistor, the dual-gate transistor having a biconical structure of an upper gate electrode and a lower gate electrode through process optimization.

[0014] According to one or more exemplary embodiments of the present disclosure, a dual-gate transistor may be provided, comprising: a first gate electrode disposed in an inverted conical shape on a first gate insulating layer; a buffer layer disposed on the first gate electrode; an active layer disposed on the buffer layer; a second gate insulating layer disposed on the active layer; and a second gate electrode disposed in a conical shape on the second gate insulating layer.

[0015] According to one or more exemplary embodiments of the present disclosure, a display device may be provided, comprising: a display panel having a plurality of sub-pixels; a gate driving circuit configured to supply at least one gate signal to the display panel; a data driving circuit configured to supply at least one data signal to the display panel; and a timing controller for controlling the gate driving circuit and the data driving circuit; each of the plurality of sub-pixels includes a dual-gate transistor, the dual-gate transistor comprising: a first gate electrode arranged in an inverted conical shape on a first gate insulating layer; a buffer layer disposed on the buffer layer; a second gate insulating layer disposed on the buffer layer; a second gate insulating layer disposed on the second gate insulating layer; and a second gate electrode arranged in a conical shape on the second gate insulating layer.

[0016] According to one or more exemplary embodiments of the present disclosure, a display device may be provided, comprising: a display panel having a plurality of sub-pixels; a gate driving circuit configured to supply at least one gate signal to the display panel; a data driving circuit configured to supply at least one data signal to the display panel; and a timing controller for controlling the gate driving circuit and the data driving circuit; wherein the gate driving circuit includes a dual-gate transistor, the dual-gate transistor comprising: a first gate electrode arranged in an inverted conical shape on a first gate insulating layer; a buffer layer disposed on the buffer layer; a second gate insulating layer disposed on the buffer layer; a second gate insulating layer disposed on the second gate insulating layer; and a second gate electrode arranged in a conical shape on the second gate insulating layer.

[0017] According to one or more aspects of this disclosure, a dual-gate transistor with improved switching characteristics and a display device including the dual-gate transistor can be provided.

[0018] According to one or more aspects of this disclosure, a dual-gate transistor and a display device including the dual-gate transistor can be provided, the dual-gate transistor having a structure in which the active layer has an increased channel width, thereby providing improved switching characteristics.

[0019] According to one or more aspects of this disclosure, a dual-gate transistor and a display device including the dual-gate transistor can be provided, the dual-gate transistor having a structure including an upper gate electrode of a first tapered shape and a lower gate electrode of a second tapered shape, thereby providing an active layer with increased channel width and improved switching characteristics.

[0020] According to one or more aspects of this disclosure, a dual-gate transistor and a display device including the dual-gate transistor can be provided, the dual-gate transistor having a biconical structure of an upper gate electrode and a lower gate electrode through process optimization. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this disclosure, illustrate aspects of this disclosure and, together with the description, serve to illustrate the principles of this disclosure. In the drawings:

[0022] Figure 1 An example display device according to aspects of this disclosure is shown;

[0023] Figure 2 An example system of a display device according to aspects of this disclosure is shown;

[0024] Figure 3 An example sub-pixel circuit of a display device according to aspects of this disclosure is shown;

[0025] Figure 4An example gate drive circuit configured to generate at least one gate signal is schematically shown in a display device according to aspects of the present disclosure;

[0026] Figure 5 An example configuration of the gate drive circuitry in a display device according to aspects of this disclosure is shown;

[0027] Figure 6 An example gate driver integrated circuit configured to output at least one scan signal in a display device according to aspects of the present disclosure is shown;

[0028] Figure 7 This is an example plan view of a dual-gate transistor included in a display device according to aspects of this disclosure;

[0029] Figure 8 The display device according to aspects of this disclosure is along Figure 7 An example cross-sectional view of a dual-gate transistor taken from line AB in the diagram;

[0030] Figures 9 to 13 An example process for manufacturing a dual-gate transistor included in a display device according to aspects of this disclosure is shown;

[0031] Figure 14 An example process is shown of forming a first gate electrode in a single layer structure of an inverted conical shape in a dual-gate transistor according to aspects of the present disclosure;

[0032] Figure 15 An example process is shown of forming a first gate electrode in a double-layer structure with an inverted conical shape in a dual-gate transistor according to aspects of the present disclosure;

[0033] Figure 16 An example process is shown of forming a first gate electrode in a three-layer structure with an inverted conical shape in a dual-gate transistor according to aspects of the present disclosure;

[0034] Figure 17 An example structure of a dual-gate transistor comprising a three-layer active layer according to aspects of this disclosure is shown; and

[0035] Figure 18 Another example structure of a dual-gate transistor comprising a three-layer active layer is shown according to aspects of this disclosure. Detailed Implementation

[0036] In the following, some embodiments of this disclosure will be described in detail with reference to exemplary accompanying drawings. Exemplary embodiments of this disclosure will now be described in detail, examples or aspects of which may be illustrated in the drawings. In the following description, unless otherwise specified, the structures, implementations, methods, and operations described herein are not limited to the specific examples, aspects, and embodiments set forth herein, and may be varied as is known in the art. Unless otherwise specified, similar reference numerals always refer to similar elements. The names of the various elements used in the following description are chosen only for ease of writing and may therefore differ from those used in actual products. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and components incorporated herein may be omitted where such detailed descriptions would make the subject matter of some embodiments of the invention quite unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed by” as used herein are generally intended to allow for the addition of additional components, unless said terms are used in conjunction with the term “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0037] Although the terms “first,” “second,” “A,” “B,” “(a),” or “(b)” may be used herein to describe various elements, these elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0038] When referring to the first element as "connected or coupled to," "in contact with," or "overlapping" with the second element, it should be interpreted that not only can the first element be "directly connected or coupled to" or "directly in contact with or overlap with" the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact with," or "overlapping" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact with," or "overlapping" with each other.

[0039] When describing positional relationships, such as using terms like "on," "above," "below," "over," "below," "next to," or "near" to describe the positional relationship between two parts, one or more other parts may be located between the two parts unless more restrictive terms such as "immediately," "directly," or "adjacent" are used. For example, if an element or layer is set "on" another element or layer, a third element or layer may be located between it. Furthermore, the terms "left," "right," "top," "bottom," "down," "up," "upper," and "lower" refer to any frame of reference.

[0040] Furthermore, when referring to any size, relative dimensions, etc., the numerical or corresponding information of the component or feature (e.g., level, range, etc.) should be considered, including tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. Additionally, the term "may" fully encompasses all the meanings of the term "can."

[0041] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0042] Figure 1 An example display device according to aspects of this disclosure is shown.

[0043] Reference Figure 1 In one or more example embodiments, the display device 100 may include a display panel 110 and at least one driving circuit for driving the display panel 110.

[0044] The display panel 110 may include a display area DA capable of displaying images and a non-display area NDA that does not display images. The non-display area NDA may also be referred to as a non-active area, a border, or a border area.

[0045] Display panel 110 may include a plurality of subpixels SP for image display. For example, the plurality of subpixels SP may be disposed in display area DA. In one or more aspects, at least one subpixel SP may be disposed in non-display area NDA. At least one subpixel SP disposed in non-display area NDA may be referred to as a dummy subpixel.

[0046] The display panel 110 may include multiple signal lines for driving multiple sub-pixels SP. For example, the multiple signal lines may include multiple data lines DL and multiple gate lines GL. Depending on the structure of the sub-pixel SP, in addition to the multiple data lines DL and multiple gate lines GL, the signal lines may also include other signal lines. For example, such signal lines may include drive voltage lines, reference voltage lines, etc.

[0047] Multiple data lines DL and multiple gate lines GL may intersect each other. Each of the multiple data lines DL may extend in a first direction. Each of the multiple gate lines GL may extend in a second direction different from the first direction. For example, the first direction may be a column or vertical direction, and the second direction may be a row or horizontal direction. In this document, the column direction and row direction may not represent absolute directions, but rather relative directions. For example, the column direction may be a vertical direction, while the row direction may be a horizontal direction. In another example, the column direction may be a horizontal direction, while the row direction may be a vertical direction.

[0048] At least one driving circuit may include a data driving circuit 130 for driving multiple data lines DL and a gate driving circuit 120 for driving multiple gate lines GL. At least one driving circuit may also include a timing controller 140 for controlling the data driving circuit 130 and the gate driving circuit 120.

[0049] The data driving circuit 130 can be a circuit for driving multiple data lines DL, and can output a data signal (which may be referred to as a data voltage) corresponding to the image signal to the multiple data lines DL. The gate driving circuit 120 can be a circuit for driving multiple gate lines GL, and can generate a gate signal and supply the generated gate signal to the multiple gate lines GL. The gate signal may include at least one scan signal and at least one light emission signal.

[0050] The timing controller 140 can start scanning pixels according to a corresponding timing set in each frame, and can control the data drive at a timing set for scanning one or more corresponding pixels. The timing controller 140 can convert image data received from an external device or system (e.g., host system 200) into a data signal form that can be read by the data drive circuit 130, and then supply the converted image data Data to the data drive circuit 130.

[0051] The timing controller 140 can receive display drive control signals and image data from the external host system 200. For example, the display drive control signals may include vertical synchronization signals, horizontal synchronization signals, input data enable signals, clock signals, etc.

[0052] The timing controller 140 can generate a data drive control signal DCS and a gate drive control signal GCS based on the display drive control signal received from the host system 200. The timing controller 140 can control the drive operation and timing of the data drive circuit 130 by supplying the data drive control signal DCS to the data drive circuit 130. The timing controller 140 can control the drive operation and timing of the gate drive circuit 120 by supplying the gate drive control signal GCS to the gate drive circuit 120.

[0053] The data driver circuit 130 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter, output buffer, etc. In one or more aspects, each source driver integrated circuit (SDIC) may also include an analog-to-digital converter (ADC).

[0054] In one or more aspects, each source driver integrated circuit (SDIC) may be connected to the display panel 110 via tape-on-board (TAB) technology, or to conductive pads such as bonding pads of the display panel 110 via chip-on-glass (COG) technology or chip-on-board (COP) technology, or to the display panel 110 via chip-on-film (COF) technology. However, the aspects of this disclosure are not limited thereto.

[0055] The gate drive circuit 120 can supply a gate signal with an on-level voltage, a gate signal with an off-level voltage, or a gate signal with both on-level and off-level voltages, according to the control of the timing controller 140. The gate drive circuit 120 can sequentially drive multiple gate lines GL by sequentially supplying the gate signal with an on-level voltage to multiple gate lines GL.

[0056] The gate drive circuit 120 may include one or more gate drive integrated circuits (GDICs).

[0057] In one or more aspects, the gate driving circuit 120 may be connected to the display panel 110 via tape-on-absence (TAB) technology, or to conductive pads such as bonding pads on the display panel 110 via chip-on-glass (COG) technology or chip-on-film (COP) technology, or to the display panel 110 via chip-on-film (COF) technology. However, the present disclosure is not limited thereto. In one or more aspects, the gate driving circuit 120 included in the display device 100 may be disposed in the non-display area NDA of the display panel 110 via gate-in-panel (GIP) technology. The gate driving circuit 120 may be disposed on or connected to the substrate. In an example where the gate driving circuit 120 is implemented in the display device 100 via gate-in-panel (GIP) technology, the gate driving circuit 120 may be disposed in the non-display area NDA of the substrate. In one or more aspects, when the gate driving circuit 120 is implemented via chip-on-glass (COG) technology, chip-on-film (COF) technology, etc., the gate driving circuit 120 may be connected to the substrate.

[0058] In one or more aspects, at least one of the data driving circuit 130 and the gate driving circuit 120 may be disposed in the display area DA. For example, at least one of the data driving circuit 130 and the gate driving circuit 120 may be configured not to overlap with the sub-pixel SP, or configured to overlap with one or more sub-pixels or all sub-pixels of the sub-pixel SP.

[0059] The data driving circuit 130 may be located and / or electrically connected to only one side or one edge (e.g., the upper or lower portion) of the display panel 110, but is not limited thereto. In one or more aspects, depending on the driving scheme, panel design, etc., the data driving circuit 130 may be located and / or electrically connected to more than two sides or two edges (e.g., the upper and lower portions) of the display panel 110 or to more than two sides or two edges (e.g., the upper, lower, left, and right portions) of the display panel 110, but is not limited thereto.

[0060] The gate driving circuit 120 may be located and / or electrically connected to only one side or one edge (e.g., the left or right portion) of the display panel 110, but is not limited thereto. In one or more aspects, depending on the driving scheme, panel design, etc., the gate driving circuit 120 may be disposed and / or electrically connected to more than two sides or two edges of the display panel 110 (e.g., the left and right portions) or four sides or four edges of the display panel 110 (e.g., the left, right, upper, and lower portions), but is not limited thereto.

[0061] The timing controller 140 can be implemented in a separate component from the data drive circuitry 130, or integrated with the data drive circuitry 130, such that the timing controller 140 and the data drive circuitry 130 can be implemented in a single integrated circuit. The timing controller 140 can be a controller used in typical display technologies, or a control device / apparatus capable of performing additional control functions beyond the typical functions of a timing controller. In one or more embodiments, the timing controller 140 can be one or more other control circuits, or circuits or components within a control device / apparatus, distinct from the timing controller. The timing controller 140 can be implemented using various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and processors.

[0062] The timing controller 140 can be mounted on a printed circuit board, flexible printed circuit, etc., and can be electrically connected to the data drive circuit 130 and the gate drive circuit 120 via the printed circuit board, flexible printed circuit, etc. The timing controller 140 can send signals to and receive signals from the data drive circuit 130 via one or more predetermined interfaces. For example, such interfaces may include a low-voltage differential signaling (LVDS) interface, an embedded point-to-point clock interface (EPI), a serial peripheral interface (SPI), etc.

[0063] In one or more aspects, the display device 100 may be a liquid crystal display device, a self-emissive display device in which light is emitted from the display panel 110 itself, etc. In an example where the display device 100 is a self-emissive display device, each of the plurality of sub-pixels SP included in the display device 100 may include a light-emitting element such as an organic light-emitting diode (OLED), an inorganic light-emitting diode (OLED), a quantum dot OLED, a micro OLED, or a miniature OLED. In one or more aspects, the display device 100 may be an organic light-emitting display device that uses an organic light-emitting diode (OLED) to realize the light-emitting element. In one or more aspects, the display device 100 may be an inorganic light-emitting display device that uses a light-emitting diode based on an inorganic material to realize the light-emitting element. In one or more aspects, the display device 100 may be a quantum dot display device that uses quantum dots, as self-emissive semiconductor crystals, to realize the light-emitting element.

[0064] Figure 2 An example system of a display device 100 according to aspects of this disclosure is shown.

[0065] Reference Figure 2In one or more example embodiments, the data driving circuit 130 and the gate driving circuit 120 included in the display device 100 may be implemented using various technologies such as tape-on-board (TAB) technology, chip-on-glass (COG) technology, chip-on-film (COF) technology, and gate-in-panel (GIP) technology.

[0066] In the example where the gate drive circuit 120 is implemented using GIP technology, multiple gate drive integrated circuits (GDICs) included in the gate drive circuit 120 can be directly disposed in the non-display area NDA of the display panel 110. In this example, the gate drive integrated circuits (GDICs) can receive various types of signals (e.g., clock signals, gate high signals, gate low signals, etc.) required to generate scan signals through gate drive related signal lines disposed in the non-display area NDA.

[0067] In one or more aspects, one or more source driver integrated circuits (SDICs) included in the data driver circuit 130 may be mounted on one or more corresponding source films (SFs), and one side of each source film (SF) may be electrically connected to the display panel 110. In one or more aspects, lines for electrically connecting one or more source driver integrated circuits (SDICs) and the display panel 110 may be respectively disposed in the upper portion of one or more source films (SFs).

[0068] The display device 100 may include: at least one source printed circuit board (SPCB) for circuit connection between one or more source driver integrated circuits (SDICs) and other units or devices; and a control printed circuit board (CPCB) for mounting control components and several types of electrical units or devices.

[0069] In one or more aspects, one side of the source film SF on which the active driver integrated circuit SDIC is mounted may be connected to at least one source printed circuit board SPCB. For example, one side of the source film SF on which the active driver integrated circuit SDIC is mounted may be electrically connected to at least one source printed circuit board SPCB, and the other side may be electrically connected to the display panel 110.

[0070] The timing controller 140 and the power management circuit 150 can be mounted on a control printed circuit board (CPCB). The timing controller 140 can control the operation of the data drive circuit 130 and the gate drive circuit 120. The power management circuit 150 can supply various levels of voltage or current to the display panel 110, the gate drive circuit 120, the data drive circuit 130, etc., or control the various levels of voltage or current to be supplied.

[0071] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be electrically connected to each other via at least one connector, such as a flexible printed circuit (FPC) or a flexible flat cable (FFC). In one or more aspects, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated into a single printed circuit board.

[0072] The display device 100 may also include a setup board 170 electrically connected to a control printed circuit board (CPCB). The setup board 170 may be referred to as a power board. A main power management circuit 160 configured to manage the overall power of the display device 100 may be mounted on the setup board 170. The main power management circuit 160 may interact with the power management circuit 150.

[0073] In the example where the display device 100 includes the power management circuit 150, setting board 170, control printed circuit board CPCB, etc. as described above, one or more driving voltages generated by the setting board 170 can be sent to the power management circuit 150 controlling the printed circuit board CPCB. The power management circuit 150 can send one or more driving voltages required for display driving or characteristic value sensing to the source printed circuit board SPCB via a flexible printed circuit FPC or a flexible flat cable FFC. One or more driving voltages sent to the source printed circuit board SPCB can be supplied to the display panel 110 via one or more source driver integrated circuits SDIC, and are used to enable one or more specific sub-pixels SP to emit light or sense one or more sub-pixels SP.

[0074] In one or more aspects, each sub-pixel SP included in the display panel 110 of the display device 100 may include circuit elements such as light-emitting elements (e.g., organic light-emitting diodes OLEDs), driving transistors for driving the light-emitting elements, etc.

[0075] The type and number of circuit elements included in each sub-pixel SP can vary depending on the panel type (e.g., LCD panel, OLED panel, etc.), the functions provided, design schemes / features, etc.

[0076] Figure 3 An example sub-pixel circuit of a display device 100 according to aspects of this disclosure is shown.

[0077] Reference Figure 3 In one or more example embodiments, each of the plurality of sub-pixels SP included in the display device 100, or one or more sub-pixels, may include a first to a seventh switching transistor (T1 to T7), a driving transistor DRT, a storage capacitor Cst, and a light-emitting element ED.

[0078] In one or more aspects, the light-emitting element (ED) can be a self-emissive element, such as an organic light-emitting diode (OLED), an inorganic light-emitting diode, a quantum dot light-emitting diode, a micro light-emitting diode, a mini light-emitting diode, etc.

[0079] In one or more aspects, the second to fourth switching transistors (T2 to T4), the sixth switching transistor T6, and the seventh switching transistor T7 may be P-type transistors. In one or more aspects, the first switching transistor T1 and the fifth switching transistor T5 may be N-type transistors.

[0080] The driving transistor DRT can be either a P-type or an N-type transistor. It should be noted here that... Figure 3 A P-type drive transistor DRT is shown as an example, but aspects of this disclosure are not limited thereto.

[0081] P-type transistors are relatively more reliable than N-type transistors. In examples where a P-type driver transistor DRT is used, since a high driving voltage VDD can be applied to the source electrode of the P-type driver transistor DRT while the light-emitting element ED is driven to emit light, the application of the P-type driver transistor DRT provides the advantage of preventing fluctuations in the current flowing to the light-emitting element ED due to the capacitor Cst. Therefore, the driver transistor DRT can stably provide the current for driving the light-emitting element ED.

[0082] In a configuration where the P-type driving transistor DRT is connected to the anode electrode of the light-emitting element ED, when the P-type driving transistor DRT operates in the saturation region, the P-type driving transistor DRT can provide a constant current to the light-emitting element ED regardless of changes in the threshold voltage, and therefore has relatively high reliability.

[0083] In the sub-pixel circuit based on the configuration discussed above, the N-type transistor can be an oxide transistor formed using oxide semiconductors, such as a transistor having a channel formed from oxide semiconductors such as indium oxide, gallium oxide, zinc oxide, indium gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO). The P-type transistor can be a silicon transistor formed using semiconductors such as silicon, such as a transistor called LTPS or low-temperature polysilicon transistor having a polysilicon channel formed by a low-temperature process.

[0084] Oxide transistors can have relatively lower leakage current than silicon transistors.

[0085] Considering these characteristics, the driving transistor DRT or at least some of the switching transistors included in the sub-pixel SP can be oxide transistors.

[0086] For example, the first switching transistor T1 and the fifth switching transistor T5 connected to the gate electrode of the driving transistor DRT can be oxide transistors.

[0087] For example, the driving transistor DRT and the remaining switching transistors (T2, T3, T4, T6 and T7) can be low-temperature polysilicon transistors.

[0088] According to these examples, each sub-pixel or one or more sub-pixels in the sub-pixels SP included in the display device 100 may include a first set of switching transistors (T1 and T5) as oxide transistors, and a driving transistor DRT as a low-temperature polysilicon transistor and a second set of switching transistors (T2, T3, T4, T6 and T7).

[0089] By using the first set of switching transistors (T1 and T5) implemented as oxide transistors, the display device 100 can provide the effect or advantage of preventing leakage current from flowing to the gate electrode of the driving transistor DRT, and thus reduce or eliminate unwanted image artifacts, such as flicker.

[0090] In one or more aspects, in order to improve the current characteristics in the on-state and provide high reliability, the first set of switching transistors (T1 and T5) may have a dual-gate structure including an upper gate electrode and a lower gate electrode.

[0091] It should be noted that, depending on the input voltage, the source and drain electrodes of a switching transistor can be referred to as the drain electrode and the source electrode, respectively.

[0092] The first scan signal SCAN1 can be applied to the gate electrode of the first switching transistor T1. The second electrode (e.g., the drain electrode) of the first switching transistor T1 can be connected to the gate electrode N2 of the driving transistor DRT. The first electrode (e.g., the source electrode) of the first switching transistor T1 can be connected to the second electrode (e.g., the drain electrode) N3 of the driving transistor DRT.

[0093] The first switching transistor T1 can be turned on by the first scan signal SCAN1, and a current path is formed between the gate electrode N2 and the second electrode N3 of the driving transistor DRT through a storage capacitor Cst with a high drive voltage VDD fixedly applied to one of its electrodes.

[0094] The first switching transistor T1 can be an N-type MOS transistor implemented as an oxide transistor. Since N-type MOS transistors use electrons instead of holes as charge carriers, they can provide a faster carrier mobility than P-type MOS transistors, and therefore a faster switching speed.

[0095] In one or more aspects, the first switching transistor T1 may have a dual-gate structure to reduce or eliminate leakage current due to charge injection when the display device 100 is driven to display an image.

[0096] The second scan signal SCAN2 can be applied to the gate electrode of the second switching transistor T2. A data voltage Vdata can be supplied to the first electrode (e.g., the source electrode) of the second switching transistor T2. The second electrode (e.g., the drain electrode) of the second switching transistor T2 can be connected to the first electrode (e.g., the source electrode) N1 of the driving transistor DRT. The second switching transistor T2 can be turned on by the second scan signal SCAN2, allowing the data voltage Vdata to be delivered to the first electrode (e.g., the source electrode) N1 of the driving transistor DRT.

[0097] When the first switching transistor T1 is turned on, since the data voltage Vdata is supplied to the first electrode (e.g., the source electrode) N1 of the driving transistor DRT through the second switching transistor T2, the difference (Vdata-Vth) between the data voltage Vdata and the threshold voltage Vth of the driving transistor DRT can be sampled and supplied to the gate electrode N2 of the driving transistor DRT. According to this operation, the first switching transistor T1 can be referred to as the sampling transistor, and the first scan signal SCAN1 can be referred to as the sampling scan signal.

[0098] A light-emitting signal EM can be applied to the gate electrode of the third switching transistor T3. A high drive voltage VDD can be applied to the first electrode (e.g., the source electrode) of the third switching transistor T3. The second electrode (e.g., the drain electrode) of the third switching transistor T3 can be connected to the first electrode (e.g., the source electrode) N1 of the driving transistor DRT. The third switching transistor T3 can be turned on by the light-emitting signal EM, allowing the high drive voltage VDD to be delivered to the first electrode (e.g., the source electrode) N1 of the driving transistor DRT.

[0099] A light-emitting signal EM can be applied to the gate electrode of a fourth switching transistor T4. The first electrode (e.g., source electrode) of the fourth switching transistor T4 can be connected to the second electrode (e.g., drain electrode) N3 of the driving transistor DRT. The second electrode (e.g., drain electrode) of the fourth switching transistor T4 can be connected to the anode electrode N4 of the light-emitting element ED. The fourth switching transistor T4 can be turned on by the light-emitting signal EM, allowing a drive current Id to flow to the anode electrode N4 of the light-emitting element ED.

[0100] The third scan signal SCAN3 can be applied to the gate electrode of the fifth switching transistor T5. For example, the third scan signal SCAN3 can be a signal with a different phase than the first scan signal SCAN1 applied to another sub-pixel SP, which is located differently from the sub-pixel SP to which the third scan signal SCAN3 is applied. For example, when the first scan signal SCAN1 is applied to the nth gate line, the third scan signal SCAN3 can be supplied using the first scan signal SCAN1 applied to the (n-1)th gate line. For example, the third scan signal SCAN3 can be supplied by using the first scan signal SCAN1 delivered through a different gate line GL, depending on the phase in which the display panel 110 is driven.

[0101] An initialization voltage Vini can be applied to the second electrode (e.g., the drain electrode) of the fifth switching transistor T5. The first electrode (e.g., the source electrode) of the fifth switching transistor T5 can be connected to the gate electrode N2 of the driving transistor DRT and the storage capacitor Cst. The fifth switching transistor T5 can be turned on by the third scan signal SCAN3, allowing the initialization voltage Vini to be applied to the gate electrode N2 of the driving transistor DRT. Based on this operation, the fifth switching transistor T5 can be referred to as the initialization transistor, and the third scan signal SCAN3 can be referred to as the initialization scan signal.

[0102] In one or more aspects, the fifth switching transistor T5 may have a dual-gate structure to reduce or eliminate leakage current due to charge injection when the display device 100 is driven to display an image.

[0103] The fourth scan signal SCAN4 can be applied to the gate electrode of the sixth switching transistor T6. The reset voltage VAR can be applied to the first electrode (e.g., the source electrode) of the sixth switching transistor T6. The second electrode (e.g., the drain electrode) of the sixth switching transistor T6 can be connected to the anode electrode N4 of the light-emitting element ED. The sixth switching transistor T6 can be turned on by the fourth scan signal SCAN4, allowing the reset voltage VAR to be delivered to the anode electrode N4 of the light-emitting element ED.

[0104] The fifth scan signal SCAN5 can be applied to the gate electrode of the seventh switching transistor T7. The bias voltage VOBS can be applied to the first electrode (e.g., the source electrode) of the seventh switching transistor T7. The second electrode (e.g., the drain electrode) of the seventh switching transistor T7 can be connected to the first electrode (e.g., the source electrode) N1 of the driving transistor DRT.

[0105] For example, the fifth scan signal SCAN5 can be a signal with a different phase than the third scan signal SCAN3 applied to another sub-pixel SP, which is located at a different position than the sub-pixel SP to which the fifth scan signal SCAN5 is applied. For example, when the third scan signal SCAN3 is applied to the nth gate line, the fifth scan signal SCAN5 can be supplied using the third scan signal SCAN3 applied to the (n-1)th gate line. For example, the fifth scan signal SCAN5 can be supplied by using the third scan signal SCAN3 delivered through a different gate line GL, depending on the phase in which the display panel 110 is driven.

[0106] Since the fifth scan signal SCAN5 is used to apply the bias voltage VOBS to the drive transistor DRT, it may be necessary for the fifth scan signal SCAN5 to be different from the second scan signal SCAN2 used to apply the data voltage Vdata.

[0107] The gate electrode N2 of the driving transistor DRT can be connected to the second electrode (e.g., the drain electrode) of the first switching transistor T1. The first electrode (e.g., the source electrode) N1 of the driving transistor DRT can be connected to the second electrode (e.g., the drain electrode) of the second switching transistor T2. The second electrode (e.g., the drain electrode) N3 of the driving transistor DRT can be connected to the first electrode (e.g., the source electrode) of the first switching transistor T1.

[0108] The driving transistor DRT can be turned on by the voltage difference between the gate electrode N2 and the first electrode (e.g., the source electrode) N1, and can supply a driving current Id to the light-emitting element ED.

[0109] The first electrode (e.g., source electrode) and the second electrode (e.g., drain electrode) of the first switching transistor T1 can be connected to the second electrode (e.g., drain electrode) N3 and the gate electrode N2 of the driving transistor DRT, respectively. When the first switching transistor T1 is turned on, the threshold voltage of the driving transistor DRT can be sampled and compensated by applying the data voltage Vdata to the first electrode (e.g., source electrode) N1 of the driving transistor DRT.

[0110] A high drive voltage VDD can be applied to one side or electrode of the storage capacitor Cst, and its other side or electrode can be connected to the gate electrode N2 of the drive transistor DRT. The storage capacitor Cst can store the voltage at the gate electrode N2 of the drive transistor DRT.

[0111] The anode N4 of the light-emitting element ED can be connected to the second electrode (e.g., drain electrode) of the fourth switching transistor T4 and the second electrode (e.g., drain electrode) of the sixth switching transistor T6. A base voltage VSS with a low level voltage can be applied to the cathode electrode of the light-emitting element ED.

[0112] The light-emitting element ED can emit light at a predetermined luminous intensity by the drive current Id supplied by the drive transistor DRT.

[0113] In one or more aspects, an initialization voltage Vini can be supplied to stabilize the change in capacitance formed by the gate electrode N2 of the driving transistor DRT, and a reset voltage VAR can be supplied to reset the anode electrode N4 of the light-emitting element ED.

[0114] When the fourth switching transistor T4, which is located between the anode electrode N4 of the light-emitting element ED and the second electrode (e.g., drain electrode) N3 of the driving transistor DRT and is turned off by the light-emitting signal EM, the anode electrode N4 of the light-emitting element ED can be reset when a reset voltage VAR is supplied to the anode electrode N4 of the light-emitting element ED.

[0115] The sixth switching transistor T6, which supplies the reset voltage VAR, can be connected to the anode N4 of the light-emitting element ED.

[0116] In order to enable the driving operation of the driving transistor DRT and the reset operation of the anode electrode N4 of the light-emitting element ED to be performed separately, the third scan signal SCAN3 for driving and / or initializing the driving transistor DRT and the fourth scan signal SCAN4 for controlling the supply of the reset voltage VAR to the anode electrode N4 of the light-emitting element ED can be supplied as different signals.

[0117] In one or more aspects, when the switching transistors T5 and T6, which supply the initialization voltage Vini and the reset voltage VAR, are turned on, the fourth switching transistor T4, which interconnects the drain electrode N3 of the driving transistor DRT and the anode electrode N4 of the light-emitting element ED, can be turned off, and thus the drive current Id from the driving transistor DRT can be prevented from flowing to the anode electrode N4 of the light-emitting element ED, and the anode electrode N4 can be prevented from being affected by any voltage other than the reset voltage VAR.

[0118] As in Figure 3 The sub-pixel circuit shown in the diagram, which includes eight transistors (DRT, T1, T2, T3, T4, T5, T6, and T7) and a storage capacitor Cst, can be referred to as an 8T1C structure.

[0119] In this document, in one or more example implementations, the 8T1C structure can be applied as an example in various sub-pixel circuit structures. Figure 3 The display device 110 shown includes each sub-pixel of the sub-pixel SP, or one or more sub-pixels, but the structure and number of transistors and capacitors included in the sub-pixel SP can be changed according to design requirements. In one or more aspects, each sub-pixel of the plurality of sub-pixels SP may have the same structure, or one or more sub-pixels of the plurality of sub-pixels SP may have a different structure from the remaining sub-pixels SP.

[0120] Figure 4 An example gate drive circuit configured to generate at least one gate signal is schematically shown in a display device 100 according to an aspect of the present disclosure.

[0121] Reference Figure 4 In one or more example embodiments, the display device 100 may include a timing controller 140, a level shifter L / S, and a gate drive circuit 120.

[0122] The level shifter L / S can output multiple gate clock signals GCLK and gate start signals GVST, etc., based on the gate control signal GCS output from the timing controller 140. The multiple gate clock signals GCLK can be output in the form of signals with different phases (e.g., 2-phase, 4-phase, or 8-phase).

[0123] The gate drive circuit 120 can operate based on the gate clock signal GCLK and the gate start signal GVST output from the level shifter L / S, and outputs at least one gate signal for turning on or off the transistors included in the display panel 110. The at least one gate signal may include scan signals (SC1-SCn), sensing signals, light emission signals, etc.

[0124] The level shifter L / S can be located in a separate integrated circuit, or it can be included in the power management circuit 150 or another device.

[0125] Figure 5 An example configuration of the gate drive circuit 120 in a display device 100 according to aspects of this disclosure is shown.

[0126] Reference Figure 5 In one or more example embodiments, the gate drive circuit 120 included in the display device 100 may be disposed in at least one side bezel area of ​​the display panel 110.

[0127] The gate drive circuit 120 may include n stages (STG1 to STGn) (where n is a natural number greater than or equal to 2), wherein the n gate drive integrated circuits (GDIC1 to GDICn) are cascaded together. Each gate drive integrated circuit (GDIC1 to GDICn) may have a gate high voltage VGH and a gate low voltage VGL applied as drive voltages, and may be operated by a gate clock signal GCLK.

[0128] The first gate driver integrated circuit GDIC1 can start operating via the gate start signal GVST, and the second gate driver integrated circuit GDIC2 to the nth gate driver integrated circuit GDICn can receive the scan signals (SC1 to SC(n-1)) output from the output terminal of the previous stage as start signals (START1 to START(n-1)).

[0129] For example, the first scan signal SC1 output from the output terminal of the first gate driver integrated circuit GDIC1 of the first stage STG1 can be applied to the start signal input terminal of the second gate driver integrated circuit GDIC2 of the second stage STG2 and the first sub-pixel line SPL1.

[0130] Therefore, the first gate driver integrated circuit GDIC1 of the first stage STG1 can use the gate start signal GVST as the start signal, but the second gate driver integrated circuit GDIC2 of the second stage STG2 to the nth gate driver integrated circuit GDICn of the nth stage STGn can respectively use the scan signal (SC1 to SC(n-1)) output from the output terminal of the gate driver integrated circuit (GDIC1 to GDIC(n-1)) located in the previous stage as the start signal (START1 to START(n-1)).

[0131] It should be noted that, Figure 5 In this context, the first scan signal SC1 output from the output terminal of the first gate driver integrated circuit GDIC1 is represented as the first start signal START1, indicating that the first scan signal SC1 generated in the first stage STG1 is used as the start signal of the next stage.

[0132] from Figure 5 The relationship between the (n-1)th STG(n-1)th and the nth STGn shows that the configuration of using the scan signal of the previous stage as the start signal of the next stage in the cascaded connection can be applied to all stages (STG1 to STGn).

[0133] It should be noted that Figure 5An example is shown in which one scan signal is output from one stage (one gate driver integrated circuit), but depending on the configuration of each or one or more gate driver integrated circuits, two or four scan signals can be output from one stage (one gate driver integrated circuit).

[0134] Figure 6 An example gate-driving integrated circuit configured to output at least one scan signal is shown in a display device 100 according to aspects of the present disclosure.

[0135] It should be noted here that Figure 6 As an example, a first gate driver integrated circuit GDIC1 that outputs the first scan signal SC1 is shown.

[0136] Reference Figure 6 In one or more example embodiments, the first gate driver integrated circuit GDIC1 may include first to seventh transistors (TG1 to TG7), an auxiliary transistor Tbv, a first capacitor CQ, and a second capacitor CQB.

[0137] The first transistor TG1 can be switched by the second gate clock signal GCLK2, and a gate start signal GVST1 is supplied to node Q1.

[0138] The second transistor TG2 can be switched by the first gate clock signal GCLK1, and one of the source and drain electrodes of the second transistor TG2 can be electrically connected to node Q1.

[0139] The third transistor TG3 can be switched by the voltage of the QB node QB and supply a high gate voltage VGH to one of the source and drain electrodes of the second transistor TG2.

[0140] The fourth transistor TG4 can be switched by the second gate clock signal GCLK2 and supplies a low gate voltage VGL to the QB node QB.

[0141] The fifth transistor TG5 can be switched by the voltage of node Q1 in Q1 and supply the second gate clock signal GCLK2 to node QB in QB.

[0142] In these configurations, when the fifth transistor TG5 is implemented as an oxide transistor, the gate drive integrated circuit can provide the effect or benefit of reducing image artifacts such as flicker by preventing current leakage.

[0143] In this implementation, the fifth transistor TG5 can have a dual-gate structure to reduce or eliminate leakage current due to charge injection during display driving.

[0144] The sixth transistor TG6 can be an output buffer, and its operation can be controlled by the voltage of node Q2. When node Q2 is at a low gate voltage VGL, the sixth transistor TG6 can be activated and output the first gate clock signal GCLK1 to output node N.

[0145] The seventh transistor TG7 can be an output buffer, and its operation can be controlled by the voltage of the QB node QB. When the QB node QB is at a low gate voltage VGL, the seventh transistor TG7 can be activated and output a scan signal of a high gate voltage VGH to the output node N.

[0146] The auxiliary transistor Tbv can be kept on by a low gate voltage VGL. The auxiliary transistor Tbv can make the voltages of node Q1 and node Q2 essentially equal.

[0147] The first capacitor CQ can be connected between node Q2 and output node N, and is configured to store the voltage of node Q2.

[0148] The second capacitor CQB can be connected between the QB node QB and the input terminal of the gate high voltage VGH, and is configured to store the voltage of the QB node QB.

[0149] In these configurations, in examples employing transistors with a dual-gate structure, when the interlayer insulating layer has a small thickness, transistors with a dual-gate structure may suffer from seam defects occurring in the boundary region of the upper gate electrode and degradation of switching characteristics as the channel width of the active layer decreases.

[0150] To address these issues, in one or more aspects, transistors with a dual-gate structure and display devices 100 including such transistors can provide the advantage of improved switching characteristics by designing the active layer to have an increased channel width.

[0151] Figure 7 This is an example plan view of a dual-gate transistor included in a display device 100 according to aspects of this disclosure. Figure 8 It is along Figure 7 An example cross-sectional view of a dual-gate transistor taken from line AB.

[0152] Reference Figure 7 and Figure 8 In one or more example embodiments, at least one sub-pixel SP or gate driving circuit 120 included in the display device 100 may include a transistor with a dual gate implemented as an oxide transistor (which may be referred to as a dual-gate transistor).

[0153] A dual-gate transistor may include a first gate electrode GE1, which includes a first gate material disposed on a substrate SUB.

[0154] In one or more aspects, a buffer layer may be disposed between the substrate SUB and the first gate electrode GE1.

[0155] In one or more aspects, the first gate material may be an opaque conductive material with low resistance, such as aluminum (Al), aluminum alloys, tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), etc. In one or more aspects, the first gate material may have a multilayer structure in which transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO) and opaque conductive materials are stacked.

[0156] The first gate electrode GE1 can be the lower gate electrode of a dual-gate transistor (it can also be called the bottom gate electrode).

[0157] The first gate electrode GE1 may include a first gate electrode GE1-1 and a first second gate electrode GE1-2 disposed on the first gate electrode GE1-1. The first gate electrode GE1-1 may be referred to as the first lower gate electrode, and the first second gate electrode GE1-2 may be referred to as the second lower gate electrode.

[0158] The foregoing description can be described differently, such that the first gate electrode GE1 includes a first-first gate region GE1-1 and a first-second gate region GE1-2. In this case, the first-second gate region GE1-2 can be referred to as the upper region of the inverted cone shape in the region of the first gate electrode GE1, and the first-first gate region GE1-1 can be referred to as the lower region of the first-second gate region GE1-2.

[0159] The first-first gate region GE1-1 and the first-second gate region GE1-2 may include the same material or different materials.

[0160] The width of the first-first gate region GE1-1 can be greater than the width of the active layer ACT.

[0161] The first-second gate region GE1-2 may have a tapered shape toward the substrate SUB at a specific angle (hereinafter, it may be referred to as an inverted tapered shape), and therefore, the lower portion of the first-second gate region GE1-2 may have a width smaller than the width of the active layer ACT disposed above the first-second gate region GE1-2.

[0162] In this implementation, the width of the upper portion of the first-second gate region GE1-2 can correspond to the first channel width LC1 at the lower portion of the active layer ACT.

[0163] The active layer ACT included in a dual-gate transistor may include an oxide semiconductor. A transistor including an active layer ACT comprising an oxide semiconductor may also be referred to as an oxide transistor. For example, the oxide semiconductor may be an N-type oxide semiconductor such as IGZO, IZO, or ITZO, or a P-type oxide semiconductor such as CuOx, SnOx, or NiOx.

[0164] The first channel width LC1 of the active layer ACT can be the width of the region created by adding the extended channel width LE of the first-second gate regions GE1-2, which are expanded during the doping process, to the initial channel width LC of the active layer ACT.

[0165] For example, the first channel width LC1 of the lower portion of the active layer ACT can have a value of (LC+2LE), which is generated by summing the initial channel width LC and the extended channel widths (2×LE) on both sides.

[0166] For example, the second channel width LC2 of the upper portion of the active layer ACT can have a value of (LC-2LD), which is generated by subtracting the extended channel width (2×LD) that is reduced due to the diffusion regions CH3 on both sides from the initial channel width LC.

[0167] Therefore, when the width of the upper portion of the first gate electrode GE1 is greater than the width of the upper portion of the second gate electrode GE2, the first channel width LC1 of the lower portion of the active layer ACT can be greater than the second channel width LC2 of the upper portion of the active layer ACT.

[0168] In this case, the corresponding cone angles of the first gate electrode GE1 and the second gate electrode GE2 can be determined to be proportional to the capacitance of the active layer ACT.

[0169] For example, when the ratio of the first capacitance formed between the active layer ACT and the first gate electrode GE1 to the second capacitance formed between the active layer ACT and the second gate electrode GE2 is 1:2, the cone angle of the first gate electrode GE1 and the cone angle of the second gate electrode GE2 can have a value of 1:2.

[0170] The first gate insulating layer GI1 can be configured such that it covers the first gate electrode GE1.

[0171] The active layer ACT included in the dual-gate transistor can be disposed on the first gate insulating layer GI1.

[0172] The active layer ACT may include a channel region CH1, a conductive semiconductor region CH2, and a diffusion region CH3.

[0173] The channel region CH1 can be the region in the active layer ACT where a channel is formed when a gate voltage at an on-level is applied to the first gate electrode GE1 and the second gate electrode GE2.

[0174] The conductive semiconductor region CH2 can be a region formed by impurity doping and electrically connected to the source electrode SE and drain electrode DE, respectively. The diffusion region CH3 can be a region where electrons or holes in the channel region CH1 diffuse toward the conductive semiconductor region CH2.

[0175] In these configurations, to provide dual-gate transistors with excellent switching characteristics, the active layer CAT of the dual-gate transistor may need to have a large channel width.

[0176] In one or more aspects, such as Figure 8 As shown, since the first gate electrode GE1 (as the lower gate electrode) of the dual-gate transistor of this disclosure is formed in an inverted conical shape, the dual-gate transistor and the display device 100 including the dual-gate transistor can provide the advantages of increasing the channel width of the active layer ACT and improving the switching characteristics.

[0177] The second gate insulating layer GI2 can be configured to cover the active layer ACT.

[0178] The second gate electrode GE2, which includes the second gate material, can be disposed on the second gate insulating layer GI2.

[0179] The second gate electrode GE2 can be the upper gate electrode of a dual-gate transistor (which can also be called the top gate electrode).

[0180] The second gate electrode GE2 may include a second-first gate electrode GE2-1 and a second-second gate electrode GE2-2 disposed on the second-first gate electrode GE2-1.

[0181] The second-first gate electrode GE2-1 can be referred to as the first upper gate electrode, and the second-second gate electrode GE2-2 can be referred to as the second upper gate electrode.

[0182] The foregoing expression can be described differently, such that the second gate electrode GE2 includes a second-first gate region GE2-1 and a second-second gate region GE2-2.

[0183] The second-first gate region GE2-1 and the second-second gate region GE2-2 may include the same material or different materials.

[0184] The second gate electrode GE2 may have a tapered shape at a specific angle in the direction opposite to the substrate SUB (hereinafter, it may be referred to as a tapered shape) to prevent seam defects from occurring in the boundary region.

[0185] In this configuration, the second-first gate region GE2-1 can be formed into a rectangular shape having a thickness less than that of the second-second gate region GE2-2, and the second-second gate region GE2-2 can be formed into a conical shape.

[0186] According to these configurations, since the first gate electrode GE1 has an inverted conical shape and the second gate electrode GE2 has a conical shape, the channel region CH1 can have different doping impurity concentrations in its upper and lower portions, and therefore the first channel width LC1 in the lower portion and the second channel width LC2 in the upper portion can become different from each other.

[0187] Therefore, the channel region CH1 may include a first channel region CH1-1 corresponding to the shape of the first gate electrode GE1 and a second channel region CH1-2 corresponding to the shape of the second gate electrode GE2. The first channel region CH1-1 may have a trapezoidal shape, wherein the first channel width LC1 of the lower portion of the first channel region CH1-1 corresponds to the width of the upper portion of the first gate electrode GE1.

[0188] In one or more aspects, the second channel region CH1-2 may have a trapezoidal shape, wherein the second channel width LC2 of the upper portion of the second channel region CH1-2 corresponds to the width of the upper portion of the second gate electrode GE2.

[0189] The interlayer insulating layer (ILD) can be disposed on the second gate electrode GE2.

[0190] Contact holes can be formed by etching corresponding portions of the interlayer insulating layer ILD and the second gate insulating layer GI2 to expose a portion of the active layer ACT, and source electrode SE and drain electrode DE in contact with the active layer ACT can be formed through the contact holes.

[0191] Based on the configuration discussed above, the dual-gate transistor of this disclosure can provide the following effects or advantages: improving switching characteristics by increasing the first channel width LC1 of the active layer ACT through the first gate electrode GE1 having an inverted conical shape, and preventing seam defects in the boundary region through the second gate electrode GE2 having a conical shape.

[0192] In one or more aspects, a dual-gate transistor comprising a first gate electrode GE1 having an inverted conical shape and a second gate electrode GE2 having a conical shape can be configured in a switching transistor comprising oxide semiconductor.

[0193] In one or more aspects, a driving transistor including an oxide semiconductor may include a first gate electrode GE1 having a rectangular shape and a second gate electrode GE2 having a tapered shape.

[0194] Figures 9 to 13 An example process for manufacturing a dual-gate transistor included in a display device 100 according to aspects of this disclosure is shown.

[0195] In one or more example embodiments, at least one switching transistor among a plurality of transistors included in the display device 100 may include a first gate electrode GE1 having an inverted conical shape and a second gate electrode GE2 having a conical shape. In one or more example embodiments, at least one driving transistor among a plurality of transistors may include a first gate electrode GE1 having a rectangular shape and a second gate electrode GE2 having a conical shape.

[0196] Reference Figure 9 The first gate electrode GE1-1, including the first gate material, can be formed on the substrate SUB in the region where the switching transistor is to be disposed and the region where the driving transistor is to be disposed.

[0197] In one or more aspects, a buffer layer may be additionally formed on the substrate SUB, and in this implementation, the first-first gate electrode GE1-1 may be located on the buffer layer.

[0198] The first-first gate electrode GE1-1 in the region where the switching transistor is to be set and the first-first gate electrode GE1-1 in the region where the driving transistor is to be set can have different widths from each other.

[0199] In one or more aspects, the first gate material may be an opaque conductive material with low resistance, such as aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), etc.

[0200] Reference Figure 10 The first-second gate electrode GE1-2 of the first gate material can be formed on the first-first gate electrode GE1-1.

[0201] In this implementation, the first and second gate electrodes GE1-2 disposed in the region of the switching transistor can have an inverted conical shape, and the first and second gate electrodes GE1-2 disposed in the region of the driving transistor can have a rectangular shape.

[0202] The first gate electrode GE1-1 and the first gate electrode GE1-2 may contain the same gate material.

[0203] The first-first gate electrode GE1-1 and the first-second gate electrode GE1-2 can be included in the first gate electrode GE1, and can be the lower gate electrode of the switching transistor and the lower gate electrode of the driving transistor.

[0204] Reference Figure 11 The first gate insulating layer GI1 can be formed such that it covers the first gate electrode GE1.

[0205] Reference Figure 12 An active layer ACT can be formed on the first gate insulating layer GI1, and a second gate insulating layer GI2 can be formed such that the second gate insulating layer GI2 covers the active layer ACT.

[0206] The active layer ACT can be a semiconductor layer, including hydrogenated amorphous silicon, etc.

[0207] A second gate electrode GE2 of the second gate material can be formed on the second gate insulating layer GI2. The second gate electrode GE2 can be the upper gate electrode. The second gate material can be the same as the first gate material.

[0208] The second gate electrode GE2 in the region of the switching transistor can be the upper gate electrode of the switching transistor, and the second gate electrode GE2 in the region of the driving transistor can be the upper gate electrode of the driving transistor.

[0209] The second gate electrode GE2 can have a width smaller than that of the active layer ACT.

[0210] With the second gate electrode GE2 formed, impurities can be doped into the active layer ACT, and thus the channel region CH1 and the conductive semiconductor region CH2 can be formed.

[0211] In one or more aspects, during the process of doping impurities into the active layer ACT, a photoresist may be applied to cover the second gate electrode GE2.

[0212] The switching transistor can be configured such that the lower channel region of the active layer ACT is formed into a cone shape corresponding to the structure of the first gate electrode GE1, which has an inverted cone shape.

[0213] In contrast, the driving transistor can be configured such that the channel region of the active layer ACT is formed into a rectangular or trapezoidal shape through the first gate electrode GE1, which has a rectangular shape.

[0214] In one or more aspects, the active layer ACT may include a diffusion region CH3 between the channel region CH1 and the conductive semiconductor region CH2.

[0215] The channel region CH1 can be a region formed on the semiconductor surface through impurity doping, and the conductive semiconductor region CH2 can be a region formed through impurity doping that is electrically connected to the source electrode SE and the drain electrode DE, respectively. The diffusion region CH3 can be a region in the channel region CH1 that diffuses towards the conductive semiconductor region CH2.

[0216] It should be understood here that when the amount of impurities doped into the active layer ACT increases, the seam defects in the boundary region may decrease, but the conductive semiconductor region CH2 may increase and the channel region CH1 may decrease, leading to a deterioration in the reliability characteristics of the transistor.

[0217] According to the above configuration, the dual-gate transistor can provide the advantage of increasing the effective channel width formed in the lower portion by forming the first gate electrode GE1 in the lower portion of the active layer ACT into an inverted cone shape.

[0218] For example, the first gate electrode GE1 can be formed to have a wider width than the second gate electrode GE2. According to this implementation, the first channel region CH1-1 of the active layer ACT formed by the first gate electrode GE1 can be formed to be wider than the second channel region CH1-2 of the active layer ACT formed by the second gate electrode GE2.

[0219] Therefore, the first channel region CH1-1 can be formed to have a width greater than that of the second gate electrode GE2. In contrast, the second channel region CH1-2 can be formed to have a width smaller than that of the first gate electrode GE1.

[0220] Therefore, the threshold voltage shift of the switching transistor can be reduced, and the mobility characteristics can be improved.

[0221] In one or more aspects, the diffusion region CH3 of the active layer ACT of a dual-gate transistor can be reduced by performing two or more processes to dope impurities into the active layer ACT.

[0222] For example, the reduction of the diffusion region CH3 of the active layer ACT can be performed by the following process: after forming a photoresist on the second gate electrode GE2, increasing the first channel width LC1 in the lower portion of the active layer ACT by first impurity doping, and thereafter, after removing the photoresist, increasing the conductive semiconductor region CH2 in the upper portion of the active layer ACT by second impurity doping.

[0223] Reference Figure 13 The interlayer insulating layer (ILD) can be disposed on the second gate electrode GE2.

[0224] Contact holes can be formed by etching corresponding portions of the interlayer insulating layer ILD and the second gate insulating layer GI2 to expose a portion of the active layer ACT, and source electrode SE and drain electrode DE in contact with the active layer ACT can be formed through the contact holes.

[0225] In one or more aspects, the corresponding first gate electrode of at least one dual-gate transistor may have a single layer of one material or a stacked structure of two or more materials.

[0226] Figure 14 An example process is shown of forming a first gate electrode in a single-layer structure with an inverted conical shape in a dual-gate transistor according to aspects of the present disclosure.

[0227] Reference Figure 14 In one or more example embodiments, the corresponding first gate electrode GE1 of at least one dual-gate transistor may be formed in a single layer of a gate material on the substrate SUB.

[0228] For example, the first gate electrode GE1 can be formed in a monolayer of molybdenum (Mo).

[0229] In this example, after the photoresist PR is applied to the first gate electrode GE1, a hard baking process can be performed to improve the adhesion between the first gate electrode GE1 and the photoresist PR.

[0230] After the first gate electrode GE1 and the photoresist PR are bonded, the side surface of the first gate electrode GE1 can be etched by a wet etching process. In this implementation, the central portion of the side surface of the first gate electrode GE1 can be etched most extensively by a wet etching process performed after the first gate electrode GE1 and the photoresist PR are bonded. In one or more aspects, the first gate electrode GE1 may include an upper first-second gate region having an inverted conical shape and a lower first-first gate region having a conical shape.

[0231] In the dual-gate transistor configured according to the above discussion, the channel width in the lower portion of the active layer ACT formed on the first gate electrode GE1 can be increased during the impurity doping process by the first and second gate regions having an inverted conical shape.

[0232] Figure 15 An example process is shown of forming a first gate electrode in a double-layer structure with an inverted conical shape in a dual-gate transistor according to aspects of the present disclosure.

[0233] Reference Figure 15 In one or more example embodiments, the corresponding first gate electrode GE1 of at least one dual-gate transistor may be formed in a bilayer of different gate materials on the substrate SUB.

[0234] For example, the first gate electrode GE1 may include: a first-first gate electrode GE1-1 comprising copper (Cu) and a first-second gate electrode GE1-2 comprising titanium (Ti) or a molybdenum-titanium alloy (MoTi).

[0235] After the photoresist PR is applied to the first gate electrode GE1, on which the first gate electrode GE1-1 and the first gate electrode GE1-2 are stacked, a hard baking process can be performed to improve the adhesion between the first gate electrode GE1 and the photoresist PR.

[0236] After the first gate electrode GE1 is bonded to the photoresist PR, the side surface of the first gate electrode GE1 can be etched by a wet etching process. In this implementation, the degree of etching can vary depending on the materials of the first gate electrode GE1-1 and the first gate electrode GE1-2.

[0237] For example, the etching degree of the first-first gate electrode GE1-1, which includes copper (Cu), can be greater than the etching degree of the first-second gate electrode GE1-2, which includes molybdenum-titanium alloy (MoTi).

[0238] In this example, the first gate electrode GE1 can be formed such that the width of the first-first gate electrode GE1-1 is greater than the width of the first-second gate electrode GE1-2 relative to the surface of the first gate insulating layer GL1.

[0239] Based on the configuration discussed above, the dual-gate transistor can provide an increased channel width in the lower portion of the active layer ACT formed on the first gate electrode GE1 during the impurity doping process by means of a first gate electrode GE1 having an inverted conical shape.

[0240] Figure 16 An example process is shown of forming a first gate electrode in a three-layer structure with an inverted conical shape in a dual-gate transistor according to aspects of this disclosure.

[0241] Reference Figure 16 In one or more example embodiments, the first gate electrode GE1 included in the dual-gate transistor may be configured as a three-layer structure in which the first-first gate electrode GE1-1, the first-second gate electrode GE1-2, and the first-third gate electrode GE1-3 are stacked on the substrate SUB.

[0242] For example, the first gate electrode GE1 may include: a first-first gate electrode GE1-1 comprising titanium (Ti) or molybdenum-titanium alloy (MoTi), a first-second gate electrode GE1-2 comprising aluminum (Al) or copper (Cu), and a first-third gate electrode GE1-3 comprising titanium (Ti) or molybdenum-titanium alloy (MoTi).

[0243] After the photoresist PR is applied to the first gate electrode GE1, on which the first gate electrode GE1-1, the first gate electrode GE1-2, and the first gate electrode GE1-3 are stacked, a hard baking process can be performed to improve the adhesion between the first gate electrode GE1 and the photoresist PR.

[0244] After the first gate electrode GE1 is bonded to the photoresist PR, the side surface of the first gate electrode GE1 can be etched by a wet etching process. In this implementation, the degree of etching can vary depending on the materials of the first gate electrode GE1-1, the first gate electrode GE1-2, and the first gate electrode GE1-3.

[0245] For example, the etching degree of the first-second gate electrode GE1-2, which includes aluminum (Al) or copper (Cu), can be greater than the corresponding etching degree of the first-first gate electrode GE1-1 and the first-third gate electrode GE1-3, which include titanium (Ti) or molybdenum-titanium alloy (MoTi).

[0246] In this example, the first gate electrode GE1 can be configured such that the width of the first-third gate electrode GE1-3 disposed on the first-second gate electrode GE1-2 is greater than the width of the first-second gate electrode GE1-2.

[0247] Based on the configuration discussed above, the dual-gate transistor can provide an increased channel width in the lower portion of the active layer ACT formed on the first gate electrode GE1 during the impurity doping process by using a first gate electrode GE1 with an inverted conical shape.

[0248] In one or more aspects, a dual-gate transistor may include performing a single impurity doping process on an active layer ACT, or may include performing two or more impurity doping processes on the active layer ACT with different impurity doping concentrations or different impurity doping times to form the active layer ACT into multiple regions with different mobilities.

[0249] Figure 17 An example structure of a dual-gate transistor comprising a three-layer active layer is shown according to aspects of this disclosure.

[0250] Reference Figure 17In one or more example embodiments, a dual-gate transistor may include a first gate electrode GE1 in which a first-first gate electrode GE1-1 and a first-second gate electrode GE1-2 are sequentially stacked on a substrate SUB. The first-first gate electrode GE1-1 may be referred to as a first-first gate region, and the first-second gate electrode GE1-2 may be referred to as a first-second gate region.

[0251] The first gate insulating layer GI1 can be configured such that it covers the first gate electrode GE1.

[0252] The active layer ACT included in the dual-gate transistor can be disposed on the first gate insulating layer GI1.

[0253] In this configuration, by applying different impurity doping concentrations or different impurity doping times to the active layer ACT, the active layer ACT can be configured into a three-region (or three-layer) form with different mobilities.

[0254] For example, the active layer ACT may include a first active region ACT1 with a first mobility, a second active region ACT2 with a second mobility, and a third active region ACT3 with a third mobility.

[0255] In this configuration, the second mobility of the second active region ACT2, located between the first active region ACT1 and the third active region ACT3, can be configured to be greater than each of the first mobility of the first active region ACT1 and the third mobility of the third active region ACT3.

[0256] In this case, considering that the current path of the dual-gate transistor can be mostly formed in the second active region ACT2 with greater mobility, in order to increase the channel width of the second active region ACT2, a first gate electrode GE1 with an inverted conical shape can be formed (i.e., Figure 17 The first-second gate electrode (GE1-2) of the dual-gate transistor has a large tilt angle A relative to the first-first gate electrode (GE1-1).

[0257] The tilt angle A of the first gate electrode GE1, which has an inverted conical shape, can vary according to the difference in mobility of the active layer ACT or region.

[0258] Figure 18 Another example structure of a dual-gate transistor comprising a three-layer active layer is shown according to aspects of this disclosure.

[0259] Reference Figure 18In one or more example embodiments, a dual-gate transistor may include a first gate electrode GE1 in which a first-first gate electrode GE1-1 and a first-second gate electrode GE1-2 are sequentially stacked on a substrate SUB. The first-first gate electrode GE1-1 may be referred to as a first-first gate region, and the first-second gate electrode GE1-2 may be referred to as a first-second gate region.

[0260] The first gate insulating layer GI1 can be configured such that it covers the first gate electrode GE1.

[0261] The active layer ACT included in the dual-gate transistor can be disposed on the first gate insulating layer GI1.

[0262] The active layer ACT can be doped with impurities to have a channel region CH1, a conductive semiconductor region CH2, and a diffusion region CH3.

[0263] In this configuration, by applying different impurity doping concentrations or different impurity doping times to the active layer ACT, the active layer ACT can be configured into a three-region (or three-layer) form with different mobilities.

[0264] For example, the active layer ACT may include a first active region ACT1 with a first mobility, a second active region ACT2 with a second mobility, and a third active region ACT3 with a third mobility.

[0265] In this configuration, the third mobility of the third active region ACT3, which is furthest from the substrate SUB, can be configured to be greater than each of the first mobility of the first active region ACT1 and the second mobility of the second active region ACT2.

[0266] In this case, the current path of the dual-gate transistor can be largely formed in the third active region ACT2, which has greater mobility. Therefore, to increase the channel width of the third active region ACT3, a first gate electrode GE1 with an inverted conical shape can be formed (i.e., Figure 18 The first-second gate electrode GE1-2) of the dual-gate transistor has a smaller tilt angle B relative to the first-first gate electrode GE1-1, thereby increasing the width of the first gate electrode GE1.

[0267] Based on the configuration discussed above, the dual-gate transistor of this disclosure can provide the following effects or advantages: the switching characteristics of the switching transistor are improved by increasing the channel width of the active layer ACT through impurity doping of the first gate electrode GE1 having an inverted conical shape, and seam defects in the boundary region are prevented by the second gate electrode GE2 having a conical shape.

[0268] The above example implementation will be briefly described below.

[0269] According to one or more example embodiments described herein, a dual-gate transistor may be provided, comprising: a first gate electrode disposed on a first gate insulating layer and having an inverted conical shape; a buffer layer disposed to cover the first gate electrode; an active layer disposed on the buffer layer; a second gate insulating layer disposed to cover the active layer; and a second gate electrode disposed on the second gate insulating layer and having a conical shape.

[0270] In one or more aspects, the first gate electrode may include: a first-first gate region disposed on a first gate insulating layer and having a rectangular shape; and a first-second gate region disposed on the first-first gate region and having an inverted conical shape.

[0271] In one or more aspects, the width of the first-first gate region may be greater than the width of the second gate electrode.

[0272] In one or more aspects, the first gate electrode may include a first-first gate region disposed on the first gate insulating layer and having a tapered shape, and a first-second gate region disposed on the first-first gate region and having an inverted tapered shape.

[0273] In one or more aspects, the first gate electrode may include a first-first gate region disposed on the first gate insulating layer and having an inverted conical shape, and a first-second gate region disposed on the first-first gate region and having an inverted conical shape. In this implementation, the width of the first-second gate region may be greater than the width of the first-first gate region.

[0274] In one or more aspects, the first-first gate region may include copper, and the first-second gate region may include titanium or a molybdenum-titanium alloy.

[0275] In one or more aspects, the first gate electrode may include a first-first gate region disposed on a first gate insulating layer and having a tapered shape, a first-second gate region disposed on the first-first gate region and having an inverted tapered shape, and a first-third gate region disposed on the first-second gate region and having an inverted tapered shape. In this implementation, the width of the first-third gate region may be greater than the width of the first-second gate region.

[0276] In one or more aspects, the first-first gate region may include titanium or a molybdenum-titanium alloy, the first-second gate region may include copper, and the first-third gate region may include titanium or a molybdenum-titanium alloy.

[0277] In one or more aspects, the active layer may include a channel region formed in its central region, conductive semiconductor regions located on both sides of the channel region and doped with impurities, and a diffusion region formed between each of the channel region and the conductive semiconductor regions. In this implementation, the conductive semiconductor regions may include multiple regions with different mobilities formed by performing two or more impurity doping processes.

[0278] In one or more aspects, the conductive semiconductor region may include a first conductive semiconductor region disposed on a buffer layer and having a first mobility, a second conductive semiconductor region disposed on the first conductive semiconductor region and having a second mobility, and a third conductive semiconductor region disposed on the second conductive semiconductor region and having a third mobility.

[0279] In one or more aspects, the second migration rate may be greater than the first and third migration rates.

[0280] In one or more aspects, the width of the first gate electrode may be the same as the width of the channel region.

[0281] In one or more aspects, the third migration rate can be greater than the first and second migration rates.

[0282] In one or more aspects, the width of the first gate electrode may be greater than the width of the channel region.

[0283] In one or more aspects, the ratio of the cone angle of the first gate electrode to the cone angle of the second gate electrode may be proportional to the ratio of the first capacitor to the second capacitor, wherein the first capacitor is formed between the active layer and the first gate electrode, and the second capacitor is formed between the active layer and the second gate electrode.

[0284] According to one or more example embodiments described herein, a display device may be provided, comprising: a display panel having a plurality of sub-pixels; a gate driving circuit configured to supply at least one gate signal to the display panel; a data driving circuit configured to supply at least one data signal to the display panel; and a timing controller for controlling the gate driving circuit and the data driving circuit; wherein at least one of the plurality of sub-pixels includes a dual-gate transistor, the dual-gate transistor comprising: a first gate electrode having an inverted conical shape disposed on a first gate insulating layer; a buffer layer disposed on the buffer layer; an active layer disposed on the buffer layer; a second gate insulating layer disposed on the second gate insulating layer and having a conical shape; and a second gate electrode disposed on the second gate insulating layer and having a conical shape.

[0285] In one or more aspects, at least one sub-pixel may include: a light-emitting element, a driving transistor for providing current to the light-emitting element, a first transistor connected between the gate node and the drain node of the driving transistor, a second transistor connected between the source node of the driving transistor and a data line, a third transistor connected between a driving voltage line and the source node of the driving transistor, a fourth transistor connected between the drain node of the driving transistor and the anode of the light-emitting element, a fifth transistor connected between the gate node of the driving transistor and an initialization voltage line, a sixth transistor connected between an anode reset voltage line and the anode of the light-emitting element, and a storage capacitor connected between the driving voltage line and the fifth transistor. In this implementation, the first transistor or the fifth transistor may be configured as a dual-gate transistor.

[0286] According to one or more example embodiments described herein, a display device may be provided, comprising: a display panel having a plurality of sub-pixels; a gate driving circuit configured to supply at least one gate signal to the display panel; a data driving circuit configured to supply at least one data signal to the display panel; and a timing controller for controlling the gate driving circuit and the data driving circuit, the gate driving circuit including a dual-gate transistor, the dual-gate transistor including: a first gate electrode having an inverted conical shape disposed on a first gate insulating layer; a buffer layer disposed covering the first gate electrode; an active layer disposed on the buffer layer; a second gate insulating layer disposed covering the active layer; and a second gate electrode disposed on the second gate insulating layer and having a conical shape.

[0287] In one or more aspects, the gate drive circuit may include: a first transistor switched by a second gate clock signal and supplying a gate start signal to node Q1; a second transistor switched by the first gate clock signal and allowing one of the source and drain electrodes to be electrically connected to node Q1; a third transistor switched by the voltage of node QB and supplying a gate high voltage to one of the source and drain electrodes of the second transistor; a fourth transistor switched by the second gate clock signal and supplying a gate low voltage to node QB; a fifth transistor switched by the voltage of node Q1 and supplying a second gate clock signal to node QB; a sixth transistor transmitting the first gate clock signal to the output node via the voltage of node Q2; a seventh transistor transmitting a gate high voltage to the output node via the voltage of node QB; an auxiliary transistor controlled by the gate low voltage and connected to nodes Q1 and Q2; a first capacitor connected between node Q2 and the output node; and a second capacitor connected between node QB and the terminal of the input gate high voltage. In this implementation, the fifth transistor may be configured as a dual-gate transistor.

[0288] The above description is presented to enable any person skilled in the art to make, use, and practice the technical features of this disclosure, and has been provided as examples in the context of specific applications and their requirements. Various modifications, additions, and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the principles described herein can be applied to other embodiments and applications without departing from the scope of this disclosure. The above description and drawings are provided as examples of the technical features of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of this disclosure.

Claims

1. A dual-gate transistor, comprising: A first gate electrode is disposed on a substrate and has an inverted conical shape; A first gate insulating layer, wherein the first gate insulating layer is configured such that the first gate insulating layer covers the first gate electrode; An active layer is disposed on the first gate insulating layer; A second gate insulating layer is configured such that the second gate insulating layer covers the active layer; as well as The second gate electrode is disposed on the second gate insulating layer and has a tapered shape; The active layer includes a channel region formed at a location where it overlaps with the first gate electrode and the second gate electrode.

2. The dual-gate transistor according to claim 1, wherein, The first gate electrode includes: A first gate region, wherein the first gate region is disposed on the substrate; and First-second gate regions, the first-second gate regions being disposed on the first-first gate regions and having the inverted conical shape.

3. The dual-gate transistor according to claim 2, wherein, The width of the first gate region is greater than the width of the second gate electrode.

4. The dual-gate transistor according to claim 1, wherein, The first gate electrode includes: A first gate region, wherein the first gate region is disposed on the substrate and has a tapered shape; and First-second gate regions, the first-second gate regions being disposed on the first-first gate regions and having an inverted conical shape.

5. The dual-gate transistor according to claim 1, wherein, The first gate electrode includes: A first-first gate region, wherein the first-first gate region is disposed on the substrate and has an inverted conical shape; and First and second gate regions, the first and second gate regions being disposed on the first and second gate regions and having an inverted conical shape, and The width of the first-second gate region is greater than the width of the first-first gate region.

6. The dual-gate transistor according to claim 5, wherein, The first-first gate region comprises copper, and the first-second gate region comprises titanium or a molybdenum-titanium alloy.

7. The dual-gate transistor according to claim 1, wherein, The first gate electrode includes: First-first gate region, the first-first gate region is disposed on the substrate and has a tapered shape; First and second gate regions, the first and second gate regions being disposed on the first and second gate regions and having an inverted conical shape; and The first and third gate regions are disposed on the first and second gate regions and have an inverted conical shape. The width of the first-third gate region is greater than the width of the first-second gate region.

8. The dual-gate transistor according to claim 7, wherein: The first-first gate region comprises titanium or a molybdenum-titanium alloy; The first and second gate regions comprise copper; and The first to third gate regions comprise titanium or a molybdenum-titanium alloy.

9. The dual-gate transistor according to claim 1, wherein, The active layer further includes: A conductive semiconductor region, the conductive semiconductor region being located on both sides of the channel region and doped with impurities; and A diffusion region is formed between each of the channel region and the conductive semiconductor region, and The active layer includes multiple regions with different mobility.

10. The dual-gate transistor according to claim 9, wherein, The active layer includes: A first active region is disposed on the substrate and has a first mobility; A second active region, disposed on the first active region and having a second mobility; and A third active region is disposed on the second active region and has a third mobility.

11. The dual-gate transistor of claim 10, wherein, The second mobility rate is greater than each of the first mobility rate and the third mobility rate.

12. The dual-gate transistor according to claim 10, wherein, The third mobility rate is greater than each of the first mobility rate and the second mobility rate.

13. The dual-gate transistor according to claim 1, wherein, The trench area includes: The first channel region adjacent to the first gate electrode; and The second channel region adjacent to the second gate electrode, and The width of the first channel region is greater than the width of the second channel region.

14. The dual-gate transistor according to claim 13, wherein, The width of the first channel region is greater than the width of the second gate electrode.

15. The dual-gate transistor according to claim 13, wherein, The width of the second channel region is smaller than the width of the first gate electrode.

16. The dual-gate transistor according to claim 1, wherein, The ratio of the cone angle of the first gate electrode to the cone angle of the second gate electrode is proportional to the ratio of the first capacitor to the second capacitor, wherein the first capacitor is formed between the active layer and the first gate electrode, and the second capacitor is formed between the active layer and the second gate electrode.

17. A display device, comprising: A display panel, wherein multiple sub-pixels are provided; A gate driving circuit, the gate driving circuit being configured to supply at least one gate signal to the display panel; A data driving circuit configured to supply at least one data signal to the display panel; as well as A timing controller configured to control the gate drive circuit and the data drive circuit. Wherein, at least one of the plurality of sub-pixels includes at least one dual-gate transistor, the dual-gate transistor comprising: A first gate electrode is disposed on a substrate and has an inverted conical shape; A first gate insulating layer, wherein the first gate insulating layer is configured such that the first gate insulating layer covers the first gate electrode; An active layer is disposed on the first gate insulating layer; A second gate insulating layer, the second gate insulating layer being configured such that the second gate insulating layer covers the active layer; and The second gate electrode is disposed on the second gate insulating layer and has a tapered shape.

18. The display device according to claim 17, wherein, The at least one sub-pixel includes: Light-emitting elements; A driving transistor, the driving transistor being used to provide current to the light-emitting element; A first transistor is connected between the gate node and the drain node of the driving transistor. The second transistor is connected between the source node of the driving transistor and the data line; A third transistor is connected between the source node of the driving transistor and the driving voltage line; A fourth transistor is connected between the drain node of the driving transistor and the anode of the light-emitting element; A fifth transistor is connected between the gate node of the driving transistor and the initialization voltage line; A sixth transistor, the sixth transistor being connected between the anode reset voltage line and the anode electrode of the light-emitting element; and A storage capacitor is connected between the drive voltage line and the fifth transistor, and The first transistor or the fifth transistor is configured as the dual-gate transistor.

19. A display device, comprising: A display panel, wherein multiple sub-pixels are provided; A gate driving circuit, the gate driving circuit being configured to supply at least one gate signal to the display panel; A data driving circuit configured to supply at least one data signal to the display panel; as well as A timing controller configured to control the gate drive circuit and the data drive circuit. The gate driving circuit includes at least a dual-gate transistor, wherein the dual-gate transistor comprises: A first gate electrode is disposed on a substrate and has an inverted conical shape; A first gate insulating layer, wherein the first gate insulating layer is configured such that the first gate insulating layer covers the first gate electrode; An active layer is disposed on the first gate insulating layer; A second gate insulating layer, the second gate insulating layer being configured such that the second gate insulating layer covers the active layer; and The second gate electrode is disposed on the second gate insulating layer and has a tapered shape.

20. The display device according to claim 19, wherein, The gate driving circuit includes: The first transistor is switched by the second gate clock signal and supplies a gate start signal to the Q1 node; The second transistor is switched by the first gate clock signal and allows one of the source and drain electrodes to be electrically connected to the Q1 node; The third transistor is voltage-switched by the QB node and supplies a gate high voltage to one of the source and drain electrodes of the second transistor; A fourth transistor, which is switched by a second gate clock signal and supplies a gate low voltage to the QB node; The fifth transistor is a voltage switch of the Q1 node and supplies the second gate clock signal to the QB node; The sixth transistor transmits the first gate clock signal to the output node through the voltage of the Q2 node; The seventh transistor transmits the gate high voltage to the output node through the voltage of the QB node; An auxiliary transistor, which is controlled by the gate low voltage and connected to the Q1 node and the Q2 node; A first capacitor, the first capacitor being connected between the Q2 node and the output node: and A second capacitor is connected between the QB node and the terminal where the high gate voltage is input, and The fifth transistor is configured as the dual-gate transistor.

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