Display panel and display device
By cascading shift register units in the display panel, utilizing transistor gate reuse as capacitor plates, and optimizing the clock signal line layout, the problems of large space occupation and high power consumption of shift registers are solved, achieving the effects of narrow bezels and low power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAMEN TIANMA DISPLAY TECH CO LTD
- Filing Date
- 2026-01-27
- Publication Date
- 2026-04-24
AI Technical Summary
The peripheral area of the display panel occupies a large space due to the shift registers and peripheral traces, which limits the realization of a narrow bezel. At the same time, the coupling between the clock signal lines and capacitors leads to increased power consumption.
By employing cascaded shift register units, the gate portion of the first transistor is reused as a capacitor plate, and the spacing between the clock signal line and the transistor gate is smaller than the spacing between the clock signal line and the capacitor plate, the size of the shift register unit is reduced and the load on the clock signal line is lowered.
It achieves narrow bezels in the display panel, reduces power consumption, and improves the overall performance of the display panel.
Smart Images
Figure CN121924828A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology
[0002] As consumers' demands for displays increase, narrow bezel displays have become a popular requirement due to their ability to provide a better user experience. However, related technologies require shift registers and peripheral wiring to be installed around the perimeter of the display panel. The shift registers, in particular, are quite complex and occupy a significant amount of space around the display panel, limiting the possibility of achieving narrow bezels. Summary of the Invention
[0003] To solve the above-mentioned technical problems, or at least partially solve them, this disclosure provides a display panel and a display device that reduce power consumption while facilitating narrow bezels.
[0004] This disclosure provides a display panel, comprising: a plurality of cascaded shift register units, each shift register unit including a first transistor and a first capacitor, the gate of the first transistor being electrically connected to a first plate of the first capacitor, the source of the first transistor being electrically connected to a clock signal line, the drain of the first transistor being electrically connected to the output terminal of the shift register unit, and a second plate of the first capacitor being electrically connected to the output terminal of the shift register unit; a substrate; a first metal layer located on one side of the substrate, the first metal layer including the gate of the first transistor, the gate portion of the first transistor being multiplexed as the first plate of the first capacitor; and a second metal layer located on the side of the first metal layer away from the substrate, the second metal layer including a first electrode. The first electrode portion includes a second electrode plate of a first capacitor, wherein the vertical projection of the first electrode plate of the first capacitor onto the plane of the substrate overlaps with the vertical projection of the second electrode plate of the first capacitor onto the plane of the substrate; a third metal layer is located on the side of the second metal layer away from the substrate, and the third metal layer includes a clock signal line extending along a first direction; along a second direction, the spacing between the vertical projection pattern of the clock signal line onto the plane of the substrate and the vertical projection pattern of the gate of the first transistor onto the plane of the substrate is less than the spacing between the vertical projection pattern of the clock signal line onto the plane of the substrate and the vertical projection pattern of the second electrode plate of the first capacitor onto the plane of the substrate, wherein the first direction and the second direction intersect.
[0005] This disclosure also provides a display device including the aforementioned display panel.
[0006] The technical solution provided in this disclosure has the following advantages compared with the prior art: The display panel disclosed herein includes a substrate, a first metal layer, a second metal layer, and a third metal layer. The first metal layer is located on one side of the substrate, the second metal layer is located on the side of the first metal layer away from the substrate, and the third metal layer is located on the side of the second metal layer away from the substrate. The first metal layer includes the gate of a first transistor, the second metal layer includes a first electrode portion, the first electrode portion includes a second plate of a first capacitor, and the third metal layer includes a clock signal line. A portion of the gate of the first transistor can be reused as the first plate of the first capacitor. The vertical projection of the first plate of the first capacitor onto the plane of the substrate overlaps with the vertical projection of the second plate of the first capacitor onto the plane of the substrate. That is, along a direction perpendicular to the plane of the substrate, a portion of the gate of the first transistor overlaps with the second plate of the first capacitor. This reuse of the gate of the first transistor as the first plate of the first capacitor helps to reduce the space occupied by the first capacitor and the first transistor as a whole, thereby helping to reduce the size of the shift register unit and facilitating a narrow bezel design for the display panel. Meanwhile, the clock signal line extends along the first direction. Along the second direction, the distance between the vertical projection pattern of the clock signal line on the plane of the substrate and the vertical projection pattern of the gate of the first transistor on the plane of the substrate is smaller than the distance between the vertical projection pattern of the clock signal line on the plane of the substrate and the vertical projection pattern of the second plate of the first capacitor on the plane of the substrate. That is, along the second direction, the distance between the clock signal line and the gate of the first transistor is smaller than the distance between the clock signal line and the second plate of the first capacitor. In other words, along the second direction, the distance between the clock signal line and the second plate of the first capacitor is larger. This helps to reduce the coupling between the clock signal line and the second plate of the first capacitor, thereby reducing the load on the clock signal line and reducing power consumption.
[0007] Correspondingly, the display device provided in this disclosure also has the above-mentioned technical effects. Attached Figure Description
[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0009] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0010] Figure 1 This is a partial layout diagram of a shift register unit in a display panel, as described in related technologies. Figure 2 This is a partial layout diagram of another shift register unit in a display panel in related technologies; Figure 3 This is a plan view of a display panel provided in this disclosure; Figure 4 This is a circuit diagram of a shift register unit provided in this disclosure; Figure 5 yes Figure 4 A partial layout diagram of the shift register unit described above; Figure 6 yes Figure 5 A cross-sectional view of the shift register unit along A-A'; Figure 7 yes Figure 4 Another partial layout diagram of the shift register unit; Figure 8 yes Figure 7 A cross-sectional view of the shift register unit along B-B'; Figure 9 This is a plan view of a display device provided in this disclosure. Detailed Implementation
[0011] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.
[0012] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.
[0013] In the field of display technology, the display area of a display panel typically includes multiple rows of gate lines and multiple columns of data lines intersecting with the gate lines. To simplify design and reduce costs, gate drive circuits comprising multiple cascaded shift register units are commonly used to drive the gate lines. For example, a gate drive on array (GOA) system comprising multiple cascaded shift registers can be used to provide scan signals to the multiple rows of gate lines in a pixel array, thereby controlling the sequential transmission of enable signals to the multiple rows of gate lines. The shift register units are typically located in the non-display area surrounding the display area, and the size of the shift register units directly affects the size of the non-display area.
[0014] Figure 1 This is a partial layout diagram of a shift register unit in a display panel, as shown in the related technology. Figure 1The shift register unit includes a capacitor C2, which can be placed on one side of the shift register unit. As a result, the shift register unit occupies a large space, which is not conducive to the narrow bezel design of the display panel.
[0015] Figure 2 This is a partial layout diagram of another shift register unit in a display panel, as shown in the related technology. Figure 2 The shift register unit includes capacitor C2. One plate of capacitor C2 can reuse the gate of transistor M8, which helps to reduce the size of the shift register unit. However, since the gate of transistor M8 is located adjacent to the clock signal line XCK and the distance between them is relatively small, reusing the gate of transistor M8 as one plate of capacitor C2 will increase the coupling capacitance between them, thereby increasing the load on the clock signal line XCK and thus increasing power consumption.
[0016] Based on this, the present disclosure provides a display panel and a display device that reduce power consumption while facilitating the achievement of narrow bezels.
[0017] The display panel and display device provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.
[0018] Figure 3 This is a plan view of a display panel provided in this disclosure. Figure 4 This is a circuit diagram of a shift register unit provided in this disclosure. Figure 5 yes Figure 4 A partial layout diagram of the shift register unit described above. Figure 6 yes Figure 5 A cross-sectional view of the shift register unit along A-A', see reference. Figures 3-6 This embodiment provides a display panel, which includes: a plurality of cascaded shift register units 10, each shift register unit 10 including a first transistor T1 and a first capacitor C1, the gate T11 of the first transistor T1 being electrically connected to the first plate C11 of the first capacitor C1, the source of the first transistor T1 being electrically connected to the clock signal line XCK, the drain of the first transistor T1 being electrically connected to the output terminal of the shift register unit 10, and the second plate C12 of the first capacitor C1 being electrically connected to the output terminal of the shift register unit 10; Substrate 21; The first metal layer 22 is located on one side of the substrate 21. The first metal layer 22 includes the gate T11 of the first transistor T1. The gate T11 of the first transistor T1 is partially multiplexed as the first plate C11 of the first capacitor C1. The second metal layer 23 is located on the side of the first metal layer 22 away from the substrate 21. The second metal layer 23 includes a first electrode portion 231, which includes a second electrode plate C12 of the first capacitor C1. The vertical projection of the first electrode plate C11 of the first capacitor C1 onto the plane where the substrate 21 is located overlaps with the vertical projection of the second electrode plate C12 of the first capacitor C1 onto the plane where the substrate 21 is located. The third metal layer 24 is located on the side of the second metal layer 23 away from the substrate 21. The third metal layer 24 includes a clock signal line XCK, which extends along the first direction X. Along the second direction Y, the distance between the vertical projection pattern of the clock signal line XCK on the plane of substrate 21 and the vertical projection pattern of the gate T11 of the first transistor T1 on the plane of substrate 21 is less than the distance between the vertical projection pattern of the clock signal line XCK on the plane of substrate 21 and the vertical projection pattern of the second plate C12 of the first capacitor C1 on the plane of substrate 21, wherein the first direction X and the second direction Y intersect.
[0019] Specifically, the display panel provided in this embodiment includes multiple cascaded shift register units 10. Optionally, the display panel includes a display area AA and a non-display area NA surrounding the display area AA. The display area AA is used for display, and the shift register units 10 are located in the non-display area NA. The shift register units 10 are used to provide gate scan signals to pixel units (not shown in the figure) located in the display area AA.
[0020] The shift register unit 10 includes a first transistor T1 and a first capacitor C1. The gate T11 of the first transistor T1 is electrically connected to the first plate C11 of the first capacitor C1. The source of the first transistor T1 is electrically connected to the clock signal line XCK. The drain of the first transistor T1 is electrically connected to the output terminal of the shift register unit 10. The second plate C12 of the first capacitor C1 is electrically connected to the output terminal of the shift register unit 10. It should be noted that... Figure 4 The present invention provides an exemplary circuit structure of shift register unit 10. In other embodiments of the present invention, shift register unit 10 may also have other circuit structures, which will not be described in detail here.
[0021] The display panel includes a substrate 21, a first metal layer 22, a second metal layer 23, and a third metal layer 24. The first metal layer 22, the second metal layer 23, and the third metal layer 24 are insulated from each other. The first metal layer 22 is located on one side of the substrate 21, the second metal layer 23 is located on the side of the first metal layer 22 away from the substrate 21, and the third metal layer 24 is located on the side of the second metal layer 23 away from the substrate 21. The first metal layer 22 includes the gate T11 of a first transistor T1, the second metal layer 23 includes a first electrode portion 231, the first electrode portion 231 includes the second electrode C12 of a first capacitor C1, and the third metal layer 24 includes a clock signal line XCK. A portion of the gate T11 of the first transistor T1 can be reused as the first plate C11 of the first capacitor C1. The vertical projection of the first plate C11 of the first capacitor C1 onto the plane of the substrate 21 overlaps with the vertical projection of the second plate C12 of the first capacitor C1 onto the plane of the substrate 21. That is, along the direction perpendicular to the plane of the substrate 21, a portion of the gate T11 of the first transistor T1 overlaps with the second plate C12 of the first capacitor C1. This portion of the gate T11 of the first transistor T1 is reused as the first plate C11 of the first capacitor C1, which helps to reduce the space occupied by the first capacitor C1 and the first transistor T1 as a whole, thereby helping to reduce the size of the shift register unit 10 and helping to achieve a narrow bezel of the display panel.
[0022] Simultaneously, the clock signal line XCK extends along the first direction X and along the second direction Y. The distance between the vertical projection pattern of the clock signal line XCK on the plane of substrate 21 and the vertical projection pattern of the gate T11 of the first transistor T1 on the plane of substrate 21 is d1, and the distance between the vertical projection pattern of the clock signal line XCK on the plane of substrate 21 and the vertical projection pattern of the second plate C12 of the first capacitor C1 on the plane of substrate 21 is d2. The first direction X and the second direction Y intersect. Optionally, the first direction X and the second direction Y are perpendicular. d1 < d2, meaning that along the second direction Y, the distance between the clock signal line XCK and the gate T11 of the first transistor T1 is less than the distance between the clock signal line XCK and the second plate C12 of the first capacitor C1, i.e., the distance between the clock signal line XCK and the second plate C12 of the first capacitor C1 is larger. This helps to reduce the coupling between the clock signal line XCK and the second plate C12 of the first capacitor C1, thereby reducing the load on the clock signal line XCK and reducing power consumption.
[0023] Figure 7 yes Figure 4 Another partial layout diagram of the shift register unit, Figure 8 yes Figure 7 A cross-sectional view of the shift register unit along B-B', see reference. Figure 3 , Figure 4 , Figure 7 and Figure 8 In some optional embodiments, the gate T11 of the first transistor T1 includes at least two first sub-gates T111 extending along the first direction X and arranged along the second direction Y, and the first plate C11 of the first capacitor C1 includes at least two first sub-plates C111, and a portion of each first sub-gate T111 is reused as each first sub-plate C111. The first electrode portion 231 includes at least two sub-electrode portions 2311 extending along the first direction X and arranged along the second direction Y. The second electrode plate C12 of the first capacitor C1 includes at least two second sub-electrode plates C121, and each sub-electrode portion 2311 includes one second sub-electrode plate C121. The first sub-gate T111 and the sub-electrode 2311 are arranged in a one-to-one correspondence. In the same set of corresponding first sub-gate T111 and sub-electrode 2311, the vertical projection of the first sub-electrode C111 on the plane where the substrate 21 is located and the vertical projection of the second sub-electrode C121 on the plane where the substrate 21 is located are overlapped in a one-to-one correspondence.
[0024] Specifically, the gate T11 of the first transistor T1 includes at least two first sub-gates T111 extending along the first direction X and arranged along the second direction Y. A portion of each first sub-gate T111 is reused as a first sub-plate C111 of the first electrode C11 of the first capacitor C1. The first electrode portion 231 includes at least two sub-electrode portions 2311 extending along the first direction X and arranged along the second direction Y. Each sub-electrode portion 2311 includes a second sub-plate C121 of the second electrode C12 of the first capacitor C1. Thus, the first electrode C11 of the first capacitor C1 includes at least two first sub-electrodes C111, and the second electrode C12 of the first capacitor C1 includes at least two second sub-electrodes C121. The first sub-gate T111 and the sub-electrode portion 2311 are arranged in a one-to-one correspondence, so that the first sub-electrodes C111 and the second sub-electrodes C121 are arranged in a one-to-one correspondence. In the same set of corresponding first sub-gate T111 and sub-electrode portion 2311, the vertical projection of the first sub-electrode C111 on the plane where the substrate 21 is located and the vertical projection of the second sub-electrode C121 on the plane where the substrate 21 is located overlap one-to-one. The overlapping part forms a sub-capacitor of the first capacitor C1. The arrangement of multiple sub-capacitors can increase the capacitance of the first capacitor C1.
[0025] It should be noted that, Figure 7The example shows that the gate T11 of the first transistor T1 includes two first sub-gates T111, and correspondingly, the first electrode C11 of the first capacitor C1 includes two first sub-electrode C111, the first electrode portion 231 includes two sub-electrode portions 2311, and correspondingly, the second electrode C12 of the first capacitor C1 includes two second sub-electrode C121. In other embodiments of this disclosure, the number of first sub-gates T111 and sub-electrode portions 2311 may be three or more, and correspondingly, the number of first sub-electrode C111 and second sub-electrode C121 may also be three or more, which will not be elaborated further in this disclosure.
[0026] Continue to refer to Figure 3 , Figure 4 , Figure 7 and Figure 8 In some optional embodiments, the first metal layer 22 further includes a first connection portion 221, each of the first sub-gates T111 is connected to the first connection portion 221, and along the first direction X, the first connection portion 221 is located on at least one side of the first sub-gate T111 that is electrically connected to it. The second metal layer 23 also includes a second connection portion 232, each sub-electrode portion 2311 is connected to the second connection portion 232, and along the first direction X, the second connection portion 232 is located on at least one side of the sub-electrode portion 2311 that is electrically connected to it.
[0027] Specifically, the gate T11 of the first transistor T1 includes at least two first sub-gates T111 extending along the first direction X and arranged along the second direction Y. The first metal layer 22 also includes a first connection portion 221. Each first sub-gate T111 is connected to the first connection portion 221. Along the first direction X, the first connection portion 221 is located on at least one side of the first sub-gate T111 that is electrically connected to it, thereby realizing the transmission of signals to each first sub-gate T111.
[0028] The first electrode portion 231 includes at least two sub-electrode portions 2311 extending along a first direction X and arranged along a second direction Y. The second metal layer 23 also includes a second connecting portion 232. Each sub-electrode portion 2311 is connected to the second connecting portion 232. Along the first direction X, the second connecting portion 232 is located on at least one side of the sub-electrode portion 2311 that is electrically connected to it, thereby realizing the transmission of signals to each sub-electrode portion 2311.
[0029] Continue to refer to Figure 3 , Figure 4 , Figure 7 and Figure 8 In some alternative embodiments, at least one set of corresponding first sub-gate T111 and sub-electrode 2311 are provided on both sides of the clock signal line XCK along the second direction Y.
[0030] Specifically, along the second direction Y, at least one set of corresponding first sub-gate T111 and sub-electrode 2311 are provided on both sides of the clock signal line XCK. That is, along the second direction Y, the clock signal line XCK can be set between different sets of corresponding first sub-gate T111 and sub-electrode 2311, which helps to reduce layout area waste, improve the overall integration density of the shift register unit 10, thereby helping to reduce the size of the shift register unit 10 and help to achieve a narrow bezel of the display panel.
[0031] Continue to refer to Figure 3 , Figure 4 , Figure 7 and Figure 8 In some alternative embodiments, in the same set of corresponding first sub-gates T111 and sub-electrodes 2311, along the second direction Y, the spacing between the vertical projection pattern of the clock signal line XCK on the plane of the substrate 21 and the vertical projection pattern of the first sub-gate T111 on the plane of the substrate 21 is smaller than the spacing between the vertical projection pattern of the clock signal line XCK on the plane of the substrate 21 and the vertical projection pattern of the sub-electrodes 2311 on the plane of the substrate 21.
[0032] Specifically, the clock signal line XCK extends along the first direction X. In the same set of corresponding first sub-gate T111 and sub-electrode 2311, along the second direction Y, the distance between the vertical projection pattern of the clock signal line XCK on the plane of substrate 21 and the vertical projection pattern of the first sub-gate T111 on the plane of substrate 21 is smaller than the distance between the vertical projection pattern of the clock signal line XCK on the plane of substrate 21 and the vertical projection pattern of the sub-electrode 2311 on the plane of substrate 21. That is, along the second direction Y, the distance between the clock signal line XCK and the first sub-gate T111 of the first transistor T1 is smaller than the distance between the clock signal line XCK and the sub-electrode 2311. In other words, the distance between the clock signal line XCK and the sub-electrode 2311 is larger in the second direction Y. Therefore, the distance between the clock signal line XCK and the second sub-electrode C121 is larger in the second direction Y, which helps to reduce the coupling between the clock signal line XCK and the first capacitor C1, thereby reducing the load on the clock signal line XCK and reducing power consumption.
[0033] For example, refer to Figure 7Along the second direction Y, in a set of corresponding first sub-gates T111 and sub-electrodes 2311 located on one side of the clock signal line XCK, the distance between the vertical projection pattern of the clock signal line XCK onto the plane of substrate 21 and the vertical projection pattern of the first sub-gate T111 onto the plane of substrate 21 is d1, and the distance between the vertical projection pattern of the clock signal line XCK onto the plane of substrate 21 and the vertical projection pattern of the sub-electrode 2311 onto the plane of substrate 21 is d2, where d1 < d2. Along the second direction Y, in a set of corresponding first sub-gates T111 and sub-electrodes 2311 located on the other side of the clock signal line XCK, the distance between the vertical projection pattern of the clock signal line XCK onto the plane of substrate 21 and the vertical projection pattern of the first sub-gate T111 onto the plane of substrate 21 is d3, and the distance between the vertical projection pattern of the clock signal line XCK onto the plane of substrate 21 and the vertical projection pattern of the sub-electrode 2311 onto the plane of substrate 21 is d4, where d3 < d3. Optionally, d3 can be the same as d1, or d3 can be different from d1. Optionally, d4 can be the same as d2, or d4 can be different from d2.
[0034] Continue to refer to Figure 3 , Figure 4 , Figure 7 and Figure 8 In some alternative embodiments, in the same set of corresponding first sub-gate T111 and sub-electrode portion 2311, the width of the second sub-electrode plate C121 along the second direction Y is smaller than the width of the first sub-gate T111 along the second direction Y.
[0035] Specifically, in the same set of corresponding first sub-gate T111 and sub-electrode 2311, the width of the second sub-electrode C121 along the second direction Y is H1, and the width of the first sub-gate T111 along the second direction Y is H2, where H1 < H2. That is, in the same set of corresponding first sub-gate T111 and sub-electrode 2311, the width of the second sub-electrode C121 along the second direction Y is smaller than that of the first sub-gate T111. This allows the spacing between the vertical projection pattern of the clock signal line XCK on the plane of substrate 21 and the vertical projection pattern of the first sub-gate T111 on the plane of substrate 21 along the second direction Y in the same set of corresponding first sub-gate T111 and sub-electrode 2311 to be smaller than the spacing between the vertical projection pattern of the clock signal line XCK on the plane of substrate 21 and the vertical projection pattern of the sub-electrode 2311 on the plane of substrate 21.
[0036] Continue to refer to Figure 3 , Figure 4 , Figure 7 and Figure 8In some alternative embodiments, the sub-electrode portion 2311 further includes an extension portion 23111 connected to the second sub-electrode plate C121. The extension portion 23111 is located on the side of the second sub-electrode plate C121 away from the clock signal line XCK. The vertical projection of the extension portion 23111 onto the plane of the substrate 21 and the vertical projection of the corresponding first sub-gate T111 onto the plane of the substrate 21 do not overlap.
[0037] Specifically, along the second direction Y, at least one set of corresponding first sub-gates T111 and sub-electrodes 2311 are provided on both sides of the clock signal line XCK. That is, along the second direction Y, the clock signal line XCK can be disposed between different sets of corresponding first sub-gates T111 and sub-electrodes 2311. At the same time, the sub-electrode 2311 also includes an extension 23111 connected to the second sub-electrode C121. The extension 23111 is located on the side of the second sub-electrode C121 away from the clock signal line XCK. The vertical projection of the extension 23111 onto the plane of the substrate 21 and the corresponding first sub-gate T111 onto the substrate are shown in the figure. Since the vertical projections of the plane containing 21 do not overlap, when the first sub-gate T111 and the sub-electrode 2311 overlap and misalign during the manufacturing process, the overlapping area between a pair of corresponding first sub-gate T111 and sub-electrode 2311 on one side of the clock signal line XCK along the second direction Y will decrease, and the overlapping area between a pair of corresponding first sub-gate T111 and sub-electrode 2311 on the other side of the clock signal line XCK along the second direction Y will increase accordingly. This reduces the impact on the capacitance of the first capacitor C1, which helps to reduce the difficulty of the display panel manufacturing process and reduce production costs.
[0038] Optionally, along the second direction Y, corresponding first sub-gates T111 and sub-electrodes 2311 are provided on both sides of the clock signal line XCK. That is, along the second direction Y, the clock signal line XCK can be centrally located between each group of corresponding first sub-gates T111 and sub-electrodes 2311. Thus, during the manufacturing process, when the first sub-gates T111 and sub-electrodes 2311 overlap and misalign, the overlap area between the corresponding group of first sub-gates T111 and sub-electrodes 2311 on one side of the clock signal line XCK along the second direction Y will decrease, and the overlap area between the corresponding group of first sub-gates T111 and sub-electrodes 2311 on the other side of the clock signal line XCK along the second direction Y will increase accordingly. Therefore, the capacitance of the first capacitor C1 can remain unchanged, which helps to reduce the difficulty of the display panel manufacturing process and reduce production costs.
[0039] Continue to refer to Figure 3 , Figure 4 , Figure 7 and Figure 8In some alternative embodiments, in the same sub-electrode portion 2311, the length of the extension portion 23111 along the first direction X is the same as the length of the second sub-electrode plate C121 along the first direction X.
[0040] Specifically, during the manufacturing process, when the first sub-gate T111 and the sub-electrode 2311 overlap and become misaligned, the overlapping area between a set of corresponding first sub-gate T111 and sub-electrode 2311 on one side of the clock signal line XCK along the second direction Y will decrease, and the overlapping area between a set of corresponding first sub-gate T111 and sub-electrode 2311 on the other side of the clock signal line XCK along the second direction Y will increase accordingly. That is, the extension 23111 can become the second sub-electrode C121, and a portion of the second sub-electrode C121 can become the extension 23111. Since the length of the extension 23111 along the first direction X in the same sub-electrode 2311 is the same as the length of the second sub-electrode C121 along the first direction X, the reduced area and the increased area can remain the same, which can reduce the impact on the capacitance of the first capacitor C1, which is beneficial to reduce the difficulty of the display panel manufacturing process and reduce production costs.
[0041] Continue to refer to Figure 3 , Figure 4 , Figure 7 and Figure 8 In some alternative embodiments, along the first direction X, the first connection portion 221 is located on one side of the first sub-gate T111 electrically connected thereto, and the vertical projection of the clock signal line XCK on the plane where the substrate 21 is located overlaps with the vertical projection of the first connection portion 221 on the plane where the substrate 21 is located. Along the first direction X, the second connection portion 232 is located on the side of the sub-electrode portion 2311 that is electrically connected to it, away from the first connection portion 221.
[0042] Specifically, along the first direction X, the first connection portion 221 is located on one side of the first sub-gate T111 electrically connected to it. Along the second direction Y, at least one set of corresponding first sub-gate T111 and sub-electrode portion 2311 are provided on both sides of the clock signal line XCK. That is, along the second direction Y, the clock signal line XCK can be disposed between different sets of corresponding first sub-gate T111 and sub-electrode portion 2311, so that the clock signal line XCK extends through the area corresponding to the first connection portion 221. That is, the vertical projection of the clock signal line XCK on the plane of the substrate 21 overlaps with the vertical projection of the first connection portion 221 on the plane of the substrate 21. Along the first direction X, the second connection portion 232 is located on the side of the sub-electrode portion 2311 that is electrically connected to it, away from the first connection portion 221. This allows the vertical projection of the clock signal line XCK onto the plane of the substrate 21 to not overlap with the vertical projection of the second connection portion 232 onto the plane of the substrate 21. This reduces the coupling between the clock signal line XCK and the second connection portion 232, thereby reducing the coupling between the clock signal line XCK and the first capacitor C1, and thus reducing the load on the clock signal line XCK, which helps to reduce power consumption.
[0043] like Figure 9 As shown, Figure 9 This is a plan view of a display device provided in this disclosure. This embodiment provides a display device 1000, which includes a display panel 100 provided in this disclosure embodiment. It is understood that the display device provided in this disclosure embodiment can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This disclosure embodiment does not make any special limitations on these categories.
[0044] The display device provided in this disclosure has the same technical features as the display panel provided in the above embodiments, so it can also solve the same technical problems and achieve the same technical effects.
[0045] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0046] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A display panel, characterized in that, include: Multiple cascaded shift register units, each shift register unit including a first transistor and a first capacitor, wherein the gate of the first transistor is electrically connected to the first plate of the first capacitor, the source of the first transistor is electrically connected to a clock signal line, the drain of the first transistor is electrically connected to the output terminal of the shift register unit, and the second plate of the first capacitor is electrically connected to the output terminal of the shift register unit. Substrate; A first metal layer is located on one side of the substrate. The first metal layer includes the gate of the first transistor, and the gate portion of the first transistor is multiplexed as the first plate of the first capacitor. The second metal layer is located on the side of the first metal layer away from the substrate. The second metal layer includes a first electrode portion, which includes a second electrode plate of the first capacitor. The vertical projection of the first electrode plate of the first capacitor onto the plane where the substrate is located overlaps with the vertical projection of the second electrode plate of the first capacitor onto the plane where the substrate is located. A third metal layer is located on the side of the second metal layer away from the substrate, and the third metal layer includes the clock signal line, which extends along a first direction; Along the second direction, the distance between the vertical projection pattern of the clock signal line on the plane of the substrate and the vertical projection pattern of the gate of the first transistor on the plane of the substrate is less than the distance between the vertical projection pattern of the clock signal line on the plane of the substrate and the vertical projection pattern of the second plate of the first capacitor on the plane of the substrate, wherein the first direction and the second direction intersect.
2. The display panel according to claim 1, characterized in that, The gate of the first transistor includes at least two first sub-gates extending along the first direction and arranged along the second direction, and the first plate of the first capacitor includes at least two first sub-plates, with portions of each first sub-gate being multiplexed as each first sub-plate. The first electrode portion includes at least two sub-electrode portions extending along the first direction and arranged along the second direction, and the second electrode plate of the first capacitor includes at least two second sub-electrode plates, with each of the sub-electrode portions including one second sub-electrode plate. The first sub-gate and the sub-electrode are arranged in a one-to-one correspondence. In the same set of corresponding first sub-gates and sub-electrodes, the vertical projection of the first sub-electrode on the plane where the substrate is located and the vertical projection of the second sub-electrode on the plane where the substrate is located are arranged in a one-to-one correspondence and overlap.
3. The display panel according to claim 2, characterized in that, The first metal layer further includes a first connection portion, each of the first sub-gates is connected to the first connection portion, and along the first direction, the first connection portion is located on at least one side of the first sub-gate electrically connected to it; The second metal layer further includes a second connection portion, each of the sub-electrode portions being connected to the second connection portion, and along the first direction, the second connection portion is located on at least one side of the sub-electrode portion electrically connected to it.
4. The display panel according to claim 3, characterized in that, Along the second direction, at least one set of corresponding first sub-gate and sub-electrode portions are provided on both sides of the clock signal line.
5. The display panel according to claim 4, characterized in that, In the same set of corresponding first sub-gate and sub-electrode portions, along the second direction, the spacing between the vertical projection pattern of the clock signal line on the plane of the substrate and the vertical projection pattern of the first sub-gate on the plane of the substrate is smaller than the spacing between the vertical projection pattern of the clock signal line on the plane of the substrate and the vertical projection pattern of the sub-electrode portion on the plane of the substrate.
6. The display panel according to claim 5, characterized in that, In the same set of corresponding first sub-gate and sub-electrode portions, the width of the second sub-electrode plate along the second direction is smaller than the width of the first sub-gate along the second direction.
7. The display panel according to claim 4, characterized in that, The sub-electrode portion further includes an extension connected to the second sub-electrode plate. The extension is located on the side of the second sub-electrode plate away from the clock signal line. The vertical projection of the extension onto the plane of the substrate and the vertical projection of the corresponding first sub-gate onto the plane of the substrate do not overlap.
8. The display panel according to claim 7, characterized in that, In the same sub-electrode portion, the length of the extension portion along the first direction is the same as the length of the second sub-electrode plate along the first direction.
9. The display panel according to claim 4, characterized in that, Along the first direction, the first connection portion is located on one side of the first sub-gate electrically connected thereto, and the vertical projection of the clock signal line on the plane where the substrate is located overlaps with the vertical projection portion of the first connection portion on the plane where the substrate is located. Along the first direction, the second connection portion is located on the side of the sub-electrode portion that is electrically connected to it, away from the first connection portion.
10. A display device, characterized in that, The display device includes the display panel as described in any one of claims 1-9.