Display device

Abstract

The present invention can provide a display device capable of achieving a narrow frame. In general, according to an embodiment, a display device includes: a display area; a peripheral region outside the display region; a plurality of scanning lines extending in a first direction and arranged in a second direction intersecting the first direction; a first semiconductor layer disposed in the display region and overlapping the plurality of scanning lines; and a second semiconductor layer disposed in the peripheral region and overlapping one of the plurality of scanning lines, the second semiconductor layer including a first dummy semiconductor patterned in an identification symbol shape.

Description

Cross-references of related applications

[0001] This application claims priority based on Japanese Patent Application No. 2024-185730, filed on October 22, 2024, and incorporates all the contents of that Japanese Patent Application. Technical Field

[0002] Embodiments of the present invention relate to display devices. Background Technology

[0003] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. These display devices require technologies that enable narrow bezels. Summary of the Invention

[0004] In general, according to the embodiments, the display device includes: a display area; a peripheral area outside the display area; a plurality of scan lines extending in a first direction and arranged in a second direction intersecting the first direction; a first semiconductor layer disposed in the display area and overlapping the plurality of scan lines; and a second semiconductor layer disposed in the peripheral area and overlapping one of the plurality of scan lines, the second semiconductor layer comprising a first dummy semiconductor patterned into the shape of an identification symbol.

[0005] According to other embodiments, the display device includes: a display area; a peripheral area outside the display area; a plurality of scan lines extending in a first direction and arranged in a second direction intersecting the first direction; a first semiconductor layer disposed in the display area and overlapping the plurality of scan lines; and a second semiconductor layer disposed in the peripheral area and overlapping the plurality of scan lines, the second semiconductor layer comprising a first segment overlapping one of the scan lines adjacent in the second direction and a second segment overlapping another of the scan lines adjacent in the second direction and separated from the first segment, the combination of the first segment and the second segment constituting an identification symbol shape.

[0006] According to the implementation method, a display device capable of achieving narrow bezels can be provided. Attached Figure Description

[0007] Figure 1 This is a diagram showing an example of the configuration of the display device according to this embodiment.

[0008] Figure 2 This is a circuit diagram illustrating an example of the configuration in which the pixel circuits of each sub-pixel can be applied.

[0009] Figure 3 This is a schematic top view showing an example of the layout of subpixels.

[0010] Figure 4 It shows along Figure 3 A schematic cross-sectional view of the display device for the IV-IV line.

[0011] Figure 5 This is a schematic cross-sectional view showing an example of the layer configuration that can be applied in a circuit layer.

[0012] Figure 6 This is a diagram illustrating an example of the configuration of transistors contained in a circuit layer.

[0013] Figure 7 This is a schematic top view showing an example of the boundary between the displayed area and the surrounding area.

[0014] Figure 8 It shows along Figure 7 A schematic cross-sectional view of the display device for lines VIII-VIII.

[0015] Figure 9 This is a schematic top view showing an example of the structure of scan lines, semiconductors, and dummy semiconductors.

[0016] Figure 10 This is a schematic top view showing another example of the structure of scan lines and dummy semiconductors.

[0017] Figure 11 This is a diagram showing an example of the shape of an identification symbol.

[0018] Figure 12 This is a cross-sectional view used to illustrate the effect of the display device in this embodiment.

[0019] Figure 13 This is another example of the shape of an identification symbol. Detailed Implementation

[0020] Several implementation methods are described with reference to the accompanying drawings.

[0021] The disclosed example is merely one instance; appropriate modifications that maintain the spirit of the invention, and modifications readily conceived by those skilled in the art, are naturally included within the scope of this invention. Furthermore, to make the description clearer, the width, thickness, shape, etc., of various parts in the drawings are sometimes schematically represented compared to the actual embodiment, but these are merely examples and not intended to limit the interpretation of the invention. Additionally, in this specification and the figures, elements that perform the same or similar functions as those described with respect to the preceding figures are sometimes labeled with the same reference numerals, and repetitive detailed descriptions are appropriately omitted.

[0022] It should be noted that, for ease of understanding, the accompanying drawings show mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction (direction 1), the direction along the Y-axis is called the Y-direction (direction 2), and the direction along the Z-axis is called the Z-direction. Furthermore, observing various elements parallel to the Z-direction is called a top-down view.

[0023] The display device in each embodiment is an organic electroluminescent display device that uses organic light-emitting diodes (OLEDs) as display elements, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle devices, tablet computers, smartphones, mobile terminals, and wearable terminals.

[0024] Figure 1 This diagram illustrates a configuration example of the display device DSP according to this embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film. The Z-direction corresponds to the thickness direction of the substrate 10.

[0025] In this embodiment, the substrate 10 is circular when viewed from above. However, the shape of the substrate 10 when viewed from above is not limited to a circle, and may also be other shapes such as rectangle, square or ellipse.

[0026] The display area DA has a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX contains a plurality of sub-pixels SP that display different colors. In this embodiment, it is envisioned that the pixel PX contains a green sub-pixel SP1, a blue sub-pixel SP2, and a red sub-pixel SP3. However, the pixel PX may also contain sub-pixels SP of other colors, such as white, together with or replacing any of the sub-pixels SP1, SP2, and SP3.

[0027] The display device DSP also includes a terminal section T disposed in the peripheral area SA. The terminal section T is connected to a flexible circuit board that supplies, for example, voltage and signals for driving the display device DSP.

[0028] Figure 2 This is a circuit diagram illustrating an example of the configuration of a pixel circuit PC that can be applied to each of the sub-pixels SP (SP1, SP2, SP3). The pixel circuit PC shown in the diagram includes seven transistors TR1 to TR7 and one holding capacitor Cst.

[0029] In the following description, one of the source and drain electrodes of transistors TR1 to TR7 will be referred to as electrode 1, and the other as electrode 2. Similarly, one electrode of the holding capacitor Cst will be referred to as electrode 1, and the other as electrode 2.

[0030] The first electrode of transistor TR1 is connected to node n3. The second electrode of transistor TR1 is connected to the signal line SL that supplies the image signal Sdata. The image signal Sdata is the signal written to the pixels for image display.

[0031] Transistor TR2 is equivalent to the driving transistor that supplies current to the display element DE contained in the sub-pixel SP. The first electrode of transistor TR2 is connected to node n1. The second electrode of transistor TR2 is connected to node n3.

[0032] The first electrode of transistor TR3 is connected to node n1. The second electrode of transistor TR3 is connected to node n2.

[0033] The first electrode of transistor TR4 is connected to node n1. The second electrode of transistor TR4 is connected to the power supply line PL1, which supplies the power supply voltage VDDEL.

[0034] The first electrode of transistor TR5 is connected to node n3. The second electrode of transistor TR5 is connected to node n4.

[0035] The first electrode of transistor TR6 is connected to node n4. The second electrode of transistor TR6 is connected to the initialization line IL, which supplies the initialization voltage Vini.

[0036] The first electrode of transistor TR7 is connected to node n1. The second electrode of transistor TR7 is connected to the power supply line PL2, which supplies the power supply voltage VSH.

[0037] Keep the first electrode of capacitor Cst connected to node n2. Keep the second electrode of capacitor Cst connected to node n4.

[0038] The gate electrode of transistor TR1 is connected to scan line GL1, which supplies scan signal Sg1. The gate electrodes of transistors TR4, TR5, and TR6 are each connected to scan line GL2, which supplies scan signal Sg2. The gate electrode of transistor TR3 is connected to scan line GL3, which supplies scan signal Sg3. The gate electrode of transistor TR7 is connected to scan line GL4, which supplies scan signal Sg4.

[0039] Node n4 is connected to the anode of display element DE. The cathode of display element DE is connected to power line PL3, which supplies power voltage VSSEL. The aforementioned power voltage VDDEL is equivalent to the anode voltage supplied to display element DE, and the power voltage VSSEL is equivalent to the cathode voltage supplied to display element DE.

[0040] It should be noted that the configuration of the pixel circuit PC is not limited to... Figure 2The example shown. For instance, the pixel circuit PC may have 6 or fewer transistors or 8 or more transistors. Additionally, the pixel circuit PC has multiple holding capacitors Cst.

[0041] Figure 3 This is a schematic top view showing an example of the layout of subpixels SP1, SP2, and SP3. Figure 3 In the example, subpixels SP2 and SP3 are arranged in the X direction along with subpixel SP1. Furthermore, subpixels SP2 and SP3 are arranged in the Y direction.

[0042] With sub-pixels SP1, SP2, and SP3 arranged in this layout, the display area DA contains columns of sub-pixels SP2 and SP3 arranged alternately in the Y direction, and multiple columns of sub-pixels SP1 arranged repeatedly in the Y direction. These columns are arranged alternately in the X direction. It should be noted that the layout of sub-pixels SP1, SP2, and SP3 is not limited to this. Figure 3 Examples.

[0043] A rib layer 5 is configured in the display area DA. Rib layer 5 has pixel openings AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. Figure 3 In the example, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3. That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio. It should be noted that the size and shape of pixel apertures AP1, AP2, and AP3 are not limited to the example shown in the attached figure.

[0044] Sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel opening AP1. Sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel opening AP2. Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel opening AP3.

[0045] The portion of the lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 overlapping with the pixel opening AP1 constitutes the display element DE1 of sub-pixel SP1. The portion of the lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 overlapping with the pixel opening AP2 constitutes the display element DE2 of sub-pixel SP2. The portion of the lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 overlapping with the pixel opening AP3 constitutes the display element DE3 of sub-pixel SP3. Display elements DE1, DE2, and DE3 may also include a capping layer described later. Rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0046] A conductive partition 6 is disposed in the display area DA. The partition 6 is located above the rib layer 5 and overlaps with the rib layer 5 in general. Figure 3 In this example, partition 6 has the same planar shape as rib 5. That is, partition 6 has openings in sub-pixels SP1, SP2, and SP3 respectively. From another perspective, rib 5 and partition 6 appear as a grid when viewed from above, surrounding each of the display elements DE1, DE2, and DE3. Partition 6 serves as wiring that supplies a common voltage to the upward electrodes UE1, UE2, and UE3.

[0047] Figure 4 It is along Figure 3 A schematic cross-sectional view of the display device DSP with IV-IV lines. A circuit layer 11 is disposed on the substrate 10 described above. The circuit layer 11 includes... Figure 2 The diagram shows various circuits and wiring, including pixel circuit PC, scan lines GL1-GL4, signal lines SL, power lines PL1-PL3, and initialization line IL. Circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film to flatten the unevenness created by circuit layer 11.

[0048] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12 and are separated from each other. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The periphery of the lower electrodes LE1, LE2, and LE3 is covered by the rib layer 5. Figure 4 The cross-section is not shown. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuit PC of the circuit layer 11 through contact holes provided in the organic insulating layer 12.

[0049] The partition 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the sides of the lower portion 61. Such a shape of the partition 6 is called a cantilever.

[0050] exist Figure 4 In this example, the lower portion 61 has a bottom layer 63 disposed above the rib layer 5 and a shaft layer 64 disposed above the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the shaft layer 64. Figure 4 In this example, the two ends of the bottom layer 63 protrude from the sides of the shaft layer 64. Furthermore, when viewed from above, the ends of the bottom layer 63 are located between the ends of the upper portion 62 and the sides of the shaft layer 64. The upper portion 62 is positioned above the shaft layer 64.

[0051] Organic layer OR1 covers lower electrode LE1 through pixel opening AP1. Upper electrode UE1 covers organic layer OR1 and is opposite to lower electrode LE1. Organic layer OR2 covers lower electrode LE2 through pixel opening AP2. Upper electrode UE2 covers organic layer OR2 and is opposite to lower electrode LE2. Organic layer OR3 covers lower electrode LE3 through pixel opening AP3. Upper electrode UE3 covers organic layer OR3 and is opposite to lower electrode LE3. Upper electrodes UE1, UE2, and UE3 are in contact with the side of the lower part 61 of partition 6.

[0052] Display element DE1 includes a capping layer CP1 covering the upper electrode UE1. Display element DE2 includes a capping layer CP2 covering the upper electrode UE2. Display element DE3 includes a capping layer CP3 covering the upper electrode UE3. The capping layers CP1, CP2, and CP3 respectively serve as optical adjustment layers to improve the light extraction efficiency emitted by the organic layers OR1, OR2, and OR3.

[0053] In the following description, the multilayer containing organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as laminated film FL1, the multilayer containing organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as laminated film FL2, and the multilayer containing organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as laminated film FL3.

[0054] Sub-pixels SP1, SP2, and SP3 are respectively provided with sealing layers SE11, SE12, and SE13 covering the laminated films FL1, FL2, and FL3. Sealing layer SE11 continuously covers display element DE1 and its surrounding partition 6. Sealing layer SE12 continuously covers display element DE2 and its surrounding partition 6. Sealing layer SE13 continuously covers display element DE3 and its surrounding partition 6.

[0055] exist Figure 4 In the example, the sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition 6. Additionally, the sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition 6. However, any two of the sealing layers SE11, SE12, and SE13 can be in contact above the partition 6.

[0056] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. Laminated membranes FL1, FL2, FL3 may also be disposed in at least a portion of these gaps.

[0057] Sealing layers SE11, SE12, and SE13 are covered by resin layer RS1. Resin layer RS1 is covered by sealing layer SE2. Sealing layer SE2 is covered by resin layer RS2. Resin layers RS1, RS2, and sealing layer SE2 are continuously disposed throughout the entire display area DA, with a portion extending to the peripheral area SA. Figure 4 In the text, elements above the resin layer RS2 are omitted.

[0058] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of resin materials (organic insulating materials) such as epoxy resin and acrylic resin.

[0059] The lower electrodes LE1, LE2, and LE3 have a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed from a metallic material with excellent light reflectivity, such as silver. Each conductive oxide layer can be formed from a transparent conductive oxide, such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0060] The upper electrodes UE1, UE2, and UE3 are formed of metallic materials such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0061] The capping layers CP1, CP2, and CP3 have a stacked structure, for example, consisting of multiple overlapping transparent layers. These transparent layers can include layers formed of inorganic materials and layers formed of organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers differ from the refractive indices of the upper electrodes UE1, UE2, and UE3, and the refractive indices of the sealing layers SE11, SE12, and SE13. It should be noted that at least one of the capping layers CP1, CP2, and CP3 may be omitted.

[0062] The bottom layer 63 and the axial layer 64 of the partition 6 are formed of, for example, metallic materials. For example, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material for the bottom layer 63. For example, aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used as the metallic material for the axial layer 64. It should be noted that at least one of the bottom layer 63 and the axial layer 64 may also have a multi-layered structure. Additionally, the axial layer 64 may also include a layer formed of an insulating material.

[0063] For example, the upper portion 62 of partition 6 has a laminated structure consisting of a lower layer made of a metallic material and an upper layer made of a conductive oxide. Examples of metallic materials forming the lower layer include titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloys, or molybdenum-niobium alloys. Examples of conductive oxides forming the upper layer include ITO or IZO. It should be noted that the upper portion 62 may also have a single-layer structure of metallic material. Furthermore, the upper portion 62 may also include a layer formed of an insulating material.

[0064] The partition 6 is supplied with a common voltage. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the sides of the lower part 61, respectively. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the image signals of the signal line SL through the pixel circuits PC of the sub-pixels SP1, SP2, and SP3, respectively.

[0065] In one example, the organic layers OR1, OR2, and OR3 are configured to emit light of different colors. In another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 can also emit light of the same color (e.g., white). In this case, the display device DSP can also include a color filter that converts the light emitted by each light-emitting layer included in the organic layers OR1, OR2, and OR3 into light of colors corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP can also include a layer containing quantum dots that generate light of colors corresponding to the sub-pixels SP1, SP2, and SP3 when excited by light emitted from the light-emitting layers.

[0066] Figure 5 This is a schematic cross-sectional view showing an example of a layer configuration that can be applied to circuit layer 11. Figure 5 In the example shown, circuit layer 11 includes semiconductor layer 31, metal layers 32, 33, 34, 35, inorganic insulating layers 41, 42, 43, 44, 45 and organic insulating layer 46.

[0067] For example, semiconductor layer 31 corresponds to the bottom layer of circuit layer 11. However, an insulating layer can also be disposed below semiconductor layer 31. Inorganic insulating layer 41 covers semiconductor layer 31. Metal layer 32 is disposed on inorganic insulating layer 41. Inorganic insulating layer 42 covers metal layer 32. Inorganic insulating layer 43 covers inorganic insulating layer 42. Metal layer 33 is disposed on inorganic insulating layer 43. Inorganic insulating layer 44 covers metal layer 33. Metal layer 34 is disposed on inorganic insulating layer 44. Inorganic insulating layer 45 covers metal layer 34. Organic insulating layer 46 covers inorganic insulating layer 45. Metal layer 35 is disposed on organic insulating layer 46, by... Figure 4 The organic insulating layer 12 shown is used for covering.

[0068] Semiconductor layer 31 is formed, for example, from polycrystalline silicon, amorphous silicon, or oxide semiconductor. Metal layers 32-35 can be constructed using a single-layer structure or a stacked structure of multiple metal materials. In one example, metal layers 32 and 33 are formed from a molybdenum-tungsten alloy (MoW), and metal layers 34 and 35 are formed from a stacked structure (so-called TAT) in which an aluminum layer is sandwiched between a pair of titanium layers.

[0069] The inorganic insulating layers 41 to 45 are formed of inorganic insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride. The organic insulating layer 46 is formed of an organic insulating material such as polyimide and is thicker than the inorganic insulating layers 41 to 45.

[0070] In addition, such as Figure 2 The signal lines SL, initialization line IL, power lines PL1, PL2, and scan lines GL1 to GL4 shown are formed from one of metal layers 32 to 35. In one example, scan lines GL1 to GL4 are formed from at least one of metal layers 32 and 33, signal line SL and power line PL1 are formed from metal layer 34, and power line PL2 and initialization line IL are formed from metal layer 35.

[0071] Figure 6 This is a diagram showing an example of the configuration of a transistor (TFT) included in circuit layer 11. Figure 6 The transistor TR shown includes a semiconductor SC, a gate electrode GE, conductive layers CLs and CLd, a source electrode SO, and a drain electrode DR.

[0072] Semiconductor SC is covered by inorganic insulating layer 41. Gate electrode GE is disposed on inorganic insulating layer 41 and covered by inorganic insulating layer 42. Conductive layers CLs and CLd are separated from each other and disposed on inorganic insulating layer 43 and covered by inorganic insulating layer 44. Source electrode SO and drain electrode DR are separated from each other and disposed on inorganic insulating layer 44 and covered by inorganic insulating layer 45.

[0073] The conductive layer CLs is connected to the semiconductor SC through contact holes CHs1 respectively provided in the inorganic insulating layers 41, 42, and 43. The conductive layer CLd is connected to the semiconductor SC through contact holes CHd1 respectively provided in the inorganic insulating layers 41, 42, and 43. The source electrode SO is connected to the conductive layer CLs through contact hole CHs2 provided in the inorganic insulating layer 44. The drain electrode DR is connected to the conductive layer CLd through contact hole CHd2 provided in the inorganic insulating layer 44. It should be noted that the source electrode SO and the drain electrode DR can also be directly connected to the semiconductor SC through contact holes respectively provided in the inorganic insulating layers 41 to 44.

[0074] Semiconductor SC is formed from semiconductor layer 31. Gate electrode GE is formed from metal layer 32. Conductive layers CLs and CLd are formed from metal layer 33. Source electrode SO and drain electrode DR are formed from metal layer 34. The structure of transistor TR can be applied to... Figure 2 The transistors shown are TR1 to TR7.

[0075] Figure 7 This is a schematic top view showing an example of the boundary between the display area DA and the surrounding area SA. Figure 7 In the example shown, Figure 1 The boundary between the display area DA and the surrounding area SA on the terminal T side is shown.

[0076] The aforementioned pixel PX is configured in the display area DA. Subpixels SP1, SP2, and SP3 within pixel PX each possess pixel circuits PC1, PC2, and PC3, respectively. In one example, pixel circuits PC1, PC2, and PC3 are arranged in the X direction. Figure 2 The pixel circuit PC shown can be applied to pixel circuits PC1, PC2, and PC3 respectively. Figure 7 In the example shown, the scan lines GL1 to GL4 contained in the pixel circuit PC extend along the X direction and are arranged in the Y direction within the display area DA and the surrounding area SA.

[0077] The semiconductor SC (first semiconductor layer) contained in each transistor of the pixel circuits PC1, PC2, and PC3 is arranged in the display area DA, overlapping with scan lines GL1 to GL4 respectively. Figure 7 In the example shown, the semiconductor SC extends along the Y direction. However, the semiconductor SC may also have a shape that is bent at multiple locations.

[0078] The surrounding area SA is configured with scan lines GL1-GL4, 2GL, signal line SL, power lines PL1 and PL2, initialization line IL, and dummy semiconductors DS1 and DS2 (second semiconductor layer). In one example, scan line 2GL is composed of... Figure 5The metal layer 33 shown is formed. The dummy semiconductors DS1 and DS2 are formed by... Figure 5 The semiconductor layer 31 shown is formed. The dummy semiconductors DS1 and DS2 are formed of the same material as the semiconductor SC.

[0079] exist Figure 7 In the diagram, dotted patterns are marked for scan lines GL1 to GL4, and diagonal patterns are marked for signal line SL, power line PL1, and dummy semiconductors DS1 and DS2. Additionally, the outline of scan line 2GL is represented by a dashed line, and the outlines of initialization line IL and power line PL2 are represented by double-dotted lines.

[0080] Multiple signal lines SL extend along the Y direction and are arranged in the X direction. Signal lines SL intersect with scan lines GL1 to GL4. Multiple scan lines 2GL extend along the Y direction and are arranged in the X direction. Scan lines 2GL are connected to signal lines SL through contact holes Cha.

[0081] The power supply line PL1 includes a power supply line PL1x extending along the X direction and multiple power supply lines PL1y extending from the power supply line PL1x along the Y direction to the display area DA and arranged in the X direction. Figure 7 In the example shown, power line PL1x overlaps with scan line 2GL, power line PL2, and initialization line IL. Multiple power lines PL1y are respectively positioned between adjacent signal lines SL in the X direction. Signal lines SL and power lines PL1 overlap with the display area DA, forming... Figure 6 The source electrode SO and drain electrode DR are shown.

[0082] The initialization line IL and power line PL2 extend along the Y direction. The initialization line IL and power line PL2 overlap with the signal line SL and power line PL1.

[0083] The dummy semiconductor DS1 (the first dummy semiconductor) is patterned into an identification symbol shape. This identification symbol shape can, for example, use numbers, letters, etc. Figure 7 In the example shown, the dummy semiconductor DS1 is patterned as a digital identification symbol shape. This digital identification symbol shape, for example, represents the wiring number of signal line SL. It should be noted that the identification symbol shape can also represent the wiring number of scan line GL, manufacturing batch number, etc. Furthermore, this wiring number can be represented by a single identification symbol shape, or multiple identification symbol shapes can be combined. Figure 7 In the example shown, the wiring number of signal line SL is represented by three identification symbol shapes.

[0084] The shape of the identification symbol can be seen from, for example, the back side of the display device DSP (DSP). Figure 4 The substrate 10 shown is read from the side. Therefore, as... Figure 7 The identification symbol shown is represented by a left-right flip. Therefore, as... Figure 7 The three identification symbols shown on the right represent "2", "3", and "0" respectively, and the combination of these symbols represents "230". Similarly, Figure 7 The three identification symbols shown on the left represent "2", "3" and "1" respectively. The combination of these identification symbol shapes represents "231".

[0085] Multiple dummy semiconductors DS1 overlap with one of the scan lines GL1 to GL4. Figure 7 In the example shown, the dummy semiconductor DS1 representing "0" and "1" overlaps with scan line GL1, the dummy semiconductor DS1 representing "3" overlaps with scan line GL2, and the dummy semiconductor DS1 representing "2" overlaps with scan line GL3. Additionally, in Figure 7 In the example shown, scan line GL4 does not overlap with the dummy semiconductor DS1.

[0086] A dummy semiconductor DS1 is positioned between adjacent signal lines SL in the X direction. Figure 7 In the example shown, the dummy semiconductor DS1 is positioned between the adjacent signal line SL and power line PL1y in the X direction.

[0087] Multiple dummy semiconductors DS2 (the second dummy semiconductor) overlap with one of the scan lines GL1 to GL4 respectively. Figure 7 In the example shown, multiple dummy semiconductors DS2 are grouped into sets of four and overlapped with scan lines GL1 to 4. Furthermore, the multiple dummy semiconductors DS2 are arranged in a matrix. The dummy semiconductors DS2 are separated from the dummy semiconductors DS1 along the X-direction.

[0088] exist Figure 7 In the example shown, the multiple dummy semiconductors DS2 are formed in a U-shape. However, the shape of the multiple dummy semiconductors DS2 is not limited to a U-shape.

[0089] Figure 8 It is along Figure 7 A schematic cross-sectional view of the display device DSP along lines VIII-VIII.

[0090] An inorganic insulating layer 41 covers the dummy semiconductors DS1 and DS2. Scan lines GL1 to GL4 are disposed on the inorganic insulating layer 41. Scan lines GL1 to GL4 are disposed directly above the dummy semiconductors DS1 and DS2. Figure 8 In the example shown, scan line GL1 is positioned directly above dummy semiconductors DS1 and DS2, and scan lines GL2 to GL4 are positioned directly above dummy semiconductor DS2.

[0091] Inorganic insulating layer 42 covers scan lines GL1 to GL4. Scan line 2GL is disposed on inorganic insulating layer 43. Inorganic insulating layer 44 covers scan line 2GL. Signal line SL and power line PL1 are disposed on inorganic insulating layer 44. Signal line SL is connected to scan line 2GL through contact hole CHa provided in inorganic insulating layer 44.

[0092] Inorganic insulating layer 45 covers signal line SL and power line PL1. Power line PL2 and initialization line IL are disposed on organic insulating layer 46. Organic insulating layer 12 covers power line PL2 and initialization line IL.

[0093] Assume that the dummy semiconductors DS1 and DS2 are formed by semiconductor layer 31, and... Figure 6 The semiconductor SC shown is located on the same layer. Scan lines GL1 to GL4 are formed by metal layer 32, and... Figure 6 The gate electrode GE shown is located in the same layer. Scan line 2GL is formed by metal layer 33. Signal line SL and power line PL1 are formed by metal layer 34. Figure 6 The source electrode SO and drain electrode DR shown are located on the same layer. The power line PL2 and the initialization line IL are formed by the metal layer 35.

[0094] Figure 9 This is a schematic top view illustrating an example of the configuration of scan line GL, semiconductor SC, and dummy semiconductors DS1 and DS2. Figure 9 In (a), the scan line GL and the semiconductor SC in the display area DA are shown. Figure 9 In (b), the scan line GL and dummy semiconductors DS1 and DS2 in the surrounding area SA are shown. The scan line GL and... Figure 7 One of the scan lines GL1 to GL4 shown is equivalent.

[0095] like Figure 9 As shown in (a), the scan line GL overlaps with the semiconductor SC in the display area DA. The area where the scan line GL overlaps with the semiconductor SC will be referred to as area AR1 below.

[0096] like Figure 9 As shown in (b), the scan line GL overlaps with dummy semiconductors DS1 and DS2 in the peripheral region SA. The region where the scan line GL overlaps with dummy semiconductor DS1 is referred to as region AR21, and the region where the scan line GL overlaps with dummy semiconductor DS2 is referred to as region AR22. Figure 9 In example (b), the dummy semiconductor DS1 intersects with the scan line GL at two locations, and the dummy semiconductor DS2 intersects with the scan line GL at two locations.

[0097] At this point, the areas of regions AR21 and AR22 are each less than the area of ​​region AR1. Figure 9In the example shown, the areas of regions AR21 and AR22 are each smaller than the area of ​​region AR1.

[0098] Figure 10 This is a schematic top view showing another example of the configuration of the scan line GL, dummy semiconductors DS1 and DS2. Here, the width in the X direction of the portion of dummy semiconductor DS1 extending along the Y direction and intersecting the scan line GL is referred to as width W1, and the width in the X direction of the portion of dummy semiconductor DS2 extending along the Y direction and intersecting the scan line GL is referred to as width W2. Figure 10 In the example shown, width W1 is smaller than width W2. Therefore, region AR21 is smaller than region AR22.

[0099] Figure 11 This is a diagram illustrating an example of the shape of an identification symbol. In Figure 11 In the example shown, the shapes of the upper identification symbols, from left to right, represent "1-5" respectively, while the shapes of the lower identification symbols, from left to right, represent "6-9" and "0" respectively. It should be noted that... Figure 11 The shape of the identification symbol shown indicates the display device DSP as viewed from the rear side.

[0100] exist Figure 11 In the example shown, each dummy semiconductor DS1 intersects the scan line GL at more than two locations. Specifically, the dummy semiconductor DS1 patterned to represent "1", "4", "7", and "0" respectively, which is patterned to represent the identification symbol shape, intersects the scan line GL at two locations, while the dummy semiconductor DS1 patterned to represent the identification symbol shape "2", "3", "5", "6", "8", and "9" respectively, intersects the scan line GL at three locations.

[0101] By combining the shapes of these identification symbols, it is possible to represent Figure 7 The wiring number of the signal line SL shown is displayed.

[0102] Next, the effects of the display device DSP in this embodiment will be explained. Figure 12 This is a cross-sectional view used to illustrate the effect of the display device DSP in this embodiment. Hereinafter, the dummy semiconductors DS1 and DS2 are collectively referred to as dummy semiconductors DS. Furthermore, the electrostatic capacitance formed between the semiconductor SC and the scan line GL is referred to as electrostatic capacitance Ca, and the electrostatic capacitance formed between the dummy semiconductor DS and the scan line GL is referred to as electrostatic capacitance Cb.

[0103] Figure 12(a) is a cross-sectional view of the display device DSP in the case where the dummy semiconductor DS is not present in the peripheral region SA. In this case, during the manufacturing process of the display device DSP, the charge E accumulated in the scan line GL may accumulate in the semiconductor SC of the display region DA, which may cause damage to the semiconductor SC due to electrostatic discharge.

[0104] Figure 12 (b) is a cross-sectional view of the display device DSP in the case where the display device DSP has a dummy semiconductor DS in the peripheral region SA. It should be noted that in... Figure 12 In (b), the case where the electrostatic capacitances Ca and Cb are equal is shown. In this case, the charge E accumulated in the scan line GL is uniformly distributed to the semiconductor SC and the dummy semiconductor DS. Therefore, compared to the case where the display device DSP does not have the dummy semiconductor DS, damage caused by electrostatic discharge can be suppressed.

[0105] However, in this display device DSP, it is desirable to achieve a narrow bezel. However, when the shapes of the identification symbols are respectively arranged between each of the scan lines GL1 to GL4, the interval between each of the scan lines GL1 to GL4 needs to be increased in order to arrange the shapes of the identification symbols, making it difficult to achieve a narrow bezel.

[0106] Assuming that the spacing between scan lines GL1 to GL4 is reduced to achieve a narrower frame, the semiconductor layer 31, patterned into the shape of an identification symbol, may overlap with multiple scan lines GL1 to GL4. As a result, the multiple scan lines overlapping with the semiconductor layer 31 may be short-circuited through the semiconductor layer 31.

[0107] In this embodiment, a dummy semiconductor DS1, patterned in the semiconductor layer 31 into the shape of an identification symbol, is disposed in the peripheral region SA. Furthermore, the dummy semiconductor DS1 overlaps with one of the scan lines GL1 to GL4. Therefore, it is unnecessary to ensure that the area for arranging the identification symbol shape between each of the scan lines GL1 to GL4 is properly positioned, thus reducing the spacing between the scan lines GL1 to GL4. As a result, a narrower bezel can be achieved in the display device DSP.

[0108] Furthermore, by overlapping the dummy semiconductor DS1 with a scan line GL, the risk of short circuits can be reduced. Additionally, by forming the shape of the identification symbol from the dummy semiconductor DS1, it is possible to... Figure 12 As shown in (b), damage to semiconductors such as SC caused by electrostatic discharge is suppressed. As a result, it is possible to suppress the decrease in manufacturing yield of the display device DSP and improve the reliability of the display device DSP.

[0109] Figure 12(c) is a cross-sectional view of the display device DSP when the electrostatic capacitance Cb is smaller than the electrostatic capacitance Ca. In this case, since the charge E moves towards the region with smaller electrostatic capacitance, the charge E accumulates in the dummy semiconductor DS in the peripheral region SA where the electrostatic capacitance Cb, which is smaller than the electrostatic capacitance Ca, is formed. Therefore, compared to the case where the electrostatic capacitances Ca and Cb are equal, damage to the semiconductor SC, etc., caused by electrostatic discharge can be further suppressed.

[0110] Here, the magnitude of the electrostatic capacitance Cb is proportional to the area of ​​the region where the scan line GL and the dummy semiconductor DS overlap. That is, as the area of ​​the region where the scan line GL and the dummy semiconductor DS overlap decreases, the magnitude of the electrostatic capacitance Cb decreases. In this embodiment, as... Figure 9 As shown, the areas AR21 and AR22, where the scan line GL overlaps with the dummy semiconductors DS1 and DS2 respectively, are smaller than the area AR1, where the scan line GL overlaps with the semiconductor SC. Therefore, damage caused by electrostatic discharge can be further suppressed.

[0111] In addition, such as Figure 10 As shown, by making the width W1 of the dummy semiconductor DS1 smaller than the width W2 of the dummy semiconductor DS2, the area of ​​region AR21 is made smaller than the area of ​​region AR22, thereby further suppressing the damage caused by electrostatic discharge.

[0112] Furthermore, as the number of intersections between the scan line GL and the dummy semiconductors DS1 and DS2 increases, the amount of charge E accumulated in the semiconductor SC decreases. Therefore, as... Figure 11 As shown, by setting the shape of the identification symbol in a manner in which the scan line GL intersects with the dummy semiconductor DS1 at more than two locations, it is possible to further suppress damage caused by electrostatic discharge.

[0113] Figure 13 This is another example of the shape of an identification symbol. In Figure 13 In the example shown, the shapes of the upper identification symbols, from left to right, represent "1-5" respectively, while the shapes of the lower identification symbols, from left to right, represent "6-9" and "0" respectively. It should be noted that... Figure 13 The shape of the identification symbol shown illustrates the display device DSP as viewed from the rear side.

[0114] Here, the dummy semiconductor DS1 that overlaps with one of the two adjacent scan lines GL in the Y direction is defined as segment SG1, and the dummy semiconductor DS1 that overlaps with the other of the two adjacent scan lines GL in the Y direction is defined as segment SG2. Figure 13In the example shown, the dummy semiconductor DS1 that overlaps with the upper scan line GL corresponds to the first segment SG1, and the dummy semiconductor DS1 that overlaps with the lower scan line GL corresponds to the second segment SG2. The first segment SG1 and the second segment SG2 are separate from each other.

[0115] exist Figure 13 In the example shown, the shape of the identification symbol is formed by a combination of segment 1 SG1 and segment 2 SG2. For example, the shape of the identification symbol representing "0" is formed by a combination of segment 1 SG1 and segment 2 SG2, which are formed into a C shape.

[0116] It should be noted that, in Figure 13 In the example shown, the shape of the identification symbol representing "1" is composed only of the first segment SG1, but it can also be composed of a combination of the first segment SG1 and the second segment SG2. In addition, the shape of the identification symbol is not limited to numbers.

[0117] By dividing the shape of the identification symbol into segment 1 (SG1) and segment 2 (SG2), the spacing between adjacent scan lines GL in the Y direction can be further reduced. As a result, the frame area of ​​the display device DSP can be further reduced.

[0118] In addition, Figure 13 In the example shown, the first segment SG1 of the identification symbol shape representing "1", "2", "3", "4", "5", "6", "7", "8", "9", and "0" intersects with the scan line GL in more than two places. Similarly, the second segment SG2 of the identification symbol shape representing "2", "3", "5", "6", "8", "9", and "0" intersects with the scan line GL in more than two places.

[0119] By dividing the shape of the identification symbol into segment 1 (SG1) and segment 2 (SG2), the area where the scan line GL intersects with the dummy semiconductor DS1 can be increased. As a result, damage caused by electrostatic discharge can be further suppressed.

[0120] Any display device that can be appropriately designed and modified by those skilled in the art based on the display device described above as an embodiment of the present invention, as long as it contains the essence of the present invention, is also within the scope of the present invention.

[0121] Within the scope of this invention, various modifications will be conceived by those skilled in the art, and these modifications should also be considered within the scope of this invention. For example, any appropriate addition, deletion, or design change of constituent elements, or the addition, omission, or alteration of processes or conditions in relation to the above embodiments, as long as they capture the essence of this invention, are also included within the scope of this invention.

[0122] Furthermore, any other effects resulting from the methods described in the above embodiments, as known from the description in this specification or that can be reasonably conceived by those skilled in the art, should naturally be considered as effects brought about by the present invention.

Claims

1. A display device, characterized in that, include: Display area; The peripheral area that is outside the display area; Multiple scan lines extend in a first direction and are arranged in a second direction that intersects the first direction; A first semiconductor layer is disposed in the display area and overlaps with the plurality of scan lines; as well as A second semiconductor layer, disposed in the peripheral region, overlaps with one of the plurality of scan lines. The second semiconductor layer includes a first dummy semiconductor patterned into the shape of an identification symbol.

2. The display device according to claim 1, characterized in that, It also includes multiple signal lines extending in the second direction and arranged in the first direction. The shape of the identification symbol indicates the wiring number of the scan line or the signal line.

3. The display device according to claim 1, characterized in that, The area of ​​the region where the scan line overlaps with the second semiconductor layer is smaller than the area of ​​the region where the scan line overlaps with the first semiconductor layer.

4. The display device according to claim 1, characterized in that, The area of ​​the region where the scan line overlaps with the first dummy semiconductor is smaller than the area of ​​the region where the scan line overlaps with the first semiconductor layer.

5. The display device according to claim 1, characterized in that, The first dummy semiconductor intersects with the scan line at two or more locations.

6. The display device according to claim 1, characterized in that, The second semiconductor layer includes a second dummy semiconductor that is separated from the first dummy semiconductor along the first direction.

7. The display device according to claim 6, characterized in that, The area of ​​the region where the scan line overlaps with the second dummy semiconductor is smaller than the area of ​​the region where the scan line overlaps with the first semiconductor layer.

8. The display device according to claim 6, characterized in that, The area of ​​the region where the scan line overlaps with the first dummy semiconductor is smaller than the area of ​​the region where the scan line overlaps with the second dummy semiconductor.

9. The display device according to claim 6, characterized in that, The second dummy semiconductor intersects with the scan line at two or more locations.

10. The display device according to claim 6, characterized in that, The width of the portion of the first dummy semiconductor that extends in the second direction and intersects the scan line in the first direction is smaller than the width of the portion of the second dummy semiconductor that extends in the second direction and intersects the scan line in the first direction.

11. The display device according to claim 1, characterized in that, It also includes multiple signal lines extending in the second direction and arranged in the first direction. The first dummy semiconductor is disposed between adjacent signal lines in the first direction.

12. The display device according to claim 11, characterized in that, It also has multiple power lines extending in the second direction and arranged in the first direction. The first dummy semiconductor is disposed between the signal line and the power line adjacent to each other in the first direction.

13. A display device, characterized in that, include: Display area; The peripheral area that is outside the display area; Multiple scan lines extend in a first direction and are arranged in a second direction that intersects the first direction; A first semiconductor layer is disposed in the display area and overlaps with the plurality of scan lines; as well as A second semiconductor layer, disposed in the peripheral region, overlaps with the plurality of scan lines. The second semiconductor layer includes a first segment that overlaps with one of the scan lines adjacent in the second direction and a second segment that overlaps with the other of the scan lines adjacent in the second direction and is separate from the first segment. The shape of the identification symbol is formed by the combination of the first segment and the second segment.

14. The display device according to claim 13, characterized in that, It also includes multiple signal lines extending in the second direction and arranged in the first direction. The shape of the identification symbol indicates the wiring number of the scan line or the signal line.

15. The display device according to claim 13, characterized in that, The first segment and the second segment intersect the scan line at two or more locations.

16. The display device according to claim 1 or 13, characterized in that, The first semiconductor layer and the second semiconductor layer are located in the same layer.

17. The display device according to claim 1 or 13, characterized in that, The first semiconductor layer and the second semiconductor layer are formed of the same material.

18. The display device according to claim 1 or 13, characterized in that, The first semiconductor layer and the second semiconductor layer are formed of polycrystalline silicon, amorphous silicon or oxide semiconductor, respectively.

19. The display device according to claim 1 or 13, characterized in that, Also includes: The lower electrode is disposed in the display area, above the first semiconductor layer; A rib layer having pixel openings overlapping the lower electrode, covering the periphery of the lower electrode and formed of an inorganic material; The partition includes a lower portion disposed on the rib layer and having electrical conductivity, and an upper portion disposed on the lower portion and projecting from the side of the lower portion; An organic layer that covers the lower electrode through the pixel opening; as well as The upper electrode covers the organic layer and is in contact with the lower part.

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