Display device and electronic device having same

Abstract

A display device and an electronic device having the same are disclosed. The display device includes a pixel and a sensor. The sensor includes: a light receiving element; a first sensor transistor; a second sensor transistor connected between a reset power line and a gate electrode of the first sensor transistor, and including a gate electrode connected to a reset control line; a third sensor transistor connected between the first sensor transistor and the readout line, and including a gate electrode connected to the first scan line; and a fourth sensor transistor connected between the gate electrode of the first sensor transistor and the anode electrode of the light receiving element, and including a gate electrode connected to the gate line. The first scan line and the gate line are connected to each other.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0144875, filed on October 22, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The embodiments of this disclosure generally relate to a display device and an electronic device having the display device, and more specifically, to a display device having a photoelectric sensor and an electronic device having the display device. Background Technology

[0003] With the advancement of information technology, display devices, serving as interfaces between users and information, have become increasingly important. Therefore, various types of display devices, such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs), are being widely adopted. Additionally, some display devices incorporate photoelectric sensors to detect users' fingerprints and perform user authentication. Summary of the Invention

[0004] Embodiments of this disclosure provide a display device and an electronic device with improved resolution and sensing performance.

[0005] According to embodiments of this disclosure, a display device includes pixels comprising light-emitting elements and a sensor. The sensor includes: a light-receiving element; a first sensor transistor; a second sensor transistor connected between a reset power line and the gate electrode of the first sensor transistor, wherein the second sensor transistor includes a gate electrode connected to a reset control line; a third sensor transistor connected between the first sensor transistor and a readout line, wherein the third sensor transistor includes a gate electrode connected to a first scan line; and a fourth sensor transistor connected between the gate electrode of the first sensor transistor and the anode electrode of the light-receiving element, wherein the fourth sensor transistor includes a gate electrode connected to a gate line. The first scan line and the gate line are connected to each other.

[0006] In this embodiment, the third sensor transistor is a p-type transistor, and the fourth sensor transistor is an n-type transistor.

[0007] In one embodiment, the third sensor transistor comprises a silicon semiconductor, and the fourth sensor transistor comprises an oxide semiconductor.

[0008] In this embodiment, the first sensor transistor is a p-type transistor, and the second sensor transistor is an n-type transistor.

[0009] In one embodiment, the pixel further includes: a first transistor that provides driving current to a light-emitting element; and a second transistor connected between a first electrode of the first transistor and a data line. The gate electrode of the second transistor is connected to the first scan line.

[0010] In this embodiment, the display device further includes a driving circuit. The driving circuit: provides a reset signal having a logic high level to a reset control line at a first time point; provides a first scan signal having a logic low level to a first scan line and a gate line at a second time point; provides a gate signal to the first scan line and the gate line at a third time point, wherein the gate signal has a logic high level at the third time point; and provides a gate signal to the first scan line and the gate line at a fourth time point, wherein the gate signal has a logic low level at the fourth time point. The first to fourth time points occur sequentially within a sensing cycle.

[0011] In one embodiment, the driving circuit reads the first sensing signal through the readout line at a second time point, reads the second sensing signal through the readout line at a fourth time point, and performs a subtraction operation on the first sensing signal and the second sensing signal.

[0012] In one embodiment, the display device further includes a plurality of sensors, each containing a sensor. The driving circuitry provides a reset signal to the plurality of sensors collectively, and sequentially provides a first scan signal to the plurality of sensors in units of horizontal lines.

[0013] In this embodiment, the exposure time for the corresponding plurality of sensors is constant between the third and fourth time points.

[0014] In an embodiment, in a plan view, the semiconductor layers of the second sensor transistor and the fourth sensor transistor extend substantially in the second direction. In the plan view, the first scan line and the gate line extend substantially in a first direction intersecting the second direction.

[0015] In one embodiment, in a plan view, the first scan line includes a protrusion stacked with the semiconductor layer of the fourth sensor transistor. In the plan view, the gate line is stacked with the protrusion of the first scan line.

[0016] In one embodiment, in a cross-sectional view, the semiconductor layer of the fourth sensor transistor is disposed between the first scan line and the gate line. In the cross-sectional view, the gate line is in contact with the first scan line through a contact hole.

[0017] According to embodiments of this disclosure, a display device includes pixels comprising light-emitting elements and a sensor. The sensor includes: a light-receiving element; a first sensor transistor; a second sensor transistor connected between a reset power line and the gate electrode of the first sensor transistor, wherein the second sensor transistor includes a gate electrode connected to a reset control line; a third sensor transistor connected between the first sensor transistor and a readout line, wherein the third sensor transistor includes a gate electrode connected to a first scan line; and a fourth sensor transistor connected between the gate electrode of the first sensor transistor and the anode electrode of the light-receiving element, wherein the fourth sensor transistor includes a gate electrode connected to a gate line. A first scan signal provided to the first scan line and a gate signal provided to the gate line have the same waveform.

[0018] In this embodiment, the third sensor transistor is a p-type transistor, and the fourth sensor transistor is an n-type transistor.

[0019] In one embodiment, the third sensor transistor comprises a silicon semiconductor, and the fourth sensor transistor comprises an oxide semiconductor.

[0020] In one embodiment, the pixel further includes: a first transistor that provides driving current to a light-emitting element; and a second transistor connected between a first electrode of the first transistor and a data line. The gate electrode of the second transistor is connected to the first scan line.

[0021] In this embodiment, the display device further includes a driving circuit. The driving circuit: provides a reset signal having a logic high level to a reset control line at a first time point; provides a first scan signal to a first scan line and a gate line at a second time point, wherein the first scan signal has a logic low level at the second time point; provides a gate signal to the first scan line and the gate line at a third time point, wherein the gate signal has a logic high level at the third time point; and provides a gate signal to the first scan line and the gate line at a fourth time point, wherein the gate signal has a logic low level at the fourth time point. The first to fourth time points occur sequentially within a sensing cycle.

[0022] In an embodiment, in a plan view, the semiconductor layers of the second sensor transistor and the fourth sensor transistor extend in a second direction. In the plan view, the first scan line and the gate line extend while intersecting the pixel along a first direction that intersects the second direction.

[0023] In an embodiment, in a plan view, the gate line is superimposed on the first scan line.

[0024] According to embodiments of this disclosure, an electronic device includes: a display device configured to display an image based on input image data; and a processor configured to provide the input image data to the display device. The display device includes pixels comprising light-emitting elements and a sensor. The sensor includes: a light-receiving element; a first sensor transistor; a second sensor transistor connected between a reset power line and the gate electrode of the first sensor transistor, wherein the second sensor transistor includes a gate electrode connected to a reset control line; a third sensor transistor connected between the first sensor transistor and a readout line, wherein the third sensor transistor includes a gate electrode connected to a first scan line; and a fourth sensor transistor connected between the gate electrode of the first sensor transistor and the anode electrode of the light-receiving element, wherein the fourth sensor transistor includes a gate electrode connected to a gate line. The first scan line and the gate line are connected to each other. Attached Figure Description

[0025] The above and other features of this disclosure will become more apparent from a detailed description of embodiments thereof with reference to the accompanying drawings.

[0026] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0027] Figure 2 It is shown Figure 1 A block diagram of an embodiment of the display device shown.

[0028] Figure 3 It is shown that it includes Figure 2 A diagram illustrating an example of the arrangement of the backplane circuitry of the display area of ​​the display panel in the display device shown.

[0029] Figure 4 It is shown that it includes Figure 2 A diagram illustrating an example of the display area of ​​a display panel in a display device.

[0030] Figure 5 It is shown that it includes Figure 4 The circuit diagram shows an example of pixels and photoelectric sensors in the display area shown.

[0031] Figure 6 It is shown Figure 5 The waveform diagram shows an embodiment of the operation of the pixels.

[0032] Figure 7 It is shown Figure 5 Waveform diagram of an embodiment of the operation of the photoelectric sensor shown.

[0033] Figures 8 to 10 It is shown Figure 5 The diagram shows the operation of the photoelectric sensor.

[0034] Figure 11 and Figure 12 It is shown Figure 4 A plan view of an embodiment of the display area shown.

[0035] Figure 13 It is shown Figure 4 A cross-sectional view of an embodiment of the display area shown.

[0036] Figure 14 It is shown Figure 4 A plan view of an embodiment of the display area shown.

[0037] Figure 15 It is shown Figure 4 A cross-sectional view of an embodiment of the display area shown.

[0038] Figure 16 It is shown Figure 4 A plan view of an embodiment of the display area shown.

[0039] Figure 17 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0040] Figure 18 Schematic diagrams illustrating various embodiments of an electronic device according to the present disclosure are shown. Detailed Implementation

[0041] Embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0042] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and the element is not limited by these terms. Thus, a “first” element in one embodiment may be described as a “second” element in another embodiment.

[0043] It should be understood that, unless the context clearly indicates otherwise, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments.

[0044] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well.

[0045] For ease of description, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another element(s) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “below” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations.

[0046] It will be understood that when a component is referred to as being "on" another component, "connected to" another component, "integrated into" another component, or "adjacent to" another component, the component may be directly on, directly connected to, directly integrated into, or directly adjacent to the other component, or there may be intermediary components. It will also be understood that when a component is referred to as being "between" two components, the component may be the only component between the two components, or there may be one or more intermediary components. It will also be understood that when a component is referred to as "covering" another component, the component may be the only component covering the other component, or one or more intermediary components may also cover the other component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0047] The term "connection" between two components can include both electrical and / or physical connections.

[0048] It will also be understood that when the terms “comprising” and / or variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements and / or components, but does not preclude the presence and / or addition of one or more other features, integrals, steps, operations, elements, components and / or groups thereof.

[0049] Here, when two or more elements or values ​​are described as substantially the same or approximately equal to each other, it will be understood that: the elements or values ​​are the same; the elements or values ​​are equal to each other within measurement error; or if they are measurably unequal, they are sufficiently close in value to be functionally equal, as will be understood by those skilled in the art. For example, the term “about” as used herein includes the stated value and means within an acceptable range of deviation of a particular value as determined by those skilled in the art taking into account the measurement in question and the error associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, “about” may mean within one or more standard deviations as understood by those skilled in the art, for example, within ±30%, ±20%, ±10%, or ±5% of the stated value. Furthermore, it will be understood that, as will be understood by those skilled in the art, although a parameter may be described herein as having “about” a certain value, according to embodiments, the parameter may be exactly that value or approximately that value within measurement error. Similarly, when a component is described as extending substantially in one direction, the component extends exactly in that direction, or extends approximately in that direction within a measurement error as would be understood by one of ordinary skill in the art. Other uses of these terms and similar terms to describe relationships between components should be interpreted in a similar manner.

[0050] Embodiments of this disclosure provide a display device with integrated sensor circuitry that improves layout efficiency, reduces parasitic interference, and increases resolution. For example, embodiments of this disclosure address the problems of excessive circuit area and coupling noise in conventional designs by introducing an improved transistor arrangement in which multiple transistors (such as the third and fourth sensor transistors of a sensor (described further below) and the second transistor of a pixel, as examples) share a common first scan line (also described further below). By utilizing this shared scan line architecture, embodiments of this disclosure eliminate the need for separate control signals for individual transistors, resulting in a simplified circuit structure, a reduced number of required signal lines, and a smaller total area occupied by the pixel and sensor circuitry. Therefore, embodiments of this disclosure can provide a more compact circuit layout by allowing more sensing and display elements to be integrated within the same space, and also improve display resolution.

[0051] Embodiments of this disclosure can reduce parasitic coupling and signal interference that can occur when different circuit components are stacked. In conventional constructions, stacked conductive elements (such as gate lines and scan lines) can introduce unwanted capacitive coupling, which can distort signal transmission and degrade sensing performance. However, according to embodiments of this disclosure, this problem can be mitigated by providing gate and scan signals that share the same waveform and phase, which can prevent or reduce substantial interference even when conductive elements are stacked. As a result, circuits according to embodiments of this disclosure can maintain stable electrical characteristics without the need for additional shielding layers or complex compensation techniques, further contributing to space efficiency.

[0052] Embodiments of this disclosure can provide a high-resolution display with improved sensing capabilities, improved circuit layout, and minimized or reduced interference. By implementing a shared scanline method and effectively managing signal synchronization, embodiments of this disclosure can achieve a balance between reducing circuit area, enhancing resolution, and improving signal integrity.

[0053] In the following description, a display device according to a disclosed embodiment will be described with reference to the accompanying drawings.

[0054] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0055] Reference Figure 1 The display device 1000 may include a display panel 100 and a driving circuit 200 (or driver). In an embodiment, the driving circuit 200 may include a panel driver 210 and a sensor driver 220.

[0056] The display device 1000 can be implemented as a self-emissive display device including multiple self-emissive elements. For example, the display device 1000 can be an organic light-emitting display device including organic light-emitting elements. However, this is only illustrative, and the display device 1000 can be implemented as a display device including inorganic light-emitting elements, a display device including light-emitting elements made of a combination of inorganic and organic materials, a display device using quantum dots to display images, etc.

[0057] The display device 1000 can be, for example, a flat panel display device, a flexible display device, a bendable display device, a foldable display device, a flexible display device, or a rollable display device. The display device 1000 can be applied to, for example, transparent display devices, head-mounted display devices, wearable display devices, etc.

[0058] Display panel 100 may include a display area AA and a non-display area NA. Display area AA may be an area in which at least one pixel PX is disposed. Pixel PX may be referred to as a subpixel or a light-emitting pixel. Pixel PX may include at least one light-emitting element (e.g., a light-emitting diode). For example, the light-emitting element may include a light-emitting layer (e.g., an organic light-emitting layer). The portion emitting light through the light-emitting element may be defined as the light-emitting area. Display device 1000 may drive pixel PX to display an image in display area AA.

[0059] The non-display area NA can be an area located on the periphery of the display area AA. In embodiments, the non-display area NA can specifically refer to other areas in the display panel 100 besides the display area AA. For example, the non-display area NA can include line areas, pad (or "solder pad") areas, various dummy areas, etc.

[0060] In an embodiment, at least one photoelectric sensor PHS may be included in the display area AA. The photoelectric sensor PHS may be referred to as a sensor pixel. The photoelectric sensor PHS may include a light-receiving element comprising a light-receiving layer. The light-receiving layer of the light-receiving element and the light-emitting layer of the light-emitting element may be located in the same layer in the display area AA, and the light-receiving layer may be separated from the light-emitting layer of the light-emitting element in a plane (e.g., in a planar view).

[0061] In this embodiment, multiple photoelectric sensors PHS can be distributed across the entire area of ​​the display area AA, while being spaced apart from each other. However, this is merely illustrative. Only a portion of the display area AA can be designated as a selectable sensing area, and the photoelectric sensors PHS can be located within the corresponding sensing area. Alternatively, the photoelectric sensors PHS can be included in at least a portion of the non-display area NA.

[0062] In an embodiment, the photoelectric sensor PHS can sense light emitted from a light source (e.g., the light-emitting element of a pixel PX) and reflected by an external object (e.g., a user's finger, etc.). For example, a user's fingerprint can be sensed by the photoelectric sensor PHS. The use of the photoelectric sensor PHS for fingerprint sensing will be described below as an example. However, in various embodiments, the photoelectric sensor PHS can sense various biometric information such as iris and vein patterns.

[0063] The driving circuit 200 may include a panel driver 210 and a sensor driver 220. The display device 1000 may include a panel driver 210 and a sensor driver 220. For example, the panel driver 210 and the sensor driver 220 may be implemented as independent integrated circuits, or the driving circuit 200 may be implemented as a single integrated circuit. For example, at least a portion of the sensor driver 220 may be included in the panel driver 210, or operate in conjunction with the panel driver 210.

[0064] The panel driver 210 can scan the pixels PX of the display area AA and supply data signals corresponding to image data (or images) to the pixels PX. The display panel 100 can display the image corresponding to the data signals.

[0065] In one embodiment, panel driver 210 may supply a drive signal for light sensing (e.g., fingerprint sensing) to pixel PX. The drive signal may be provided to allow pixel PX to emit light, thereby operating as a light source for photoelectric sensor PHS. In another embodiment, panel driver 210 may supply a drive signal for light sensing and / or another drive signal to photoelectric sensor PHS. However, this is merely illustrative, and the drive signal for light sensing may be provided by sensor driver 220.

[0066] The sensor driver 220 can detect biometric information, such as fingerprint information corresponding to a user's finger, based on sensing signals received from the photoelectric sensor PHS. In an embodiment, the sensor driver 220 can supply drive signals to the photoelectric sensor PHS and / or the pixel PX.

[0067] In one embodiment, panel driver 210 may provide a readout control signal RCS to sensor driver 220, and sensor driver 220 may read out (or sample) a sensing signal associated with panel driver 210 based on the readout control signal RCS. For example, sensor driver 220 may read out or sample the sensing signal in units of at least one pixel row (or horizontal line) in response to the readout control signal RCS.

[0068] Figure 2 It is shown Figure 1 A block diagram of an embodiment of the display device shown.

[0069] Reference Figure 1 and Figure 2 The display panel 100 may include signal lines, at least one pixel PX, and at least one photoelectric sensor PHS. The signal lines may include scan lines S1 to Sn, data lines D1 to Dm, readout lines RX1 to RXo, and reset control line RSTL (or reset line). Here, n, m, and o can be positive integers greater than 1.

[0070] Pixels PX can be arranged or disposed in an area (e.g., a pixel region) divided by scan lines S1 to Sn and data lines D1 to Dm. Photodetector PHS can be arranged or disposed in an area divided by scan lines S1 to Sn and readout lines RX1 to RXo. Pixels PX and photodetector PHS can be arranged in a two-dimensional array in the display area AA of display panel 100, but the disclosure is not limited thereto.

[0071] Pixel PX can be electrically connected (or electrically coupled) to at least one of scan lines S1 to Sn and one of data lines D1 to Dm. Photoelectric sensor PHS can be electrically connected to one of scan lines S1 to Sn, one of readout lines RX1 to RXo, and reset control line RSTL. (Refer to the following...) Figure 5 The connection structure between the pixel PX, the photoelectric sensor PHS, and the signal lines is further described.

[0072] The power voltages VDD, VSS, VRST, and VOBS required to drive the pixel PX and photoelectric sensor PHS can be supplied to the display panel 100. These power voltages can be supplied from a power supply. The power supply can be implemented as a power management IC (PMIC).

[0073] The driving circuit 200 may include a scan driver 211 (or gate driver), a data driver 212 (or source driver), a controller 213 (timing controller or second processor), a reset circuit 221 (or reset unit), and a readout circuit 222 (or readout unit). For example, the scan driver 211, data driver 212, and controller 213 may be included in the panel driver 210, and the reset circuit 221 and readout circuit 222 may be included in the sensor driver 220. However, the disclosure is not limited thereto. For example, the reset circuit 221 may be included in the panel driver 210 (or controller 213).

[0074] The scan driver 211 can be electrically connected to the pixel PX and the photoelectric sensor PHS via scan lines S1 to Sn. The scan driver 211 can generate scan signals based on a scan control signal SCS (or a gate control signal) and sequentially provide the scan signals to scan lines S1 to Sn. The scan control signal SCS may include a start signal, a clock signal, etc., and is provided to the scan driver 211 from the controller 213. For example, the scan driver 211 can be implemented as a shift register that generates and outputs scan signals by sequentially shifting a pulsed start signal using a clock signal. That is, the scan driver 211 can selectively drive the pixel PX and the photoelectric sensor PHS while scanning the display panel 100.

[0075] The scan driver 211 can be formed together with the pixels PX of the display panel 100. However, the scan driver 211 is not limited to this. For example, the scan driver 211 can be implemented as an integrated circuit.

[0076] A pixel PX selectively driven by scan driver 211 can emit light with a brightness corresponding to the data signal provided to the data line. A photoelectric sensor PHS selectively driven by scan driver 211 can output an electrical signal (e.g., a sensing signal, such as current / voltage) corresponding to the sensed light to the readout line. For example, a pixel PX selectively driven by the i-th scan line Si can emit light with a brightness corresponding to the data signal provided to the j-th data line Dj (where i and j are positive integers). For example, a photoelectric sensor PHS selectively driven by the i-th scan line Si can output an electrical signal corresponding to the sensed light to the k-th readout line RXk (where k is a positive integer).

[0077] Data driver 212 can generate data signals (or data voltages) based on image data DATA2 provided from controller 213 and data control signal DCS, and supply the data signals to display panel 100 (or pixels PX) via data lines D1 to Dm. Data control signal DCS can be a signal used to control the operation of data driver 212 and includes a data enable signal (or load signal) indicating the output of a valid data signal, a level start signal, a data clock signal, etc. For example, data driver 212 may include a shift register, a latch, a digital-to-analog converter (or decoder), and a buffer (or amplifier). The shift register generates a sampling signal by shifting the level start signal in sync with the data clock signal. The latch latches image data DATA2 in response to the sampling signal. The digital-to-analog converter (or decoder) converts the latched image data DATA2 (e.g., data in digital form) into a data signal in analog form. The buffer (or amplifier) ​​outputs the data signal to the corresponding data line (e.g., the j-th data line Dj).

[0078] The controller 213 can receive input image data DATA1 and a control signal CS from an external device (e.g., a graphics processor, an application processor, or a first processor), generate a scan control signal SCS and a data control signal DCS based on the control signal CS, and generate image data DATA2 by converting the input image data DATA1. The control signal CS may include, for example, a vertical synchronization signal, a horizontal synchronization signal, a reference clock signal, etc. The vertical synchronization signal may indicate the start of frame data (e.g., data corresponding to the frame period in which a frame image is displayed), and the horizontal synchronization signal may indicate the start of a data line (e.g., a data line included among multiple data lines in the frame data). The controller 213 can convert the input image data DATA1 into image data DATA2 having a format corresponding to the pixel arrangement in the display panel 100.

[0079] Controller 213 can generate a reset control signal and read out the control signal RCS based on the control signal CS.

[0080] The reset circuit 221 can be connected to the photoelectric sensor PHS disposed in the display panel 100 via the reset control line RSTL. For example, the reset circuit 221 can be connected to all photoelectric sensors PHS disposed in the display panel 100 via the reset control line RSTL. The reset circuit 221 can simultaneously provide a reset signal (or reset control signal) to all photoelectric sensors PHS in response to a reset control signal. The reset signal can be a control signal used to provide a reset voltage VRST. Since the reset signal is provided to all photoelectric sensors PHS simultaneously, the reset signal can be referred to as a global reset signal. However, the reset circuit 221 is not limited to this. For example, the reset circuit 221 can be implemented similarly to the scan driver 211 to provide the reset signal sequentially to the photoelectric sensors PHS.

[0081] The readout circuit 222 can receive sensing signals from the photoelectric sensor PHS via readout lines RX1 to RXo and perform signal processing on the sensing signals. For example, the readout circuit 222 can convert the sensing signals in analog form into signals (or digital values) in digital form.

[0082] The read-out sensing signal can be provided as sensing data (or biometric information) to an external device (e.g., an application processor), and biometric authentication (e.g., fingerprint authentication) can be performed based on the sensing data. For example, the read-out sensing signal can be provided to controller 213, and biometric authentication can be performed in controller 213.

[0083] Figure 3 It is shown that it includes Figure 2 A diagram illustrating an example of the arrangement of the backplane circuitry of the display area of ​​the display panel in the display device shown. Figure 4 It is shown that it includes Figure 2 A diagram illustrating an example of the display area of ​​a display panel in a display device.

[0084] Reference Figures 1 to 4 Pixels PX1 to PX4 and multiple photoelectric sensors PHS can be arranged in the display area AA of the display panel 100.

[0085] The display area AA can be divided into pixel rows R1 to R4. Each of the pixel rows R1 to R4 can extend in a first direction DR1 and be arranged in a second direction DR2. Each of the pixel rows R1 to R4 can include pixels PX1 to PX4. Each of the pixels PX1 to PX4 can include one of pixel circuits PXC11 to PXC48 and one of light-emitting elements LED1 to LED4.

[0086] In an embodiment, the first pixel PX1, the second pixel PX2, and the third pixel PX3 can emit light of a first color, a second color, and a third color, respectively. The first color, the second color, and the third color can be different colors of light, and each of the first color, the second color, and the third color can be one of red, green, and blue. In an embodiment, the fourth pixel PX4 and the second pixel PX2 can emit light of the same color. For example, the first light-emitting element LED1 can emit light of the first color, the second light-emitting elements LED2 and the fourth light-emitting element LED4 can emit light of the second color, and the third light-emitting element LED3 can emit light of the third color.

[0087] exist Figure 4 In this context, each of the light-emitting elements LED1 to LED4 can be understood as a light-emitting region corresponding to the light-emitting layer. However, this is for ease of description, and the color of the light emitted by each of the light-emitting elements LED1 to LED4, as well as the position, area, shape, etc. of each of the light-emitting elements LED1 to LED4, are not limited thereto.

[0088] In an embodiment, pixels PX1 to PX4 may be arranged relative to the first direction DR1 in each of an odd-numbered pixel row including a first pixel row R1 (or a first horizontal line) and a third pixel row R3 (or a third horizontal line) in the order of a first pixel PX1 emitting red light, a second pixel PX2 emitting green light, a third pixel PX3 emitting blue light, and a fourth pixel PX4 emitting green light.

[0089] Pixels PX1 to PX4 can be arranged relative to the first direction DR1 in the order of third pixel PX3, fourth pixel PX4, first pixel PX1 and second pixel PX2 in each of the even-numbered pixel rows including the second pixel row R2 (or the second horizontal line) and the fourth pixel row R4 (or the fourth horizontal line).

[0090] In this embodiment, the first pixel PX1 and the second pixel PX2 can constitute a first sub-pixel unit SPU1, and the third pixel PX3 and the fourth pixel PX4 can constitute a second sub-pixel unit SPU2. Therefore, the first sub-pixel unit SPU1 and the second sub-pixel unit SPU2 can be alternately arranged on odd-numbered pixel rows R1 and R3, and the second sub-pixel unit SPU2 and the first sub-pixel unit SPU1 can be alternately arranged on even-numbered pixel rows R2 and R4 in a pattern opposite to the pattern in which the first sub-pixel unit SPU1 and the second sub-pixel unit SPU2 are alternately arranged on odd-numbered pixel rows R1 and R3.

[0091] It is understandable that adjacent first sub-pixel units SPU1 and second sub-pixel units SPU2 constitute a pixel unit PU. For example, Figure 4 The pixel unit PU of each of the first pixel row R1 and the second pixel row R2 is shown. However, this is only illustrative, and the arrangement of pixels PX is not limited to this.

[0092] Pixel circuits PXC11 to PXC18, corresponding to pixels PX1 to PX4 of the first pixel row R1, can be arranged in the first pixel row R1 along the first direction DR1. Pixel circuits PXC21 to PXC28, corresponding to pixels PX1 to PX4 of the second pixel row R2, can be arranged in the second pixel row R2 along the first direction DR1. Similarly, pixel circuits PXC31 to PXC38 and PXC41 to PXC48, corresponding to pixels PX1 to PX4 of the third pixel row R3 and the fourth pixel row R4, respectively, can be arranged in the third pixel row R3 and the fourth pixel row R4 along the first direction DR1.

[0093] exist Figure 3 In the first pixel row R1, the first pixel circuit PXC11, the second pixel circuit PXC12, the third pixel circuit PXC13, and the fourth pixel circuit PXC14 can be included in the pixel unit PU, and the fifth pixel circuit PXC15, the sixth pixel circuit PXC16, the seventh pixel circuit PXC17, and the eighth pixel circuit PXC18 of the first pixel row R1 can be included in another pixel unit PU.

[0094] Similarly, the first pixel circuits PXC21 to PXC24 of the second pixel row R2, the fifth pixel circuits PXC25 to PXC28 of the second pixel row R2, the first pixel circuits PXC31 to PXC34 of the third pixel row R3, the fifth pixel circuits PXC35 to PXC38 of the third pixel row R3, the first pixel circuits PXC41 to PXC44 of the fourth pixel row R4, and the fifth pixel circuits PXC45 to PXC48 of the fourth pixel row R4 can also be included in different pixel units PU.

[0095] In an embodiment, each of pixel rows R1 to R4 may include light receiving elements LRD1 to LRD4. Figure 4 In this context, each of the optical receiving elements LRD1 to LRD4 can be understood as an optical receiving region corresponding to the optical receiving layer. However, this is only for ease of description, and the position, area, shape, etc., of each of the optical receiving elements LRD1 to LRD4 are not limited thereto.

[0096] The light-receiving elements LRD1 and LRD2 of the first pixel row R1 can be stacked with at least a portion of the pixel circuits PXC11 to PXC14 of the first pixel row R1 and the sensor circuits SC11 and SC12 of the first pixel row R1, respectively. The light-receiving elements LRD3 and LRD4 of the second pixel row R2 can be stacked with at least a portion of the pixel circuits PXC21 to PXC24 of the second pixel row R2 and the sensor circuits SC21 and SC22 of the second pixel row R2, respectively.

[0097] In an embodiment, the first light receiving element LRD1 may be superimposed on at least a portion of the first sensor circuit SC11 of the first pixel row R1, and the third light receiving element LRD3 may be superimposed on at least a portion of the first sensor circuit SC21 of the second pixel row R2.

[0098] Additionally, refer to Figure 4 The second light receiving element LRD2 can be superimposed on at least a portion of the second sensor circuit SC12 of the first pixel row R1, and the fourth light receiving element LRD4 can be superimposed on at least a portion of the second sensor circuit SC22 of the second pixel row R2.

[0099] Optical receiving elements LRD1 to LRD4 can be used as Figure 4 The arrangement shown is formed in the display area AA.

[0100] In this embodiment, sensor circuits SC11 to SC44 can be connected to corresponding light-receiving elements, respectively. For example, the first sensor circuit SC11 of the first pixel row R1 can be connected to the first light-receiving element LRD1, and the first sensor circuit SC11 and the first light-receiving element LRD1 can constitute a photoelectric sensor PHS. Similarly, the second sensor circuit SC12 of the first pixel row R1 can be connected to the second light-receiving element LRD2, the first sensor circuit SC21 of the second pixel row R2 can be connected to the third light-receiving element LRD3, and the second sensor circuit SC22 of the second pixel row R2 can be connected to the fourth light-receiving element LRD4. However, the disclosure is not limited thereto. For example, only some of the sensor circuits SC11 to SC44 can be provided, and some of the sensor circuits SC11 to SC44 can be connected to multiple light-receiving elements LRD1 to LRD4.

[0101] The first sensor circuit SC11 of the first pixel row R1 can be arranged between the first sub-pixel unit SPU1 and the second sub-pixel unit SPU2 included in the pixel unit PU. For example, the first pixel circuit PXC11 and the second pixel circuit PXC12 of the first pixel row R1 can be included in the first sub-pixel unit SPU1, and the third pixel circuit PXC13 and the fourth pixel circuit PXC14 of the first pixel row R1 can be included in the second sub-pixel unit SPU2. Therefore, at least two pixel circuits (e.g., pixel circuits PXC13 and PXC14) can be arranged between the first sensor circuit SC11 and the second sensor circuit SC12 that are adjacent to each other in the first pixel row R1.

[0102] Similar to the first sensor circuit SC11 of the first pixel row R1, the second sensor circuit SC12 of the first pixel row R1, the first sensor circuit SC21 of the second pixel row R2, and the second sensor circuit SC22 of the second pixel row R2 can be arranged between the first sub-pixel unit SPU1 and the second sub-pixel unit SPU2. The arrangement of other sensor circuits (e.g., sensor circuits SC13, SC14, SC23, SC24, SC31, SC32, SC33, SC34, SC41, SC42, SC43, and SC44) is similar to that of the first sensor circuit SC21 and the second sensor circuit SC22.

[0103] Figure 5 It is shown that it includes Figure 4 The circuit diagram shows an example of pixels and a photoelectric sensor in the display area shown. For ease of description, in Figure 5 The image shows a pixel PX positioned on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj. Additionally, the i-th scan lines S1i to S4i (and the j-th emission control line Ei) can be included in, for example... Figure 2 The scan lines S1 to Sn or the i-th scan line Si shown are shown.

[0104] Reference Figures 1 to 5 The pixel PX and the photoelectric sensor PHS can be set on the i-th horizontal line.

[0105] A pixel PX may include a light-emitting element LED and a pixel circuit PXC. The pixel circuit PXC may include a first transistor T1 and a second transistor T2. In an embodiment, the pixel circuit PXC may also include a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, as well as a storage capacitor Cst.

[0106] A first transistor T1 (or driving transistor) may be connected between a first power line PL1 and a first electrode of a light-emitting element (LED). The first transistor T1 may include a gate electrode connected to a first node N1. The first transistor T1 may control the amount of current (or driving current) flowing from the first power line PL1 through the LED to the electrode EP (or power line) based on the voltage of the first node N1. A first power voltage VDD may be provided to the first power line PL1, and a second power voltage VSS may be provided to the electrode EP. The first power voltage VDD may be set to a voltage higher than the second power voltage VSS.

[0107] The second transistor T2 (or switching transistor) can be connected to the j-th data line Dj and the second node N2. The gate electrode of the second transistor T2 can be connected to the 1i-th scan line S1i (or the first scan line). The second transistor T2 can be turned on when the first scan signal GW[i] (e.g., a first scan signal with a low level) is supplied to the 1i-th scan line S1i to electrically connect the j-th data line Dj and the second node N2 to each other. With each of the first transistor T1 and the third transistor T3 in the on state, the second transistor T2 can transmit the data signal of the j-th data line Dj to the first node N1 in response to the first scan signal GW[i].

[0108] The third transistor T3 can be connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 can be connected to the 4i scan line S4i (or the fourth scan line). The third transistor T3 can be turned on when the fourth scan signal GC[i] is supplied to the 4i scan line S4i. When the third transistor T3 is turned on, the first transistor T1 can be a diode.

[0109] A fourth transistor T4 can be connected between the first node N1 and the second power line PL2. The gate electrode of the fourth transistor T4 can be connected to the 2i scan line S2i (or the second scan line). A first initialization power voltage Vint1 can be provided to the second power line PL2. The fourth transistor T4 can be turned on by the second scan signal GI[i] supplied to the 2i scan line S2i. When the fourth transistor T4 is turned on, the first initialization power voltage Vint1 can be supplied to the first node N1 (e.g., the gate electrode of the first transistor T1).

[0110] The fifth transistor T5 can be connected between the first power line PL1 and the second node N2. The gate electrode of the fifth transistor T5 can be connected to the i-th emitter control line Ei. The sixth transistor T6 can be connected between the third node N3 and the light-emitting element LED (or the fourth node N4). The gate electrode of the sixth transistor T6 can be connected to the i-th emitter control line Ei. The fifth transistor T5 and the sixth transistor T6 can be turned off when the emitter control signal EM[i] (e.g., an emitter control signal EM[i] with a high level) is supplied to the i-th emitter control line Ei, and turned on under other conditions.

[0111] A seventh transistor T7 can be connected between the first electrode (e.g., the fourth node N4) of the LED and the third power line PL3. The gate electrode of the seventh transistor T7 can be connected to the 3i scan line S3i (or the third scan line). A second initialization voltage Vint2 can be provided to the third power line PL3. The second initialization voltage Vint2 can be approximately equal to or different from the first initialization voltage Vint1. The seventh transistor T7 can be turned on by the third scan signal GB[i] supplied to the 3i scan line S3i to supply the second initialization voltage Vint2 to the first electrode of the LED.

[0112] The eighth transistor T8 can be connected between the fifth power line PL5 and the second node N2. The gate electrode of the eighth transistor T8 can be connected to the third scan line S3i. The bias voltage VOBS can be provided to the fifth power line PL5. The eighth transistor T8 can be turned on by the third scan signal GB[i] supplied to the third scan line S3i to supply the bias voltage VOBS to the second node N2.

[0113] The storage capacitor Cst (or capacitor) can be connected or formed between the first power line PL1 and the first node N1.

[0114] The photoelectric sensor PHS may include a sensor circuit SC and a light receiving element LRD. The sensor circuit SC may include a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12.

[0115] The ninth transistor T9 and the eleventh transistor T11 can be connected in series between the third power line PL3 (or the reference power line) and the k-th readout line RXk (k is a positive integer).

[0116] The ninth transistor T9 (or the first sensor transistor) can be connected between the third power line PL3 and the eleventh transistor T11. The gate electrode of the ninth transistor T9 can be connected to the fifth node N5 (or the sensor node). The ninth transistor T9 can respond to the voltage control of the fifth node N5 to the current flowing from the third power line PL3 through the eleventh transistor T11 to the k-th readout line RXk. A capacitor Cd (or parasitic capacitor) can be formed between the fifth node N5 and any signal line (e.g., the fourth power line PL4).

[0117] The tenth transistor T10 (or the second sensor transistor) can be connected between the fourth power line PL4 (or the reset power line) and the fifth node N5. The gate electrode of the tenth transistor T10 can be connected to the reset control line RSTL. The reset voltage VRST can be provided to the fourth power line PL4.

[0118] The eleventh transistor T11 (or the third sensor transistor) can be connected between the ninth transistor T9 and the k-th readout line RXk. The gate electrode of the eleventh transistor T11 can be connected to the 1i scan line S1i. That is, the gate electrode of the eleventh transistor T11 and the gate electrode of the second transistor T2 can share the 1i scan line S1i.

[0119] The eleventh transistor T11 may include two sub-transistors connected in series between the ninth transistor T9 and the k-th readout line RXk (see...). Figure 11 In other words, the eleventh transistor T11 can be implemented as a dual-gate transistor. Therefore, current leakage through the eleventh transistor T11 and the sensing error of the sensor circuit SC caused by current leakage can be reduced, and the stability of the photoelectric sensor PHS can be improved.

[0120] The twelfth transistor T12 (or the fourth sensor transistor) can be connected between the optical receiver element LRD and the fifth node N5. The gate electrode of the twelfth transistor T12 can be connected to the gate line TGL. The twelfth transistor T12 can be turned on by the gate signal TG (or control signal) supplied to the gate line TGL to connect the optical receiver element LRD to the fifth node N5.

[0121] In an embodiment, the gate signal TG provided to the gate line TGL and the first scan signal GW[i] provided to the first scan line S1i can have the same wavelength and the same phase. In an embodiment, the gate line TGL can be connected to the first scan line S1i.

[0122] At least one light-receiving element (LRD) can be connected between the fifth node N5 and the electrode EP to which the second electrical voltage VSS is supplied. The light-receiving element LRD can generate charge (or current) based on incident light. That is, the light-receiving element LRD can perform photoelectric conversion. For example, the light-receiving element LRD can be implemented as a photodiode. A capacitor Cpd (or parasitic capacitor) can be formed between the anode electrode and the electrode EP of the light-receiving element LRD.

[0123] With the tenth transistor T10 turned on by the reset signal RST supplied to the reset control line RSTL, the reset voltage VRST can be provided to the fifth node N5. For example, the voltage of the fifth node N5 can be reset by the reset voltage VRST. The photodetector LRD can then perform photoelectric conversion after the reset voltage VRST is applied to the fifth node N5.

[0124] The voltage of the fifth node N5 can be changed by the operation of the optical receiver element LRD. The voltage of the fifth node N5 (or the charge or current generated by the optical receiver element LRD) can be changed according to the intensity of the light incident on the optical receiver element LRD and the time of light incident (or the time the optical receiver element LRD is exposed to light).

[0125] When the eleventh transistor T11 is turned on by the first scan signal GW[i] supplied to the 1i scan line S1i, the detected value (current and / or voltage) generated based on the voltage of the fifth node N5 can flow into the k-th readout line RXk.

[0126] In this embodiment, each of the pixel circuit PXC and the sensor circuit SC may include a p-type transistor and an n-type transistor. In this embodiment, the third transistor T3, the fourth transistor T4, the tenth transistor T10, and the twelfth transistor T12 may be implemented using oxide semiconductor transistors that include oxide semiconductors (or a second type of semiconductor). For example, the third transistor T3, the fourth transistor T4, the tenth transistor T10, and the twelfth transistor T12 may be implemented using n-type oxide semiconductor transistors and include an oxide semiconductor layer as an active layer.

[0127] Oxide semiconductor transistors can be fabricated using low-temperature processes and have a lower charge mobility than polycrystalline silicon semiconductor transistors. In other words, oxide semiconductor transistors exhibit excellent cutoff current characteristics. Therefore, current leakage in the third transistor T3, the fourth transistor T4, the tenth transistor T10, and the twelfth transistor T12 can be minimized or reduced.

[0128] Other transistors (e.g., first transistor T1, second transistor T2, fifth transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8, ninth transistor T9, and eleventh transistor T11) can be implemented using polycrystalline silicon semiconductor transistors that include silicon semiconductors (or first-type semiconductors), and include a polycrystalline silicon semiconductor layer as the active layer. For example, the active layer can be formed using a low-temperature polycrystalline silicon (LTPS) process. For example, the polycrystalline silicon semiconductor transistor can be a p-type polycrystalline silicon transistor. Polycrystalline silicon semiconductor transistors can be used as switching elements that operate with fast switching speeds due to their high response speed.

[0129] Figure 6 It is shown Figure 5 The waveform diagram shows an embodiment of the operation of the pixels.

[0130] Reference Figure 1 , Figure 2 , Figure 5 and Figure 6 The transmit control signal EM[i] can be provided to the i-th transmit control line Ei, the second scan signal GI[i] can be provided to the 2i-th scan line S2i, the fourth scan signal GC[i] can be provided to the 4i-th scan line S4i, the first scan signal GW[i] can be provided to the 1i-th scan line S1i, and the third scan signal GB[i] can be provided to the 3i-th scan line S3i.

[0131] At time t1, the emission control signal EM[i] can be high (or at the first voltage level). The fifth transistor T5 and the sixth transistor T6 can be turned off in response to the high-level emission control signal EM[i], therefore, pixel PX does not emit light.

[0132] At time point t2, the second scan signal GI[i] can be high. The fourth transistor T4 can be turned on in response to the second scan signal GI[i] being high, and the first initial power voltage Vint1 of the second power line PL2 can be provided to the first node N1 (or the gate electrode of the first transistor T1).

[0133] At time point t3, the fourth scan signal GC[i] can be high. The third transistor T3 can turn on in response to the high-level fourth scan signal GC[i], and the first transistor T1 can be diode-connected.

[0134] At time t4, the first scan signal GW[i] can be at a low level (or a second voltage level). The second transistor T2 can turn on in response to the low-level first scan signal GW[i], and the data signal from the j-th data line Dj can be provided to the second node N2. Additionally, because the third transistor T3 is in a state where it turns on in response to the high-level fourth scan signal GC[i], the data signal from the second node N2 can be transmitted to the first node N1 via the first transistor T1 and the third transistor T3. Because the diode-connected first transistor T1 is held in place by the conducting third transistor T3, the voltage of the first node N1 can have a voltage obtained by compensating for the threshold voltage of the first transistor T1 in the data signal.

[0135] At time point t5, the third scan signal GB[i] may be low. The seventh transistor T7 may turn on in response to the low-level third scan signal GB[i], and the second initialization power voltage Vint2 may be supplied to the light-emitting element LED. Additionally, the eighth transistor T8 may turn on in response to the low-level third scan signal GB[i], and the bias voltage VOBS may be supplied to the second node N2. In this embodiment, the third scan signal GB[i] may be the first scan signal provided to the previous row. However, the third scan signal GB[i] is not limited to this.

[0136] At time point t6, the transmit control signal EM[i] can be low. The fifth transistor T5 and the sixth transistor T6 can turn on in response to the low-level transmit control signal EM[i], and a current flow path can be formed from the first power line PL1 through the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting element LED to the electrode EP. The drive current corresponding to the voltage (e.g., a data signal) of the first node N1 can flow through the light-emitting element LED according to the operation of the first transistor T1, and the light-emitting element LED can emit light with a brightness corresponding to the drive current.

[0137] Figure 7 It is shown Figure 5 Waveform diagram of an embodiment of the operation of the photoelectric sensor shown. Figures 8 to 10 It is shown Figure 5 The diagram shows the operation of the photoelectric sensor.

[0138] Reference Figures 7 to 10The reset signal RST can be provided to the reset control line RSTL, the first scan signal GW[i] can be provided to the first scan line S1i, and the gate signal TG can be provided to the gate line TGL. The reset signal RST can be provided to multiple photodetectors PHS, and the first scan signal GW[i] and the gate signal TG can be provided to multiple photodetectors PHS sequentially in units of horizontal lines. The gate signal TG and the first scan signal GW[i] can have the same wavelength and the same phase. In some embodiments, when the gate line TGL is connected to the first scan line S1i, the gate signal TG can be the first scan signal GW[i].

[0139] The sensing period may include a first frame (FRAME1) and a second frame (FRAME2). The first frame (FRAME1) and the second frame (FRAME2) may be adjacent to each other (e.g., directly adjacent), but the disclosure is not limited thereto. For example, at least one frame may be set between the first frame (FRAME1) and the second frame (FRAME2). Time points t7 to t10 may occur sequentially within the sensing period.

[0140] At time point t7 (or the first time point) of the first frame FRAME1, each of the reset signal RST, gate signal TG, and first scan signal GW[i] can be high. For example... Figure 8 As shown, the tenth transistor T10 can be turned on in response to a high-level reset signal RST, and the voltage of the fifth node N5 (and capacitor Cd) can be reset by the reset signal RST. Additionally, the twelfth transistor T12 can be turned on in response to a high-level gate signal TG, the photodetector LRD can be connected to the fifth node N5, and the anode electrode of the photodetector LRD (and capacitor Cpd) can be reset. The eleventh transistor T11 can remain off in response to a high-level first scan signal GW[i].

[0141] Subsequently, at time point t8 (or the second time point), each of the reset signal RST, the first scan signal GW[i], and the gate signal TG can be at a low level. For example... Figure 9 As shown, the tenth transistor T10 can be turned off in response to a low-level reset signal RST, and the twelfth transistor T12 can be turned off in response to a low-level gate signal TG. The eleventh transistor T11 can be turned on in response to a low-level first scan signal GW[i], and the current corresponding to the voltage of the fifth node N5 can flow from the third power line PL3 through the ninth transistor T9 and the eleventh transistor T11 into the k-th readout line RXk. From the perspective of photosensing, the current can represent the substrate or noise. The current read through the k-th readout line RXk at time point t8 can be called the first sensing current.

[0142] Subsequently, at time point t9 (or the third time point), each of the gate signal TG and the first scan signal GW[i] can have a high level. For example... Figure 10 As shown, the twelfth transistor T12 can be turned on in response to a gate signal TG with a high level, and the optical receiver element LRD can be connected to the fifth node N5.

[0143] During the period between time point t9 and time point t10, the light receiving element LRD can generate charge (or current) based on the incident light. When light is incident on the light receiving element LRD during the exposure time EIT, the voltage of the fifth node N5 can be changed by the photoelectric conversion function of the light receiving element LRD.

[0144] Subsequently, at time point t10 (or the fourth time point) of the second frame FRAME2, each of the first scan signal GW[i] and the gate signal TG can be at a low level. For example... Figure 9 As shown, the twelfth transistor T12 can be turned off in response to a gate signal TG with a low level. The eleventh transistor T11 can be turned on in response to a first scan signal GW[i] with a low level, and the current corresponding to the voltage of the fifth node N5 can flow from the third power line PL3 through the ninth transistor T9 and the eleventh transistor T11 into the k-th read line RXk. For example, in Figure 1 In the event of a user's touch input on the display panel 100 shown, a current corresponding to the light reflected by the user (e.g., the user's finger) can be read at time point t10 via the k-th readout line RXk. This current can represent the amount of light during the exposure time EIT and includes noise at time point t8. The current read at time point t10 via the k-th readout line RXk can be referred to as the second sensing current.

[0145] Figure 2 The readout circuit 222 shown can perform a subtraction operation on the first sensing current read at time point t8 (or the second time point) and the second sensing current read at time point t10 (or the fourth time point) to obtain a sensing signal corresponding to the amount of light during the exposure time EIT. In other words, noise in the sensing signal is removed, thus improving sensing capability.

[0146] In some embodiments, the exposure time EIT for the respective plurality of photoelectric sensors PHS can be constant or identical. Therefore, by taking into account the differences in exposure time EIT for each photoelectric sensor PHS, no additional correction to the sensing signal is required, and the load on sensing operations can be reduced.

[0147] Figure 11 and Figure 12 It is shown Figure 4 A plan view of an embodiment of the display area shown. Figure 11 and Figure 12 In, it is shown Figure 5 The pixel circuit PXC and sensor circuit SC are shown in the diagram. Figure 13 It is shown Figure 4 A cross-sectional view of an embodiment of the display area shown.

[0148] exist Figures 11 to 13 In this work, for illustrative purposes, subpixels are simplified and each electrode is represented as having a single-layer structure, and each insulating layer is depicted as a single layer. However, the disclosure is not limited thereto.

[0149] In the disclosed embodiments, "formed and / or disposed in the same layer" can mean formed by the same process, and "formed and / or disposed in different layers" can mean formed by different processes.

[0150] Reference Figure 4 , Figure 5 and Figures 11 to 13 The pixel circuit PXC and the sensor circuit SC can be respectively connected to... Figure 4 The fourth pixel circuit PXC14 of the first pixel row R1 shown corresponds to the second sensor circuit SC12. Figure 4 Each of the other pixel circuits PXC11 to PXC13 and PXC21 to PXC24 shown can be substantially the same as, or laterally symmetrical to, the fourth pixel circuit PXC14. Additionally, Figure 4 Each of the other sensor circuits SC11, SC21, and SC22 shown can be substantially the same as or similar to the second sensor circuit SC12. Figure 13 The diagram exemplarily illustrates a first transistor T1, a fourth transistor T4, an eleventh transistor T11, and a twelfth transistor T12. Each of the other transistors T2, T3, T5, T6, T7, T8, T9, and T10 may have a cross-sectional structure substantially the same as or similar to that of the first transistor T1, the fourth transistor T4, the eleventh transistor T11, or the twelfth transistor T12.

[0151] In the following text, based on Figure 13 The components are described according to the order in which they are stacked on the base layer BL.

[0152] The substrate layer (BL) can be made of an insulating material such as glass or resin. The substrate layer (BL) can be made of a reflective material that is flexible or foldable. The substrate layer (BL) can have a single-layer structure or a multi-layer structure.

[0153] The backplane structure BP, which includes the pixel circuit PXC and the sensor circuit SC, can be disposed on the substrate layer BL. The backplane structure BP may include a semiconductor layer, multiple conductive layers, and multiple insulating layers.

[0154] The buffer layer BF can be disposed on the substrate layer BL. The buffer layer BF can be an insulating layer comprising inorganic materials. For example, the inorganic material can include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and such as aluminum oxide (AlO) x At least one of the metal oxides of ( ). The buffer layer BF can be a single layer or a multilayer comprising at least two layers. The buffer layer BF can prevent impurities from diffusing into the transistor.

[0155] In some embodiments, the lower electrode BML may be disposed between the substrate layer BL and the buffer layer BF. The lower electrode BML may be stacked with the first transistor T1 (or the first capacitor electrode CE1 and the second capacitor electrode CE2). The lower electrode BML may shield the first transistor T1 (or the first capacitor electrode CE1 and the second capacitor electrode CE2) below it. A constant voltage may be applied to the lower electrode BML. For example, a first electrical voltage VDD may be applied to the lower electrode BML, but the disclosure is not limited thereto. The lower electrode BML may include a conductive material.

[0156] The first active layer ACT (or the first semiconductor layer) may be disposed on the buffer layer BF. The first active layer ACT may include a first semiconductor pattern ACT1 of the pixel circuit PXC and a second semiconductor pattern ACT2 of the sensor circuit SC. The first semiconductor pattern ACT1 and the second semiconductor pattern ACT2 may include polysilicon semiconductors.

[0157] The first semiconductor pattern ACT1, superimposed on the first capacitor electrode CE1, can constitute the channel region of the first transistor T1. The first semiconductor pattern ACT1 can extend from both opposite ends of the channel region of the first transistor T1 along the second direction DR2. The first semiconductor pattern ACT1, superimposed on the i-th emitter control line Ei (or emitter bridge pattern BR_Ei), can constitute the channel regions of the fifth transistor T5 and the sixth transistor T6. The first semiconductor pattern ACT1 can also extend from the channel region of the sixth transistor T6 along the second direction DR2. The first semiconductor pattern ACT1, superimposed on the 3i scan line S3i, can constitute the channel region of the seventh transistor T7. The first semiconductor pattern ACT1 can also extend from the channel region of the fifth transistor T5 along the second direction DR2. The first semiconductor pattern ACT1, superimposed on the 3i scan line S3i, can constitute the channel region of the eighth transistor T8. The first semiconductor pattern ACT1 can extend from the right end of the channel region of the first transistor T1 in the opposite direction to the second direction DR2. The first semiconductor pattern ACT1 superimposed on the first scan line S1i can form the channel region of the second transistor T2.

[0158] For example, the channel region is an undoped semiconductor pattern and may be an intrinsic semiconductor. Other regions of the semiconductor pattern besides the channel region (e.g., other regions of the first semiconductor pattern ACT1) may be doped semiconductor patterns.

[0159] The second semiconductor pattern ACT2 can be separated from the first semiconductor pattern ACT1 in the first direction DR1. The second semiconductor pattern ACT2 superimposed on the first bridging pattern BRP1 can form the channel region of the ninth transistor T9. The second semiconductor pattern ACT2 superimposed on the first scan line S1i can form the channel region of the eleventh transistor T11 (or two sub-transistors).

[0160] A first gate insulating layer GI1 (or a first insulating layer) may be disposed above the first active layer ACT. The first gate insulating layer GI1 may be an insulating layer made of inorganic material.

[0161] A first conductive layer GAT1 may be disposed on a first gate insulating layer GI1. The first conductive layer GAT1 may include a conductive material. For example, the conductive material may include copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and / or any alloy thereof. The first conductive layer GAT1 may include a lower electrode BML.

[0162] The first conductive layer GAT1 may include a first capacitor electrode CE1, a first bridging pattern BRP1, an emission bridging pattern BR_Ei, a first i-th scan line S1i, a third i-th scan line S3i, and a second power line PL2. The emission bridging pattern BR_Ei may be connected to the i-th emission control line Ei, which will be further described below.

[0163] The first capacitor electrode CE1, which is superimposed on the first semiconductor pattern ACT1, can form the gate electrode of the first transistor T1.

[0164] The first bridging pattern BRP1 superimposed on the first semiconductor pattern ACT1 can form the gate electrode of the ninth transistor T9.

[0165] The first scan line S1i and the emitter bridging pattern BR_Ei can be separated from each other, while the first capacitor electrode CE1 is placed between the first scan line S1i and the emitter bridging pattern BR_Ei. Each of the first scan line S1i, the emitter bridging pattern BR_Ei, the third scan line S3i, and the second electric field line PL2 can extend substantially in the first direction DR1.

[0166] The first scan line S1i, which is superimposed on the first semiconductor pattern ACT1, can form the gate electrode of the second transistor T2.

[0167] The first scan line S1i, superimposed on the second semiconductor pattern ACT2, can constitute the gate electrode of the eleventh transistor T11. In an embodiment, the first scan line S1i can be superimposed on the channel region of the twelfth transistor T12. In some embodiments, the first scan line S1i may include a protrusion superimposed on the channel region of the twelfth transistor T12.

[0168] The emitter bridge pattern BR_Ei superimposed on the first semiconductor pattern ACT1 can form the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6.

[0169] The third scan line S3i, which is superimposed on the first semiconductor pattern ACT1, can form the gate electrode of the seventh transistor T7 and the gate electrode of the eighth transistor T8.

[0170] The second gate insulating layer GI2 (or the second insulating layer) can be disposed on the first conductive layer GAT1. The second gate insulating layer GI2 can be an insulating layer made of inorganic material.

[0171] The second conductive layer GAT2 may be disposed on the second gate insulating layer GI2. The second conductive layer GAT2 may include a conductive material. The second conductive layer GAT2 may include a second capacitor electrode CE2, a second scan line S2i, a fourth scan line S4i, a reset control line RSTL, and a fourth power bridge pattern BR_PL4.

[0172] The second capacitor electrode CE2 may be stacked with the first capacitor electrode CE1 to form a storage capacitor Cst. A large portion of the second capacitor electrode CE2 may be stacked with the first capacitor electrode CE1. The second capacitor electrode CE2 may include an opening that exposes the first capacitor electrode CE1.

[0173] In the plane (in the plan view), the 2i scan line S2i, the 4i scan line S4i, the reset control line RSTL and the fourth power bridge pattern BR_PL4 can be separated from each other in the second direction DR2, and each of the 2i scan line S2i, the 4i scan line S4i, the reset control line RSTL and the fourth power bridge pattern BR_PL4 can extend substantially in the first direction DR1.

[0174] The first interlayer insulating layer ILD1 (or the third insulating layer) can be disposed on top of the second conductive layer GAT2. The first interlayer insulating layer ILD1 can be an insulating layer made of inorganic material.

[0175] The second active layer OCT (or second semiconductor layer) may be disposed on the first interlayer insulating layer ILD1. The second active layer OCT may include a third semiconductor pattern ACT3 of the pixel circuit PXC and a fourth semiconductor pattern ACT4 of the sensor circuit SC. The third semiconductor pattern ACT3 and the fourth semiconductor pattern ACT4 may include oxide semiconductors.

[0176] The third semiconductor pattern ACT3 (or the third semiconductor pattern ACT3a) superimposed on the second scan line S2i (and the second scan gate electrode A_S2i) can form the channel region of the fourth transistor T4. The third semiconductor pattern ACT3 superimposed on the fourth scan line S4i (and the fourth scan gate electrode A_S4i) can form the channel region of the third transistor T3. The third semiconductor pattern ACT3 (or the third semiconductor pattern ACT3b) can be partially superimposed on the second power line PL2. The fourth semiconductor pattern ACT4 superimposed on the reset control line RSTL (and the reset bridge pattern BR_RSTL) can form the channel region of the tenth transistor T10. The fourth semiconductor pattern ACT4 superimposed on the gate line TGL (or the gate pattern A_TGL) can form the channel region of the twelfth transistor T12.

[0177] The third gate insulating layer GI3 (or the fourth insulating layer) can be disposed above the second active layer OCT. The third gate insulating layer GI3 can be an insulating layer made of inorganic material.

[0178] The third conductive layer GAT3 can be disposed on the third gate insulating layer GI3. The third conductive layer GAT3 may include a conductive material. The third conductive layer GAT3 may include the second scan gate electrode A_S2i, the fourth scan gate electrode A_S4i, the first emitter control line Ei, the fifth power line PL5, the gate line TGL, the reset bridge pattern BR_RSTL, and the second bridge pattern BRP2.

[0179] The second scan gate electrode A_S2i can be connected to the second scan line S2i through a contact hole CNT that penetrates the third gate insulating layer GI3, the first interlayer insulating layer ILD1, and the second gate insulating layer GI2. The second scan gate electrode A_S2i, which is superimposed on the third semiconductor pattern ACT3, can form the gate electrode of the fourth transistor T4.

[0180] The 4i scan gate electrode A_S4i can be connected to the 4i scan line S4i through a contact hole. The 4i scan gate electrode A_S4i, which is superimposed on the third semiconductor pattern ACT3, can form the gate electrode of the third transistor T3.

[0181] The reset bridge pattern BR_RSTL can be connected to the reset control line RSTL via a contact hole. The reset bridge pattern BR_RSTL, superimposed on the fourth semiconductor pattern ACT4, can form the gate electrode of the tenth transistor T10.

[0182] The i-th transmit control line Ei can be connected to the transmit bridging pattern BR_Ei via a contact hole.

[0183] The fifth power line PL5 can be connected to the fourth power bridge pattern BR_PL4 via a contact hole. The fifth power line PL5 can also be connected to the first semiconductor pattern ACT1 via a contact hole.

[0184] The gate line TGL can extend in the first direction DR1. The gate line TGL superimposed with the fourth semiconductor pattern ACT4 can form the gate electrode of the twelfth transistor T12. In some embodiments, the gate line TGL can be superimposed with the first scan line S1i (or a protrusion of the first scan line S1i).

[0185] The second interlayer insulating layer ILD2 can be disposed on top of the third conductive layer GAT3. The second interlayer insulating layer ILD2 can be an insulating layer made of inorganic materials, but the disclosure is not limited thereto.

[0186] The fourth conductive layer SD1 may be disposed on the second interlayer insulating layer ILD2. The fourth conductive layer SD1 may include a conductive material. The fourth conductive layer SD1 may include the third bridging pattern BRP3 to the ninth bridging pattern BRP9, the first electric field line PL1, the third electric field line PL3, and the fourth electric field line PL4.

[0187] The third bridging pattern BRP3 can be connected to the third semiconductor pattern ACT3 (e.g., the third semiconductor pattern ACT3 between the third transistor T3 and the fourth transistor T4) through a contact hole. The third bridging pattern BRP3 can be connected to the first capacitor electrode CE1 through an opening in the second capacitor electrode CE2. The third bridging pattern BRP3 can be configured as... Figure 5 The first node N1 is shown in the diagram.

[0188] The fourth bridging pattern BRP4 can be connected to the first semiconductor pattern ACT1 (e.g., the first semiconductor pattern ACT1 on the upper side of the second transistor T2) through a contact hole.

[0189] The fifth bridging pattern BRP5 can be connected to the first semiconductor pattern ACT1 (e.g., the first semiconductor pattern ACT1 between the sixth transistor T6 and the seventh transistor T7) via a contact hole. The fifth bridging pattern BRP5 can constitute... Figure 5 The fourth node N4 is shown in the diagram.

[0190] The sixth bridging pattern BRP6 can be connected to the third semiconductor pattern ACT3 (or the 3b semiconductor pattern ACT3b) via a contact hole. The sixth bridging pattern BRP6 can be connected to the second power line PL2 via a contact hole. The sixth bridging pattern BRP6 can connect the third semiconductor pattern ACT3 (or the 3b semiconductor pattern ACT3b) to the second power line PL2.

[0191] The seventh bridging pattern BRP7 can be connected to the first bridging pattern BRP1 and the fourth semiconductor pattern ACT4 (e.g., the fourth semiconductor pattern ACT4 located on the underside of the twelfth transistor T12) via contact holes. The seventh bridging pattern BRP7 can connect the first bridging pattern BRP1 and the fourth semiconductor pattern ACT4 to each other, and constitutes... Figure 5 The fifth node N5 is shown in the diagram.

[0192] The eighth bridging pattern BRP8 can be connected to the second semiconductor pattern ACT2 (e.g., the second semiconductor pattern ACT2 on the upper side of the eleventh transistor T11) through a contact hole.

[0193] The ninth bridging pattern BRP9 can be connected to the fourth semiconductor pattern ACT4 (e.g., the fourth semiconductor pattern ACT4 on the upper side of the twelfth transistor T12) via a contact hole.

[0194] The first electric field line PL1, the third electric field line PL3, and the fourth electric field line PL4 can be separated from each other in the second direction DR2, and each of the first electric field line PL1, the third electric field line PL3, and the fourth electric field line PL4 can extend substantially in the first direction DR1. That is, the electric field lines (or horizontal electric field lines) extending in the first direction DR1 can be arranged in the fourth conductive layer SD1.

[0195] The first electric field line PL1 can be connected to the second capacitor electrode CE2 and the first semiconductor pattern ACT1 (e.g., the first semiconductor pattern ACT1 on the upper side of the fifth transistor T5) through a contact hole.

[0196] The third power line PL3 can be connected to the second semiconductor pattern ACT2 (e.g., the second semiconductor pattern ACT2 located on the underside of the ninth transistor T9) through a contact hole.

[0197] The fourth power line PL4 can be connected to the fourth semiconductor pattern ACT4 (e.g., the fourth semiconductor pattern ACT4 on the underside of the tenth transistor T10) through a contact hole.

[0198] The first via layer VIA1 can be disposed on the fourth conductive layer SD1. The first via layer VIA1 can be an insulating layer made of inorganic or organic materials. For example, organic materials may include acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin.

[0199] The fifth conductive layer SD2 may be disposed on the first via layer VIA1. The fifth conductive layer SD2 may include a conductive material. The fifth conductive layer SD2 may include the eleventh bridging pattern BRP11 to the fifteenth bridging pattern BRP15, the first power line PL1, and the fourth power line PL4a.

[0200] The eleventh bridging pattern BRP11 can be connected to the fourth bridging pattern BRP4 via a contact hole.

[0201] The twelfth bridging pattern BRP12 can be connected to the sixth bridging pattern BRP6 via a contact hole.

[0202] The thirteenth bridging pattern BRP13 can be connected to the fifth bridging pattern BRP5 via a contact hole.

[0203] The fourteenth bridging pattern BRP14 can be connected to the eighth bridging pattern BRP8 via a contact hole.

[0204] The fifteenth bridging pattern BRP15 can be connected to the ninth bridging pattern BRP9 via a contact hole.

[0205] The first electric field line PL1 can extend in the second direction DR2 and cover the lower components (e.g., the first transistor T1, the fifth transistor T5, etc.). The first electric field line PL1 can be connected to the first electric field line PL1 in the fourth conductive layer SD1 (e.g., a horizontal electric field line) through contact holes. That is, the first electric field line PL1 can be arranged throughout the fourth conductive layer SD1 and the fifth conductive layer SD2 and has a grid structure.

[0206] The 4a power line PL4a (or the fourth power bridge pattern) can be connected to the fourth power line PL4 through the contact hole.

[0207] The second via layer VIA2 can be disposed above the fifth conductive layer SD2. The second via layer VIA2 can be an insulating layer made of inorganic or organic materials.

[0208] The sixth conductive layer SD3 may be disposed on the second via layer VIA2. The sixth conductive layer SD3 may include a conductive material. The sixth conductive layer SD3 may include the twenty-first bridging pattern BRP21, the twenty-second bridging pattern BRP22, the j-th data line Dj, the k-th readout line RXk, the second power line PL2, the 2a power line PL2a, and the 4b power line PL4b.

[0209] The 21st bridging pattern BRP21 can be connected to the 13th bridging pattern BRP13 via a contact hole. The light-emitting element LED can be connected to the 6th transistor T6 via the 21st bridging pattern BRP21, the 13th bridging pattern BRP13, and the 5th bridging pattern BRP5.

[0210] The 22nd bridging pattern BRP22 can be connected to the 15th bridging pattern BRP15 via a contact hole. The optical receiver element LRD can be connected to the 12th transistor T12 via the 22nd bridging pattern BRP22, the 15th bridging pattern BRP15, and the 9th bridging pattern BRP9.

[0211] The j-th data line Dj, the k-th readout line RXk, the second power line PL2, the 2a power line PL2a, and the 4b power line PL4b can be separated from each other in the first direction DR1, and each of the j-th data line Dj, the k-th readout line RXk, the second power line PL2, the 2a power line PL2a, and the 4b power line PL4b can extend substantially in the second direction DR2. That is, the lines (or vertical lines) extending in the second direction DR2 can be arranged in the sixth conductive layer SD3.

[0212] Data line j (Dj) can be connected to the eleventh bridging pattern BRP11 via a contact hole. Data line j (Dj) can be connected to the second transistor T2 via the eleventh bridging pattern BRP11 and the fourth bridging pattern BRP4.

[0213] The k-th read line RXk can be connected to the fourteenth bridge pattern BRP14 via a contact hole. The k-th read line RXk can be connected to the eleventh transistor T11 via the fourteenth bridge pattern BRP14 and the eighth bridge pattern BRP8.

[0214] The second electric field line PL2 and the second electric field line PL2a can be connected to the twelfth bridging pattern BRP12 through contact holes. The second electric field line PL2 and the second electric field line PL2a can also be connected to the second electric field line PL2 of the first conductive layer GAT1 through the twelfth bridging pattern BRP12. That is, the second electric field line PL2 can be distributed throughout the first conductive layer GAT1 and the sixth conductive layer SD3, and has a mesh structure.

[0215] The 4b power line PL4b can be connected to the 4a power line PL4a through a contact hole. The 4b power line PL4b can be connected to the fourth power line PL4 through the 4a power line PL4a. That is, the fourth power line PL4 can be disposed throughout the fourth conductive layer SD1 to the sixth conductive layer SD3 and has a mesh structure.

[0216] The third via layer VIA3 and the fourth via layer VIA4 can be disposed on the sixth conductive layer SD3. Each of the third via layer VIA3 and the fourth via layer VIA4 can be an insulating layer made of inorganic or organic materials.

[0217] The first connecting electrode TCO1 and the second connecting electrode TCO2 can be disposed between the third via layer VIA3 and the fourth via layer VIA4. The first connecting electrode TCO1 can extend from the twenty-first bridging pattern BRP21 to the light-emitting element LED (e.g., the fourth light-emitting element LED4 (see...)). Figure 4 (), to connect the twenty-first bridging pattern BRP21 and the light-emitting element LED to each other. Similarly, the second connecting electrode TCO2 can extend from the twenty-second bridging pattern BRP22 to the light-receiving element LRD (e.g., Figure 4 The second optical receiver element LRD2 shown is used to connect the twenty-second bridging pattern BRP22 and the optical receiver element LRD to each other.

[0218] The pixel layer, including the pixel electrode PEL, the sensor electrode SEL, and the dam layer BK, can be disposed on the fourth via layer VIA4.

[0219] The pixel layer may include light-emitting elements (LEDs) connected to the pixel circuit PXC and light-receiving elements (LRDs) connected to the sensor circuit SC.

[0220] In one embodiment, the light-emitting element (LED) may include a pixel electrode (PEL), a light-emitting layer (EML), and a common electrode (CD). In another embodiment, the light-receiving element (LRD) may include a sensor electrode (SEL), a light-receiving layer (LRL), and a common electrode (CD).

[0221] In embodiments, the pixel electrode PEL and sensor electrode SEL can be made of metal layers such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any alloy thereof and / or indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. The pixel electrode PEL and sensor electrode SEL can be formed simultaneously using patterning with a mask.

[0222] A barrier layer BK (or pixel defining layer) separating the light-emitting region and the light-receiving region can be disposed on a fourth via layer VIA4 on which pixel electrodes PEL and sensor electrodes SEL are formed. The barrier layer BK may include openings corresponding to the light-emitting region and the light-receiving region. The barrier layer BK may be an insulating layer made of organic material.

[0223] In some embodiments, the dam layer BK may include a light-absorbing material or have a light-absorbing agent coated on the dam layer to absorb external light. For example, the dam layer BK may include a carbon-based black pigment. However, the disclosure is not limited thereto, and the dam layer BK may include an opaque metallic material with a high absorptivity, such as chromium (Cr), molybdenum (Mo), any alloy of molybdenum and titanium (MoTi), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), manganese (Mn), cobalt (Co), or nickel (Ni).

[0224] The light-emitting layer (EML) can be disposed on the top surface of the pixel electrode (PEL) exposed by the diaphragm layer (BK), and the light-receiving layer (LRL) can be disposed on the top surface of the sensor electrode (SEL) exposed by the diaphragm layer (BK). In an embodiment, the EML can be implemented as an organic light-emitting layer. Depending on the organic material included in the EML, the EML can emit light such as red, green, or blue light. The LRL can emit electrons corresponding to light in a specific wavelength band, thereby sensing the intensity of the light.

[0225] The common electrode CD can be disposed on the light-emitting layer EML and the light-receiving layer LRL. A second electrical voltage VSS can be supplied to the common electrode CD. The common electrode CD can be made of a metal layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), or chromium (Cr) and / or a transparent conductive layer such as ITO, IZO, ZnO, or ITZO.

[0226] The encapsulation layer TFE can be disposed on the common electrode CD. The encapsulation layer TFE can be a single layer or multiple layers. In an embodiment, the encapsulation layer TFE can have a stacked structure in which inorganic materials, organic materials, and inorganic materials are sequentially deposited. The uppermost layer of the encapsulation layer TFE may include inorganic material.

[0227] As described above, the gate line TGL can be stacked with and connected to the first scan line S1i. Because the second transistor T2, the eleventh transistor T11, and the twelfth transistor T12 share the first scan line S1i, signal lines for individually controlling the eleventh transistor T11 and the twelfth transistor T12 can be omitted. Therefore, the area of ​​the pixel circuit PXC and the sensor circuit SC can be reduced, and the resolution can be improved.

[0228] Figure 14 It is shown Figure 4 A plan view of an embodiment of the display area shown. Figure 15 It is shown Figure 4 A cross-sectional view of an embodiment of the display area shown.

[0229] Reference Figures 11 to 15 Apart from the gate line TGL_C and the bridging pattern BRP_C, Figure 14 and Figure 15 The embodiments shown can be compared with Figures 11 to 13 The embodiments shown are substantially the same or similar. Therefore, for ease of explanation, further descriptions of the previously described components and technical aspects will be omitted.

[0230] The gate pattern A_TGL (or gate electrode) may be included in the third conductive layer GAT3 and disposed on the third gate insulating layer GI3. The gate pattern A_TGL may be stacked with the fourth semiconductor pattern ACT4 and constitute the gate electrode of the twelfth transistor T12_C.

[0231] The bridging pattern BRP_C can be included in the fourth conductive layer SD1 and disposed on the second interlayer insulating layer ILD2. The bridging pattern BRP_C can be connected to the gate pattern A_TGL through a contact hole.

[0232] The gate line TGL_C may be included in the fifth conductive layer SD2 and may be disposed on the first via layer VIA1. The gate line TGL_C may extend substantially in the second direction DR2. In an embodiment, the gate line TGL_C is not stacked with the pixel circuit PXC. The gate line TGL_C may be connected to the gate pattern A_TGL through a contact hole and a bridging pattern BRP_C.

[0233] The gate line TGL_C can be extended in the second direction DR2 to avoid coupling with the components of the pixel circuit PXC, but the area of ​​the sensor circuit SC can be increased in the first direction DR1 to accommodate the gate line TGL_C. Additionally, while the gate line TGL_C is stacked with components of the fourth conductive layer SD1 and the sixth conductive layer SD3 (e.g., the 4th power line PL4b), coupling between the gate line TGL_C and the components may occur, and the load (e.g., capacitance) on the gate line TGL_C (and the components) may increase.

[0234] Therefore, as referenced Figures 11 to 13 As described, the twelfth transistor T12 is controlled by the first scan line S1i, thus reducing the area of ​​the sensor circuit SC. As a result, the resolution can be improved.

[0235] For example, as referenced Figures 11 to 13 As described in the embodiments of this disclosure, the twelfth transistor T12 can be controlled by the first scan line S1i, which enables a more efficient circuit layout. By utilizing the first scan line S1i, the sensor circuit SC can be designed with a reduced area, thereby improving the use of available space within the display device 1000. As a result, more sensing elements can be accommodated in a given area, thereby contributing to increased resolution and an overall improvement in fingerprint sensing accuracy.

[0236] Figure 16 It is shown Figure 4 A plan view of an embodiment of the display area shown.

[0237] Reference Figures 11 to 13 and Figure 16 Apart from gate line TGL_1, Figure 16 The embodiments shown can be compared with Figures 11 to 13 The embodiments shown are substantially the same or similar. Therefore, for ease of explanation, further descriptions of the previously described components and technical aspects will be omitted.

[0238] Gate line TGL_1 may be included in the third conductive layer GAT3 and disposed on the third gate insulating layer GI3. Gate line TGL_1 may be stacked with the fourth semiconductor pattern ACT4 and constitute the gate electrode of the twelfth transistor T12. In an embodiment, gate line TGL_1 is not connected to the first scan line S1i. However, the disclosure is not limited thereto.

[0239] The gate line TGL_1 can extend substantially in the first direction DR1. The gate line TGL_1 can also extend while intersecting with the pixel circuit PXC (or pixel PX).

[0240] In an embodiment, the gate line TGL_1 can be stacked with the first scan line S1i. For example... Figure 16 As shown, gate line TGL_1 may be partially superimposed on the first scan line S1i. A portion of gate line TGL_1 may be completely superimposed on the first scan line S1i. However, the disclosure is not limited thereto. For example, in an embodiment, gate line TGL_1 may be configured to be completely superimposed on the first scan line S1i.

[0241] When gate line TGL_1 is superimposed on a lower component (e.g., scan line S1i), coupling may occur, causing the gate signal TG applied to gate line TGL_1 to affect the lower component. To mitigate this effect, gate line TGL_1 can be configured to avoid superimposing on the lower component. However, this placement may increase the area of ​​the pixel circuit PXC and sensor circuit SC, which could lead to a reduction in resolution.

[0242] However, as referenced Figure 7 As described, according to embodiments of this disclosure, the gate signal TG of gate line TGL_1 and the first scan signal GW[i] of the first scan line S1i have the same waveform and the same phase. As a result, even if gate line TGL_1 and the first scan line S1i are superimposed on each other, no substantial interference occurs between them.

[0243] The display device according to embodiments of this disclosure can be applied to various types of electronic devices. In embodiments, the electronic device includes the above-described display device, and may also include other modules or devices with additional functions in addition to the display device.

[0244] Figure 17 This is a block diagram of an electronic device according to embodiments of the present disclosure. (Refer to...) Figure 17 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0245] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0246] The memory 13 can store data and / or information used to operate the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11. The display module 11 can process the provided signals and output image information on the display screen.

[0247] The power module 14 may include a power module, such as a power adapter or battery device, and a power conversion module. The power conversion module converts the power supplied by the power module and generates power to operate the electronic device 10.

[0248] At least one of the aforementioned components of the electronic device 10 may be included in the display device according to the embodiment described above. Furthermore, in terms of functionality, some modules included in a single module may be included in the display device, while other modules may be separately disposed from the display device. For example, in an embodiment, the display module 11 is included in the display device, while the processor 12, memory 13, and power module 14 are not included in the display device but are disposed separately in the electronic device 10.

[0249] Figure 18 Schematic diagrams illustrating various embodiments of an electronic device according to the present disclosure are shown.

[0250] Reference Figure 18 The various types of electronic devices to which the display device embodiments are applied may include electronic devices that display images (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, and desktop monitors 10_1e, for example), wearable electronic devices that include display modules (such as smart glasses 10_2a, head-mounted displays (HMDs) 10_2b, and smartwatches 10_2c), and automotive electronic devices 10_3 that include display modules (such as central information displays (CIDs) and interior mirror displays located on the dashboard, center instrument panel, and dashboard of a vehicle).

[0251] In the display device and electronic device according to embodiments of the present disclosure, the third and fourth sensor transistors of the sensor (and the second transistor of the pixel) can share a first scan line. Therefore, signals for individually controlling the third and fourth sensor transistors can be omitted, the area of ​​the pixel and sensor can be reduced, and the resolution can be improved.

[0252] For example, in display devices and electronic devices according to embodiments of the present disclosure, the third and fourth sensor transistors of the sensor, together with the second transistor of the pixel, can be designed to share a common first scan line. By integrating these components under a single scan line, the need for separate control signals for individually operating the third and fourth sensor transistors can be eliminated. As a result, circuit design can be simplified, the number of required signal lines can be reduced, and the total area occupied by both pixel circuitry and sensor circuitry can be decreased. This improved layout not only improves space efficiency within the display panel but also contributes to increased resolution by allowing a greater number of sensing and display elements to be accommodated in a given area. As a result, a more compact and higher resolution display device with enhanced sensing capabilities can be provided.

[0253] In the display device and electronic device according to embodiments of the present disclosure, noise of the sensor is sensed after a reset, and the noise can be removed from the sensing signal. As a result, the sensing capability of the sensor can be enhanced.

[0254] Although this disclosure has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the claims.

Claims

1. A display device, the display device comprising: Pixels, including light-emitting elements; as well as sensor, The sensor includes: a light-receiving element; a first sensor transistor; a second sensor transistor connected between a reset power line and the gate electrode of the first sensor transistor, wherein the second sensor transistor includes a gate electrode connected to a reset control line; a third sensor transistor connected between the first sensor transistor and a readout line, wherein the third sensor transistor includes a gate electrode connected to a first scan line; and a fourth sensor transistor connected between the gate electrode of the first sensor transistor and the anode electrode of the light-receiving element, wherein the fourth sensor transistor includes a gate electrode connected to a gate line. The first scan line and the gate line are connected to each other.

2. The display device according to claim 1, wherein, The third sensor transistor is a p-type transistor, and the fourth sensor transistor is an n-type transistor.

3. The display device according to claim 2, wherein, The third sensor transistor comprises a silicon semiconductor, and the fourth sensor transistor comprises an oxide semiconductor.

4. The display device according to claim 2, wherein, The first sensor transistor is a p-type transistor, and the second sensor transistor is an n-type transistor.

5. The display device according to claim 1, wherein, The pixels also include: The first transistor provides drive current to the light-emitting element; and The second transistor is connected between the first electrode of the first transistor and the data line. The gate electrode of the second transistor is connected to the first scan line.

6. The display device according to claim 1, further comprising: drive circuit, The driving circuit wherein: at a first time point, it provides a reset signal with a logic high level to the reset control line; at a second time point, it provides a first scan signal with a logic low level to the first scan line and the gate line; at a third time point, it provides a gate signal to the first scan line and the gate line, wherein the gate signal has a logic high level at the third time point; and at a fourth time point, it provides the gate signal to the first scan line and the gate line, wherein the gate signal has a logic low level at the fourth time point. The first time point to the fourth time point occur sequentially within the sensing cycle.

7. The display device according to claim 6, wherein, The driving circuit reads the first sensing signal through the readout line at the second time point, reads the second sensing signal through the readout line at the fourth time point, and performs a subtraction operation on the first sensing signal and the second sensing signal.

8. The display device according to claim 6, further comprising: Multiple sensors, including the sensor mentioned above, The driving circuit provides the reset signal to the plurality of sensors together, and provides the first scan signal to the plurality of sensors sequentially in units of horizontal lines.

9. The display device according to claim 8, wherein, The exposure time for the corresponding plurality of sensors is constant between the third time point and the fourth time point.

10. The display device according to claim 1, wherein, In the plan view, the semiconductor layers of the second sensor transistor and the fourth sensor transistor extend in the second direction. In the plan view, the first scan line and the gate line extend in a first direction that intersects with the second direction.

11. The display device according to claim 10, wherein, In the plan view, the first scan line includes a protrusion that is stacked with the semiconductor layer of the fourth sensor transistor. In the plan view, the gate line is superimposed on the protrusion of the first scan line.

12. The display device according to claim 10, wherein, In the cross-sectional view, the semiconductor layer of the fourth sensor transistor is disposed between the first scan line and the gate line. In the cross-sectional view, the gate line is in contact with the first scan line through a contact hole.

13. A display device, the display device comprising: Pixels, including light-emitting elements; as well as sensor, The sensor includes: a light-receiving element; a first sensor transistor; a second sensor transistor connected between a reset power line and the gate electrode of the first sensor transistor, wherein the second sensor transistor includes a gate electrode connected to a reset control line; a third sensor transistor connected between the first sensor transistor and a readout line, wherein the third sensor transistor includes a gate electrode connected to a first scan line; and a fourth sensor transistor connected between the gate electrode of the first sensor transistor and the anode electrode of the light-receiving element, wherein the fourth sensor transistor includes a gate electrode connected to a gate line. The first scan signal provided to the first scan line and the gate signal provided to the gate line have the same waveform.

14. The display device according to claim 13, wherein, The third sensor transistor is a p-type transistor, and the fourth sensor transistor is an n-type transistor.

15. The display device according to claim 14, wherein, The third sensor transistor comprises a silicon semiconductor, and the fourth sensor transistor comprises an oxide semiconductor.

16. The display device according to claim 13, wherein, The pixels also include: The first transistor provides drive current to the light-emitting element; and The second transistor is connected between the first electrode of the first transistor and the data line, and The gate electrode of the second transistor is connected to the first scan line.

17. The display device according to claim 13, further comprising: drive circuit, The driving circuit comprises: providing a reset signal with a logic high level to the reset control line at a first time point; providing a first scan signal to the first scan line and the gate line at a second time point, wherein the first scan signal has a logic low level at the second time point; providing a gate signal to the first scan line and the gate line at a third time point, wherein the gate signal has a logic high level at the third time point; and providing the gate signal to the first scan line and the gate line at a fourth time point, wherein the gate signal has a logic low level at the fourth time point. The first time point to the fourth time point occur sequentially within the sensing cycle.

18. The display device according to claim 13, wherein, In the plan view, the semiconductor layers of the second sensor transistor and the fourth sensor transistor extend in the second direction. In the planar view, the first scan line and the gate line extend while intersecting the pixel along a first direction that intersects with the second direction.

19. The display device according to claim 18, wherein, In the plan view, the gate line is superimposed on the first scan line.

20. An electronic device, the electronic device comprising: The display device is configured to display an image based on input image data; as well as The processor is configured to provide the input image data to the display device. The display device includes: pixels, including light-emitting elements; and sensors. The sensor includes: a light-receiving element; a first sensor transistor; a second sensor transistor connected between a reset power line and the gate electrode of the first sensor transistor, wherein the second sensor transistor includes a gate electrode connected to a reset control line; a third sensor transistor connected between the first sensor transistor and a readout line, wherein the third sensor transistor includes a gate electrode connected to a first scan line; and a fourth sensor transistor connected between the gate electrode of the first sensor transistor and the anode electrode of the light-receiving element, wherein the fourth sensor transistor includes a gate electrode connected to a gate line. The first scan line and the gate line are connected to each other.

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