Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a substrate and a plurality of sub-pixels located on the substrate. The sub-pixel comprises a semiconductor layer which comprises a first active layer of an initialization transistor and a third active layer of a data writing transistor; a first conductive layer including: a data signal line extending in a first direction; a second conductive layer including: a driving gate driving the transistor; a shielding structure; the conductive connection structure is electrically connected with the shielding structure; the driving grid is electrically connected with the first conductive region of the first active layer; the data signal line is electrically connected with the first conductive area of the third active layer; the orthographic projection of the shielding structure on the substrate is located between the orthographic projection of the first conductive area of the first active layer on the substrate and the orthographic projection of the first conductive area of the third active layer on the substrate.

Description

[0001] This patent application document was filed on [date]. August 31, 2020 The application number is 202080001755.7, and the invention title is " Display panel and display device The divisional application of the invention patent application document of 》 The entire contents of the original application are cited in the conclusion This is incorporated in this application. Technical Field

[0002] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] Organic light-emitting diode (OLED) display panels have advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and high response speed, and are increasingly being used in various electronic devices.

[0004] With the continuous development of display technology, people's requirements for display effects are also getting higher and higher. In recent years, high refresh rate display products have received more and more attention. However, for high refresh rate display panels, the transition of data signals will affect the gate of the driving transistor, thus affecting the display effect. Summary of the Invention

[0005] The display panel provided in this disclosure includes: a substrate and a plurality of sub-pixels located on the substrate; The sub-pixel includes: A semiconductor layer is located on the substrate; the semiconductor layer includes: a first active layer for initializing transistors and a third active layer for writing data transistors; A first conductive layer is located on the semiconductor layer away from the substrate; the first conductive layer includes: a data signal line extending along a first direction; A second conductive layer is located on the substrate; the second conductive layer includes: a driving gate of a driving transistor; A shielding structure is located on the substrate. A conductive connection structure is located on the substrate and is electrically connected to the shielding structure. The driving gate is electrically connected to the first conductive region of the first active layer. The data signal line is electrically connected to the first conductive region of the third active layer. The orthographic projection of the shielding structure on the substrate is located between the orthographic projection of the first conductive region of the first active layer on the substrate and the orthographic projection of the first conductive region of the third active layer on the substrate. The orthographic projection of the conductive connection structure on the substrate at least partially overlaps with the orthographic projection of the first conductive region of the first active layer on the substrate.

[0006] Optionally, in this embodiment of the present disclosure, the first conductive layer further includes: a data signal adapter electrically connected to the data signal line; The orthographic projection of the data signal adapter on the substrate at least partially overlaps with the orthographic projection of the conductive connection structure on the substrate.

[0007] Optionally, in this embodiment of the disclosure, the plurality of sub-pixels are arranged in an array in the first direction and the second direction, wherein the second direction is a direction that intersects with the first direction; The display panel includes multiple data signal lines, and the multiple data signal lines include a first data signal line and a second data signal line; The plurality of sub-pixels includes a first sub-pixel and a third sub-pixel, wherein the first sub-pixel and the third sub-pixel are located in adjacent rows of the same column; One of the first sub-pixel and the third sub-pixel is electrically connected to the first data signal line, and the other is electrically connected to the second data signal line; The first data signal line and the second data signal line are located on opposite sides of the column containing the first sub-pixel and the third sub-pixel.

[0008] Optionally, in this embodiment of the disclosure, the data signal switching unit includes a first data signal switching unit and a second data signal switching unit; One of the first sub-pixel and the third sub-pixel is electrically connected to the first data signal line through the first data signal adapter, and the other is electrically connected to the second data signal line through the second data signal adapter.

[0009] Optionally, in this embodiment of the disclosure, the size of the first data signal adapter is different from the size of the second data signal adapter in the second direction.

[0010] Optionally, in embodiments of this disclosure, the semiconductor layer further includes a second active layer with a reset transistor, and the sub-pixel further includes: A third conductive layer is located on the substrate; the third conductive layer includes: an initialization signal line extending along a second direction, the second direction being a direction intersecting the first direction; the initialization signal line is electrically connected to a first conductive region of the second active layer; The first conductive region of the second active layer is located at one end of the second active layer away from the first active layer.

[0011] Optionally, in embodiments of this disclosure, the following are also included: A fourth conductive layer is located on the side of the semiconductor layer that is away from the substrate. The fourth conductive layer includes: a fixed potential signal line extending along the first direction; The shielding structure is electrically connected to the fixed potential signal line.

[0012] Optionally, in an embodiment of this disclosure, the conductive connection structure is located in the third conductive layer; The fixed potential signal line is electrically connected to the shielding structure through the conductive connection structure.

[0013] Optionally, in this embodiment of the disclosure, the shielding structure and the conductive connection structure are an integral structure.

[0014] Optionally, in this embodiment of the present disclosure, the fourth conductive layer further includes: a first conductive connection portion, a second conductive connection portion, and a third conductive connection portion that are mutually insulated; The driving gate is electrically connected to the first conductive region of the first active layer through the first conductive connection portion. The data signal line is electrically connected to the first conductive region of the third active layer through the second conductive connection portion. The initialization signal line is electrically connected to the first conductive region of the second active layer through the third conductive connection portion.

[0015] Optionally, in an embodiment of this disclosure, the data signal adapter is electrically connected to the second conductive connection via a first via.

[0016] Optionally, in this embodiment of the disclosure, the display panel includes sub-pixels of multiple colors, and the sub-pixels further include: A fifth conductive layer is located on the side of the first conductive layer away from the substrate. The fifth conductive layer includes a plurality of anodes, and the orthographic projection of the anode of at least one color sub-pixel on the substrate does not overlap with the orthographic projection of the first via on the substrate.

[0017] Optionally, in this embodiment of the disclosure, the display panel includes sub-pixels of multiple colors, and the sub-pixels further include: The fifth conductive layer is located on the side of the first conductive layer away from the substrate. The fifth conductive layer includes a plurality of anodes. The orthographic projection of the anode of at least one color sub-pixel on the substrate overlaps with the orthographic projection of the data signal transfer portion on the substrate, but does not overlap with the orthographic projection of the second conductive connection portion on the substrate.

[0018] Optionally, in this embodiment of the disclosure, the sub-pixel includes a pixel driving circuit and a light-emitting device, the pixel driving circuit including: A drive control circuit is electrically connected between a first voltage terminal and the anode of the light-emitting device, and is configured to drive the light-emitting device to emit light. The first voltage terminal is electrically connected to the fixed potential signal line.

[0019] Optionally, in this embodiment of the disclosure, the sub-pixel further includes: a storage capacitor located in the second conductive layer; The first terminal of the storage capacitor is electrically connected to the fixed potential signal line, and the second terminal of the storage capacitor is electrically connected to the driving gate. The orthographic projection of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of the fixed potential signal line on the substrate.

[0020] Optionally, in this embodiment of the disclosure, the shielding structure is disposed on the same layer as the initialization signal line.

[0021] Optionally, in this embodiment of the disclosure, the semiconductor layer further includes a channel region of the first active layer and a channel region of the second active layer, and the sub-pixel further includes: The orthographic projection of the channel region of the second active layer on the substrate is located between the orthographic projection of the channel region of the first active layer on the substrate and the orthographic projection of the third conductive connection portion on the substrate.

[0022] Accordingly, this disclosure also provides a display device, including the aforementioned display panel. Attached Figure Description

[0023] Figure 1 A top view of the display panel provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the structure of a pixel driving circuit in an embodiment of this disclosure; Figure 3 for Figure 2 The signal timing diagram corresponding to the pixel driving circuit shown; Figure 4 This is a schematic diagram of the layout structure of multiple sub-pixels in a display panel provided in an embodiment of this disclosure; Figure 5 for Figure 4 A schematic diagram of the cross-section at the dashed line A1-A2; Figure 6 A schematic diagram of the layout structure of a sub-pixel in a display panel provided in an embodiment of this disclosure; Figures 7 to 9 This is a top view of the structure of multiple film layers in a display panel provided in an embodiment of the present disclosure; Figure 10 A top view of the semiconductor layer corresponding to multiple sub-pixels; Figure 11 for Figure 10 A magnified schematic diagram of the semiconductor layer corresponding to a sub-pixel; Figure 12 A top view of the first conductive layer corresponding to multiple sub-pixels; Figure 13 for Figure 12 An enlarged schematic diagram of the first conductive layer corresponding to a sub-pixel; Figure 14 A top view of the second conductive layer corresponding to multiple sub-pixels; Figure 15 for Figure 14 A magnified schematic diagram of the second conductive layer corresponding to a sub-pixel; Figure 16 A top view of the third conductive layer corresponding to multiple sub-pixels; Figure 17 for Figure 16 A magnified schematic diagram of the third conductive layer corresponding to a sub-pixel; Figure 18 A top view of the fourth conductive layer corresponding to multiple sub-pixels; Figure 19 for Figure 18 A magnified schematic diagram of the fourth conductive layer corresponding to a sub-pixel; Figure 20 This is a top view of the fifth conductive layer corresponding to multiple sub-pixels. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0025] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0026] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0027] Figure 1 This is a top view of the display panel provided in an embodiment of the present disclosure, as shown in the figure. Figure 1 As shown, the display panel provided in this embodiment may include: a substrate 10, and a plurality of sub-pixels spx located on the substrate 10, wherein the plurality of sub-pixels spx are arranged in an array in a first direction F1 and a second direction F2.

[0028] For example, Figure 2 This is a schematic diagram of the structure of a pixel driving circuit in an embodiment of this disclosure, combined with... Figure 1 and Figure 2 As shown, at least one of the multiple sub-pixels spx may include: a pixel driving circuit 121 and a light-emitting device 120. The pixel driving circuit 121 has a transistor and a capacitor, and generates an electrical signal through the interaction of the transistor and the capacitor. The generated electrical signal is input to the anode of the light-emitting device 120, and a corresponding voltage is applied to the cathode of the light-emitting device 120, which can drive the light-emitting device 120 to emit light.

[0029] Combination Figure 2 As shown, the pixel driving circuit 121 may include: a driving control circuit 122, a first light emission control circuit 123, a second light emission control circuit 124, a data writing circuit 125, a storage circuit 126, a threshold compensation circuit 127, and a reset circuit 128.

[0030] The drive control circuit 122 may include a control terminal, a first terminal, and a second terminal. The drive control circuit 122 is configured to provide a drive current to the light-emitting device 120 to drive the light-emitting device 120 to emit light. For example, a first light-emitting control circuit 123 is connected to the first terminal and the first voltage terminal VDD of the drive control circuit 122, and the first light-emitting control circuit 123 is configured to enable or disable the connection between the drive control circuit 122 and the first voltage terminal VDD.

[0031] The second light-emitting control circuit 124 is electrically connected to the second terminal of the drive control circuit 122 and the anode of the light-emitting device 120, and the second light-emitting control circuit 124 is configured to enable or disable the connection between the drive control circuit 122 and the light-emitting device 120.

[0032] The data writing circuit 125 is electrically connected to the first terminal of the drive control circuit 122. The second light-emitting control circuit 124 is configured to write the signal on the data signal line VD into the storage circuit 126.

[0033] The storage circuit 126 is electrically connected to the control terminal and the first voltage terminal VDD of the drive control circuit 122. The storage circuit 126 is configured to store data signals.

[0034] The threshold compensation circuit 127 is electrically connected to the control terminal and the second terminal of the drive control circuit 122, respectively. The threshold compensation circuit 127 is configured to perform threshold compensation on the drive control circuit 122.

[0035] The reset circuit 128 is electrically connected to the control terminal of the drive control circuit 122 and the anode of the light-emitting device 120. The reset circuit 128 is configured to reset the anode of the light-emitting device 120 and the control terminal of the drive control circuit 122.

[0036] The light-emitting device 120 can be configured as an electroluminescent diode, such as at least one of OLED and QLED. The light-emitting device 120 may include an anode, a light-emitting functional layer, and a cathode stacked together. Further, the light-emitting functional layer may include film layers such as a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. Of course, in practical applications, the design of the light-emitting device 120 can be determined according to the requirements of the actual application environment, and is not limited here.

[0037] For example, combined Figure 2 As shown, the drive control circuit 122 may include: a drive transistor T4, the control terminal of the drive control circuit 122 includes the drive gate of the drive transistor T4, the first terminal of the drive control circuit 122 includes the first electrode of the drive transistor T4, and the second terminal of the drive control circuit 122 includes the second electrode of the drive transistor T4.

[0038] For example, combined Figure 2 As shown, the data writing circuit 125 may include a data writing transistor T3. The storage circuit 126 may include a storage capacitor CST. The threshold compensation circuit 127 includes a threshold compensation transistor T7. The first light-emitting control circuit 123 may include a first light-emitting control transistor T5. The second light-emitting control circuit 124 may include a second light-emitting control transistor T6. The reset circuit 128 may include an initialization transistor T1 and a reset transistor T2.

[0039] Specifically, the first terminal of the data writing transistor T3 is electrically connected to the first terminal of the driving transistor T4, the second terminal of the data writing transistor T3 is configured to be electrically connected to the data signal line VD to receive the data signal, and the gate of the data writing transistor T3 is configured to be electrically connected to the scan line GA to receive the signal.

[0040] The first terminal of the storage capacitor CST is electrically connected to the first power supply terminal VDD, and the second terminal of the storage capacitor CST is electrically connected to the driving gate of the driving transistor T4.

[0041] The first terminal of the threshold compensation transistor T7 is electrically connected to the second terminal of the driving transistor T4, and the second terminal of the threshold compensation transistor T7 is electrically connected to the gate of the driving transistor T4. The gate of the threshold compensation transistor T7 is configured to be electrically connected to the scan line GA to receive the signal.

[0042] The first terminal of the initialization transistor T1 is configured to be electrically connected to the initialization signal line VINIT to receive a reset signal. The second terminal of the initialization transistor T1 is electrically connected to the drive gate of the drive transistor T4. The gate of the initialization transistor T1 is configured to be electrically connected to the reset line RST to receive a signal.

[0043] The first terminal of the reset transistor T2 is configured to be electrically connected to the initialization signal line VINIT to receive a reset signal, the second terminal of the reset transistor T2 is electrically connected to the anode of the light-emitting device 120, and the gate of the reset transistor T2 is configured to be electrically connected to the reset line RST to receive a signal.

[0044] The first terminal of the first light-emitting control transistor T5 is electrically connected to the first power supply terminal VDD, the second terminal of the first light-emitting control transistor T5 is electrically connected to the first terminal of the driving transistor T4, and the gate of the first light-emitting control transistor T5 is configured to be electrically connected to the light-emitting control line EM to receive the light-emitting control signal.

[0045] The first terminal of the second light-emitting control transistor T6 is electrically connected to the second terminal of the driving transistor T4, the second terminal of the second light-emitting control transistor T6 is electrically connected to the anode of the light-emitting device 120, and the gate of the second light-emitting control transistor T6 is configured to be electrically connected to the light-emitting control line EM to receive the light-emitting control signal.

[0046] The cathode of the light-emitting device 120 is electrically connected to the second power supply terminal VSS. The first and second terminals of the aforementioned transistor can be determined as source or drain depending on the actual application, and are not limited here.

[0047] For example, one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal. For example, as... Figure 2 In the illustrated embodiment, the first power supply terminal VDD is a voltage source that outputs a constant first voltage, which is a positive voltage; while the second power supply terminal VSS can be a voltage source that outputs a constant second voltage, which is a negative voltage, etc. For example, in some examples, the second power supply terminal VSS can be grounded.

[0048] Figure 3 for Figure 2 The signal timing diagram corresponding to the pixel driving circuit shown is as follows: Figure 3 As shown, the pixel driving circuit operates in three stages during one frame of display time: T10, T20, and T30. Here, rst represents the signal transmitted on the reset line RST, ga represents the signal transmitted on the scan line GA, and em represents the signal transmitted on the light emission control line EM.

[0049] In stage T10, the signal rst controls the initialization transistor T1 to turn on, thereby providing the signal transmitted on the initialization signal line VINIT to the gate of the driving transistor T4 to reset the driving gate of the driving transistor T4. The signal rst also controls the reset transistor T2 to turn on, providing the signal transmitted on the initialization signal line VINIT to the anode of the light-emitting device 120 to reset the anode of the light-emitting device 120. Furthermore, in this stage, the signal ga controls both the data writing transistor T3 and the threshold compensation transistor T7 to turn off. The signal em controls both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to turn off.

[0050] In stage T20, signal ga controls the data writing transistor T3 and threshold compensation transistor T7 to turn on. The turned-on data writing transistor T3 charges the driving gate of driving transistor T4 with the data signal transmitted on the data signal line VD, causing the voltage of the driving gate of driving transistor T4 to become: Vdata + |Vth|, where Vth represents the threshold voltage of driving transistor T4 and Vdata represents the voltage of the data signal. Furthermore, in this stage, signal rst controls the initialization transistor T1 and reset transistor T2 to turn off. Signal em controls the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to turn off.

[0051] In stage T30, signal em controls both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to turn on. The turned-on first light-emitting control transistor T5 provides the voltage Vdd from the first power supply terminal VDD to the first terminal of the driving transistor T4, making the voltage at the first terminal of the driving transistor T4 Vdd. The driving transistor T4 generates a driving current based on its driving gate voltage Vdata+|Vth| and the voltage at its first terminal Vdd. This driving current is supplied to the light-emitting device 120 through the turned-on second light-emitting control transistor T6, driving the light-emitting device 120 to emit light. Furthermore, in this stage, signal rst controls the initialization transistor T1 and the reset transistor T2 to turn off. Signal ga controls the data writing transistor T3 and the threshold compensation transistor T7 to turn off.

[0052] It should be noted that, in the embodiments disclosed herein, except for Figure 2 In addition to the pixel driving circuit shown, the sub-pixels in this embodiment may also include pixel driving circuits with other structures, that is, they may also include structures with other numbers of transistors. This embodiment does not limit this.

[0053] In the display panel provided in the embodiments of this disclosure, such as Figure 1 As shown, the display panel may include: a substrate 10, and a plurality of sub-pixels spx located on the substrate 10. Figure 1 The diagram illustrates a layout using a limited number of sub-pixels (spx), without specifying the number or layout of the sub-pixels (spx).

[0054] Figure 4 This is a schematic diagram of the layout structure of multiple sub-pixels in a display panel provided in an embodiment of this disclosure. Figure 5 for Figure 4 A cross-sectional diagram at the point between the dashed lines A1 and A2. Figure 6 This is a schematic diagram of the layout structure of a sub-pixel in a display panel provided in an embodiment of this disclosure. The diagram is intended to more clearly illustrate the structure of each film layer. Figures 7 to 9 It shows Figure 6 A top view of the middle membrane layer, as shown in the diagram. Figures 4 to 9 As shown in this embodiment of the disclosure, the aforementioned sub-pixel may include: Semiconductor layer 20 is located on the substrate; Figure 10 This is a top view of the semiconductor layer 20 corresponding to multiple sub-pixels. Figure 11 for Figure 10 An enlarged schematic diagram of the semiconductor layer 20 corresponding to a sub-pixel, combined with... Figure 10 and Figure 11 As shown, the semiconductor layer 20 includes: a first active layer 201 for initializing transistors, a second active layer 202 for resetting transistors, and a third active layer 203 for data writing transistors. Specifically, the semiconductor layer 20 can be formed by patterning a semiconductor material, and each active layer in the semiconductor layer 20 can include a first conductive region, a second conductive region, and a channel region. The channel region can be located between the first conductive region and the second conductive region. The first and second conductive regions can be obtained by conductiveizing the semiconductor layer 20. For example, the first and second conductive regions can be obtained by doping the semiconductor layer 20 with n-type and p-type impurities. Optionally, the first conductive region serves as the source of the transistor, and the second conductive region serves as the drain of the transistor; or, the first conductive region serves as the drain of the transistor, and the second conductive region serves as the source of the transistor. No limitation is made here.

[0055] The first conductive layer 21 is located on the side of the semiconductor layer 20 that is away from the substrate. Figure 12 This is a top view of the first conductive layer 21 corresponding to multiple sub-pixels. Figure 13 for Figure 12 An enlarged schematic diagram of the first conductive layer 21 corresponding to a sub-pixel, combined with... Figure 12 and Figure 13 As shown, the first conductive layer 21 includes a data signal line VD extending along a first direction F; The second conductive layer 22 is located on the substrate. Figure 14 This is a top view of the second conductive layer 22 corresponding to multiple sub-pixels. Figure 15 for Figure 14 An enlarged schematic diagram of the second conductive layer corresponding to a sub-pixel, combined with... Figure 14 and Figure 15 As shown, the second conductive layer 22 includes: a driving gate G1 for a driving transistor; The driving gate G1 is electrically connected to the first conductive region 201a of the first active layer 201; The data signal line VD is electrically connected to the first conductive region 203a of the third active layer 203. The orthographic projection of the second active layer 202 on the substrate is located between the orthographic projection of the first active layer 201 on the substrate and the orthographic projection of the data signal line VD on the substrate.

[0056] In practical applications, due to the high refresh rate of the display panel, the potential in the data signal line fluctuates during the light emission process, which may cause disturbances caused by electric field coupling. This can lead to changes in the potential of the driving gate of the driving transistor, thereby affecting the display effect. In this embodiment, by setting the first active layer 201 on the side of the second active layer 202 away from the data signal line VD, the distance between the first active layer 201 connected to the driving gate G1 and the third active layer 203 connected to the data signal line VD is increased, thereby mitigating the influence of the data signal line VD on the driving gate G1 of the driving transistor and improving the display effect of the display panel.

[0057] Specifically, in the display panel provided in the embodiments of this disclosure, combined with Figure 6 , Figure 11 and Figure 13 The orthographic projection of the channel region 202c of the second active layer 202 onto the substrate is located between the orthographic projection of the channel region 201c of the first active layer 201 onto the substrate and the orthographic projection of the data signal line VD onto the substrate. This further ensures that the distance between the first active layer 201 connected to the driving gate G1 and the third active layer 203 connected to the data signal line VD is relatively large, further reducing the influence of the data signal line VD on the driving gate G1 of the driving transistor and ensuring that the display panel has a better display effect.

[0058] Furthermore, in the display panel provided in the embodiments of this disclosure, such as Figures 7 to 9 As shown, it may also include: The third conductive layer 23 is located on the substrate. Figure 16 This is a top view of the third conductive layer 23 corresponding to multiple sub-pixels. Figure 17 for Figure 16 An enlarged schematic diagram of the third conductive layer 23 corresponding to a sub-pixel, combined with... Figure 16 and Figure 17 As shown, the third conductive layer 23 includes: an initialization signal line VINIT extending along the second direction F2; the second direction F2 is a direction that intersects with the first direction F1; The initialization signal line VINIT is electrically connected to the first conductive region 202a of the second active layer 202; The first conductive region 202a of the second active layer 202 is located at one end of the second active layer 202 away from the first active layer 201.

[0059] By placing the first conductive region 202a, which is connected to the initialization signal line VINIT, at one end of the second active layer 202 away from the first active layer 201, more space can be left for the first active layer 201. This results in a greater distance between the pattern of the first active layer 201 and the first conductive region 203a of the third active layer 203, preventing the signal of the data signal line VD from passing through the third active layer 203 and the second active layer 202 and affecting the potential of the driving gate of the driving transistor, thus ensuring that the display panel has a better display effect.

[0060] Furthermore, in the display panel provided in the embodiments of this disclosure, reference is made to... Figure 7 It may also include: a shielding structure 231 located on the substrate; The orthographic projection of the shielding structure 231 on the substrate is located between the orthographic projection of the first conductive region 201a of the first active layer 201 on the substrate and the orthographic projection of the first conductive region 203a of the three active layers 203 on the substrate.

[0061] By setting a shielding structure 231 between the first conductive region 201a of the first active layer 201 and the first conductive region 203a of the third active layer 203, signal interference between the third active layer 203 and the first active layer 201 can be shielded, further preventing disturbances to the data signal line VD. Through the third active layer 203 and the first active layer 201, the potential of the driving gate G1 of the driving transistor is affected, ensuring that the display panel has a better display effect.

[0062] In a specific implementation, the display panel provided in the embodiments of this disclosure may further include: a fourth conductive layer 24 located on the side of the semiconductor layer 20 away from the substrate. Figure 18 This is a top view of the fourth conductive layer 24 corresponding to multiple sub-pixels. Figure 19 for Figure 18 An enlarged schematic diagram of the fourth conductive layer 24 corresponding to a sub-pixel, combined with... Figure 18 and Figure 19 As shown, the fourth conductive layer 24 includes a fixed potential signal line VDD extending along the first direction F1; The shielding structure 231 is electrically connected to the fixed potential signal line VDD.

[0063] During the light emission process, a stable power supply signal is provided in the fixed potential signal line VDD. For example, a high-level power supply signal or a low-level power supply signal can be applied to the fixed potential signal line VDD. The magnitude of the power supply signal applied to the fixed potential signal line VDD is not limited here. The shielding structure 231 is electrically connected to the fixed potential signal line VDD. During the light emission process, the shielding structure 231 has a stable power supply signal, thereby achieving a better shielding effect and further reducing signal interference between the third active layer 203 and the first active layer 201. This prevents signal fluctuations in the data signal line VD from affecting the driving gate G1 of the driving transistor.

[0064] In specific implementation, the display panel provided in the embodiments of this disclosure refers to... Figure 16 and Figure 17 The shielding structure 231 and the initialization signal line VINIT are set on the same layer. In this way, during the manufacturing process, the shielding structure 231 and the initialization signal line VINIT can be fabricated using the same patterning process. Specifically, when the third conductive layer 23 is patterned, the patterns of the shielding structure 231 and the initialization signal line VINIT can be obtained simultaneously, thereby reducing one manufacturing step and saving manufacturing costs.

[0065] Specifically, in the display panel provided in the embodiments of this disclosure, reference is made to... Figure 17 The third conductive layer 23 may further include: a conductive connection structure 232 connected to the shielding structure 231; The fixed potential signal line VDD is electrically connected to the shielding structure 231 through the conductive connection structure 232.

[0066] For example, such as Figure 17 As shown, the shielding structure 231 and the conductive connection structure 232 are an integral structure.

[0067] Simultaneously refer to Figure 8 The orthographic projection of the fixed potential signal line VDD on the substrate is at a certain distance from the orthographic projection of the shielding structure 231 on the substrate. By setting a conductive connection structure 232 in the third conductive layer 23, an electrical connection between the fixed potential signal line VDD and the shielding structure 231 can be realized. Specifically, there is an insulating layer between the third conductive layer 23 and the fourth conductive layer 24. The conductive connection structure 232 can be connected to the fixed potential signal line VDD through a via in the insulating layer. Furthermore, the conductive connection structure 232 is connected to the shielding structure 231 in the same layer. During the manufacturing process, the conductive connection structure 232 and the shielding structure 231 can be fabricated as a single pattern, thereby avoiding the need to set up a separate connection structure, which simplifies the manufacturing process.

[0068] For example, such as Figure 4 , Figure 6 , Figure 12 , Figure 17 As shown, the first conductive layer 21 may further include: The data signal adapter DZ is electrically connected to the data signal line VD. The orthographic projection of the data signal converter DZ on the substrate 10 at least partially overlaps with the orthographic projection of the conductive connection structure 232 on the substrate 10.

[0069] In specific implementation, such as Figure 5 As shown, a first conductive layer 21 can be disposed on the side of the semiconductor layer 20 facing away from the substrate 10. A second conductive layer 22 can be disposed between the first conductive layer 21 and the semiconductor layer 20. A third conductive layer 23 can be disposed between the first conductive layer 21 and the second conductive layer 22. A fourth conductive layer 24 can be disposed between the first conductive layer 21 and the third conductive layer 23. In addition, a fifth conductive layer 25 is also provided on the side of the first conductive layer 21 facing away from the substrate 10. The fifth conductive layer 25 includes a plurality of anodes 251. To prevent short circuits between conductive components of adjacent conductive layers, a first gate insulating layer GI1 can be disposed between the semiconductor layer 20 and the second conductive layer 22. A second gate insulating layer GI2 can be disposed between the second conductive layer 22 and the third conductive layer 23. An interlayer insulating layer ILD can be disposed between the third conductive layer 23 and the fourth conductive layer 24. A first planarization layer PLN1 can be disposed between the first conductive layer 21 and the fourth conductive layer 24. A second planarization layer PLN2 can be disposed between the first conductive layer 21 and the fifth conductive layer 25.

[0070] In practical applications, the display panel provided in the embodiments of this disclosure refers to... Figure 19 The fourth conductive layer 24 may further include: a first conductive connection portion LB1, a second conductive connection portion LB2 and a third conductive connection portion LB3 that are mutually insulated; Simultaneously refer to Figure 5 The driving gate G1 is electrically connected to the first conductive region 201a of the first active layer 201 through the first conductive connection portion LB1. Specifically, one end of the first conductive connection portion LB1 (i.e., Figure 19 The uppermost end of the first active layer 201 is connected to the first conductive region 201a of the first active layer 201 through at least one via penetrating the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1. The other end (i.e. Figure 19 The lower end of the gate is connected to the driving gate G1 through at least one via that penetrates the interlayer insulating layer ILD and the second gate insulating layer GI2.

[0071] The data signal line VD is electrically connected to the first conductive region 203a of the third active layer 203 via the second conductive connection portion LB2. Specifically, one end of the second conductive connection portion LB2 (i.e. Figure 19 The uppermost end of the third active layer 203 is connected to the first conductive region 203a of the third active layer 203 through at least one via penetrating the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1. The other end (i.e. Figure 19 The lower end of the line is connected to the data signal line VD through at least one via penetrating the first planarization layer PLN1.

[0072] The initialization signal line VINIT is electrically connected to the first conductive region 202a of the second active layer 202 via the third conductive connection portion LB3. Specifically, the third conductive connection portion LB3 (i.e. Figure 19 The uppermost end is connected to the initialization signal line VINIT through at least one via penetrating the interlayer insulating layer (ILD), and the other end (i.e. Figure 19 The lower end of the second active layer 202 is connected to the first conductive region 202a of the second active layer 202 through at least one via that penetrates the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0073] For example, such as Figure 4 , Figure 11 , Figure 19 As shown, the semiconductor layer 20 further includes a channel region of the first active layer 201 and a channel region of the second active layer 202, and the sub-pixel may further include: The orthographic projection of the channel region of the second active layer 202 onto the substrate 10 is located between the orthographic projection of the channel region of the first active layer 201 onto the substrate 10 and the orthographic projection of the third conductive connection portion LB3 onto the substrate 10.

[0074] For example, such as Figure 4 As shown, the data signal converter DZ is electrically connected to the second conductive connection LB2 through the first via K1.

[0075] In practical implementation, the display panel can include sub-pixels (spx) of multiple colors. For example, it can include sub-pixels of three colors: red, green, and blue. Alternatively, it can include sub-pixels of four colors, or even more colors; there is no limitation here. Multiple sub-pixels (spx) in the display panel can be arranged as follows: Figure 1 The neat arrangement shown can also be set to have adjacent sub-pixel rows staggered by a certain distance; the arrangement of sub-pixels is not limited here.

[0076] For example, such as Figure 4As shown, the orthographic projection of the anode 251 of at least one color sub-pixel on the substrate 10 does not overlap with the orthographic projection of the first via K1 on the substrate 10.

[0077] For example, such as Figure 4 As shown, the orthographic projection of the anode 251 of at least one color sub-pixel on the substrate 10 overlaps with the orthographic projection of the data signal transfer section DZ on the substrate 10, but does not overlap with the orthographic projection of the second conductive connection section LB2 on the substrate 10.

[0078] Furthermore, the fourth conductive layer 24 may also include: a fourth conductive connection portion LB4, one end of the fourth conductive connection portion LB4 (e.g., Figure 19 One end (rightmost) is connected to the first conductive region 206a of the sixth active layer 206 of the second light-emitting control transistor through at least one via penetrating the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1; the other end (as shown in the image) is connected to the first conductive region 206a of the sixth active layer 206 of the second light-emitting control transistor. Figure 19 The left end of the light-emitting transistor is connected to the anode transition portion YZ located in the first conductive layer 21 through at least one via penetrating the first planarization layer PLN1. The anode transition portion YZ is connected to the anode 251 through at least one via penetrating the second planarization layer PLN2, thereby realizing the electrical connection between the second light-emitting control transistor and the anode of the light-emitting device 120.

[0079] Specifically, in the display panel provided in the embodiments of this disclosure, such as Figure 11 As shown, the first active layer 201 includes: a first bending portion LZ1 and a second bending portion LZ2; One end of the first bending portion LZ1 is the first conductive region 201a of the first active layer 201, and the other end is connected to the second bending portion LZ2 and bends toward the side away from the data signal line VD. The second bend LZ2 is "n" shaped. One end of the second bend LZ2 is connected to the first bend LZ1, and the other end is connected to the second active layer 202.

[0080] Simultaneously refer to Figure 14 and Figure 15 The second conductive layer 22 may further include a reset line RST, wherein the gate of the initialization transistor is the portion where the reset line RST overlaps with the first active layer 201, in combination with... Figure 7As can be seen, the first active layer 201 has two parts that overlap with the reset line RST. Therefore, the initialization transistor is a dual-gate structure. Setting the second bending portion LZ2 into an "n" shape makes it easier to form a dual-gate structure with the reset line RST. Furthermore, setting the first bending portion LZ1 such that one end is the first conductive region 201a of the first active layer 201 and the other end bends towards the side away from the data signal line VD allows for more space for the second bending portion LZ2, so that the distance between the first bending portion LZ1 and the second bending portion LZ2 and the first conductive region 203a of the third active layer 203 is relatively large.

[0081] Specifically, such as Figure 11 As shown, the distance between the first conductive region 201a of the first active layer 201 and the first conductive region 203a of the third active layer 203 in the second direction F2 is d1. The distance between any point on the edge of the first bent portion LZ1 and the first conductive region 203a of the third active layer 203 in the second direction F2 is d2. It can be clearly seen from the figure that d2 is greater than d1, that is, the distance between the first bent portion LZ1 and the first conductive region 203a of the third active layer 203 is relatively large.

[0082] Optionally, in the display panel provided in the embodiments of this disclosure, such as Figure 11 As shown, the second active layer 202 includes: a first branch FZ1 and a second branch FZ2; One end of the first branch FZ1 is the first conductive region 202a of the second active layer 202, and the other end is connected to the second branch FZ2. The first branch FZ1 extends along the second direction F2, and the second branch FZ2 extends along the first direction F1.

[0083] By positioning the first conductive region 202a of the second active layer 202 on the side of the first branch FZ1 away from the first active layer 201, it is more convenient to connect the first conductive region 202a of the second active layer 202 to the initialization signal line VINIT. Furthermore, by positioning the first branch FZ1 on the side of the second branch FZ2 away from the first active layer 201, more space can be reserved for the first active layer 201. Setting the second branch FZ2 to extend along the first direction F1 facilitates connection with the sixth active layer 206.

[0084] In specific implementation, the display panel provided in the embodiments of this disclosure, such as Figure 11 As shown, the third active layer 203 includes: a conductive protrusion TQ, and a conductive extension YS extending along the first direction F1; One end of the conductive protrusion TQ is the first conductive region 203a of the third active layer 203, and the other end is connected to the conductive extension YS.

[0085] like Figure 14 and Figure 15 As shown, the second conductive layer 22 may further include: a scan line GA extending along the second direction F2, the gate of the data writing transistor being the portion where the scan line GA overlaps with the third active layer 203, and a conductive extension YS extending along the first direction F1, so that the third active layer 203 can overlap with the scan line GA. By providing a conductive protrusion TQ, it is convenient for the first conductive region 203a to be electrically connected to the data signal line VD. Furthermore, the conductive protrusion TQ can be located on the side of the conductive extension YS closer to the first active layer 201, or it can be located on the side of the conductive extension YS farther away from the first active layer 201; this is not limited here.

[0086] In addition, such as Figure 11 As shown, the semiconductor layer 20 may further include: a fourth active layer 204 for driving transistor T4, a fifth active layer 205 for the first light-emitting control transistor, a sixth active layer 206 for the second light-emitting control transistor, and a seventh active layer 207 for the threshold compensation transistor. Each active layer in the semiconductor layer 20 may include a first conductive region, a second conductive region, and a channel region. The channel region may be located between the first conductive region and the second conductive region. Optionally, the first conductive region serves as the source of the transistor, and the second conductive region serves as the drain of the transistor; or the first conductive region serves as the drain of the transistor, and the second conductive region serves as the source of the transistor. No limitation is made here. Furthermore, each active layer in the semiconductor layer 20 may be integrally formed.

[0087] In practical implementation, connected active layers can share a common conductive region, for example, such as Figure 11 As shown, the first active layer 201 and the second active layer 202 share the conductive region b1. Similarly, the third active layer 203, the fourth active layer 204, and the fifth active layer 205 share the conductive region b2. In addition, other active layers can also share the conductive region, which will not be described in detail here.

[0088] Specifically, the semiconductor layer 20 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned first and second conductive regions can be regions doped with n-type or p-type impurities.

[0089] For example, such as Figure 14 and Figure 15As shown, the second conductive layer 22 may include the second terminal c2 of the storage capacitor CST, the scan line GA, the reset line RST, the light emission control line EM, the driving gate G1 of the driving transistor, the gate of the data writing transistor, the gate of the threshold compensation transistor, the gate of the first light emission control transistor, the gate of the second light emission control transistor, the gate of the initialization transistor, and the gate of the reset transistor, wherein the driving gate G1 of the driving transistor may be the second terminal c2 of the storage CST.

[0090] For example, such as Figure 4 , Figure 6 , Figure 8 As shown, the orthographic projection of the storage capacitor CST on the substrate 10 at least partially overlaps with the orthographic projection of the fixed potential signal line VDD on the substrate 10.

[0091] For example, combining Figure 7 and Figure 11 As shown, the gate of the data writing transistor can be the part where the scan line GA overlaps with the third active layer; the gate of the first light-emitting control transistor can be the part where the light-emitting control line EM overlaps with the fifth active layer 205; the gate of the second light-emitting control transistor can be the part where the light-emitting control line EM overlaps with the sixth active layer 206; the gate of the initialization transistor is the part where the reset line RST overlaps with the first active layer 201; the gate of the reset transistor is the part where the reset line RST overlaps with the second active layer 202; the threshold compensation transistor can be a thin-film transistor with a dual-gate structure; the first gate of the threshold compensation transistor can be the part where the scan line GA overlaps with the seventh active layer 207; and the second gate of the threshold compensation transistor can be the part where the protrusion protruding from the scan line GA overlaps with the seventh active layer 207.

[0092] For example, such as Figure 15 As shown, the scan line GA, reset line RST, and light emission control line EM are arranged along the first direction F1. Furthermore, the scan line GA, reset line RST, and light emission control line EM extend approximately along the second direction F2. For example, the scan line GA is located between the reset line RST and the light emission control line EM.

[0093] For example, in the first direction F1, the second terminal c2 of the storage capacitor CST is located between the scan line GA and the light emission control line EM. Furthermore, the protrusion extending from the scan line GA is located on the side of the scan line GA furthest from the light emission control line EM.

[0094] For example, refer to Figure 16 and Figure 17The aforementioned third conductive layer 13 may include the first electrode c1 of the storage capacitor CST, the initialization signal line VINIT, the shielding structure 231, and the conductive connection structure 232, wherein the first electrode c1 of the storage capacitor CST and the second electrode c2 of the storage capacitor CST at least partially overlap to form the storage capacitor CST.

[0095] Figure 20 This is a top view of the fifth conductive layer in an embodiment of this disclosure, as shown below. Figure 20 As shown, the multiple anodes in the fifth conductive layer can be divided into a first anode 251a, a second anode 251b, a third anode 251c, and a fourth anode 251d. Correspondingly, the multiple sub-pixels in the display panel can be divided into multiple repeating units. Each repeating unit can include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The first sub-pixel can include the first anode 251a, the second sub-pixel can include the second anode 251b, the third sub-pixel can include the third anode 251c, and the fourth sub-pixel can include the fourth anode 251d. In specific implementations, the number of sub-pixels in the repeating structure can also be other values, which are not limited here.

[0096] In practical applications, the display panel provided in the embodiments of this disclosure, such as Figure 1 As shown, multiple sub-pixels spx in the display panel are arranged in an array in the first direction F1 and the second direction F2; Simultaneously refer to Figure 12 The display panel includes multiple data signal lines, which are divided into a first data signal line VD1 and a second data signal line VD2. In each column of sub-pixels spx, sub-pixels spx in odd-numbered rows share a first data signal line VD1, and sub-pixels spx in even-numbered rows share a second data signal line VD2, for example... Figure 1 In the first column of sub-pixels spx, the first, third, and fifth sub-pixels spx are all connected to the first data signal line VD1, and the second, fourth, and sixth sub-pixels spx are all connected to the second data signal line VD2.

[0097] For high refresh rate display panels, increasing the refresh rate will compress each row of subpixels (e.g., Figure 1The data signal writing time of a row of sub-pixels arranged along the second direction F2 is determined by setting the data signal writing time of each column of sub-pixels spx as follows: sub-pixels spx in odd-numbered rows share a first data signal line VD1, and sub-pixels spx in even-numbered rows share a second data signal line VD2. During the driving process, the odd-numbered row sub-pixels and even-numbered row sub-pixels can be driven separately, thereby solving the problem of insufficient data writing time for each row of sub-pixels when displaying at high frame rates. It should be noted that in this embodiment, the second direction F2 is used as the row direction and the first direction F1 is used as the column direction for explanation. In specific implementation, the first direction F1 can also be used as the row direction and the second direction F2 as the column direction; this is not limited here.

[0098] For example, such as Figure 4 , Figure 12 , Figure 20 As shown, the first sub-pixel and the third sub-pixel are located in adjacent rows of the same column; One of the first sub-pixel and the third sub-pixel is electrically connected to the first data signal line VD1, and the other is electrically connected to the second data signal line VD2. The first data signal line VD1 and the second data signal line VD2 are located on opposite sides of the columns containing the first and third sub-pixels.

[0099] For example, such as Figure 4 , Figure 12 , Figure 20 As shown, the data signal conversion section DZ includes a first data signal conversion section DZ1 and a second data signal conversion section DZ2. One of the first sub-pixel and the third sub-pixel is electrically connected to the first data signal line VD1 via the first data signal adapter DZ1, and the other is electrically connected to the second data signal line VD2 via the second data signal adapter DZ2.

[0100] For example, such as Figure 4 , Figure 12 As shown, in the second direction F2, the dimensions of the first data signal adapter DZ1 and the second data signal adapter DZ2 are different.

[0101] Based on the same inventive concept, this disclosure also provides a display device, including the aforementioned display panel. This display device can be applied to any product or component with display function, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators. Since the principle by which this display device solves the problem is similar to that of the aforementioned display panel, the implementation of this display device can refer to the implementation of the aforementioned display panel, and repeated details will not be described again.

[0102] The display panel and display device provided in this disclosure increase the distance between the first active layer connected to the driving gate and the third active layer connected to the data signal line by disposing the first active layer on the side of the second active layer away from the data signal line, thereby mitigating the influence of the data signal line on the driving gate of the driving transistor and improving the display effect of the display panel.

[0103] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0104] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein, The display panel includes: a substrate, and a plurality of sub-pixels located on the substrate; The sub-pixel includes: A semiconductor layer is located on the substrate; the semiconductor layer includes: a first active layer for initializing transistors and a third active layer for writing data transistors; A first conductive layer is located on the semiconductor layer away from the substrate; the first conductive layer includes: a data signal line extending along a first direction; A second conductive layer is located on the substrate; the second conductive layer includes: a driving gate of a driving transistor; A shielding structure is located on the substrate. A conductive connection structure is located on the substrate and is electrically connected to the shielding structure. The driving gate is electrically connected to the first conductive region of the first active layer. The data signal line is electrically connected to the first conductive region of the third active layer. The orthographic projection of the shielding structure on the substrate is located between the orthographic projection of the first conductive region of the first active layer on the substrate and the orthographic projection of the first conductive region of the third active layer on the substrate. The orthographic projection of the conductive connection structure on the substrate at least partially overlaps with the orthographic projection of the first conductive region of the first active layer on the substrate.

2. The display panel as claimed in claim 1, wherein, The first conductive layer further includes: a data signal adapter that is electrically connected to the data signal line; The orthographic projection of the data signal adapter on the substrate at least partially overlaps with the orthographic projection of the conductive connection structure on the substrate.

3. The display panel as described in claim 2, wherein, The plurality of sub-pixels are arranged in an array in the first direction and the second direction, wherein the second direction is a direction that intersects with the first direction; The display panel includes multiple data signal lines, and the multiple data signal lines include a first data signal line and a second data signal line; The plurality of sub-pixels includes a first sub-pixel and a third sub-pixel, wherein the first sub-pixel and the third sub-pixel are located in adjacent rows of the same column; One of the first sub-pixel and the third sub-pixel is electrically connected to the first data signal line, and the other is electrically connected to the second data signal line; The first data signal line and the second data signal line are located on opposite sides of the column containing the first sub-pixel and the third sub-pixel.

4. The display panel as claimed in claim 3, wherein, The data signal conversion unit includes a first data signal conversion unit and a second data signal conversion unit; One of the first sub-pixel and the third sub-pixel is electrically connected to the first data signal line through the first data signal adapter, and the other is electrically connected to the second data signal line through the second data signal adapter.

5. The display panel as claimed in claim 4, wherein, In the second direction, the size of the first data signal adapter is different from the size of the second data signal adapter.

6. The display panel as described in any one of claims 2-5, wherein, The semiconductor layer further includes a second active layer with a reset transistor, and the sub-pixel further includes: A third conductive layer is located on the substrate; the third conductive layer includes: an initialization signal line extending along a second direction, the second direction being a direction intersecting the first direction; the initialization signal line is electrically connected to a first conductive region of the second active layer; The first conductive region of the second active layer is located at one end of the second active layer away from the first active layer.

7. The display panel as claimed in claim 6, wherein, Also includes: The fourth conductive layer is located on the side of the semiconductor layer that is away from the substrate. The fourth conductive layer includes: a fixed potential signal line extending along the first direction; The shielding structure is electrically connected to the fixed potential signal line.

8. The display panel as claimed in claim 7, wherein, The conductive connection structure is located in the third conductive layer; The fixed potential signal line is electrically connected to the shielding structure through the conductive connection structure.

9. The display panel as claimed in claim 8, wherein, The shielding structure and the conductive connection structure are an integral part of each other.

10. The display panel according to any one of claims 7-9, wherein, The fourth conductive layer further includes: a first conductive connection portion, a second conductive connection portion, and a third conductive connection portion that are mutually insulated from each other; The driving gate is electrically connected to the first conductive region of the first active layer through the first conductive connection portion. The data signal line is electrically connected to the first conductive region of the third active layer through the second conductive connection portion. The initialization signal line is electrically connected to the first conductive region of the second active layer through the third conductive connection portion.

11. The display panel as claimed in claim 10, wherein, The data signal adapter is electrically connected to the second conductive connector through a first via.

12. The display panel as claimed in claim 11, wherein, The display panel includes sub-pixels of multiple colors, and the sub-pixels further include: A fifth conductive layer is located on the side of the first conductive layer away from the substrate. The fifth conductive layer includes a plurality of anodes, and the orthographic projection of the anode of at least one color sub-pixel on the substrate does not overlap with the orthographic projection of the first via on the substrate.

13. The display panel as claimed in claim 11, wherein, The display panel includes sub-pixels of multiple colors, and the sub-pixels further include: The fifth conductive layer is located on the side of the first conductive layer away from the substrate. The fifth conductive layer includes a plurality of anodes. The orthographic projection of the anode of at least one color sub-pixel on the substrate overlaps with the orthographic projection of the data signal transfer portion on the substrate, but does not overlap with the orthographic projection of the second conductive connection portion on the substrate.

14. The display panel according to any one of claims 7-13, wherein, The sub-pixel includes a pixel driving circuit and a light-emitting device, wherein the pixel driving circuit includes: A drive control circuit is electrically connected between a first voltage terminal and the anode of the light-emitting device, and is configured to drive the light-emitting device to emit light. The first voltage terminal is electrically connected to the fixed potential signal line.

15. The display panel as claimed in claim 14, wherein, The sub-pixel further includes: a storage capacitor located in the second conductive layer; The first terminal of the storage capacitor is electrically connected to the fixed potential signal line, and the second terminal of the storage capacitor is electrically connected to the driving gate. The orthographic projection of the storage capacitor on the substrate at least partially overlaps with the orthographic projection of the fixed potential signal line on the substrate.

16. The display panel according to any one of claims 6-15, wherein, The shielding structure is disposed on the same layer as the initialization signal line.

17. The display panel as claimed in claim 10, wherein, The semiconductor layer further includes a channel region of the first active layer and a channel region of the second active layer, and the sub-pixel further includes: The orthographic projection of the channel region of the second active layer on the substrate is located between the orthographic projection of the channel region of the first active layer on the substrate and the orthographic projection of the third conductive connection portion on the substrate.

18. A display device, wherein, Includes the display panel as described in any one of claims 1-17.

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