Pixel driving circuit, driving method thereof and display panel

Abstract

The invention relates to the technical field of display, and provides a pixel driving circuit, a driving method thereof and a display panel. The pixel driving circuit comprises a driving circuit, a first capacitor, a second capacitor, a data write-in circuit, a first isolation circuit, a second isolation circuit and a threshold compensation circuit, wherein the driving circuit is used for providing driving current for a third node by utilizing a second node according to the voltage of a first node; a first electrode of the first capacitor is connected with the first node and a second electrode is connected with the fourth node; the first electrode of the second capacitor is connected with the fourth node and the second electrode; the data write-in circuit is used for transmitting a signal of a data signal end to a seventh node in response to a signal of a control end of the data write-in circuit, and the seventh node is connected with a fourth node; the first isolation circuit is used for responding to a signal of a control end to connect the first node and the fifth node; the second isolation circuit is used for responding to a signal of a control end to connect a fifth node and a sixth node; the threshold compensation circuit is used for responding to a signal of the control end so as to connect the sixth node and the third node. The pixel driving circuit can output more stable driving current.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel driving circuit and its driving method, and a display panel. Background Technology

[0002] In related technologies, pixel driving circuits include driving transistors, which output driving current based on their gate voltage. However, due to leakage problems in the gate voltage of the driving transistors, the driving current output by the pixel driving circuit is unstable.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a pixel driving circuit is provided, wherein the pixel driving circuit includes:

[0005] A driving circuit is connected to a first node, a second node, and a third node. The driving circuit is used to provide a driving current to the third node through the second node based on the voltage of the first node.

[0006] A first capacitor, with its first electrode connected to the first node and its second electrode connected to the fourth node;

[0007] The second capacitor has its first electrode connected to the fourth node and its second electrode connected to the constant voltage signal terminal.

[0008] A data writing circuit is connected to the seventh node and the data signal terminal. The data writing circuit is used to respond to the signal of its control terminal to transmit the signal of the data signal terminal to the seventh node. The seventh node is connected to the fourth node.

[0009] A first isolation circuit connects the first node and the fifth node, and the first isolation circuit is used to connect the first node and the fifth node in response to a signal at its control terminal.

[0010] A second isolation circuit is connected to the fifth node and the sixth node. The second isolation circuit is used to respond to signals at its control terminal to connect the fifth node and the sixth node.

[0011] A threshold compensation circuit is connected to the sixth node and the third node. The threshold compensation circuit is used to respond to the signal at its control terminal to connect the sixth node and the third node.

[0012] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes one or more of a first reset circuit, a first light emission control circuit, a second reset circuit, and a third reset circuit;

[0013] The first reset circuit is connected to the first initial signal terminal, and the first reset circuit is used to respond to the signal of its control terminal to transmit the signal of the first initial signal terminal to the fifth node;

[0014] The first light-emitting control circuit is connected to the third node, the first electrode of the light-emitting unit, and the first enable signal terminal. The first light-emitting control circuit is used to respond to the signal of the first enable signal terminal to connect the third node and the first electrode of the light-emitting unit.

[0015] The second reset circuit is connected to the first initial signal terminal or the second initial signal terminal. The second reset circuit is used to respond to the signal of its control terminal to transmit the signal of the first initial signal terminal or the second initial signal terminal to the first electrode of the light-emitting unit.

[0016] The third reset circuit is connected to the seventh node and the reference voltage terminal. The third reset circuit is used to respond to the signal at its control terminal to transmit the signal at the reference voltage terminal to the seventh node.

[0017] In an exemplary embodiment of this disclosure, the first reset circuit is connected to a first initial signal terminal and a fifth node, and the first reset circuit is used to respond to a signal at its control terminal to transmit the signal at the first initial signal terminal to the fifth node;

[0018] The second reset circuit is connected to the first electrode, the first initial signal terminal, or the second initial signal terminal of the light-emitting unit. The second reset circuit is used to respond to the signal of its control terminal to transmit the signal of the first initial signal terminal or the second initial signal terminal to the first electrode of the light-emitting unit.

[0019] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0020] The second light-emitting control circuit is connected to the second node, the first power supply terminal, the first enable signal terminal, or the second enable signal terminal. The second light-emitting control circuit is used to respond to the signal of the first enable signal terminal or the second enable signal terminal to connect the second node and the first power supply terminal.

[0021] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0022] The fourth reset circuit is connected to the third node, the third initial signal terminal, and the first reset signal terminal. The fourth reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the third initial signal terminal to the third node.

[0023] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0024] The fourth reset circuit is connected to the second node, the third initial signal terminal, and the first reset signal terminal. The fourth reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the third initial signal terminal to the second node.

[0025] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0026] A third isolation circuit connects the fourth node and the seventh node, and the third isolation circuit is used to respond to signals from its control terminal to connect the fourth node and the seventh node.

[0027] In one exemplary embodiment of this disclosure, the control terminals of the third isolation circuit and the first isolation circuit are connected to the same control signal terminal.

[0028] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0029] A third reset circuit is connected to the seventh node and the reference voltage terminal. The third reset circuit is used to respond to the signal at its control terminal to transmit the signal at the reference voltage terminal to the seventh node.

[0030] At least some of the circuits in the first isolation circuit, the second isolation circuit, and the third reset circuit have the same conduction level polarity, and the control terminals of the circuits in the first isolation circuit, the second isolation circuit, and the third reset circuit with the same conduction level polarity are connected to the same control signal terminal.

[0031] And / or, at least some of the circuits in the first isolation circuit, the second isolation circuit, and the third reset circuit have opposite polarities in their conduction levels, and the control terminals of the circuits in the first isolation circuit, the second isolation circuit, and the third reset circuit with opposite polarities in their conduction levels are respectively connected to different control signal terminals, and the different control signal terminals are used to provide control signals with opposite polarities respectively.

[0032] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0033] A third reset circuit is connected to the seventh node and the reference voltage terminal. The third reset circuit is used to respond to the signal at its control terminal to transmit the signal at the reference voltage terminal to the seventh node.

[0034] The conduction level of at least one of the first isolation circuit, the second isolation circuit, and the third reset circuit has the same polarity as the conduction level of the threshold compensation circuit. In the first isolation circuit, the second isolation circuit, and the third reset circuit, the circuit with the same polarity as the conduction level of the threshold compensation circuit is connected to different shift register units in the same gate drive circuit, respectively, as the control terminal of the threshold compensation circuit.

[0035] Alternatively, the conduction voltages of the first isolation circuit, the second isolation circuit, and the third reset circuit may be opposite in polarity to the conduction voltage of the threshold compensation circuit, and the threshold compensation circuit may be connected to different gate drive circuits along with any one of the first isolation circuit, the second isolation circuit, and the third reset circuit.

[0036] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0037] A first reset circuit is connected to a first initial signal terminal and a fifth node. The first reset circuit is used to respond to a signal from its control terminal to transmit the signal from the first initial signal terminal to the fifth node.

[0038] A third reset circuit is connected to the seventh node and the reference voltage terminal. The third reset circuit is used to respond to the signal at its control terminal to transmit the signal at the reference voltage terminal to the seventh node.

[0039] The conduction level of at least one of the first isolation circuit, the second isolation circuit, the third reset circuit, and the threshold compensation circuit has the same polarity as the conduction level of the first reset circuit. Furthermore, among the first isolation circuit, the second isolation circuit, the third reset circuit, and the threshold compensation circuit, the circuit with the same polarity as the conduction level of the first reset circuit is connected to different shift register units in the same gate drive circuit, respectively, as the control terminal of the first reset circuit.

[0040] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0041] A first reset circuit is connected to a first initial signal terminal and a fifth node. The first reset circuit is used to respond to a signal from its control terminal to transmit the signal from the first initial signal terminal to the fifth node.

[0042] The data writing circuit and the first reset circuit have the same conduction level polarity, and the control terminals of the data writing circuit and the first reset circuit are respectively connected to different shift register units in the same gate drive circuit.

[0043] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0044] The second reset circuit is connected to the first electrode, the first initial signal terminal, or the second initial signal terminal of the light-emitting unit. The second reset circuit is used to respond to the signal of its control terminal to transmit the signal of the first initial signal terminal or the second initial signal terminal to the first electrode of the light-emitting unit.

[0045] The second reset circuit and the data writing circuit have the same conduction level polarity, and the control terminals of the second reset circuit and the data writing circuit are connected to the same control signal terminal.

[0046] Alternatively, the conduction levels of the second reset circuit and the data writing circuit have opposite polarities, and the control terminals of the second reset circuit and the data writing circuit are connected to different control signal terminals, which are used to output signals with opposite polarities.

[0047] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0048] A first reset circuit is connected to a first initial signal terminal and a fifth node. The first reset circuit is used to respond to a signal from its control terminal to transmit the signal from the first initial signal terminal to the fifth node.

[0049] The second reset circuit is connected to the first electrode, the first initial signal terminal, or the second initial signal terminal of the light-emitting unit. The second reset circuit is used to respond to the signal of its control terminal to transmit the signal of the first initial signal terminal or the second initial signal terminal to the first electrode of the light-emitting unit.

[0050] A third reset circuit is connected to the seventh node and the reference voltage terminal. The third reset circuit is used to respond to the signal at its control terminal to transmit the signal at the reference voltage terminal to the seventh node.

[0051] The conduction level of at least one of the first isolation circuit, the second isolation circuit, the third reset circuit, the threshold compensation circuit, and the first reset circuit has the same polarity as the conduction level of the second reset circuit. Furthermore, among the first isolation circuit, the second isolation circuit, the third reset circuit, the threshold compensation circuit, and the first reset circuit, the circuit with the same polarity as the conduction level of the second reset circuit is connected to the control terminal of the second reset circuit in the same shift register unit or different shift register units in the same gate drive circuit.

[0052] In one exemplary embodiment of this disclosure, the driving circuit includes:

[0053] A driving transistor, with its first terminal connected to the second node, its second terminal connected to the third node, and its gate connected to the first node;

[0054] The data writing circuit includes:

[0055] The fourth transistor has its first terminal connected to the data signal terminal, its second terminal connected to the seventh node, and its gate forming the control terminal of the data writing circuit.

[0056] The first isolation circuit includes:

[0057] The eighth transistor has its first terminal connected to the first node, its second terminal connected to the fifth node, and its gate forming the control terminal of the first isolation circuit.

[0058] The second isolation circuit includes:

[0059] The ninth transistor has its first terminal connected to the fifth node, its second terminal connected to the sixth node, and its gate forming the control terminal of the second isolation circuit.

[0060] The threshold compensation circuit includes:

[0061] The second transistor has its first terminal connected to the sixth node, its second terminal connected to the third node, and its gate forming the control terminal of the threshold compensation circuit.

[0062] In one exemplary embodiment of this disclosure, the first reset circuit includes:

[0063] The first transistor has a first terminal connected to the first initial signal terminal, a second terminal connected to the fifth node, and a gate forming the control terminal of the second isolation circuit.

[0064] The first light-emitting control circuit includes:

[0065] The sixth transistor has its first electrode connected to the third node, its second electrode connected to the first electrode of the light-emitting unit, and its gate forming the control terminal of the first light-emitting control circuit.

[0066] The second reset circuit includes:

[0067] The seventh transistor has its first electrode connected to either the first initial signal terminal or the second initial signal terminal, its second electrode connected to the first electrode of the light-emitting unit, and its gate forming the control terminal of the second reset circuit.

[0068] The third reset circuit includes:

[0069] The fifth transistor has its first terminal connected to the reference voltage terminal, its second terminal connected to the seventh node, and its gate forming the control terminal of the third reset circuit.

[0070] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes one or more of a fourth reset circuit and a third isolation circuit;

[0071] The fourth reset circuit is connected to the third node or the second node, the third initial signal terminal, and the first reset signal terminal. The fourth reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the third initial signal terminal to the third node or the fourth node.

[0072] The third isolation circuit connects the fourth node and the seventh node, and the third isolation circuit is used to connect the fourth node and the seventh node in response to the signal at its control terminal;

[0073] The fourth reset circuit includes:

[0074] The tenth transistor has its first terminal connected to the third initial signal terminal, its second terminal connected to the second or third node, and its gate connected to the first reset signal terminal.

[0075] The third isolation circuit includes:

[0076] The eleventh transistor has its first terminal connected to the seventh node, its second terminal connected to the fourth node, and its gate forming the control terminal of the third isolation circuit.

[0077] In one exemplary embodiment of this disclosure, the second light-emitting control circuit includes:

[0078] The twelfth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the second node, and its gate connected to either the first enable signal terminal or the second enable signal terminal.

[0079] In one exemplary embodiment of this disclosure, the driving circuit includes a driving transistor, a first terminal of the driving transistor is connected to the second node, a second terminal is connected to the third node, and a gate is connected to the first node;

[0080] The driving transistor is a P-type polysilicon transistor. At least one N-type oxide transistor is included between the fourth node and the data signal terminal. At least one N-type oxide transistor is included between the fourth node and the reference voltage terminal. At least one N-type oxide transistor is included between the first node and the first initial signal terminal. At least one N-type oxide transistor is included between the first node and the third node.

[0081] In one exemplary embodiment of this disclosure, the seventh node and the fourth node are the same node.

[0082] In one exemplary embodiment of this disclosure, the constant voltage signal terminal is a first power supply terminal or a reference voltage terminal.

[0083] According to one aspect of this disclosure, a pixel driving circuit driving method is provided, wherein the driving method is used to drive the aforementioned pixel driving circuit, the driving method comprising:

[0084] During the pre-reset phase: the first isolation circuit, the second isolation circuit, and the threshold compensation circuit are turned off, and the first reset circuit is turned on to transmit the signal from the first initial signal terminal to the fifth node;

[0085] During the reset phase: the threshold compensation circuit is turned off, and the first reset circuit and the first isolation circuit are turned on to transmit the signal from the first initial signal terminal to the first node;

[0086] During the threshold compensation stage: the first reset circuit is turned off, and the first isolation circuit, the second isolation circuit, and the threshold compensation circuit are turned on, so that the second node can input the compensation voltage to the first node.

[0087] During the data writing phase: the first isolation circuit and the first reset circuit are turned off, and the data writing circuit is turned on to transmit the signal from the data signal terminal to the fourth node. The voltage change of the fourth node is coupled to the first node using the first capacitor.

[0088] During the light-emitting phase: the driving circuit provides driving current to the third node according to the voltage of the first node.

[0089] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0090] A first light-emitting control circuit is connected to the third node, the first electrode of the light-emitting unit, and the first enable signal terminal. The first light-emitting control circuit is used to respond to the signal of the first enable signal terminal to connect the third node and the first electrode of the light-emitting unit.

[0091] The driving method further includes:

[0092] During the pre-reset phase, the first light-emitting control circuit is turned on or off.

[0093] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes the pixel driving circuit described above.

[0094] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0095] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0096] Figure 1 A schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure;

[0097] Figure 2 A schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure;

[0098] Figure 3 for Figure 2 The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0099] Figure 4 for Figure 2 The timing diagram of each node in another driving method of the pixel driving circuit shown is shown.

[0100] Figure 5 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0101] Figure 6 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0102] Figure 7 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0103] Figure 8 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0104] Figure 9 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0105] Figure 10 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0106] Figure 11 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0107] Figure 12 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0108] Figure 13 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0109] Figure 14 This is a schematic diagram of the structure of an exemplary embodiment of the display panel disclosed herein;

[0110] Figure 15 This is a schematic diagram of another exemplary embodiment of the display panel disclosed herein. Detailed Implementation

[0111] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0112] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0113] like Figure 1 The diagram shown is a schematic representation of an exemplary embodiment of the pixel driving circuit of this disclosure. The pixel driving circuit includes: a driving circuit 1, a first capacitor C1, a second capacitor C2, a data writing circuit 2, a first isolation circuit 31, a second isolation circuit 32, a threshold compensation circuit 4, and a first reset circuit 51. The driving circuit 1 is connected to a first node N1, a second node N2, and a third node N3. The driving circuit is used to provide a driving current to the third node N3 using the second node N2 based on the voltage of the first node N1. The first electrode of the first capacitor C1 is connected to the first node N1, and the second electrode is connected to the fourth node N4. The first electrode of the second capacitor C2 is connected to the fourth node N4, and the second electrode is connected to the first power supply terminal VDD1. The data writing circuit 2 is connected to a seventh node N7 and a data signal terminal Data. The data writing circuit 2 is used to transmit the signal of the data signal terminal Data to the seventh node N7 in response to the signal of its control terminal CN. The seventh node N7 is connected to the fourth node N4. The first isolation circuit 31 is connected to the first node N1 and a fifth node N2. N5, the first isolation circuit 31 is used to connect the first node N1 and the fifth node N5 in response to the signal of its control terminal CN; the second isolation circuit 32 connects the fifth node N5 and the sixth node N6, and the second isolation circuit 32 is used to connect the fifth node N5 and the sixth node N6 in response to the signal of its control terminal CN; the threshold compensation circuit 4 connects the sixth node N6 and the third node N3, and the threshold compensation circuit 4 is used to connect the sixth node N6 and the third node N3 in response to the signal of its control terminal CN; the first reset circuit 51 connects the fifth node N5 and the first initial signal terminal Vinit1, and the first reset circuit 51 is used to transmit the signal of the first initial signal terminal Vinit1 to the fifth node N5 in response to the signal of its control terminal CN.

[0114] In this exemplary embodiment, the driving method of the pixel driving circuit may include: a pre-reset stage, a reset stage, a threshold compensation stage, a data writing stage, and a light emission stage. In the pre-reset phase: the first isolation circuit 31, the second isolation circuit 32, and the threshold compensation circuit 4 are turned off, and the first reset circuit 51 is turned on to transmit the signal of the first initial signal terminal Vinit1 to the fifth node N5; in the reset phase: the threshold compensation circuit 4 is turned off, and the first reset circuit 51 and the first isolation circuit 31 are turned on to transmit the signal of the first initial signal terminal Vinit1 to the first node N1; in the threshold compensation phase: the first reset circuit 51 is turned off, and the first isolation circuit 31, the second isolation circuit 32, and the threshold compensation circuit 4 are turned on to input a compensation voltage to the first node N1 using the first power supply terminal VDD1; in the data writing phase: the first isolation circuit 31 and the first reset circuit 51 are turned off, and the data writing circuit 2 is turned on to transmit the signal of the data signal terminal Data to the fourth node N4, while the voltage change of the fourth node N4 is coupled to the first node N1 using the first capacitor C1; in the light emission phase: the driving circuit provides a driving current to the third node N3 according to the voltage of the first node N1. The pixel driving circuit provided in this exemplary embodiment adds the first isolation circuit 31 and the second isolation circuit 32. On the one hand, the first isolation circuit 31 and the second isolation circuit 32 can reduce the leakage current of the first node N1, thereby improving the stability of the output drive current of the pixel driving circuit. On the other hand, the pixel driving circuit can use the first initial signal terminal Vinit1 to input the initial signal to the fifth node N5 in advance during the pre-reset stage before the reset stage. Since the fifth node N5 has parasitic capacitance, the initial signal can charge the parasitic capacitance of the fifth node N5 in advance. Therefore, this setting can improve the reset speed of the first node N1 during the reset stage.

[0115] It should be understood that, in other exemplary embodiments, the first reset circuit 51 may also be connected to the sixth node N6 or the third node N3. The first reset circuit 51 may provide an initial signal to the fifth node N5 through the sixth node N6 or the third node N3.

[0116] like Figure 1As shown, the pixel driving circuit may further include: a first light-emitting control circuit 61, a second reset circuit 52, and a third reset circuit 53. The first light-emitting control circuit 61 is connected to the third node N3, the first electrode of the light-emitting unit L, and the first enable signal terminal EM1. The first light-emitting control circuit 61 is used to connect the third node N3 and the first electrode of the light-emitting unit in response to the signal of the first enable signal terminal EM1. The second reset circuit 52 is connected to the first electrode of the light-emitting unit L and the second initial signal terminal Vinit2. The second reset circuit 52 is used to transmit the signal of the second initial signal terminal Vinit2 to the first electrode of the light-emitting unit in response to the signal of its control terminal CN. The third reset circuit 53 is connected to the seventh node N7 and a reference voltage terminal. The third reset circuit 53 is used to transmit the signal of the reference voltage terminal to the seventh node N7 in response to the signal of its control terminal CN. It should be understood that in other exemplary embodiments, the pixel driving circuit may not include the third reset circuit 53, and the data signal terminal Data can provide a reference voltage to the fourth node through the data writing circuit 2.

[0117] like Figure 2The diagram shown is a schematic representation of an exemplary embodiment of the pixel driving circuit of this disclosure. The driving circuit includes a driving transistor T3, whose first terminal is connected to a second node N2, its second terminal is connected to a third node N3, and its gate is connected to a first node N1. The data writing circuit 2 includes a fourth transistor T4, whose first terminal is connected to a data signal terminal Data, its second terminal is connected to a seventh node N7, and its gate forms the control terminal of the data writing circuit 2. The first isolation circuit 31 includes an eighth transistor T8, whose first terminal is connected to a first node N1, its second terminal is connected to a fifth node N5, and its gate forms the control terminal of the first isolation circuit 31. The second isolation circuit 32 includes a ninth transistor T9, whose first terminal is connected to a fifth node N5, its second terminal is connected to a sixth node N6, and its gate forms the control terminal of the second isolation circuit 32. The first reset circuit 51 includes a first transistor T1, whose first terminal is connected to a first initial signal terminal Vinit1, its second terminal is connected to a fifth node N5, and its gate forms the control terminal of the second isolation circuit 32. The threshold compensation circuit 4 includes a second transistor T2, whose first terminal is connected to the sixth node N6, its second terminal is connected to the third node N3, and its gate forms the control terminal of the threshold compensation circuit 4. The first light-emitting control circuit 61 includes a sixth transistor T6, whose first terminal is connected to the third node N3, its second terminal is connected to the first electrode of the light-emitting unit L, and its gate forms the control terminal of the first light-emitting control circuit 61. The second reset circuit 52 includes a seventh transistor T7, whose first terminal is connected to the second initial signal terminal Vinit2, its second terminal is connected to the first electrode of the light-emitting unit, and its gate forms the control terminal of the second reset circuit 52. The third reset circuit 53 includes a fifth transistor T5, whose first terminal is connected to the reference voltage terminal Vref, its second terminal is connected to the seventh node N7, and its gate forms the control terminal of the third reset circuit 53.

[0118] In this exemplary embodiment, as Figure 2 As shown, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are P-type transistors. For example, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be P-type polysilicon transistors.

[0119] In this exemplary embodiment, as Figure 2As shown, at least some circuits in the first isolation circuit 31, the second isolation circuit 32, and the third reset circuit 53 have the same conduction level polarity, and the control terminals of the circuits in the first isolation circuit 31, the second isolation circuit 32, and the third reset circuit 53 with the same conduction level polarity are connected to the same control signal terminal. For example, the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 can be connected to the same control signal terminal (the first control signal terminal AZ[N]).

[0120] In this exemplary embodiment, as Figure 2 As shown, the conduction level of at least one of the first isolation circuit 31, the second isolation circuit 32, and the third reset circuit 53 has the same polarity as the conduction level of the threshold compensation circuit 4. Furthermore, in the first isolation circuit 31, the second isolation circuit 32, and the third reset circuit 53, the circuit with the same polarity as the conduction level of the threshold compensation circuit 4 is connected to different shift register units in the same gate drive circuit, respectively, along with the control terminal of the threshold compensation circuit 4. For example, the gate of the second transistor T2 can be connected to the third control signal terminal AZ[N+1].

[0121] In this exemplary embodiment, as Figure 2 As shown, the conduction level of at least one of the first isolation circuit 31, the second isolation circuit 32, the third reset circuit 53, and the threshold compensation circuit 4 has the same polarity as the conduction level of the first reset circuit 51. Furthermore, among the first isolation circuit 31, the second isolation circuit 32, the third reset circuit 53, and the threshold compensation circuit 4, the circuit with the same polarity as the conduction level of the first reset circuit 51 is connected to different shift register units in the same gate drive circuit, respectively, along with the control terminal of the first reset circuit 51. For example, the gate of the first transistor T1 can be connected to the second control signal terminal AZ[N-2].

[0122] In this exemplary embodiment, as Figure 2 As shown, the second reset circuit 52 and the data writing circuit 2 have the same conduction level polarity, and their control terminals are connected to the same control signal terminal. For example, the gate of the fourth transistor T4 can be connected to the first gate drive signal terminal PG[N], and the gate of the seventh transistor T7 can be connected to the first gate drive signal terminal PG[N].

[0123] In this exemplary embodiment, as Figure 2As shown, the first control signal terminal AZ[N], the second control signal terminal AZ[N-2], and the third control signal terminal AZ[N+1] can be connected to different shift register units in the same gate drive circuit. For example, the first control signal terminal AZ[N] can be connected to the nth stage shift register unit in the gate drive circuit, the second control signal terminal AZ[N-2] can be connected to the (n-2)th stage shift register unit in the gate drive circuit, and the third control signal terminal AZ[N+1] can be connected to the (n+1)th stage shift register unit in the gate drive circuit.

[0124] like Figure 3 As shown, Figure 2 The diagram shows the timing diagrams of each node in a driving method of the pixel driving circuit shown. Specifically, EM1 is the timing diagram of the signal at the first enable signal terminal, AZ[N] is the timing diagram of the signal at the first control signal terminal, AZ[N-2] is the timing diagram of the signal at the second control signal terminal, AZ[N+1] is the timing diagram of the signal at the third control signal terminal, PG[N] is the timing diagram of the signal at the first gate drive signal terminal, Data is the timing diagram of the signal at the data signal terminal, N1 is the timing diagram of the signal at the first node, N3 is the timing diagram of the signal at the third node, N4 is the timing diagram of the signal at the fourth node, N5 is the timing diagram of the signal at the fifth node, and Vanode is the timing diagram of the signal at the first electrode of the light-emitting unit L.

[0125] The driving method of the pixel driving circuit may include: a pre-reset stage t1, a reset stage t2, a threshold compensation stage t3, a data writing stage t4, and a light emission stage t5.

[0126] During the pre-reset phase t1: the second control signal terminal AZ[N-2] outputs a low level, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the fifth node N5.

[0127] During the reset phase t2: the first control signal terminal AZ[N] and the second control signal terminal AZ[N-2] output low level, the first transistor T1, the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 are turned on, the first initial signal terminal Vinit1 inputs the initial signal to the fifth node N5, the first node N1, and the sixth node N6, and the reference voltage terminal Vref inputs the reference voltage Vf to the fourth node N4.

[0128] During the threshold compensation stage t3: the first control signal terminal AZ[N] and the third control signal terminal AZ[N+1] output low level, the second control signal terminal AZ[N-2] outputs high level, the first transistor T1 is turned off, and the second transistor T2, the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 are turned on. The reference voltage terminal Vref continuously inputs the reference voltage Vf to the fourth node N4. At the same time, the first power supply terminal VDD1 inputs the compensation voltage Vdd+Vth to the first node N1, where Vdd is the voltage of the first power supply terminal VDD1 and Vth is the threshold voltage of the driving transistor T3.

[0129] During the data writing phase t4: the first gate drive signal terminal PG[N] outputs a low level, the first control signal terminal AZ[N] outputs a high level, the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 are turned off, the fourth transistor T4 is turned on, the data signal terminal Data inputs a data signal to the fourth node N4, the voltage of the fourth node N4 changes from Vf to Vdata, Vdata is the voltage of the data signal, the first capacitor C1 couples the voltage change of the fourth node N4 to the first node N1, the voltage of the first node N1 changes from Vdd+Vth to Vdd+Vth+Vdata-Vf. At the same time, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 provides a reset signal to the first electrode of the light-emitting unit L.

[0130] During the light-emitting stage t5: the first enable signal terminal EM1 outputs a low-level signal, the sixth transistor T6 is turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the voltage Vdd+Vth+Vdata-Vf stored in the first capacitor C1.

[0131] The formula for the output current of the driving transistor is as follows:

[0132] I = (μWCox / 2L)(Vgs-Vth) 2

[0133] Where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; and Vgs is the gate-source voltage difference of the driving transistor. In the pixel driving circuit of this disclosure, the output current of the driving transistor I = (μWCox / 2L)(Vdd + Vth + Vdata - Vf - Vdd - Vth) 2 This pixel driving circuit avoids the influence of the driving transistor threshold on its output current. Furthermore, the threshold compensation stage is separated from the data writing stage, and the threshold compensation stage can span multiple scan times, enabling high-frequency refresh.

[0134] like Figure 4 As shown, Figure 2 The timing diagrams for each node in another driving method of the pixel driving circuit shown are as follows: EM1 is the timing diagram for the signal at the first enable signal terminal; AZ[N] is the timing diagram for the signal at the first control signal terminal; AZ[N-2] is the timing diagram for the signal at the second control signal terminal; AZ[N+1] is the timing diagram for the signal at the third control signal terminal; PG[N] is the timing diagram for the signal at the first gate drive signal terminal; Data is the timing diagram for the signal at the data signal terminal; N1 is the timing diagram for the signal at the first node; N3 is the timing diagram for the signal at the third node; N4 is the timing diagram for the signal at the fourth node; N5 is the timing diagram for the signal at the fifth node; and Vanode is the timing diagram for the signal at the first electrode of the light-emitting unit L.

[0135] Figure 4 The driving method shown and Figure 3 The driving method shown is different in that, Figure 4 In the pre-reset phase t1 of the driving method shown, the first enable signal terminal EM1 outputs a low level. This setting can increase the light emission duration of the light-emitting unit, thereby improving the screen flickering problem.

[0136] like Figure 2 As shown in this exemplary embodiment, the first terminal of the seventh transistor T7 is connected to the second initial signal terminal Vinit2. It should be understood that in other exemplary embodiments, the first terminal of the seventh transistor T7 may be shared with the first transistor and connected to the first initial signal terminal Vinit1.

[0137] like Figure 2As shown in this exemplary embodiment, the gate of the seventh transistor T7 is connected to the first gate drive signal terminal PG[N]. It should be understood that in other exemplary embodiments, the conduction level of at least one of the first isolation circuit 31, the second isolation circuit 32, the third reset circuit 53, the threshold compensation circuit 4, and the first reset circuit 51 has the same polarity as the conduction level of the second reset circuit 52. Furthermore, among the first isolation circuit 31, the second isolation circuit 32, the third reset circuit 53, the threshold compensation circuit 4, and the first reset circuit 51, the circuit with the same polarity as the conduction level of the second reset circuit 52 is connected to different shift register units in the same gate drive circuit, respectively, along with the control terminal of the second reset circuit 52. For example, the gate of the seventh transistor T7 can also be connected to the fourth control signal terminal AZ[Nx]. The fourth control signal terminal AZ[Nx] can be connected to the same shift register unit or different shift register units in the same gate drive circuit as the first control signal terminal AZ[N], the second control signal terminal AZ[N-2], and the third control signal terminal AZ[N+1]. For example, the fourth control signal terminal AZ[Nx] can be connected to the nx-th shift register unit, where x is an integer between -1 and 2. The value range of x is controlled by the pulse width of the effective pulse signal on the fourth control signal terminal, the shift length of the adjacent shift signal output by the gate drive circuit connected to the fourth control signal terminal, and the duration of the effective level output by the first enable signal terminal. When the driving timing of the pixel drive circuit changes, the value range of x will also change.

[0138] In this exemplary embodiment, as Figure 2As shown, the gate of the first transistor T1 is connected to the second control signal terminal AZ[N-2]. It should be understood that in other exemplary embodiments, when the conduction level polarities of the data writing circuit 2 and the first reset circuit 51 are the same, the control terminals of the data writing circuit 2 and the first reset circuit 51 can be connected to different shift register units in the same gate driving circuit. For example, the gate of the first transistor T1 can also be connected to the second gate driving signal terminal PG[Ny]. The second gate driving signal terminal PG[Ny] and the first gate driving signal terminal PG[N] can be connected to different shift register units in the same gate driving circuit. For example, the first gate driving signal terminal PG[N] can be connected to the nth stage shift register unit in the same gate driving circuit, and the second gate driving signal terminal PG[Ny] can be connected to the nyth stage shift register unit in the same gate driving circuit. In the same scan cycle, the second gate driving signal terminal PG[Ny] needs to turn on the first transistor T1 before the fourth transistor T4 turns on. Therefore, y is an integer greater than or equal to 1. For example, y can be equal to 1, 2, 3, 4, 5, 6, 7, 8, etc. The value range of y is controlled by the pulse width of the effective pulse signal on the second gate drive signal terminal and the shift length of the adjacent shift signal output by the gate drive circuit connected to the second gate drive signal terminal. When the driving timing of the pixel drive circuit changes, the value range of y will also change.

[0139] In this exemplary embodiment, as Figure 5 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 2 The pixel driving circuit shown is Figure 5 The pixel driving circuit shown is equipped with a second light-emitting control circuit 62. The second light-emitting control circuit 62 is connected to the second node N2, the first power supply terminal VDD1, and the second enable signal terminal EM2. The second light-emitting control circuit 62 is used to respond to the signal of the second enable signal terminal EM2 to connect the second node N2 and the first power supply terminal VDD1.

[0140] In this exemplary embodiment, as Figure 5 As shown, the second light-emitting control circuit 62 may include a twelfth transistor T12, the first terminal of which is connected to the first power supply terminal VDD1, the second terminal of which is connected to the second node N2, and the gate of which is connected to the second enable signal terminal EM2. The twelfth transistor T12 may be a P-type transistor, for example, a P-type polysilicon transistor.

[0141] In this exemplary embodiment, as Figure 5As shown, the second enable signal terminal EM2 can turn on the second light emission control circuit 62 during the threshold compensation stage and the light emission stage, thereby enabling normal scanning and light emission of the pixel driving circuit. Furthermore, the second enable signal terminal EM2 can turn off the second light emission control circuit 62 during one or more stages, including the pre-reset stage, the reset circuit, and the data writing stage. On the one hand, this setting can reduce the voltage impact of the first power supply terminal VDD1 on the first node N1; on the other hand, this setting can reduce the duration of the bias state of the driving transistor T3, thereby reducing the aging speed of the driving transistor T3.

[0142] It should be understood that, in other exemplary embodiments, the gate of the twelfth transistor T12 may also be connected to the first enable signal terminal EM1. The first enable signal terminal EM1 needs to turn on the second light-emitting control circuit 62 during the threshold compensation stage. Correspondingly, the first enable signal terminal EM1 will also turn on the sixth transistor T6. This setting may cause the light-emitting unit to be abnormally lit.

[0143] In this exemplary embodiment, as Figure 6 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 2 The pixel driving circuit shown is Figure 6 The pixel driving circuit shown includes a fourth reset circuit 54. This fourth reset circuit 54 is connected to the third node N3, the third initial signal terminal Vinit3, and the first reset signal terminal ResetH. The fourth reset circuit 54 is used to transmit the signal from the third initial signal terminal Vinit3 to the third node N3 in response to the signal from the first reset signal terminal ResetH. On one hand, the fourth reset circuit 54 can provide an initial signal to the third node N3 before the threshold compensation stage to improve the display panel afterimage and flicker problems caused by the hysteresis effect of the driving transistor T3. For example, the fourth reset circuit 54 can provide an initial signal to the third node N3 during the pre-reset stage or the reset stage. On the other hand, the fourth reset circuit 54 can provide an initial signal to the third node N3 after the threshold compensation stage and before the light emission stage, so that the voltage of the third node N3 before the light emission stage is consistent in both the scan frame and the hold frame. This setting allows the brightness of the light-emitting units to be more similar in the scan frame and the hold frame. It should be noted that... Figure 5 The pixel driving circuit shown can also be equipped with a fourth reset circuit 54, which is connected to the third node.

[0144] In this exemplary embodiment, as Figure 6As shown, the fourth reset circuit 54 may include: a tenth transistor T10, the first terminal of the tenth transistor T10 being connected to the third initial signal terminal Vinit3, the second terminal being connected to the third node N3, and the gate being connected to the first reset signal terminal ResetH. The tenth transistor T10 may be a P-type transistor, for example, the tenth transistor T10 may be a P-type polysilicon transistor.

[0145] In this exemplary embodiment, as Figure 7 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 5 The pixel driving circuit shown is Figure 7 The pixel driving circuit shown includes a fourth reset circuit 54. This fourth reset circuit 54 is connected to the second node N2, the third initial signal terminal Vinit3, and the first reset signal terminal ResetH. The fourth reset circuit 54 responds to the signal from the first reset signal terminal ResetH to transmit the signal from the third initial signal terminal Vinit3 to the second node N2. Similarly, on one hand, the fourth reset circuit 54 can provide an initial signal to the second node N2 before the threshold compensation stage to improve the display panel afterimage and flickering problems caused by the hysteresis effect of the driving transistor T3. For example, the fourth reset circuit 54 can provide an initial signal to the second node N2 during the pre-reset stage or the reset stage. On the other hand, the fourth reset circuit 54 can provide an initial signal to the second node N2 after the threshold compensation stage and before the light emission stage, so that the voltage of the second node N2 before the light emission stage is consistent in both the scan frame and the hold frame. This setting allows the brightness of the light-emitting unit to be more similar in the scan frame and the hold frame. It should be noted that when the first reset signal terminal ResetH is activated by the fourth reset circuit 54, the second light emission control circuit needs to turn off the first power supply terminal VDD1 and the second node.

[0146] In this exemplary embodiment, as Figure 7 As shown, the fourth reset circuit 54 may include: a tenth transistor T10, the first terminal of the tenth transistor T10 being connected to the third initial signal terminal Vinit3, the second terminal being connected to the second node N2, and the gate being connected to the first reset signal terminal ResetH. The tenth transistor T10 may be a P-type transistor, for example, the tenth transistor T10 may be a P-type polysilicon transistor.

[0147] In this exemplary embodiment, as Figure 8 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 2 The pixel driving circuit shown is Figure 8In the pixel driving circuit shown, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 can be N-type transistors. For example, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 can be N-type oxide transistors (optionally indium gallium zinc oxide transistors). N-type oxide transistors have smaller leakage current, which can reduce the leakage current of the first node N1 and the fourth node N4.

[0148] In this exemplary embodiment, when at least some circuits in the first isolation circuit 31, the second isolation circuit 32, and the third reset circuit 53 have opposite conduction level polarities, and the control terminals of the circuits with opposite conduction level polarities in the first isolation circuit 31, the second isolation circuit 32, and the third reset circuit 53 are respectively connected to different control signal terminals, and the different control signal terminals are used to provide control signals with opposite polarities respectively. For example, such as Figure 8 As shown, the gates of the fifth transistor T5 and the eighth transistor T8 can be connected to the third gate drive signal terminal NG[N]. The signal on the third gate drive signal terminal NG[N] can have opposite polarities to the signal on the first control signal terminal AZ[N].

[0149] In this exemplary embodiment, the gate of the fourth transistor T4 can be connected to the fourth gate drive signal terminal PGF[N], and the signal on the fourth gate drive signal terminal PGF[N] and the signal on the first gate drive signal terminal PG[N] can have opposite polarities.

[0150] In this exemplary embodiment, as Figure 9 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 8 The pixel driving circuit shown is in Figure 9 In the pixel driving circuit shown, the ninth transistor T9 can be an N-type transistor, for example, an N-type oxide transistor (optionally an indium gallium zinc oxide transistor). N-type oxide transistors have lower leakage current, which further reduces the leakage current of the first node N1. Figure 9 As shown, the gate of the ninth transistor T9 can be connected to the third gate drive signal terminal NG[N].

[0151] In this exemplary embodiment, as Figure 10 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 9 The pixel driving circuit shown is in Figure 10 In the pixel driving circuit shown, all transistors except driving transistor T3 and the sixth transistor T6 are N-type transistors. For example, the transistors except driving transistor T3 and the sixth transistor T6 can be N-type oxide transistors (optionally indium gallium zinc oxide transistors).

[0152] In this exemplary embodiment, as Figure 10 As shown, the gate of the second transistor T2 is connected to the fifth gate drive signal terminal NG[N+1], the gate of the first transistor T1 is connected to the sixth gate drive signal terminal NG[N-2], and the gate of the seventh transistor T7 is connected to the fourth gate drive signal terminal PGF[N].

[0153] In this exemplary embodiment, the third gate drive signal terminal NG[N], the fifth gate drive signal terminal NG[N+1], and the sixth gate drive signal terminal NG[N-2] can be connected to different shift register units in the same gate drive circuit. The driving method of this pixel drive circuit is similar to... Figure 2 The driving method of the pixel driving circuit shown can be the same. Correspondingly, the signal polarity of the third gate driving signal terminal NG[N] is opposite to that of the first control signal terminal AZ[N], the signal polarity of the fifth gate driving signal terminal NG[N+1] is opposite to that of the third control signal terminal AZ[N+1], and the signal polarity of the sixth gate driving signal terminal NG[N-2] is opposite to that of the second control signal terminal AZ[N-2].

[0154] It should be understood that in other exemplary embodiments, such as Figure 10 As shown, the gate of the first transistor T1 can also be connected to the seventh gate drive signal terminal PGF[Ny]. The seventh gate drive signal terminal PGF[Ny] and the fourth gate drive signal terminal PGF[N] are connected to different shift register units in the same gate drive circuit. The gate of the seventh transistor T7 can also be connected to the eighth gate drive signal terminal NG[Nx]. The eighth gate drive signal terminal NG[Nx] and the third gate drive signal terminal NG[N] are connected to different shift register units or the same shift register unit in the same gate drive circuit. Furthermore, in other exemplary embodiments, the sixth transistor T6 can also be an N-type transistor. For example, the sixth transistor T6 can be an N-type oxide transistor, specifically, the sixth transistor T6 can be an N-type indium gallium zinc oxide transistor.

[0155] In this exemplary embodiment, as Figure 11 The diagram shown is a schematic representation of another exemplary embodiment of the pixel driving circuit of this disclosure. Figure 2 Compared to the pixel driving circuit shown, Figure 11 The pixel driving circuit shown is further equipped with a third isolation circuit 33, which connects the fourth node N4 and the seventh node N7. The third isolation circuit 33 is used to respond to signals from its control terminal to connect the fourth node N4 and the seventh node N7. Furthermore, with... Figure 2 Compared to the pixel driving circuit shown, Figure 11The pixel driving circuit shown sets the eighth transistor T8 as an N-type transistor. For example, the eighth transistor T8 can be an N-type oxide transistor (optionally an indium gallium zinc oxide transistor). N-type oxide transistors have a smaller turn-off leakage current, which can reduce the leakage current of the first node N1.

[0156] In this exemplary embodiment, as Figure 11 As shown, the third isolation circuit 33 includes an eleventh transistor T11. The first terminal of the eleventh transistor T11 is connected to the seventh node N7, the second terminal is connected to the fourth node N4, and the gate forms the control terminal of the third isolation circuit 33. The eleventh transistor T11 can be an N-type transistor, for example, an N-type oxide transistor (optionally an indium gallium zinc oxide transistor). N-type oxide transistors have a smaller turn-off leakage current. This configuration can reduce the leakage current of the fourth node, thereby improving the stability of the voltage of the first node N1.

[0157] In this exemplary embodiment, the control terminal of the third isolation circuit 33 and the control terminal of the first isolation circuit can be shared and connected to the third gate drive signal terminal NG[N].

[0158] It should be noted that, Figures 5-10 The pixel driving circuit shown can also be equipped with a third isolation circuit 33.

[0159] In this exemplary embodiment, as Figure 12 The diagram shown is a schematic representation of another exemplary embodiment of the pixel driving circuit of this disclosure. Figure 11 The pixel driving circuit shown is different, Figure 12 The pixel driving circuit shown sets the first transistor T1, the second transistor T2, the seventh transistor T7, and the ninth transistor T9 as N-type transistors. For example, the first transistor T1, the second transistor T2, the seventh transistor T7, and the ninth transistor T9 can be N-type oxide transistors (optionally indium gallium zinc oxide transistors).

[0160] In this exemplary embodiment, as Figure 12 As shown, the gate of the ninth transistor T9 is connected to the third gate drive signal terminal NG[N], the gate of the second transistor T2 is connected to the fifth gate drive signal terminal NG[N+1], and the gate of the first transistor T1 is connected to the sixth gate drive signal terminal NG[N-2].

[0161] In this exemplary embodiment, as Figure 12As shown, when the conduction levels of the second reset circuit 52 and the data writing circuit 2 are opposite in polarity, the control terminals of the second reset circuit 52 and the data writing circuit 2 are connected to different control signal terminals, which are used to output signals with opposite polarities. For example, the gate of the seventh transistor T7 is connected to the fourth gate drive signal terminal PGF[N], and the fourth gate drive signal terminal PGF[N] and the first gate drive signal terminal PG[N] are used to output signals with opposite polarities.

[0162] In this exemplary embodiment, the third gate drive signal terminal NG[N], the fifth gate drive signal terminal NG[N+1], and the sixth gate drive signal terminal NG[N-2] can be connected to different shift register units in the same gate drive circuit. The driving method of this pixel drive circuit is similar to... Figure 2 The driving method of the pixel driving circuit shown can be the same. Correspondingly, the signal polarity of the third gate driving signal terminal NG[N] is opposite to that of the first control signal terminal AZ[N], the signal polarity of the fifth gate driving signal terminal NG[N+1] is opposite to that of the third control signal terminal AZ[N+1], and the signal polarity of the sixth gate driving signal terminal NG[N-2] is opposite to that of the second control signal terminal AZ[N-2].

[0163] It should be understood that in other exemplary embodiments, such as Figure 12 As shown, the gate of the seventh transistor T7 can also be connected to the eighth gate drive signal terminal NG[Nx]. The eighth gate drive signal terminal NG[Nx] and the third gate drive signal terminal NG[N] are connected to different shift register units or the same shift register unit in the same gate drive circuit.

[0164] In this exemplary embodiment, as Figure 13 The diagram shown is a schematic representation of another exemplary embodiment of the pixel driving circuit of this disclosure. Figure 11 The pixel driving circuit shown is different, Figure 13 The pixel driving circuit shown adds a fourth reset circuit 54 to the third node N3. It should be understood that, in other exemplary embodiments, the fourth reset circuit 54 can also be connected between the second electrode of the first capacitor C1 and the fourth node N4. The fourth reset circuit 54 can respond to a signal at its control terminal to connect the second electrode of the first capacitor C1 and the fourth node N4. During the light-emitting phase, the fourth reset circuit 54 is turned off; this setting can prevent the voltage change of the fourth node N4 from having a coupling effect on the first node N1.

[0165] In this exemplary embodiment, as Figures 8-13As shown, at least one N-type oxide transistor is included between the fourth node N4 and the data signal terminal Data, at least one N-type oxide transistor is included between the fourth node N4 and the reference voltage terminal, at least one N-type oxide transistor is included between the first node N1 and the first initial signal terminal Vinit1, and at least one N-type oxide transistor is included between the first node N1 and the third node N3. This arrangement can reduce the leakage current of the first node N1 and the fourth node N4.

[0166] In this exemplary embodiment, as Figures 2-13 As shown, the eighth transistor T8, the ninth transistor T9, and the second transistor T2 can all be single-gate transistors, meaning that the eighth transistor T8, the ninth transistor T9, and the second transistor T2 each have only one channel region. This setting facilitates the corresponding layout design and enables high PPI display effects.

[0167] In this exemplary embodiment, as Figures 1-13 As shown, the second electrode of the second capacitor C2 can also be connected to other constant voltage signal terminals, such as the reference voltage terminal Vref, the second power supply terminal VDD2, etc.

[0168] like Figure 14 The diagram shown illustrates a structural embodiment of the display panel disclosed herein. The display panel may include multiple arrayed pixel driving circuits (Pix) and multiple gate driving circuits. The multiple gate driving circuits include a first gate driving circuit (GOA1), a second gate driving circuit (GOA2), and a third gate driving circuit (GOA3). The first gate driving circuit (GOA1) includes multiple cascaded shift register units (EM), the second gate driving circuit (GOA2) includes multiple cascaded shift register units (AZ), and the third gate driving circuit (GOA3) includes multiple cascaded shift register units (Gate). The structure of the pixel driving circuit (Pix) can be as follows: Figure 2 As shown. The first gate drive circuit GOA1 provides a gate drive signal to the first enable signal terminal through a gate line extending along the row direction. Different shift register units in the second gate drive circuit GOA2 provide gate drive signals to the first control signal terminal AZ[N], the second control signal terminal AZ[N-2], and the third control signal terminal AZ[N+1] through different gate lines extending along the row direction. The third gate drive circuit GOA3 provides a gate drive signal to the first gate drive signal terminal PG[N] through a gate line extending along the row direction.

[0169] In this exemplary embodiment, as Figure 14As shown, the first gate driving circuit GOA1 can adopt a 2CLK architecture, and the output of the shift register unit EM can be connected to two rows of pixel driving circuits Pix. The second gate driving circuit GOA2 can adopt a 6CLK architecture, and the output of the shift register unit AZ can be connected to two rows of pixel driving circuits Pix. Furthermore, the output of the nth-stage shift register unit AZ is connected to the input of the (n+3)th-stage shift register unit AZ, where n is a positive integer greater than or equal to 1. The third gate driving circuit GOA3 can adopt a 4CLK architecture, and the output of the shift register unit Gate can be connected to one row of pixel driving circuits Pix. Furthermore, the output of the nth-stage shift register unit Gate is connected to the input of the (n+2)th-stage shift register unit Gate, where n is a positive integer greater than or equal to 1.

[0170] like Figure 14 As shown, the display panel includes two first gate drive circuits GOA1, two second gate drive circuits GOA2, and two third gate drive circuits GOA3. The two first gate drive circuits GOA1 are respectively connected to the two ends of their corresponding gate lines, the two second gate drive circuits GOA2 are respectively connected to the two ends of their corresponding gate lines, and the two third gate drive circuits GOA3 are respectively connected to the two ends of their corresponding gate lines. This arrangement can improve the driving capability of the gate drive signal on the gate line.

[0171] like Figure 15 The diagram shown is a structural schematic of another exemplary embodiment of the display panel of this disclosure. Figure 14 The difference is that the display panel shown is that... Figure 15 The display panel shown includes a first gate driving circuit GOA1 and a second gate driving circuit GOA2, and the first gate driving circuit GOA1 and the second gate driving circuit GOA2 are respectively disposed on both sides of the display panel.

[0172] In this exemplary embodiment, the display panel can be applied to display devices such as mobile phones, tablets, televisions, and vehicle displays.

[0173] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0174] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A pixel driving circuit, wherein, The pixel driving circuit includes: A driving circuit is connected to a first node, a second node, and a third node. The driving circuit is used to provide a driving current to the third node through the second node based on the voltage of the first node. A first capacitor, with its first electrode connected to the first node and its second electrode connected to the fourth node; The second capacitor has its first electrode connected to the fourth node and its second electrode connected to the constant voltage signal terminal. A data writing circuit is connected to the seventh node and the data signal terminal. The data writing circuit is used to respond to the signal of its control terminal to transmit the signal of the data signal terminal to the seventh node. The seventh node is connected to the fourth node. A first isolation circuit connects the first node and the fifth node, and the first isolation circuit is used to connect the first node and the fifth node in response to a signal at its control terminal. A second isolation circuit is connected to the fifth node and the sixth node. The second isolation circuit is used to respond to signals at its control terminal to connect the fifth node and the sixth node. A threshold compensation circuit is connected to the sixth node and the third node. The threshold compensation circuit is used to respond to the signal at its control terminal to connect the sixth node and the third node.

2. The pixel driving circuit according to claim 1, wherein, The pixel driving circuit further includes one or more of the following: a first reset circuit, a first light emission control circuit, a second reset circuit, and a third reset circuit; The first reset circuit is connected to the first initial signal terminal, and the first reset circuit is used to respond to the signal of its control terminal to transmit the signal of the first initial signal terminal to the fifth node; The first light-emitting control circuit is connected to the third node, the first electrode of the light-emitting unit, and the first enable signal terminal. The first light-emitting control circuit is used to respond to the signal of the first enable signal terminal to connect the third node and the first electrode of the light-emitting unit. The second reset circuit is connected to the first initial signal terminal or the second initial signal terminal. The second reset circuit is used to respond to the signal of its control terminal to transmit the signal of the first initial signal terminal or the second initial signal terminal to the first electrode of the light-emitting unit. The third reset circuit is connected to the seventh node and the reference voltage terminal. The third reset circuit is used to respond to the signal at its control terminal to transmit the signal at the reference voltage terminal to the seventh node.

3. The pixel driving circuit according to claim 2, wherein, The first reset circuit is connected to the first initial signal terminal and the fifth node. The first reset circuit is used to respond to the signal of its control terminal to transmit the signal of the first initial signal terminal to the fifth node. The second reset circuit is connected to the first electrode, the first initial signal terminal, or the second initial signal terminal of the light-emitting unit. The second reset circuit is used to respond to the signal of its control terminal to transmit the signal of the first initial signal terminal or the second initial signal terminal to the first electrode of the light-emitting unit.

4. The pixel driving circuit according to any one of claims 1-3, wherein, The pixel driving circuit also includes: The second light-emitting control circuit is connected to the second node, the first power supply terminal, the first enable signal terminal, or the second enable signal terminal. The second light-emitting control circuit is used to respond to the signal of the first enable signal terminal or the second enable signal terminal to connect the second node and the first power supply terminal.

5. The pixel driving circuit according to any one of claims 1-4, wherein, The pixel driving circuit also includes: The fourth reset circuit is connected to the third node, the third initial signal terminal, and the first reset signal terminal. The fourth reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the third initial signal terminal to the third node.

6. The pixel driving circuit according to claim 4, wherein, The pixel driving circuit also includes: The fourth reset circuit is connected to the second node, the third initial signal terminal, and the first reset signal terminal. The fourth reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the third initial signal terminal to the second node.

7. The pixel driving circuit according to any one of claims 1-6, wherein, The pixel driving circuit also includes: A third isolation circuit connects the fourth node and the seventh node, and the third isolation circuit is used to respond to signals from its control terminal to connect the fourth node and the seventh node.

8. The pixel driving circuit according to claim 7, wherein, The control terminals of the third isolation circuit and the first isolation circuit are connected to the same control signal terminal.

9. The pixel driving circuit according to any one of claims 1-8, wherein, The pixel driving circuit also includes: A third reset circuit is connected to the seventh node and the reference voltage terminal. The third reset circuit is used to respond to the signal at its control terminal to transmit the signal at the reference voltage terminal to the seventh node. At least some of the circuits in the first isolation circuit, the second isolation circuit, and the third reset circuit have the same conduction level polarity, and the control terminals of the circuits in the first isolation circuit, the second isolation circuit, and the third reset circuit with the same conduction level polarity are connected to the same control signal terminal. And / or, at least some of the circuits in the first isolation circuit, the second isolation circuit, and the third reset circuit have opposite polarities in their conduction levels, and the control terminals of the circuits in the first isolation circuit, the second isolation circuit, and the third reset circuit with opposite polarities in their conduction levels are respectively connected to different control signal terminals, and the different control signal terminals are used to provide control signals with opposite polarities respectively.

10. The pixel driving circuit according to any one of claims 1-8, wherein, The pixel driving circuit also includes: A third reset circuit is connected to the seventh node and the reference voltage terminal. The third reset circuit is used to respond to the signal at its control terminal to transmit the signal at the reference voltage terminal to the seventh node. The conduction level of at least one of the first isolation circuit, the second isolation circuit, and the third reset circuit has the same polarity as the conduction level of the threshold compensation circuit. In the first isolation circuit, the second isolation circuit, and the third reset circuit, the circuit with the same polarity as the conduction level of the threshold compensation circuit is connected to different shift register units in the same gate drive circuit, respectively, as the control terminal of the threshold compensation circuit. Alternatively, the conduction voltages of the first isolation circuit, the second isolation circuit, and the third reset circuit may be opposite in polarity to the conduction voltage of the threshold compensation circuit, and the threshold compensation circuit may be connected to different gate drive circuits along with any one of the first isolation circuit, the second isolation circuit, and the third reset circuit.

11. The pixel driving circuit according to any one of claims 1-10, wherein, The pixel driving circuit also includes: A first reset circuit is connected to a first initial signal terminal and a fifth node. The first reset circuit is used to respond to a signal from its control terminal to transmit the signal from the first initial signal terminal to the fifth node. A third reset circuit is connected to the seventh node and the reference voltage terminal. The third reset circuit is used to respond to the signal at its control terminal to transmit the signal at the reference voltage terminal to the seventh node. The conduction level of at least one of the first isolation circuit, the second isolation circuit, the third reset circuit, and the threshold compensation circuit has the same polarity as the conduction level of the first reset circuit. Furthermore, among the first isolation circuit, the second isolation circuit, the third reset circuit, and the threshold compensation circuit, the circuit with the same polarity as the conduction level of the first reset circuit is connected to different shift register units in the same gate drive circuit, respectively, as the control terminal of the first reset circuit.

12. The pixel driving circuit according to any one of claims 1-10, wherein, The pixel driving circuit also includes: A first reset circuit is connected to a first initial signal terminal and a fifth node. The first reset circuit is used to respond to a signal from its control terminal to transmit the signal from the first initial signal terminal to the fifth node. The data writing circuit and the first reset circuit have the same conduction level polarity, and the control terminals of the data writing circuit and the first reset circuit are respectively connected to different shift register units in the same gate drive circuit.

13. The pixel driving circuit according to any one of claims 1-12, wherein, The pixel driving circuit also includes: The second reset circuit is connected to the first electrode, the first initial signal terminal, or the second initial signal terminal of the light-emitting unit. The second reset circuit is used to respond to the signal of its control terminal to transmit the signal of the first initial signal terminal or the second initial signal terminal to the first electrode of the light-emitting unit. The second reset circuit and the data writing circuit have the same conduction level polarity, and the control terminals of the second reset circuit and the data writing circuit are connected to the same control signal terminal. Alternatively, the conduction levels of the second reset circuit and the data writing circuit have opposite polarities, and the control terminals of the second reset circuit and the data writing circuit are connected to different control signal terminals, which are used to output signals with opposite polarities.

14. The pixel driving circuit according to any one of claims 1-12, wherein, The pixel driving circuit also includes: A first reset circuit is connected to a first initial signal terminal and a fifth node. The first reset circuit is used to respond to a signal from its control terminal to transmit the signal from the first initial signal terminal to the fifth node. The second reset circuit is connected to the first electrode, the first initial signal terminal, or the second initial signal terminal of the light-emitting unit. The second reset circuit is used to respond to the signal of its control terminal to transmit the signal of the first initial signal terminal or the second initial signal terminal to the first electrode of the light-emitting unit. A third reset circuit is connected to the seventh node and the reference voltage terminal. The third reset circuit is used to respond to the signal at its control terminal to transmit the signal at the reference voltage terminal to the seventh node. The conduction level of at least one of the first isolation circuit, the second isolation circuit, the third reset circuit, the threshold compensation circuit, and the first reset circuit has the same polarity as the conduction level of the second reset circuit. Furthermore, among the first isolation circuit, the second isolation circuit, the third reset circuit, the threshold compensation circuit, and the first reset circuit, the circuit with the same polarity as the conduction level of the second reset circuit is connected to the control terminal of the second reset circuit in the same shift register unit or different shift register units in the same gate drive circuit.

15. The pixel driving circuit according to claim 1, wherein, The driving circuit includes: A driving transistor, with its first terminal connected to the second node, its second terminal connected to the third node, and its gate connected to the first node; The data writing circuit includes: The fourth transistor has its first terminal connected to the data signal terminal, its second terminal connected to the seventh node, and its gate forming the control terminal of the data writing circuit. The first isolation circuit includes: The eighth transistor has its first terminal connected to the first node, its second terminal connected to the fifth node, and its gate forming the control terminal of the first isolation circuit. The second isolation circuit includes: The ninth transistor has its first terminal connected to the fifth node, its second terminal connected to the sixth node, and its gate forming the control terminal of the second isolation circuit. The threshold compensation circuit includes: The second transistor has its first terminal connected to the sixth node, its second terminal connected to the third node, and its gate forming the control terminal of the threshold compensation circuit.

16. The pixel driving circuit according to claim 2, wherein, The first reset circuit includes: The first transistor has a first terminal connected to the first initial signal terminal, a second terminal connected to the fifth node, and a gate forming the control terminal of the second isolation circuit. The first light-emitting control circuit includes: The sixth transistor has its first electrode connected to the third node, its second electrode connected to the first electrode of the light-emitting unit, and its gate forming the control terminal of the first light-emitting control circuit. The second reset circuit includes: The seventh transistor has its first electrode connected to either the first initial signal terminal or the second initial signal terminal, its second electrode connected to the first electrode of the light-emitting unit, and its gate forming the control terminal of the second reset circuit. The third reset circuit includes: The fifth transistor has its first terminal connected to the reference voltage terminal, its second terminal connected to the seventh node, and its gate forming the control terminal of the third reset circuit.

17. The pixel driving circuit according to any one of claims 1-16, wherein, The pixel driving circuit further includes one or more of a fourth reset circuit and a third isolation circuit; The fourth reset circuit is connected to the third node or the second node, the third initial signal terminal, and the first reset signal terminal. The fourth reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the third initial signal terminal to the third node or the fourth node. The third isolation circuit connects the fourth node and the seventh node, and the third isolation circuit is used to connect the fourth node and the seventh node in response to the signal at its control terminal; The fourth reset circuit includes: The tenth transistor has its first terminal connected to the third initial signal terminal, its second terminal connected to the second node or the third node, and its gate connected to the first reset signal terminal. The third isolation circuit includes: The eleventh transistor has its first terminal connected to the seventh node, its second terminal connected to the fourth node, and its gate forming the control terminal of the third isolation circuit.

18. The pixel driving circuit according to claim 4, wherein, The second light-emitting control circuit includes: The twelfth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the second node, and its gate connected to either the first enable signal terminal or the second enable signal terminal.

19. The pixel driving circuit according to claim 2, wherein, The driving circuit includes a driving transistor, with the first terminal of the driving transistor connected to the second node, the second terminal connected to the third node, and the gate connected to the first node. The driving transistor is a P-type polysilicon transistor. At least one N-type oxide transistor is included between the fourth node and the data signal terminal. At least one N-type oxide transistor is included between the fourth node and the reference voltage terminal. At least one N-type oxide transistor is included between the first node and the first initial signal terminal. At least one N-type oxide transistor is included between the first node and the third node.

20. The pixel driving circuit according to any one of claims 1-6, wherein, The seventh node and the fourth node are the same node.

21. The pixel driving circuit according to any one of claims 1-20, wherein, The constant voltage signal terminal is either the first power supply terminal or the reference voltage terminal.

22. A pixel driving circuit driving method, wherein, The driving method is used to drive the pixel driving circuit according to any one of claims 2-21, the pixel driving circuit including a first reset circuit, and the driving method includes: During the pre-reset phase: the first isolation circuit, the second isolation circuit, and the threshold compensation circuit are turned off, and the first reset circuit is turned on to transmit the signal from the first initial signal terminal to the fifth node; During the reset phase: the threshold compensation circuit is turned off, and the first reset circuit and the first isolation circuit are turned on to transmit the signal from the first initial signal terminal to the first node; During the threshold compensation stage: the first reset circuit is turned off, and the first isolation circuit, the second isolation circuit, and the threshold compensation circuit are turned on, so that the second node can input the compensation voltage to the first node. During the data writing phase: the first isolation circuit and the first reset circuit are turned off, and the data writing circuit is turned on to transmit the signal from the data signal terminal to the fourth node. The voltage change of the fourth node is coupled to the first node using the first capacitor. During the light-emitting phase: the driving circuit provides driving current to the third node according to the voltage of the first node.

23. The pixel driving circuit driving method according to claim 22, wherein, The pixel driving circuit also includes: A first light-emitting control circuit is connected to the third node, the first electrode of the light-emitting unit, and the first enable signal terminal. The first light-emitting control circuit is used to respond to the signal of the first enable signal terminal to connect the third node and the first electrode of the light-emitting unit. The driving method further includes: During the pre-reset phase, the first light-emitting control circuit is turned on or off.

24. A display panel, wherein, The display panel includes the pixel driving circuit according to any one of claims 1-21.

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