Fully differential ultrasonic measurement transmitting and receiving circuit and control method

Abstract

The invention discloses a fully differential ultrasonic measurement transmitting and receiving circuit and a control method, a strictly symmetrical dual-channel architecture is constructed, a first receiving and transmitting circuit RTX1 and a second receiving and transmitting circuit RTX2 work cooperatively, and a mode control circuit CTRL schedules the timing sequence switching between uplink / downlink transmitting and receiving states in a unified manner; the circuit is characterized in that blocking capacitors C0 and C1 in an alternating current coupling circuit are dynamically multiplexed for transmitting and receiving paths through T-shaped switches TSWp1 / TSWn1 and TSWp2 / TSWn2, and adjustable matching resistors Resmatchp1 / Resmatchn1 and Resmatchp2 / Resmatchn2 are completely multiplexed in two states, so that the equivalent impedance of a transmitting port is highly consistent with that of a receiving port; through cooperation of a fully differential signal transmission path and common-mode voltage Vcm bias, the amplitude of received echo signals is nearly doubled, common-mode interference is effectively counteracted, zero-point errors are remarkably reduced, and the precision, stability and anti-interference capacity of ultrasonic flow measurement are fundamentally improved.

Description

Technical Field

[0001] This invention relates to the field of ultrasonic electronic measurement technology, specifically to a fully differential ultrasonic measurement transmitting and receiving circuit and control method. Background Technology

[0002] Currently, the transmitting and receiving circuits in an ultrasonic flow measurement system mainly include a first transceiver circuit RTX1, a second transceiver circuit RTX2, a control circuit CTRL, a test pulse generation circuit PPG, and an output circuit. To improve the accuracy and stability of the measurement, the quality of the uplink and downlink transmitted and received signals in ultrasonic flow measurement must be guaranteed. Several common methods exist, including:

[0003] 1. Impedance Matching: For example, patent (CN111366204A) adjusts the receiver impedance of the receiving circuit through the receiver control circuit, improving the impedance matching degree between the receiving circuit and the transmitting circuit, reducing system asymmetry errors, and thus improving measurement accuracy and stability. A similar application is found in the practical application of TI's MSP430RF6043 chip, where external resistors R1 and R0 are used to enhance system matching. Figure 1 As shown.

[0004] 2. Echo Signal Filtering and Amplification: In some ultrasonic flow measurement scenarios, the receiving transducer converts the received ultrasonic signal into a sinusoidal voltage signal with a spindle-shaped envelope, the amplitude of which is usually extremely small. To amplify the signal amplitude while meeting system noise requirements, the signal needs to be processed by a low-noise amplifier before being passed to subsequent circuits.

[0005] Impedance matching methods have shortcomings in existing schemes: they fail to achieve complete impedance matching between the transmitting circuit, receiving circuit and transducer, which can easily lead to asymmetry in the measurement system and reduce measurement accuracy.

[0006] While adding an external low-noise amplifier to filter and amplify the echo signal can improve the quality of the received signal, it increases the system cost. Furthermore, based on a single-ended transmit, single-ended receive measurement architecture, the received echo signal is susceptible to common-mode noise interference, especially when the echo signal amplitude is extremely small, which can severely affect measurement accuracy and stability. Summary of the Invention

[0007] The present invention aims to provide a fully differential ultrasonic measurement transmitting and receiving circuit and control method, which can further improve the accuracy and stability of ultrasonic measurement.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a fully differential ultrasonic measurement transmitting and receiving circuit, comprising: a first receiving and transmitting circuit RTX1, a second receiving and transmitting circuit RTX2, a mode control circuit CTRL, a test pulse generation circuit PPG, an AC coupling circuit, and a subsequent signal processing circuit.

[0009] The output of the test pulse generation circuit PPG is connected to the input of the mode control circuit CTRL.

[0010] The output terminal of the mode control circuit CTRL is connected to the control terminals of the first receiving and transmitting circuit RTX1 and the second receiving and transmitting circuit RTX2, respectively.

[0011] The differential ports RTXP1 and RTXN1 of the first receiving and transmitting circuit RTX1 are connected to the first transducer T1;

[0012] The differential ports RTXP2 and RTXN2 of the second receiving and transmitting circuit RTX2 are connected to the second transducer T2;

[0013] The AC coupling circuit includes a first DC blocking capacitor C0 and a second DC blocking capacitor C1. The first end of C0 and the first end of C1 are selectively connected to the differential ports RTXP1, RTXN1 or RTXP2, RTXN2 through the first T-type switches TSWp1 and TSWn1 in the first receiving and transmitting circuit RTX1 and the second T-type switches TSWp2 and TSWn2 in the second receiving and transmitting circuit RTX2, respectively.

[0014] The second terminals of C0 and C1 are connected to the differential input terminals of the subsequent signal processing circuit, and the subsequent signal processing circuit receives a common-mode voltage Vcm to provide DC bias.

[0015] Preferably, the first receiving and transmitting circuit RTX1 includes adjustable matching resistors Res_matchp1 and Res_matchn1. One end of Res_matchp1 is connected to the RTXP1 port, and the other end is grounded through the first NMOS switch SWp1. One end of Res_matchn1 is connected to the RTXN1 port, and the other end is grounded through the first NMOS switch SWn1.

[0016] The second receiver-transmitter circuit RTX2 includes adjustable matching resistors Res_matchp2 and Res_matchn2. One end of Res_matchp2 is connected to the RTXP2 port, and the other end is grounded through the second NMOS switch SWp2. One end of Res_matchn2 is connected to the RTXN2 port, and the other end is grounded through the second NMOS switch SWn2.

[0017] The first receiving and transmitting circuit RTX1 and the second receiving and transmitting circuit RTX2 both further include driving circuits Tx_drvp and Tx_drvn, and the driving circuit is composed of multiple Tx_drv_cells connected in parallel.

[0018] Preferably, the Tx_drv_cell consists of an inverter INV, a NAND gate NAND2, a NOR gate NOR2, an NMOS transistor, a PMOS transistor, and a unit matching resistor Ru_match, and performs the following functions:

[0019] When Pulldown is low and either Psel or En control signal is low, the PMOS gate voltage is high and the NMOS gate voltage is low, and the output Out is in a high-impedance state.

[0020] When Pulldown is low and both Psel and En control signals are high, the output Out is the inverted version of the input In.

[0021] When Pulldown is high, the gate voltages of both the PMOS and NMOS transistors are high. The PMOS transistor is turned off, and the NMOS transistor is turned on. The output Out is pulled down to ground through the matching resistor Ru_match via the NMOS transistor.

[0022] Preferably, the Tx_drvp / Tx_drvn is composed of 16 Tx_drv_cells connected in parallel. The input In, enable En, and pulldown of these 16 parallel Tx_drv_cells are each connected together. The gating control signal Psel is controlled by En_tx_drv and Tx_drv_cfg<3:0>, specifically:

[0023] En_tx_drv is connected to the Psel input control terminal of a Tx_drv_cell;

[0024] Tx_drv_cfg <3> Connect to the Psel input control terminals of eight Tx_drv_cells;

[0025] Tx_drv_cfg <2> Connect to the Psel input control terminals of four Tx_drv_cells;

[0026] Tx_drv_cfg <1> Connect to the Psel input control terminals of two Tx_drv_cells;

[0027] Tx_drv_cfg <0> Connect to a Psel input control terminal of a Tx_drv_cell.

[0028] Preferably, different matching resistors Res_match are selected by configuring Tx_drv_cfg<3:0>, and its expression is:

[0029] Res_match=Ru_match / (1+bin2dec(Tx_drv_cfg<3:0>))

[0030] The function bin2dec(Tx_drv_cfg<3:0>) converts the binary number Tx_drv_cfg<3:0> to a decimal number.

[0031] Preferably, the Ru_match resistance is 2000 Ohm, and the adjustable matching resistor has 16 settings.

[0032] On the other hand, the present invention proposes a control method for a fully differential ultrasonic measurement transmitting and receiving circuit, comprising the following steps:

[0033] (a) Select and configure Tx_drv_cfg1<3:0> and Tx_drv_cfg2<3:0> according to the transducer used to make the impedance matching of the ultrasonic measurement receiving and transmitting circuits;

[0034] (b) During uplink transmission, switches SWp1 and SWn1 in the first receiving and transmitting circuit are opened, and TSWp1 and TSWn1 are closed and turned on. The RTXP1 and RTXN1 ports are connected to the left plates of capacitors C0 and C1, respectively, and the AC coupling circuit is used as part of the load of the transmitting circuit. Switches TSWp2 and TSWn2 in the second receiving and transmitting circuit are opened, and SWp2 and SWn2 are closed and turned on. The RTXP2 and RTXN2 ports are connected to ground. En_tx_drv1 is configured to high level, and Pulldown_tx_drv1, Pulldown_tx_drv2 and En_tx_drv2 are configured to low level. The test pulse signal Txdata1 is transmitted, and the fully differential test pulse signal is generated and transmitted to the T1 transducer through the RTXP1 and RTXN1 ports.

[0035] (c) During uplink reception, En_tx_drv1 in the first receiving and transmitting circuit is configured to low level, switches TSWp1 and TSWn1 are opened, and SWp1 and SWn1 are closed and turned on. The RTXP1 and RTXN1 ports are connected to ground. Pulldown_tx_drv2 in the second receiving and transmitting circuit is configured to high level, switches SWp2 and SWn2 are opened, and TSWp2 and TSWn2 are closed and turned on. The RTXP2 and RTXN2 ports are connected to the left plates of capacitors C0 and C1 respectively. The RTXP2 and RTXN2 ports are connected to ground through adjustable matching resistors Res_matchp2 and Res_matchn2 to ensure impedance matching of the transmitting and receiving paths. After waiting for time T12, the receiving second transducer T2 converts the received ultrasonic signal into a spindle-shaped envelope sinusoidal voltage signal. The received differential electrical signal is transmitted to the input terminal of the signal processing circuit through DC blocking capacitors C0 and C1.

[0036] (d) During downlink transmission, disconnect switches SWp2 and SWn2 in the second receiver-transmitter circuit, and close and conduct switches TSWp2 and TSWn2. Connect the RTXP2 and RTXN2 ports to the left plates of capacitors C0 and C1 respectively, and use the AC coupling circuit as part of the load of the transmitter circuit. Disconnect switches TSWp1 and TSWn1 in the first receiver-transmitter circuit, and close and conduct switches SWp1 and SWn1. Connect the RTXP1 and RTXN1 ports to ground respectively. Configure En_tx_drv2 to high level, and configure Pulldown_tx_drv1, Pulldown_tx_drv2 and En_tx_drv1 to low level. Transmit the test pulse signal Txdata2, and generate a fully differential test pulse signal that is transmitted to the second transducer T2 through the RTXP2 and RTXN2 ports.

[0037] (e) During downlink reception, En_tx_drv2 in the second receiving and transmitting circuit is configured to low level, switches TSWp2 and TSWn2 are opened, and SWp2 and SWn2 are closed and turned on. The RTXP2 and RTXN2 ports are connected to ground. Pulldown_tx_drv1 in the first receiving and transmitting circuit is configured to high level, switches SWp1 and SWn1 are opened, and TSWp1 and TSWn1 are closed and turned on. The RTXP1 and RTXN1 ports are connected to the left plates of capacitors C0 and C1 respectively. The RTXP1 and RTXN1 ports are connected to ground through adjustable matching resistors Res_matchp1 and Res_matchn1 to ensure impedance matching of the transmitting and receiving paths. After waiting for time T21, the receiving first transducer T1 converts the received ultrasonic signal into a spindle-shaped envelope sinusoidal voltage signal. The received differential small signal voltage is transmitted to the input of the signal processing circuit through capacitors C0 and C1.

[0038] (f) The signals received from the uplink and downlink are amplified and quantized into digital signals by the signal processing circuit and stored in RAM1 and RAM2 respectively. The flow rate v is calculated by the digital arithmetic module.

[0039] Preferably, the mode control circuit CTRL generates timing control signals for controlling the first receive-transmit circuit RTX1 and the second receive-transmit circuit RTX2, and the timing control signals sequentially correspond to the uplink transmit control stage, the uplink receive control stage, the downlink transmit control stage, and the downlink receive control stage.

[0040] Preferably, during uplink reception, the control signal Pulldown_tx_drv2 in the second receiving and transmitting circuit is set to a high level to connect ports RTXP2 and RTXN2 to ground or a low level via adjustable matching resistors Res_matchp2 and Res_matchn2, respectively, to ensure impedance matching of the transmitting and receiving paths.

[0041] Preferably, during downlink reception, the control signal Pulldown_tx_drv1 in the first receiving and transmitting circuit is set to a high level to connect ports RTXP1 and RTXN1 to ground or a low level via adjustable matching resistors Res_matchp1 and Res_matchn1, respectively, to ensure impedance matching of the transmitting and receiving paths.

[0042] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0043] This invention constructs a strictly symmetrical dual-channel architecture, where the first receiving and transmitting circuit RTX1 and the second receiving and transmitting circuit RTX2 work together, and the timing switching between uplink / downlink transmitting and receiving states is uniformly scheduled by the mode control circuit CTRL. Crucially, the DC blocking capacitors C0 and C1 in the AC coupling circuit are dynamically reused in the transmitting and receiving paths through T-type switches TSWp1 / TSWn1 and TSWp2 / TSWn2, and the adjustable matching resistors Res_matchp1 / Res_matchn1 and Res_matchp2 / Res_matchn2 are fully reused in both states, thereby ensuring a high degree of consistency in the equivalent impedance of the transmitting and receiving ports. Combined with a fully differential signal transmission path and a common-mode voltage Vcm bias, the amplitude of the received echo signal is nearly doubled, common-mode interference is effectively canceled, and zero-point error is significantly reduced, fundamentally improving the accuracy, stability, and anti-interference capability of ultrasonic flow measurement. Attached Figure Description

[0044] Figure 1 A schematic diagram of the matching scheme for the MSP430RF6043 chip in the existing technology;

[0045] Figure 2This is a circuit diagram of the fully differential ultrasonic measurement architecture of the present invention;

[0046] Figure 3 The circuit diagrams are for the first and second implementation examples of the receiving and transmitting circuits of this invention;

[0047] Figure 4 This is a circuit diagram of an embodiment of the impedance-configurable emitter drive circuit of the present invention;

[0048] Figure 5 This is a simplified diagram of the transmitting circuit and control of the present invention;

[0049] Figure 6 This is a simplified diagram of the uplink receiving circuit and control of the present invention;

[0050] Figure 7 This is a simplified diagram of the downlink transmitting circuit and control of the present invention;

[0051] Figure 8 This is a simplified diagram of the downlink receiving circuit and control of the present invention;

[0052] Figure 9 This is a timing diagram for the transmission and reception control of the fully differential ultrasonic measurement system of this invention. Detailed Implementation

[0053] The following description is intended to disclose the invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art.

[0054] This invention proposes a fully differential ultrasonic measurement transmitting and receiving circuit, comprising: a first receiving and transmitting circuit RTX1, a second receiving and transmitting circuit RTX2, a mode control circuit CTRL, a test pulse generation circuit PPG, an AC coupling circuit, and a subsequent signal processing circuit.

[0055] The output of the test pulse generation circuit PPG is connected to the input of the mode control circuit CTRL; the output of the mode control circuit CTRL is connected to the control terminals of the first receiving and transmitting circuit RTX1 and the second receiving and transmitting circuit RTX2 respectively; the differential ports RTXP1 and RTXN1 of the first receiving and transmitting circuit RTX1 are connected to the first transducer T1; and the differential ports RTXP2 and RTXN2 of the second receiving and transmitting circuit RTX2 are connected to the second transducer T2.

[0056] The AC coupling circuit includes a first DC blocking capacitor C0 and a second DC blocking capacitor C1. The first terminals of C0 and C1 are selectively connected to the differential ports RTXP1, RTXN1 or RTXP2, RTXN2 via the first T-type switches TSWp1 and TSWn1 in the first receiving and transmitting circuit RTX1 and the second T-type switches TSWp2 and TSWn2 in the second receiving and transmitting circuit RTX2, respectively. The second terminals of C0 and C1 are connected to the differential input terminals of the subsequent signal processing circuit, and the subsequent signal processing circuit receives a common-mode voltage Vcm to provide DC bias.

[0057] Furthermore, the first receiver-transmitter circuit RTX1 includes adjustable matching resistors Res_matchp1 and Res_matchn1. One end of Res_matchp1 is connected to the RTXP1 port, and the other end is grounded through the first NMOS switch SWp1. One end of Res_matchn1 is connected to the RTXN1 port, and the other end is grounded through the first NMOS switch SWn1.

[0058] The second receiver-transmitter circuit RTX2 includes adjustable matching resistors Res_matchp2 and Res_matchn2. One end of Res_matchp2 is connected to the RTXP2 port, and the other end is grounded through the second NMOS switch SWp2. One end of Res_matchn2 is connected to the RTXN2 port, and the other end is grounded through the second NMOS switch SWn2.

[0059] The first receiving and transmitting circuit RTX1 and the second receiving and transmitting circuit RTX2 both further include driving circuits Tx_drvp and Tx_drvn, and the driving circuit is composed of multiple Tx_drv_cells connected in parallel.

[0060] Specifically, the Tx_drv_cell consists of an inverter INV, a NAND gate NAND2, a NOR gate NOR2, an NMOS transistor, a PMOS transistor, and a unit matching resistor Ru_match, and performs the following functions:

[0061] When Pulldown is low and either Psel or En control signal is low, the PMOS gate voltage is high and the NMOS gate voltage is low, and the output Out is in a high-impedance state.

[0062] When Pulldown is low and both Psel and En control signals are high, the output Out is the inverted version of the input In.

[0063] When Pulldown is high, the gate voltages of both the PMOS and NMOS transistors are high. The PMOS transistor is turned off, and the NMOS transistor is turned on. The output Out is pulled down to ground through the matching resistor Ru_match via the NMOS transistor.

[0064] Among them, Tx_drvp / Tx_drvn is composed of 16 Tx_drv_cells connected in parallel. The input In, enable En, and pulldown enable of these 16 parallel Tx_drv_cells are each connected together. The gating control signal Psel is controlled by En_tx_drv and Tx_drv_cfg<3:0>, specifically:

[0065] En_tx_drv is connected to the Psel input control terminal of a Tx_drv_cell;

[0066] Tx_drv_cfg <3> Connect to the Psel input control terminals of eight Tx_drv_cells;

[0067] Tx_drv_cfg <2> Connect to the Psel input control terminals of four Tx_drv_cells;

[0068] Tx_drv_cfg <1> Connect to the Psel input control terminals of two Tx_drv_cells;

[0069] Tx_drv_cfg <0> Connect to a Psel input control terminal of a Tx_drv_cell.

[0070] On the other hand, the present invention proposes a control method for a fully differential ultrasonic measurement transmitting and receiving circuit, comprising the following steps:

[0071] (a) Select and configure Tx_drv_cfg1<3:0> and Tx_drv_cfg2<3:0> according to the transducer used to make the impedance matching of the ultrasonic measurement receiving and transmitting circuits;

[0072] (b) During uplink transmission, switches SWp1 and SWn1 in the first receiving and transmitting circuit are opened, and TSWp1 and TSWn1 are closed and turned on. The RTXP1 and RTXN1 ports are connected to the left plates of capacitors C0 and C1, respectively, and the AC coupling circuit is used as part of the load of the transmitting circuit. Switches TSWp2 and TSWn2 in the second receiving and transmitting circuit are opened, and SWp2 and SWn2 are closed and turned on. The RTXP2 and RTXN2 ports are connected to ground. En_tx_drv1 is configured to high level, and Pulldown_tx_drv1, Pulldown_tx_drv2 and En_tx_drv2 are configured to low level. The test pulse signal Txdata1 is transmitted, and the fully differential test pulse signal is generated and transmitted to the T1 transducer through the RTXP1 and RTXN1 ports.

[0073] (c) During uplink reception, En_tx_drv1 in the first receiving and transmitting circuit is configured to low level, switches TSWp1 and TSWn1 are opened, and SWp1 and SWn1 are closed and turned on. The RTXP1 and RTXN1 ports are connected to ground. Pulldown_tx_drv2 in the second receiving and transmitting circuit is configured to high level, switches SWp2 and SWn2 are opened, and TSWp2 and TSWn2 are closed and turned on. The RTXP2 and RTXN2 ports are connected to the left plates of capacitors C0 and C1 respectively. The RTXP2 and RTXN2 ports are connected to ground through adjustable matching resistors Res_matchp2 and Res_matchn2 to ensure impedance matching of the transmitting and receiving paths. After waiting for time T12, the receiving second transducer T2 converts the received ultrasonic signal into a spindle-shaped envelope sinusoidal voltage signal. The received differential electrical signal is transmitted to the input terminal of the signal processing circuit through DC blocking capacitors C0 and C1.

[0074] (d) During downlink transmission, disconnect switches SWp2 and SWn2 in the second receiver-transmitter circuit, and close and conduct switches TSWp2 and TSWn2. Connect the RTXP2 and RTXN2 ports to the left plates of capacitors C0 and C1 respectively, and use the AC coupling circuit as part of the load of the transmitter circuit. Disconnect switches TSWp1 and TSWn1 in the first receiver-transmitter circuit, and close and conduct switches SWp1 and SWn1. Connect the RTXP1 and RTXN1 ports to ground respectively. Configure En_tx_drv2 to high level, and configure Pulldown_tx_drv1, Pulldown_tx_drv2 and En_tx_drv1 to low level. Transmit the test pulse signal Txdata2, and generate a fully differential test pulse signal that is transmitted to the second transducer T2 through the RTXP2 and RTXN2 ports.

[0075] (e) During downlink reception, En_tx_drv2 in the second receiving and transmitting circuit is configured to low level, switches TSWp2 and TSWn2 are opened, and SWp2 and SWn2 are closed and turned on. The RTXP2 and RTXN2 ports are connected to ground. Pulldown_tx_drv1 in the first receiving and transmitting circuit is configured to high level, switches SWp1 and SWn1 are opened, and TSWp1 and TSWn1 are closed and turned on. The RTXP1 and RTXN1 ports are connected to the left plates of capacitors C0 and C1 respectively. The RTXP1 and RTXN1 ports are connected to ground through adjustable matching resistors Res_matchp1 and Res_matchn1 to ensure impedance matching of the transmitting and receiving paths. After waiting for time T21, the receiving first transducer T1 converts the received ultrasonic signal into a spindle-shaped envelope sinusoidal voltage signal. The received differential small signal voltage is transmitted to the input of the signal processing circuit through capacitors C0 and C1.

[0076] (f) The signals received from the uplink and downlink are amplified and quantized into digital signals by the signal processing circuit and stored in RAM1 and RAM2 respectively. The flow velocity v is calculated by the digital arithmetic module according to the relevant algorithm for flow measurement.

[0077] The aforementioned mode control circuit CTRL generates timing control signals for controlling the first receive-transmit circuit RTX1 and the second receive-transmit circuit RTX2. These timing control signals sequentially correspond to the uplink transmit control stage, the uplink receive control stage, the downlink transmit control stage, and the downlink receive control stage.

[0078] Furthermore, during uplink reception, the control signal Pulldown_tx_drv2 in the second receiving and transmitting circuit is set to a high level to connect ports RTXP2 and RTXN2 to ground or a low level via adjustable matching resistors Res_matchp2 and Res_matchn2, respectively, to ensure impedance matching of the transmitting and receiving paths.

[0079] Furthermore, during downlink reception, the control signal Pulldown_tx_drv1 in the first receiving and transmitting circuit is set to a high level to connect ports RTXP1 and RTXN1 to ground or a low level via adjustable matching resistors Res_matchp1 and Res_matchn1, respectively, to ensure impedance matching of the transmitting and receiving paths.

[0080] The following will provide further explanation with reference to the accompanying drawings:

[0081] The fully differential ultrasonic measurement and impedance matching circuit architecture proposed in this method is as follows: Figure 2As shown, the main components include a first receiving and transmitting circuit RTX1, a second receiving and transmitting circuit RTX2, a mode control circuit CTRL, a test pulse generation circuit PPG, an AC coupling circuit, and a subsequent signal processing circuit. The test pulse generation circuit outputs test pulses as inputs to the mode control circuit. RTX1 and RTX2 are controlled by the CTRL circuit to achieve fully differential test pulse transmission and fully differential echo signal reception. These differential echo signals are transmitted to the subsequent signal processing circuit via the AC coupling circuit (ACCouple), where Vcm provides a suitable DC bias voltage for the subsequent circuit.

[0082] Differential receiver / transmitter circuits (RTX1 / RTX2) such as Figure 3 As shown, it mainly includes a pair of NMOS switches SWp and SWn, a pair of "T" type switches TSWp and TSWn, and differential test output pulse signal driving circuits Tx_drvp and Tx_drvn.

[0083] In this implementation, the driving unit Tx_drv_cell consists of an inverter INV, a NAND gate NAND2, a NOR gate NOR2, an NMOS transistor, a PMOS transistor, and a unit matching resistor Ru_match, as shown in Figure 4. It implements the following functions:

[0084] (1) When Pulldown is low and one of the Psel and En control signals is low, the PMOS gate voltage is high and the NMOS gate voltage is low, and the output Out is in a high-impedance state.

[0085] (2) When Pulldown is low and both Psel and En control signals are high, the output Out is the inverted input In.

[0086] (3) When Pulldown is high, the gate voltages of both PMOS and NMOS transistors are high. PMOS transistor is turned off and NMOS transistor is turned on. Output Out is pulled down to ground (or low level) through the matching resistor Ru_match via NMOS.

[0087] In this implementation, Tx_drvp / Tx_drvn consists of 16 Tx_drv_cells connected in parallel. The inputs In, enable En, and pulldown of these 16 parallel Tx_drv_cells are each connected together. Their gating control signal Psel is controlled by En_tx_drv and Tx_drv_cfg<3:0>, as detailed below:

[0088] En_tx_drv is connected to the Psel input control terminal of a Tx_drv_cell;

[0089] Tx_drv_cfg <3> Connected to the Psel input control terminals of eight Tx_drv_cells, in Figure 4 The Chinese character set is represented as <*8>Tx_drv_cfg <3> ;Tx_drv_cfg <2> Connected to the Psel input control terminals of four Tx_drv_cells, in Figure 4 The Chinese character set is represented as <*4>Tx_drv_cfg <2> ;Tx_drv_cfg <1> Connected to the Psel input control terminals of two Tx_drv_cells, in Figure 4 The Chinese character set is represented as <*2>Tx_drv_cfg <1> ;Tx_drv_cfg <0> Connected to a Psel input control terminal of a Tx_drv_cell, in Figure 4 The Chinese representation is Tx_drv_cfg <0> ;

[0090] For ease of representation, the decimal equivalent of the binary number Tx_drv_cfg<3:0> is represented as bin2dec(Tx_drv_cfg<3:0>). By configuring Tx_drv_cfg<3:0>, different matching resistors Res_match can be selected, and its expression is shown in formula (1) below.

[0091] Res_match=Ru_match / (1+bin2dec(Tx_drv_cfg<3:0>))(1)

[0092] In this implementation example, the Ru_match resistance is 2000 Ohm, and the adjustable matching resistor is set to 16 levels, as follows:

[0093] 2000 / 1333 / 1000 / 800 / 666 / 571 / 500 / 444 / 400 / 363 / 333 / 307 / 285 / 266 / 250Ohm.

[0094] Since the underlying circuitry of the first receiver / transmitter circuit RTX1 and the second receiver / transmitter circuit RTX2 is the same, such as Figure 3 As shown. SWp / SWn and TSWp / TSWn are also controlled by the mode control circuit. To facilitate the description of the entire control process, a "1" is added after the port name in the RTX circuit to represent a port related to the RTX1 circuit, such as En_tx_drvp1; a "2" is added after the port name in the RTX circuit to represent a port related to the RTX2 circuit, such as En_tx_drv2. First, Tx_drv_cfg1<3:0> and Tx_drv_cfg2<3:0> are configured according to the transducer used to achieve impedance matching of the ultrasonic measurement receiving and transmitting circuits. The fully differential ultrasonic measurement control process is as follows:

[0095] (1) During uplink transmission, firstly, disconnect switches SWp1 and SWn1 in the first receiving and transmitting circuit, and close and conduct switches TSWp1 and TSWn1. Connect the RTXP1 and RTXN1 ports to the left plates of capacitors C0 and C1 respectively, that is, use the AC coupling circuit as part of the load of the transmitting circuit. Then, disconnect switches TSWp2 and TSWn2 in the second receiving and transmitting circuit, and close and conduct switches SWp2 and SWn2. Connect the RTXP2 and RTXN2 ports to ground respectively. Then, En_tx_drv1 is configured to high level, and Pulldown_tx_drv1, Pulldown_tx_drv2, and En_tx_drv2 are configured to low level. The transmitted test pulse signal Txdata1 is sent to Tx_drvp1 and Tx_drvn1 respectively via inverter INV and transmission gate TG. Then, a fully differential test pulse signal is generated and transmitted to the positive and negative ports of transducer T1 via RTXP1 and RTXN1 ports. Transducer T1 converts the electrical signal into an ultrasonic signal and then transmits it. (Simplified version follows) Figure 5 As shown.

[0096] (2) After transmitting the test pulse signal, configure En_tx_drv1 in the first receiving-transmitting circuit to low level, open switches TSWp1 and TSWn1, and close SWp1 and SWn1 to conduct, connecting the RTXP1 and RTXN1 ports to ground or low level; configure Pulldown_tx_drv2 in the second receiving-transmitting circuit to high level, open switches SWp2 and SWn2, and close TSWp2 and TSWn2 to conduct, connecting the RTXP2 and RTXN2 ports to the left plates of capacitors C0 and C1 respectively, which constitutes the load circuit. Here, setting the control signal Pulldown_tx_drv2 in the second receiving-transmitting circuit to high level is to connect the RTXP2 and RTXN2 ports to ground or low level through adjustable matching resistors Res_matchp2 and Res_matchn2 respectively, ensuring impedance matching of the transmitting and receiving paths.

[0097] (3) After a waiting time T12, the receiving transducer T2 begins to convert the received ultrasonic signal into a spindle-shaped envelope sinusoidal voltage signal. This received differential signal is then transmitted to the input of the signal processing circuit via DC blocking capacitors C0 and C1. The signal is then amplified and quantized into a digital signal and stored in RAM1. Finally, the analog link is shut down. (Simplified version follows) Figure 6 As shown. The control signals for uplink transmit and receive RTX1 and RTX2 are generated by the mode control module CTRL. Detailed control timing is as follows: Figure 9 As shown.

[0098] (4) During downlink transmission, first disconnect switches SWp2 and SWn2 in the second receiver-transmitter circuit, and close and conduct switches TSWp2 and TSWn2. Connect the RTXP2 and RTXN2 ports to the left plates of capacitors C0 and C1 respectively, that is, use the AC coupling circuit as part of the load of the transmitter circuit. Then disconnect switches TSWp1 and TSWn1 in the first receiver-transmitter circuit, and close and conduct switches SWp1 and SWn1. Connect the RTXP1 and RTXN1 ports to ground respectively. Then, En_tx_drv2 is configured to high level, and Pulldown_tx_drv1, Pulldown_tx_drv2, and En_tx_drv1 are configured to low level. The transmitted test pulse signal Txdata2 is sent to Tx_drvp2 and Tx_drvn2 respectively via inverter INV and transmission gate TG. Then, a fully differential test pulse signal is generated and transmitted to the positive and negative ports of transducer T2 via RTXP2 and RTXN2 ports. Transducer T2 converts the electrical signal into an ultrasonic signal and then transmits it. (Simplified...) Figure 7 As shown.

[0099] (5) After transmitting the test pulse signal, configure En_tx_drv2 in the second receiving and transmitting circuit to low level, open switches TSWp2 and TSWn2, and close SWp2 and SWn2 to conduct, connecting the RTXP2 and RTXN2 ports to ground or low level; configure Pulldown_tx_drv1 in the first receiving and transmitting circuit to high level, open switches SWp1 and SWn1, and close TSWp1 and TSWn1 to conduct, connecting the RTXP1 and RTXN1 ports to the left plates of capacitors C0 and C1 respectively, which is the load circuit. At the same time, set the control signal Pulldown_tx_drv1 in the first receiving and transmitting circuit to high level to connect the RTXP1 and RTXN1 ports to ground or low level through the adjustable matching resistors Res_matchp1 and Res_matchn1 respectively, ensuring impedance matching of the transmitting and receiving paths.

[0100] (6) After a waiting time T21, the receiving transducer T1 begins to convert the received ultrasonic signal into a spindle-shaped envelope sinusoidal voltage signal. This received differential small-signal voltage is then transmitted to the input of the signal processing circuit via capacitors C0 and C1. The signal is then amplified and quantized into a digital signal and stored in RAM2. Finally, the analog link is shut down. (Simplified version follows) Figure 8 As shown. The control signals for downlink transmit and receive RTX1 and RTX2 are generated by the mode control module CTRL. Detailed control timing is as follows: Figure 9 As shown.

[0101] (7) Finally, the digital processing stage begins. The digital processing module uses the data from RAM1 and RAM2 to calculate the flow rate according to the relevant algorithms for flow measurement.

[0102] In summary, by constructing a strictly symmetrical dual-channel architecture, the first receive-transmit circuit RTX1 and the second receive-transmit circuit RTX2 work together, and the timing switching between uplink / downlink transmit and receive states is uniformly scheduled by the mode control circuit CTRL.

[0103] In the AC coupling circuit, the DC blocking capacitors C0 and C1 are dynamically reused in the transmission and reception paths via T-type switches TSWp1 / TSWn1 and TSWp2 / TSWn2. Furthermore, the adjustable matching resistors Res_matchp1 / Res_matchn1 and Res_matchp2 / Res_matchn2 are fully reused in both states, ensuring a high degree of consistency in the equivalent impedance between the transmission and reception ports. Combined with the fully differential signal transmission path and common-mode voltage Vcm bias, the amplitude of the received echo signal is nearly doubled, common-mode interference is effectively canceled, and zero-point error is significantly reduced, fundamentally improving the accuracy, stability, and anti-interference capability of ultrasonic flow measurement.

[0104] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention. The scope of protection claimed by the appended claims and their equivalents is defined.

Claims

1. A fully differential ultrasonic measurement transmitting and receiving circuit, characterized in that, include: The circuit consists of a first receiving and transmitting circuit RTX1, a second receiving and transmitting circuit RTX2, a mode control circuit CTRL, a test pulse generation circuit PPG, an AC coupling circuit, and a subsequent signal processing circuit. The output of the test pulse generation circuit PPG is connected to the input of the mode control circuit CTRL. The output terminal of the mode control circuit CTRL is connected to the control terminals of the first receiving and transmitting circuit RTX1 and the second receiving and transmitting circuit RTX2, respectively. The differential ports RTXP1 and RTXN1 of the first receiving and transmitting circuit RTX1 are connected to the first transducer T1; The differential ports RTXP2 and RTXN2 of the second receiving and transmitting circuit RTX2 are connected to the second transducer T2; The AC coupling circuit includes a first DC blocking capacitor C0 and a second DC blocking capacitor C1. The first end of C0 and the first end of C1 are selectively connected to the differential ports RTXP1, RTXN1 or RTXP2, RTXN2 through the first T-type switches TSWp1 and TSWn1 in the first receiving and transmitting circuit RTX1 and the second T-type switches TSWp2 and TSWn2 in the second receiving and transmitting circuit RTX2, respectively. The second terminals of C0 and C1 are connected to the differential input terminals of the subsequent signal processing circuit, and the subsequent signal processing circuit receives a common-mode voltage Vcm to provide DC bias.

2. The fully differential ultrasonic measurement transmitting and receiving circuit according to claim 1, characterized in that, The first receiving and transmitting circuit RTX1 includes adjustable matching resistors Res_matchp1 and Res_matchn1. One end of Res_matchp1 is connected to the RTXP1 port, and the other end is grounded through the first NMOS switch SWp1. One end of Res_matchn1 is connected to the RTXN1 port, and the other end is grounded through the first NMOS switch SWn1. The second receiver-transmitter circuit RTX2 includes adjustable matching resistors Res_matchp2 and Res_matchn2. One end of Res_matchp2 is connected to the RTXP2 port, and the other end is grounded through the second NMOS switch SWp2. One end of Res_matchn2 is connected to the RTXN2 port, and the other end is grounded through the second NMOS switch SWn2. The first receiving and transmitting circuit RTX1 and the second receiving and transmitting circuit RTX2 both further include driving circuits Tx_drvp and Tx_drvn, and the driving circuit is composed of multiple Tx_drv_cells connected in parallel.

3. The fully differential ultrasonic measurement transmitting and receiving circuit according to claim 2, characterized in that, The Tx_drv_cell consists of an inverter INV, a NAND gate NAND2, a NOR gate NOR2, an NMOS transistor, a PMOS transistor, and a unit matching resistor Ru_match, and performs the following functions: When Pulldown is low and either Psel or En control signal is low, the PMOS gate voltage is high and the NMOS gate voltage is low, and the output Out is in a high-impedance state. When Pulldown is low and both Psel and En control signals are high, the output Out is the inverted version of the input In. When Pulldown is high, the gate voltages of both the PMOS and NMOS transistors are high. The PMOS transistor is turned off, and the NMOS transistor is turned on. The output Out is pulled down to ground through the matching resistor Ru_match via the NMOS transistor.

4. The fully differential ultrasonic measurement transmitting and receiving circuit according to claim 3, characterized in that, The Tx_drvp / Tx_drvn is composed of 16 Tx_drv_cells connected in parallel. The inputs In, enable En, and pulldown of these 16 parallel Tx_drv_cells are each connected together. The gating control signal Psel is controlled by En_tx_drv and Tx_drv_cfg<3:0>, specifically: En_tx_drv is connected to the Psel input control terminal of a Tx_drv_cell; Tx_drv_cfg <3> Connect to the Psel input control terminals of eight Tx_drv_cells; Tx_drv_cfg <2> Connect to the Psel input control terminals of four Tx_drv_cells; Tx_drv_cfg <1> Connect to the Psel input control terminals of two Tx_drv_cells; Tx_drv_cfg <0> Connect to a Psel input control terminal of a Tx_drv_cell.

5. The fully differential ultrasonic measurement transmitting and receiving circuit according to claim 4, characterized in that, Different matching resistors Res_match can be selected by configuring Tx_drv_cfg<3:0>, and its expression is: Res_match=Ru_match / (1+bin2dec(Tx_drv_cfg<3:0>)) The function bin2dec(Tx_drv_cfg<3:0>) converts the binary number Tx_drv_cfg<3:0> to a decimal number.

6. The fully differential ultrasonic measurement transmitting and receiving circuit according to claim 5, characterized in that, The Ru_match resistance is 2000 Ohm, and the adjustable matching resistor has 16 settings.

7. A control method for a fully differential ultrasonic measurement transmitting and receiving circuit according to any one of claims 1-6, characterized in that, Includes the following steps: (a) Select and configure Tx_drv_cfg1<3:0> and Tx_drv_cfg2<3:0> according to the transducer used to make the impedance matching of the ultrasonic measurement receiving and transmitting circuits; (b) During uplink transmission, switches SWp1 and SWn1 in the first receiving and transmitting circuit are opened, and TSWp1 and TSWn1 are closed and turned on. The RTXP1 and RTXN1 ports are connected to the left plates of capacitors C0 and C1, respectively, and the AC coupling circuit is used as part of the load of the transmitting circuit. Switches TSWp2 and TSWn2 in the second receiving and transmitting circuit are opened, and SWp2 and SWn2 are closed and turned on. The RTXP2 and RTXN2 ports are connected to ground. En_tx_drv1 is configured to high level, and Pulldown_tx_drv1, Pulldown_tx_drv2 and En_tx_drv2 are configured to low level. The test pulse signal Txdata1 is transmitted, and the fully differential test pulse signal is generated and transmitted to the T1 transducer through the RTXP1 and RTXN1 ports. (c) During uplink reception, En_tx_drv1 in the first receiving and transmitting circuit is configured to low level, switches TSWp1 and TSWn1 are opened, and SWp1 and SWn1 are closed and turned on. The RTXP1 and RTXN1 ports are connected to ground. Pulldown_tx_drv2 in the second receiving and transmitting circuit is configured to high level, switches SWp2 and SWn2 are opened, and TSWp2 and TSWn2 are closed and turned on. The RTXP2 and RTXN2 ports are connected to the left plates of capacitors C0 and C1 respectively. The RTXP2 and RTXN2 ports are connected to ground through adjustable matching resistors Res_matchp2 and Res_matchn2 to ensure impedance matching of the transmitting and receiving paths. After waiting for time T12, the receiving second transducer T2 converts the received ultrasonic signal into a spindle-shaped envelope sinusoidal voltage signal. The received differential electrical signal is transmitted to the input terminal of the signal processing circuit through DC blocking capacitors C0 and C1. (d) During downlink transmission, disconnect switches SWp2 and SWn2 in the second receiver-transmitter circuit, and close and conduct switches TSWp2 and TSWn2. Connect the RTXP2 and RTXN2 ports to the left plates of capacitors C0 and C1 respectively, and use the AC coupling circuit as part of the load of the transmitter circuit. Disconnect switches TSWp1 and TSWn1 in the first receiver-transmitter circuit, and close and conduct switches SWp1 and SWn1. Connect the RTXP1 and RTXN1 ports to ground respectively. Configure En_tx_drv2 to high level, and configure Pulldown_tx_drv1, Pulldown_tx_drv2 and En_tx_drv1 to low level. Transmit the test pulse signal Txdata2, and generate a fully differential test pulse signal that is transmitted to the second transducer T2 through the RTXP2 and RTXN2 ports. (e) During downlink reception, En_tx_drv2 in the second receiving and transmitting circuit is configured to low level, switches TSWp2 and TSWn2 are opened, and SWp2 and SWn2 are closed and turned on. The RTXP2 and RTXN2 ports are connected to ground. Pulldown_tx_drv1 in the first receiving and transmitting circuit is configured to high level, switches SWp1 and SWn1 are opened, and TSWp1 and TSWn1 are closed and turned on. The RTXP1 and RTXN1 ports are connected to the left plates of capacitors C0 and C1 respectively. The RTXP1 and RTXN1 ports are connected to ground through adjustable matching resistors Res_matchp1 and Res_matchn1 to ensure impedance matching of the transmitting and receiving paths. After waiting for time T21, the receiving first transducer T1 converts the received ultrasonic signal into a spindle-shaped envelope sinusoidal voltage signal. The received differential small signal voltage is transmitted to the input of the signal processing circuit through capacitors C0 and C1. (f) The signals received from the uplink and downlink are amplified and quantized into digital signals by the signal processing circuit and stored in RAM1 and RAM2 respectively. The flow rate is calculated by the digital arithmetic module.

8. The control method according to claim 7, characterized in that, The mode control circuit CTRL generates timing control signals for controlling the first receive-transmit circuit RTX1 and the second receive-transmit circuit RTX2. The timing control signals correspond sequentially to the uplink transmit control stage, the uplink receive control stage, the downlink transmit control stage, and the downlink receive control stage.

9. The control method according to claim 8, characterized in that, During uplink reception, the control signal Pulldown_tx_drv2 in the second receiver-transmitter circuit is set to a high level to connect ports RTXP2 and RTXN2 to ground or a low level via adjustable matching resistors Res_matchp2 and Res_matchn2, respectively, to ensure impedance matching of the transmit and receive paths.

10. The control method according to claim 8, characterized in that, During downlink reception, the control signal Pulldown_tx_drv1 in the first receiving and transmitting circuit is set to a high level, which is used to connect ports RTXP1 and RTXN1 to ground or a low level through adjustable matching resistors Res_matchp1 and Res_matchn1 respectively, to ensure impedance matching of the transmitting and receiving paths.

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