Virtual debugging system and method
By simulating the hardware behavior of the main control board in a nuclear power plant through a virtual debugging system, the problem of low efficiency in traditional debugging is solved, enabling efficient software development and testing and reducing dependence on physical hardware.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHINA TECHENERGY
- Filing Date
- 2026-01-30
- Publication Date
- 2026-04-28
AI Technical Summary
Traditional nuclear power plant digital control systems have low debugging efficiency for main control boards, rely on physical hardware resources, and require a long time to set up the debugging environment.
A virtual debugging system is provided, including a board simulator, a run control and scheduling module, a clock synchronization module, a debugging module, and a fault injection module. It simulates hardware behavior through software, generates simulation status information, and supports virtual debugging and fault injection.
It significantly improves the debugging efficiency of the main control board, shortens the development cycle, reduces the dependence on physical hardware, realizes the parallel development mode, and improves the development and testing efficiency.
Smart Images
Figure CN121934418A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a virtual debugging system and method. Background Technology
[0002] The digital control system of a nuclear power plant is a core infrastructure that ensures the safe and stable operation of nuclear power units. Its main control board undertakes key tasks such as system calculation, logic control, data acquisition, communication interaction and log management.
[0003] Traditional nuclear power plant digital control systems typically consist of a specific type of embedded central processing unit (CPU), such as the PowerPC MPC5200 series, along with supporting memory, buses, and peripheral interfaces, running a dedicated real-time operating system. However, this type of control board, which relies heavily on physical hardware, requires substantial physical hardware resources, and the setup of the debugging environment is time-consuming and inefficient.
[0004] Improving the debugging efficiency of the main control board is a technical problem that urgently needs to be solved. Summary of the Invention
[0005] To address the aforementioned issues, this application provides a virtual debugging system and method, aiming to improve the debugging efficiency of the main control board.
[0006] The embodiments of this application disclose the following technical solutions: The first aspect of this application provides a virtual debugging system, which includes: a board simulator, a run control and scheduling module, a clock synchronization module, a debugging module, and a fault injection module; The board simulator is used to simulate the operating behavior of various hardware components in the physical board under test based on the simulation control instructions of the operation control scheduling module, and generate simulation status information; the various hardware components include at least a processor, a storage module, an interface module, and a logic control module. The debugging module is used to receive external debugging instructions and convert the external debugging instructions into debugging requests and send them to the operation control and scheduling module to perform virtual debugging on the board simulator based on the received simulation status information; The operation control and scheduling module is used to respond to the debugging request, send simulation control instructions to the board simulator, obtain the simulation status information of the board simulator and send it to the debugging module, and coordinate the data interaction and execution timing between the board simulator, the clock synchronization module and the fault injection module. The clock synchronization module is used to provide a synchronization clock signal for each module in the virtual debugging system; The fault injection module is used to inject preset faults into the board simulator based on the simulation control commands of the operation control and scheduling module.
[0007] Optionally, the board simulator includes: a processor emulation unit; The processor emulation unit is used to simulate the instruction set behavior of the MPC5200B and to simulate the double data rate controller, peripheral control registers, and bus access logic; the instruction set behavior includes interrupt handling and exception response mechanisms.
[0008] Optionally, the board simulator includes: a storage module simulation unit; The storage module simulation unit is used to simulate various types of memory, including 128M DDR memory, 16M×16bit Localbus Flash, 4M SPI Flash and 2kB EEPROM.
[0009] Optionally, the board simulator includes: an interface module simulation unit; The interface module simulation unit is used to simulate various peripheral interfaces, including a universal asynchronous transceiver serial port, a serial peripheral interface bus, and an Ethernet controller.
[0010] Optionally, the board simulator includes: a logic control module simulation unit; The logic control module simulation unit is used to simulate various control behaviors through virtual programmable logic; the various control behaviors include bus interaction control, peripheral drive control and backplane bus interface control.
[0011] Optionally, the system further includes: a monitoring module; The monitoring module is used to monitor and display the operating status of the board; the operating status includes resource utilization, bus load and communication status.
[0012] Optionally, the system further includes: an extended interface simulation module; The extended interface simulation module is used to simulate general-purpose interfaces and backplane buses; the data exchange of the backplane bus is simulated based on a shared memory and dual-port random access memory mechanism; the general-purpose interface includes general-purpose input / output pins and an inter-integrated circuit bus.
[0013] A second aspect of this application provides a virtual debugging method, which is applied to the virtual debugging system described in the first aspect, the method comprising: The board simulator simulates the operating behavior of various hardware components in the physical board under test based on the simulation control instructions of the operation control scheduling module, and generates simulation status information; the various hardware components include at least a processor, a storage module, an interface module, and a logic control module. The debugging module receives external debugging instructions and converts the external debugging instructions into debugging requests, which are then sent to the operation control and scheduling module to perform virtual debugging on the board simulator based on the received simulation status information. In response to the debugging request, the operation control and scheduling module sends simulation control instructions to the board simulator, obtains the simulation status information of the board simulator and sends it to the debugging module, and coordinates the data interaction and execution timing between the board simulator, the clock synchronization module and the fault injection module. The clock synchronization module provides a synchronization clock signal for each module in the virtual debugging system; The fault injection module injects a preset fault into the board simulator based on the simulation control command of the operation control and scheduling module.
[0014] Optionally, the board simulator, based on the simulation control instructions of the operation control scheduling module, simulates the operating behavior of various hardware components in the physical board under test, and generates simulation status information, including: The instruction set behavior of the MPC5200B is simulated, as well as the DDR controller, peripheral control registers, and bus access logic. The instruction set behavior includes interrupt handling and exception response mechanisms.
[0015] Optionally, the board simulator, based on the simulation control instructions of the operation control scheduling module, simulates the operating behavior of various hardware components in the physical board under test, and generates simulation status information, including: Simulates multiple types of memory; the multiple types of memory include 128M DDR memory, 16M×16bit LocalbusFlash, 4M SPI Flash and 2kB EEPROM.
[0016] Compared with the prior art, this application has the following beneficial effects: The virtual debugging system provided in this application includes: a board simulator, a runtime control and scheduling module, a clock synchronization module, a debugging module, and a fault injection module. The board simulator is used to simulate the operating behavior of various hardware components in a physical board under test based on simulation control commands from the runtime control and scheduling module, generating simulation status information. The various hardware components include at least a processor, a storage module, an interface module, and a logic control module. The debugging module receives external debugging commands and converts them into debugging requests, sending them to the runtime control and scheduling module for virtual debugging of the board simulator based on the received simulation status information. The runtime control and scheduling module, in response to the debugging request, sends simulation control commands to the board simulator, obtains the simulation status information of the board simulator and sends it to the debugging module, and coordinates the data interaction and execution timing between the board simulator, the clock synchronization module, and the fault injection module. The clock synchronization module provides a synchronous clock signal for each module in the virtual debugging system. The fault injection module injects a preset fault into the board simulator based on the simulation control commands from the runtime control and scheduling module.
[0017] The board simulator reconstructs various hardware components at the software level, including processors, storage modules, interface modules, and logic control modules. It implements the behavioral models of these hardware components and their interconnection and interaction logic on the bus, ensuring a high degree of reproduction of the underlying hardware behavior. Based on this, a system operating framework with scheduling, debugging, and integration testing capabilities is constructed. The runtime control scheduling module and clock synchronization module ensure simulation timing consistency, while the debugging module and fault injection module provide deep debugging and reliability testing capabilities. This provides embedded software with an operating environment highly consistent with real hardware, supporting the entire process of firmware loading, protocol debugging, and functional verification, significantly improving development and testing efficiency and reducing dependence on physical hardware. Compared to existing technologies where main control boards rely on physical hardware and require actual hardware resources, and where setting up the debugging environment is time-consuming and inefficient, the virtual debugging system provided in this application allows software development and integration testing to begin without waiting for hardware. This transforms the traditional serial development mode into a parallel mode, greatly shortening the development cycle and improving the debugging efficiency of the main control board. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of the structure of a virtual debugging system provided in an embodiment of this application; Figure 2 This is a flowchart of a virtual debugging method provided in an embodiment of this application. Detailed Implementation
[0020] As described earlier, the main control board of the current digital control system of nuclear power plants typically consists of a specific type of embedded CPU, such as the PowerPC MPC5200 series, along with supporting memory, buses, and peripheral interfaces, and runs a dedicated real-time operating system. However, this type of main control board, which mainly relies on physical hardware, requires actual hardware resources, and the setup of the debugging environment is time-consuming and inefficient.
[0021] In view of the above problems, this application proposes a virtual debugging system and method. The system includes: a board simulator, a runtime control and scheduling module, a clock synchronization module, a debugging module, and a fault injection module. The board simulator is used to simulate the operating behavior of various hardware components in a physical board under test based on simulation control instructions from the runtime control and scheduling module, and generate simulation status information. The various hardware components include at least a processor, a storage module, an interface module, and a logic control module. The debugging module is used to receive external debugging instructions and convert them into debugging requests, which are then sent to the runtime control and scheduling module to perform virtual debugging on the board simulator based on the received simulation status information. The runtime control and scheduling module is used to respond to the debugging request by sending simulation control instructions to the board simulator, obtaining the simulation status information of the board simulator and sending it to the debugging module, and coordinating the data interaction and execution timing between the board simulator, the clock synchronization module, and the fault injection module. The clock synchronization module is used to provide a synchronization clock signal for each module in the virtual debugging system. The fault injection module is used to inject a preset fault into the board simulator based on the simulation control instructions from the runtime control and scheduling module.
[0022] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0023] See Figure 1 This figure is a schematic diagram of the structure of a virtual debugging system provided in an embodiment of this application. Figure 1As shown, the virtual debugging system includes: a board simulator, a run control and scheduling module, a clock synchronization module, a debugging module, and a fault injection module.
[0024] The board simulator is used to simulate the operating behavior of various hardware components in the physical board under test based on the simulation control instructions of the operation control scheduling module, and generate simulation status information; the various hardware components include at least a processor, a storage module, an interface module, and a logic control module.
[0025] The simulation status information includes processor register values, data at specified memory addresses, peripheral controls, status register contents, interrupt pending bits, and Direct Memory Access (DMA) transfer status.
[0026] By fully virtualizing the processor, storage, peripherals, and control logic, the virtual microprocessor unit (MPU) can provide embedded software with a runtime environment that is highly consistent with real hardware, supporting the entire process of firmware loading, protocol debugging, and functional verification, significantly improving development and testing efficiency and reducing dependence on physical hardware.
[0027] The debugging module is used to receive external debugging instructions and convert the external debugging instructions into debugging requests and send them to the operation control and scheduling module to perform virtual debugging on the board simulator based on the received simulation status information.
[0028] The debugging module includes the GNU Debugger (GDB), which serves as an interface between external debugging tools and the virtual debugging system. It receives external debugging commands, such as continue execution or single-step execution, through standard protocols, such as the GDB Remote Serial Protocol.
[0029] The operation control and scheduling module is used to respond to the debugging request, send simulation control instructions to the board simulator, obtain the simulation status information of the board simulator and send it to the debugging module, and coordinate the data interaction and execution timing between the board simulator, the clock synchronization module and the fault injection module.
[0030] The runtime control and scheduling module serves as the system's scheduling hub, uniformly managing the execution timing and interactions of each simulator component.
[0031] The clock synchronization module is used to provide a synchronization clock signal for each module in the virtual debugging system.
[0032] The clock synchronization module ensures clock synchronization between modules in the virtual debugging system, maintaining the accuracy of simulation timing.
[0033] The fault injection module is used to inject preset faults into the board simulator based on the simulation control commands of the operation control and scheduling module.
[0034] Preset faults include memory bit flips, bus timeouts, or peripheral response errors.
[0035] The fault injection module supports simulating various hardware anomalies and bus faults in a virtual environment, which can be used to test the robustness and fault tolerance of embedded software.
[0036] In one optional implementation, the board simulator includes: a processor emulation unit; The processor emulation unit is used to simulate the instruction set behavior of the MPC5200B and to simulate the double data rate controller, peripheral control registers, and bus access logic; the instruction set behavior includes interrupt handling and exception response mechanisms.
[0037] The MPC5200B is a 32-bit power architecture embedded processor.
[0038] In one optional implementation, the board simulator includes: a storage module simulation unit; The storage module simulation unit is used to simulate various types of memory, including 128M DDR memory, 16M×16bit Localbus Flash, 4M SPI Flash and 2kB EEPROM.
[0039] Simulates the address mapping and access characteristics of 128 megabytes of Double Data Rate (DDR) memory; 16M×16bit Localbus Flash represents a flash memory chip based on the Localbus local bus, with a 16-bit data width and a total capacity of 32MB. Simulates the code and data read / write operation of this flash memory chip, supporting sector erase and write protection operations; virtually implements the boot image storage function of 4M SPI Flash, following the Serial Peripheral Interface (SPI) bus protocol; simulates 2 kilobytes of electrically erasable programmable read-only memory (EEPROM), supporting byte-level access, used to store operating parameters.
[0040] In one optional implementation, the board simulator includes: an interface module simulation unit; The interface module simulation unit is used to simulate various peripheral interfaces, including a universal asynchronous transceiver serial port, a serial peripheral interface bus, and an Ethernet controller.
[0041] Implement serial port data transmission and reception of Universal Asynchronous Receiver / Transmitter (UART) for virtual debugging and data interaction; simulate SPI bus device communication; simulate the KSZ8851 Ethernet controller to support network frame transmission and reception, link status changes, and virtual connection with the host computer.
[0042] In one optional implementation, the board simulator includes: a logic control module simulation unit; The logic control module simulation unit is used to simulate various control behaviors through virtual programmable logic; the various control behaviors include bus interaction control, peripheral drive control and backplane bus interface control.
[0043] The system simulates bus interaction with the MPC5200B using a virtual Complex Programmable Logic Device (CPLD) to control light-emitting diodes (LEDs), push-button switches, dot matrix modules, and station / slot number DIP switches. It also simulates the First In First Out (FIFO) buffer and Physical Layer (PHY) interface to achieve high-speed data link buffering and transmission. Furthermore, it virtually implements the SN2 backplane bus interface to support control and data interaction with external expansion boards.
[0044] In one optional implementation, the system further includes: an extended interface simulation module; The extended interface simulation module is used to simulate general-purpose interfaces and backplane buses; the data exchange of the backplane bus is simulated based on a shared memory and dual-port random access memory mechanism; the general-purpose interface includes general-purpose input / output pins and an inter-integrated circuit bus.
[0045] While simulating core hardware such as the MPC5200B core, LocalBus bus, DDR3 memory, and SPI-FLASH, the simulation also extends to general-purpose input / output (GPIO) pins and inter-integrated circuit (I²C) interfaces. Through shared memory and dual-port random access memory (DPRAM) mechanisms, the SN2 bus data exchange is efficiently simulated, enabling collaborative operation with the FIFO+PHY interface and completing the virtualization of the high-speed data link.
[0046] The virtual MPU interacts with the external network environment through Ethernet interface emulation and network communication modules. UART serial port emulation provides basic serial data input / output capabilities for debugging information output or simulating traditional device connections.
[0047] The virtual debugging system provides an interface for integration with NCU simulators of other control stations. Other Neural Computing Unit (NCU) simulators can simulate the behavior of other nodes in the network, supporting joint simulation and testing of distributed systems with multiple boards and nodes.
[0048] The virtual node status monitoring service monitors and displays the real-time operating status of the virtual MPU and its host system, including resource utilization, bus load, and communication status. The operation log output service records key events, error messages, and debugging data during system operation, providing a basis for problem localization and system analysis.
[0049] The virtual debugging system provided in this application includes: a board simulator, a runtime control and scheduling module, a clock synchronization module, a debugging module, and a fault injection module. The board simulator is used to simulate the operating behavior of various hardware components in a physical board under test based on simulation control instructions from the runtime control and scheduling module, generating simulation status information. The various hardware components include at least a processor, a storage module, an interface module, and a logic control module. The debugging module receives external debugging instructions and converts these instructions into debugging requests, sending them to the runtime control and scheduling module for virtual debugging of the board simulator based on the received simulation status information. The runtime control and scheduling module, in response to the debugging request, sends simulation control instructions to the board simulator, obtains the simulation status information of the board simulator and sends it to the debugging module, and coordinates the data interaction and execution timing between the board simulator, the clock synchronization module, and the fault injection module. The clock synchronization module provides a synchronous clock signal for each module in the virtual debugging system. The fault injection module injects a preset fault into the board simulator based on the simulation control instructions from the runtime control and scheduling module.
[0050] The board simulator reconstructs various hardware components at the software level, including processors, storage modules, interface modules, and logic control modules. It implements the behavioral models of these hardware components and their interconnection and interaction logic on the bus, ensuring a high degree of reproduction of the underlying hardware behavior. Based on this, a system operating framework with scheduling, debugging, and integration testing capabilities is constructed. The runtime control scheduling module and clock synchronization module ensure simulation timing consistency, while the debugging module and fault injection module provide deep debugging and reliability testing capabilities. This provides embedded software with an operating environment highly consistent with real hardware, supporting the entire process of firmware loading, protocol debugging, and functional verification, significantly improving development and testing efficiency and reducing dependence on physical hardware. Compared to existing technologies where main control boards rely on physical hardware and require actual hardware resources, and where setting up the debugging environment is time-consuming and inefficient, the virtual debugging system provided in this application allows software development and integration testing to begin without waiting for hardware. This transforms the traditional serial development mode into a parallel mode, greatly shortening the development cycle and improving the debugging efficiency of the main control board.
[0051] See Figure 2 This figure is a flowchart of a virtual debugging method provided in an embodiment of this application. The method is applied to the virtual debugging system described in the above embodiments, such as... Figure 2 As shown, the method includes the following steps: S201, the board simulator simulates the operating behavior of various hardware components in the physical board under test based on the simulation control instructions of the operation control scheduling module, and generates simulation status information.
[0052] The various hardware components include at least a processor, a storage module, an interface module, and a logic control module.
[0053] In one feasible implementation: The instruction set behavior of the MPC5200B is simulated, as well as the DDR controller, peripheral control registers, and bus access logic. The instruction set behavior includes interrupt handling and exception response mechanisms.
[0054] In another feasible implementation: Simulates multiple types of memory; the multiple types of memory include 128M DDR memory, 16M×16bit LocalbusFlash, 4M SPI Flash and 2kB EEPROM.
[0055] In yet another feasible implementation: Simulates multiple peripheral interfaces; the multiple peripheral interfaces include a universal asynchronous transceiver serial port, a serial peripheral interface bus, and an Ethernet controller.
[0056] In another feasible implementation: Various control behaviors are simulated through virtual programmable logic; these behaviors include bus interaction control, peripheral drive control, and backplane bus interface control.
[0057] S202. The debugging module receives external debugging instructions and converts them into debugging requests, which are then sent to the operation control and scheduling module to perform virtual debugging of the board simulator based on the received simulation status information.
[0058] S203. The operation control and scheduling module responds to the debugging request by sending simulation control commands to the board simulator, obtaining the simulation status information of the board simulator and sending it to the debugging module, and coordinating the data interaction and execution timing between the board simulator, the clock synchronization module and the fault injection module.
[0059] S204, the clock synchronization module provides a synchronization clock signal for each module in the virtual debugging system.
[0060] S205. The fault injection module injects preset faults into the board simulator based on the simulation control instructions of the operation control scheduling module.
[0061] In one feasible implementation, the method further includes: The simulation includes a general-purpose interface and a backplane bus; the data exchange of the backplane bus is simulated based on a shared memory and dual-port random access memory mechanism; the general-purpose interface includes general-purpose input / output pins and an inter-integrated circuit bus.
[0062] The virtual debugging method provided in this application embodiment is applied to a virtual debugging system. The method includes: the board simulator, based on the simulation control instructions of the operation control scheduling module, simulates the operating behavior of various hardware components in the physical board under test, and generates simulation status information; the various hardware components include at least a processor, a storage module, an interface module, and a logic control module; the debugging module receives external debugging instructions and converts the external debugging instructions into debugging requests, which are then sent to the operation control scheduling module to perform virtual debugging on the board simulator based on the received simulation status information; the operation control scheduling module responds to the debugging request by sending simulation control instructions to the board simulator, obtaining the simulation status information of the board simulator and sending it to the debugging module, and coordinating the data interaction and execution timing between the board simulator, the clock synchronization module, and the fault injection module; the clock synchronization module provides a synchronization clock signal for each module in the virtual debugging system; and the fault injection module injects a preset fault into the board simulator based on the simulation control instructions of the operation control scheduling module.
[0063] The board simulator reconstructs various hardware components at the software level, including processors, storage modules, interface modules, and logic control modules. It implements the behavioral models of these hardware components and their interconnection and interaction logic on the bus, ensuring a high degree of reproduction of the underlying hardware behavior. Based on this, a system operating framework with scheduling, debugging, and integration testing capabilities is constructed. The runtime control scheduling module and clock synchronization module ensure simulation timing consistency, while the debugging module and fault injection module provide deep debugging and reliability testing capabilities. This provides embedded software with an operating environment highly consistent with real hardware, supporting the entire process of firmware loading, protocol debugging, and functional verification, significantly improving development and testing efficiency and reducing dependence on physical hardware. Compared to existing technologies where main control boards rely on physical hardware and require actual hardware resources, and where setting up the debugging environment is time-consuming and inefficient, the virtual debugging system provided in this application allows software development and integration testing to begin without waiting for hardware. This transforms the traditional serial development mode into a parallel mode, greatly shortening the development cycle and improving the debugging efficiency of the main control board. Furthermore, embodiments of this application also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the virtual debugging method as described in any of the method embodiments.
[0064] Furthermore, this application embodiment also provides a processor for running a computer program, wherein the program executes a virtual debugging method as described in any of the aforementioned method embodiments.
[0065] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments. The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate. The components indicated as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the solution in this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.
[0066] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A virtual debugging system, characterized in that, The virtual debugging system includes: a board simulator, a runtime control and scheduling module, a clock synchronization module, a debugging module, and a fault injection module; The board simulator is used to simulate the operating behavior of various hardware components in the physical board under test based on the simulation control instructions of the operation control scheduling module, and generate simulation status information; the various hardware components include at least a processor, a storage module, an interface module, and a logic control module. The debugging module is used to receive external debugging instructions and convert the external debugging instructions into debugging requests and send them to the operation control and scheduling module to perform virtual debugging on the board simulator based on the received simulation status information; The operation control and scheduling module is used to respond to the debugging request, send simulation control instructions to the board simulator, obtain the simulation status information of the board simulator and send it to the debugging module, and coordinate the data interaction and execution timing between the board simulator, the clock synchronization module and the fault injection module. The clock synchronization module is used to provide a synchronization clock signal for each module in the virtual debugging system; The fault injection module is used to inject preset faults into the board simulator based on the simulation control commands of the operation control and scheduling module.
2. The system according to claim 1, characterized in that, The board simulator includes: a processor simulation unit; The processor emulation unit is used to simulate the instruction set behavior of the MPC5200B and to simulate the double data rate controller, peripheral control registers, and bus access logic; the instruction set behavior includes interrupt handling and exception response mechanisms.
3. The system according to claim 1, characterized in that, The board simulator includes: a storage module simulation unit; The storage module simulation unit is used to simulate various types of memory, including 128M DDR memory, 16M×16bit Localbus Flash, 4M SPI Flash and 2kB EEPROM.
4. The system according to claim 1, characterized in that, The board simulator includes: an interface module simulation unit; The interface module simulation unit is used to simulate various peripheral interfaces, including a universal asynchronous transceiver serial port, a serial peripheral interface bus, and an Ethernet controller.
5. The system according to claim 1, characterized in that, The board simulator includes: a logic control module simulation unit; The logic control module simulation unit is used to simulate various control behaviors through virtual programmable logic; the various control behaviors include bus interaction control, peripheral drive control and backplane bus interface control.
6. The system according to claim 1, characterized in that, The system also includes: a monitoring module; The monitoring module is used to monitor and display the operating status of the board; the operating status includes resource utilization, bus load and communication status.
7. The system according to claim 1, characterized in that, The system also includes: an extended interface simulation module; The extended interface simulation module is used to simulate general-purpose interfaces and backplane buses; the data exchange of the backplane bus is simulated based on a shared memory and dual-port random access memory mechanism; the general-purpose interface includes general-purpose input / output pins and an inter-integrated circuit bus.
8. A virtual debugging method, characterized in that, The method is applied to the virtual debugging system according to claim 1, wherein the virtual debugging method includes: The board simulator simulates the operating behavior of various hardware components in the physical board under test based on the simulation control instructions of the operation control scheduling module, and generates simulation status information; the various hardware components include at least a processor, a storage module, an interface module, and a logic control module. The debugging module receives external debugging instructions and converts the external debugging instructions into debugging requests, which are then sent to the operation control and scheduling module to perform virtual debugging on the board simulator based on the received simulation status information. In response to the debugging request, the operation control and scheduling module sends simulation control instructions to the board simulator, obtains the simulation status information of the board simulator and sends it to the debugging module, and coordinates the data interaction and execution timing between the board simulator, the clock synchronization module and the fault injection module. The clock synchronization module provides a synchronization clock signal for each module in the virtual debugging system; The fault injection module injects a preset fault into the board simulator based on the simulation control command of the operation control and scheduling module.
9. The method according to claim 8, characterized in that, The board simulator, based on the simulation control commands of the operation control scheduling module, simulates the operating behavior of various hardware components in the physical board under test, and generates simulation status information, including: The instruction set behavior of the MPC5200B is simulated, as well as the DDR controller, peripheral control registers, and bus access logic. The instruction set behavior includes interrupt handling and exception response mechanisms.
10. The method according to claim 8, characterized in that, The board simulator, based on the simulation control commands of the operation control scheduling module, simulates the operating behavior of various hardware components in the physical board under test, and generates simulation status information, including: Simulates multiple types of memory; the multiple types of memory include 128M DDR memory, 16M×16bit Localbus Flash, 4M SPI Flash and 2kB EEPROM.