Digital-analog hybrid LDO (Low Dropout Regulator) with high power supply rejection and transient enhancement and without off-chip capacitor

Abstract

The invention belongs to the technical field of integrated circuit power supply management, and particularly relates to an off-chip capacitor-free digital-analog hybrid LDO (Low Dropout Regulator) with high power supply rejection and transient enhancement. According to the method, an NMOS pre-filter circuit, an FVF-based analog LDO, a digital auxiliary LDO and a slew rate enhancement circuit are included; the output end of the NMOS pre-filtering circuit is connected with an FVF-based analog LDO, a digital auxiliary LDO and a slew rate enhancement circuit; the output end of the analog LDO based on the FVF is connected with one end of the digital auxiliary LDO, one end of the slew rate enhancement circuit and one end of the capacitor, and the other end of the capacitor is grounded; according to the invention, full-band high PSR performance and fast transient response are realized under the condition that an off-chip large capacitor is not used, and the application prospect is good.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit power management technology, specifically relating to a capacitorless hybrid digital-analog LDO with high power supply rejection and transient enhancement. Background Technology

[0002] Low dropout linear regulators (LDOs) are commonly used after switching power supplies to suppress ripple and provide low-noise power to the load. As system-on-chip (SoC) integration increases and switching power supply operating frequencies rise, LDOs need to maintain high power supply rejection ratio (PSR) performance at higher frequencies while still requiring low dropout and fast transient response.

[0003] Existing solutions for improving PSR performance include: using an NMOS pre-filter structure to utilize the shielding effect of NMOS on drain voltage fluctuations to achieve high PSR performance across the entire frequency band, but this has three drawbacks: large input-output voltage difference, limited maximum load current, and deterioration of PSR performance under light load; using feedforward ripple cancellation and other techniques to improve PSR performance, but often requires a large external output capacitor, reducing system integration; and LDOs based on flip-flop voltage followers (FVF) can achieve full-band PSR performance without using a large external output capacitor, but PSR performance deteriorates at mid-to-high frequencies.

[0004] Therefore, existing technologies generally face the challenge of simultaneously achieving high PSR performance (especially at mid-to-high frequencies), moderate dropout voltage, large load current capability, and fast transient response without using large external capacitors. There is an urgent need for a new type of LDO that can achieve high PSR performance and fast transient response across the entire frequency band without the use of large external capacitors. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention proposes a capacitorless hybrid analog-digital LDO with high power supply rejection and transient enhancement. The method includes: an NMOS pre-filter circuit, an FVF-based analog LDO, a digital auxiliary LDO, and a slew rate enhancement circuit; the output of the NMOS pre-filter circuit is connected to the FVF-based analog LDO, the digital auxiliary LDO, and the slew rate enhancement circuit; the output of the FVF-based analog LDO is connected to the digital auxiliary LDO, the slew rate enhancement circuit, and a capacitor. One end of the capacitor The other end is grounded.

[0006] Preferably, the NMOS pre-filter circuit includes a charge pump, an operational transconductance amplifier (OTA), and a capacitor. NMOS transistor NMOS transistor and resistance One input of the charge pump is connected to the power supply, the other input is connected to the digital auxiliary LDO, and the output is connected to the charge pump input of the operational transconductance amplifier OTA; the negative input of the operational transconductance amplifier OTA is connected to an NMOS transistor. source and resistor One end; the output of the operational transconductance amplifier OTA is connected to a capacitor. One end and NMOS transistor At one end of the gate, the NMOS transistor The other end of the gate is connected to the NMOS transistor. Gate of NMOS transistor drain and NMOS transistor The drains of the capacitors are all connected to the power supply; The other end is connected to the resistor The other end is grounded; NMOS transistor The source connection is based on an analog LDO, a digital-assisted LDO, and a slew rate enhancement circuit using an FVF.

[0007] Preferably, the FVF-based analog LDO includes a super source follower and a PMOS transistor. Error amplifier EA, NOR gate, NMOS transistor ,capacitance and PMOS transistor The input terminal of the super source follower is connected to the power supply, and the output terminal of the super source follower is connected to the PMOS transistor. The gate of the LDO is connected to a digital auxiliary LDO, and the other output is connected to a PMOS transistor. Drain of PMOS transistor The source is connected to the power supply, PMOS transistor The drain of the error amplifier EA is connected to the negative input terminal of the PMOS transistor. The source of the PMOS transistor. The drain of the gate is also connected to a digital auxiliary LDO and a slew rate enhancement circuit; the two inputs of the NOR gate are connected to the digital auxiliary LDO, and the output of the NOR gate is connected to an NMOS transistor. The gate of the error amplifier EA is connected to the NMOS transistor. Drain of NMOS transistor The source of the PMOS transistor is connected. gate and capacitor One end of the capacitor The other end is grounded; PMOS transistor The drain is also connected to a capacitor. One end.

[0008] Preferably, the digital auxiliary LDO includes four comparators CMP1~CMP4, a 4MHz oscillator, a 100MHz oscillator, a control unit, and a digital LDO based on a bidirectional shift register. The outputs of the four comparators CMP1~CMP4, the 4MHz oscillator, and the 100MHz oscillator are all connected to the input of the control unit. The output of the 4MHz oscillator is also connected to the charge pump in the NMOS pre-filter circuit. The output of the control unit is connected to the input of the digital LDO based on the bidirectional shift register. The input of the digital LDO based on the bidirectional shift register is also connected to the NMOS transistor in the NMOS pre-filter circuit. The source of the LDO is connected to the slew rate enhancement circuit; the output of the digital LDO based on the bidirectional shift register is connected to the slew rate enhancement circuit; the outputs of comparators CMP1 and CMP2 are respectively connected to the two inputs of the NOR gate in the FVF-based analog LDO; the positive inputs of comparators CMP1 and CMP2 are connected to the PMOS transistor in the FVF-based analog LDO. The gate of the comparator; the positive input terminals of comparators CMP3 and CMP4 are connected to the PMOS transistor in an FVF-based analog LDO. The drain electrode.

[0009] Preferably, the slew rate enhancement circuit includes a hysteresis comparator CMP5, a hysteresis comparator CMP6, an injection circuit, and a decimation circuit; the positive input terminals of both hysteresis comparators CMP5 and CMP6 are connected to the PMOS transistors in an FVF-based analog LDO. The drain of the hysteresis comparator CMP5 is connected to one input of the injection circuit, and the other input of the injection circuit is connected to the NMOS transistor in the NMOS pre-filter circuit. The source of the hysteresis comparator CMP6 is connected to one input of the decimation circuit, and the other input of the decimation circuit is connected to the output of the injection circuit and the PMOS transistor in the FVF-based analog LDO. The drain of the circuit is grounded at the output terminal of the extraction circuit.

[0010] Furthermore, the injection circuit includes a bidirectional shift register with asynchronous reset function, a PMOS power transistor driver circuit, and a PMOS power transistor array. The input of the bidirectional shift register with asynchronous reset function is connected to the output of the hysteresis comparator CMP5, the output of the bidirectional shift register with asynchronous reset function is connected to the input of the PMOS power transistor driver circuit, the output of the PMOS power transistor driver circuit is connected to one input of the PMOS power transistor array, and the other input of the PMOS power transistor array is connected to the NMOS transistor in the NMOS pre-filter circuit. The source of the PMOS power transistor array is connected to the injection circuit at its output terminal.

[0011] Furthermore, the extraction circuit includes a bidirectional shift register with asynchronous set function, an NMOS power transistor driver circuit, and an NMOS power transistor array; the input of the bidirectional shift register with asynchronous set function is connected to the output of the hysteresis comparator CMP6, the output of the bidirectional shift register with asynchronous set function is connected to the input of the NMOS power transistor driver circuit, the output of the NMOS power transistor driver circuit is connected to one input of the NMOS power transistor array, the other input of the NMOS power transistor array is connected to the output of the PMOS power transistor array in the injection circuit, and the output of the NMOS power transistor array is grounded.

[0012] The beneficial effects of this invention are as follows: This invention achieves excellent PSR performance across the entire frequency band without using large off-chip capacitors. It improves upon the three shortcomings of NMOS pre-filter circuits—PSR performance degradation, large voltage difference, and limited maximum load current—under light load conditions by using a hybrid analog-digital LDO structure. Specifically, the FVF-based analog LDO improves the PSR performance degradation under light load conditions, while the digitally assisted LDO improves the large voltage difference and limited maximum load current. The FVF-based analog LDO also improves the PSR performance degradation of the NMOS pre-filter circuit under light load conditions. This invention enhances the overall transient response performance of the LDO through two transient enhancement circuits: a loop control circuit and a slew rate enhancement circuit. The loop control circuit enhances the stability during transient response and shortens the recovery time; the slew rate enhancement circuit suppresses output voltage fluctuations during transient response. The LDO designed in this invention exhibits small overshoot voltage, small undershoot voltage, and a short recovery time during transient responses. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the capacitorless hybrid digital-analog LDO structure with high power supply rejection and transient enhancement in this invention;

[0014] Figure 2 This is a schematic diagram of the simulated LDO structure based on FVF in this invention;

[0015] Figure 3 This is the transient response diagram of the LDO of the present invention in the case of a loopless control circuit and a slew rate enhancement circuit;

[0016] Figure 4 This is the transient response diagram of the LDO of the present invention with a loop control circuit but no slew rate enhancement circuit;

[0017] Figure 5 This is a schematic diagram of the digital LDO structure based on a bidirectional shift register in this invention;

[0018] Figure 6 This is the control logic diagram of the control unit in this invention;

[0019] Figure 7This is a schematic diagram of the slew rate enhancement circuit structure in this invention;

[0020] Figure 8 This is a PSR performance diagram of the circuit of the present invention;

[0021] Figure 9 This is a transient response performance diagram of the LDO circuit of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] This invention proposes a capacitorless hybrid digital-analog LDO with high power supply rejection and transient enhancement, such as... Figure 1 As shown, the method includes the following: an NMOS pre-filter circuit, an FVF-based analog LDO, a digital auxiliary LDO, and a slew rate enhancement circuit; the output of the NMOS pre-filter circuit is connected to the FVF-based analog LDO, the digital auxiliary LDO, and the slew rate enhancement circuit; the output of the FVF-based analog LDO is connected to the digital auxiliary LDO, the slew rate enhancement circuit, and a capacitor. One end of the capacitor The other end is grounded.

[0024] NMOS pre-filter circuit:

[0025] The NMOS pre-filter circuit utilizes an NMOS transistor. The shielding effect against drain voltage fluctuations achieves high PSR performance across the entire frequency band. In some preferred embodiments of the invention, the NMOS pre-filter circuit includes a charge pump, an operational transconductance amplifier (OTA), and a capacitor. NMOS transistor NMOS transistor and resistance One input of the charge pump is connected to the power supply, the other input is connected to the digital auxiliary LDO, and the output is connected to the charge pump input of the operational transconductance amplifier OTA; the negative input of the operational transconductance amplifier OTA is connected to an NMOS transistor. source and resistor One end; the output of the operational transconductance amplifier OTA is connected to a capacitor. One end and NMOS transistor At one end of the gate, the NMOS transistor The other end of the gate is connected to the NMOS transistor. Gate of NMOS transistor drain and NMOS transistor The drains of the capacitors are all connected to the power supply; The other end is connected to the resistor The other end is grounded; NMOS transistor The source connection is based on an analog LDO, a digital-assisted LDO, and a slew rate enhancement circuit using an FVF.

[0026] The bias circuit consists of a charge pump, OTA, , , Composition, its main function is to provide gate voltage A suitable voltage.

[0027] From the virtual shortness characteristic of OTA, we can obtain gate voltage ,in for The gate-source voltage difference.

[0028] The function of a charge pump is to increase the voltage, so that... gate voltage It can be higher than the power supply voltage, thereby reducing The voltage difference between the drain and source. Simultaneously using To filter out the ripple noise of the charge pump.

[0029] FVF-based simulated LDO:

[0030] This invention utilizes a fast and slow dual-loop structure of an analog LDO based on FVF to achieve good full-band PSR performance under light load, thereby improving the defect of PSR performance degradation of NMOS pre-filtering technology under light load.

[0031] like Figure 2 As shown, in some preferred embodiments of the present invention, the FVF-based analog LDO includes a super source follower and a PMOS transistor. Error amplifier EA, NOR gate, NMOS transistor ,capacitance and PMOS transistor The input terminal of the super source follower is connected to the power supply, and the output terminal of the super source follower is connected to the PMOS transistor. The gate of the LDO is connected to a digital auxiliary LDO, and the other output is connected to a PMOS transistor. Drain of PMOS transistor The source is connected to the power supply, PMOS transistor The drain of the error amplifier EA is connected to the negative input terminal of the PMOS transistor. The source of the PMOS transistor. The drain of the gate is also connected to a digital auxiliary LDO and a slew rate enhancement circuit; the two inputs of the NOR gate are connected to the digital auxiliary LDO, and the output of the NOR gate is connected to an NMOS transistor. The gate of the error amplifier EA is connected to the NMOS transistor. Drain of NMOS transistor The source of the PMOS transistor is connected. gate and capacitor One end of the capacitor The other end is grounded; PMOS transistor The drain is also connected to a capacitor. One end.

[0032] The slow loop determines the output voltage and its accuracy. This is known from the amplifier's virtual short characteristic. To improve the accuracy of the output voltage, the error amplifier EA employs a folded cascode structure to increase the gain.

[0033] The fast loop determines the bandwidth and phase margin of the entire analog LDO. In the fast loop, The parasitic capacitance at the node is very small, therefore The poles at the node are located at high frequencies; at the same time, a super source follower (SSF) is used to reduce the frequency. The impedance at the node, therefore The poles at the nodes are also located at high frequencies.

[0034] because and Since both non-dominant poles are located at high frequencies, a small on-chip capacitor (250pF) is sufficient to achieve loop stability when the output pole is the dominant pole. Because the output pole is the dominant pole, this FVF-based analog LDO achieves good PSR performance across the entire frequency range.

[0035] This invention designs a loop control circuit consisting of a NOR logic gate and an NMOS transistor used as a switch. This loop control circuit can improve the stability during transient response. When the load current changes drastically, the loop control circuit disconnects the slow loop of the analog LDO, allowing the digital LDO to adjust first. After the digital LDO has basically completed its adjustment and the overall LDO has stabilized, the loop control circuit reconnects the slow loop of the analog LDO, allowing the slow loop of the analog LDO to precisely fine-tune the output voltage. The principle is as follows:

[0036] During transient response, the output voltage The voltage deviates significantly from 1.5 V, and the simulated LDO enters the nonlinear build-up phase. During this period, the simulated LDO error amplifier EA operates at its maximum slew rate against the capacitor. Perform charging and discharging. Because the adjustment process of a digital LDO is time-consuming, an analog LDO will continuously remain in a non-linear build-up state, which can easily lead to bias voltage issues. Too high or too low a value can lead to a prolonged transient response time, or cause... A significant negative overshoot occurs. For example... Figure 3 As shown. The loop control circuit proposed in this invention can disconnect the slow loop when a transient response occurs, thus avoiding... The voltage is too high or too low. or When the level is high, it is determined that a transient response has occurred, or the NOR gate outputs a low level. The pipe is turned off, thus breaking the slow loop; when and When all levels are low, it is determined that the transient response has basically ended, and the NOR gate enables... When the tube is turned on, it connects to the slow loop and regulates the output voltage. Adjustments can be made, such as Figure 4 As shown.

[0037] Digital Auxiliary LDO:

[0038] In some preferred embodiments of the present invention, the digital auxiliary LDO includes four comparators CMP1~CMP4, a 4MHz oscillator, a 100MHz oscillator, a control unit, and a digital LDO based on a bidirectional shift register. The outputs of the four comparators CMP1~CMP4, the 4MHz oscillator, and the 100MHz oscillator are all connected to the input of the control unit. The output of the 4MHz oscillator is also connected to the charge pump in the NMOS pre-filter circuit. The output of the control unit is connected to the input of the digital LDO based on the bidirectional shift register. The input of the digital LDO based on the bidirectional shift register is also connected to the NMOS transistor in the NMOS pre-filter circuit. The source of the LDO is connected to the slew rate enhancement circuit; the output of the digital LDO based on the bidirectional shift register is connected to the slew rate enhancement circuit; the outputs of comparators CMP1 and CMP2 are respectively connected to the two inputs of the NOR gate in the FVF-based analog LDO; the positive inputs of comparators CMP1 and CMP2 are connected to the PMOS transistor in the FVF-based analog LDO. The gate of the comparator; the positive input terminals of comparators CMP3 and CMP4 are connected to the PMOS transistor in an FVF-based analog LDO. The drain electrode.

[0039] In this hybrid digital-analog LDO structure, the analog LDO handles only a small portion of the load current, while the digital LDO handles the majority. This invention, through the assistance of the digital LDO, increases the overall load-carrying capacity of the hybrid digital-analog LDO; simultaneously, since the analog LDO only needs to handle a small load current, a large input-output voltage difference is not required. This hybrid digital-analog LDO structure can overcome the two shortcomings of NMOS pre-filtering technology: large voltage drop and limited maximum load current.

[0040] Digital LDOs based on bidirectional shift registers, such as Figure 5 As shown, when the circuit is on, all bits of the shift register are at a high level, and all PMOS transistors in the switch array are off. When the clock signal arrives, the bidirectional shift register begins to shift according to the level of the SEL pin, which selects the shift direction. When SEL is low, each bit in the shift register shifts one unit to the right, and a "0" signal is shifted into the leftmost bit. This increases the number of switches turned on, thereby increasing the output current. Conversely, when SEL is high, when the next rising edge of the clock arrives, each bit in the shift register shifts one unit to the left, and a "1" is shifted into the rightmost bit, reducing the number of switches turned on and decreasing the output current. This operating mode ensures the stability of the output voltage.

[0041] The control unit acquires data through four comparators (CMP1-CMP4). and Voltage information from two key nodes is used to generate , , , Four level signals, of which CMP1 and CMP2 are used for acquisition. The voltage information is used to determine the operating status of the analog LDO. CMP3 and CMP4 are used for data acquisition. The voltage information is provided, along with a 30mV hysteresis voltage. The control unit coordinates the operation of the analog LDO and digital LDO based on these four voltage levels, supplying different SEL levels and CLK frequencies to the bidirectional shift register, thereby controlling the increase or decrease of the digital LDO output current and the rate of increase or decrease.

[0042] The increase or decrease of the digital LDO output current (i.e., the SEL level of the bidirectional shift register) is determined by the outputs of CMP1 and CMP2. hour, , This indicates that the output current of the analog LDO is too high. The control unit sets SEL to low, shifts the shift register to the right, increases the output current of the digital LDO, and thus reduces the output current of the analog LDO, allowing the analog LDO to work normally. hour, , This indicates that the output current of the analog LDO is appropriate and the analog LDO is working normally. At this time, the control unit sets CLK to a low level, and the shift register stops shifting because there is no clock signal. The output current of the digital LDO remains unchanged. hour, , This indicates that the output current of the analog LDO is too small at this time. The control unit sets SEL to a high level, shifts the shift register to the left, reduces the output current of the digital LDO, thereby increasing the output current of the analog LDO and allowing the analog LDO to work normally.

[0043] The rate at which the digital LDO output current increases or decreases (i.e., the CLK frequency of the bidirectional shift register) is simultaneously determined by four comparators, CMP1-CMP4. The control unit, based on... , , , These four signals determine whether the load current changes abruptly and change the frequency of CLK to control the rate at which the digital LDO output current increases or decreases.

[0044] When the load current increases slowly, it will not cause a sharp drop in the output voltage. , ,at this time , , , The control unit adjusts the CLK frequency to 4MHz, causing the current of the digital LDO to increase slowly, achieving a gradual fine-tuning effect and making the overall LDO operation more stable. Similarly, when the load current decreases slowly, it will not cause a sharp surge in the output voltage. , ,at this time , , , The control unit adjusts the CLK frequency to 4MHz, causing the current of the digital LDO to decrease slowly.

[0045] when at the same time This indicates a sudden increase in load current. , , , The control unit adjusts the CLK frequency to 100MHz, causing the digital LDO current to increase rapidly. Simultaneously, due to the CMP4's 30mV hysteresis voltage, the CLK frequency will remain at 100MHz until the output voltage is adjusted to 1.5V; therefore, this 30mV hysteresis voltage accelerates transient response. Similarly, when... at the same time This indicates a sudden increase in load current. , , , The control unit adjusts the CLK frequency to 100MHz, and the current of the digital LDO decreases rapidly.

[0046] The overall control logic of the control unit is as follows: Figure 6 As shown.

[0047] Slew rate enhancement circuit:

[0048] like Figure 7 As shown, in some preferred embodiments of the present invention, the slew rate enhancement circuit includes a hysteresis comparator CMP5, a hysteresis comparator CMP6, an injection circuit, and a decimation circuit; the positive input terminals of both hysteresis comparators CMP5 and CMP6 are connected to the PMOS transistors in an FVF-based analog LDO. The drain of the hysteresis comparator CMP5 is connected to one input of the injection circuit, and the other input of the injection circuit is connected to the NMOS transistor in the NMOS pre-filter circuit. The source of the hysteresis comparator CMP6 is connected to one input of the decimation circuit, and the other input of the decimation circuit is connected to the output of the injection circuit and the PMOS transistor in the FVF-based analog LDO. The drain of the circuit is grounded at the output terminal of the extraction circuit.

[0049] The injection circuit includes a bidirectional shift register with asynchronous reset function, a PMOS power transistor driver circuit, and a PMOS power transistor array. The input of the bidirectional shift register with asynchronous reset function is connected to the output of the hysteresis comparator CMP5, the output of the bidirectional shift register with asynchronous reset function is connected to the input of the PMOS power transistor driver circuit, the output of the PMOS power transistor driver circuit is connected to one input of the PMOS power transistor array, and the other input of the PMOS power transistor array is connected to the NMOS transistor in the NMOS pre-filter circuit. The source of the PMOS power transistor array is connected to the injection circuit at its output terminal.

[0050] The extraction circuit includes a bidirectional shift register with asynchronous set function, an NMOS power transistor driver circuit, and an NMOS power transistor array. The input of the bidirectional shift register with asynchronous set function is connected to the output of the hysteresis comparator CMP6, the output of the bidirectional shift register with asynchronous set function is connected to the input of the NMOS power transistor driver circuit, the output of the NMOS power transistor driver circuit is connected to one input of the NMOS power transistor array, the other input of the NMOS power transistor array is connected to the output of the PMOS power transistor array in the injection circuit, and the output of the NMOS power transistor array is grounded.

[0051] A slew rate enhancement circuit can be viewed as adding two additional digital LDOs in parallel to the existing digital LDO. During severe transient responses, this circuit works in conjunction with the original digital LDOs to improve the slew rate and suppress the output voltage. The slew rate fluctuation. Meanwhile, all power transistors in the slew rate enhancement circuit will slowly turn off before the transient response ends, ensuring that system stability is not affected. The principle is as follows:

[0052] In the hybrid analog-digital LDO of this invention, the digital LDO handles the majority of the load current; therefore, the system's transient response speed is essentially determined by the digital LDO. For a digital LDO, a higher slew rate results in a stronger transient response. The expression for the slew rate is:

[0053]

[0054] in, For clock frequency, This represents the current of each power transistor in the digital LDO. and The larger the value, the greater the slew rate, the faster the transient response, and the smaller the output voltage fluctuation during transient response.

[0055] However, in this hybrid analog-digital LDO structure, in order to ensure stability, The maximum value is limited. This is because the overall output current of the mixed-signal LDO can be expressed as:

[0056]

[0057] in, To simulate the output current of an LDO, The number of power transistors enabled for the digital LDO. The output current of the simulated LDO is denoted as , The output current of the simulated LDO is denoted as ,but The maximum value is .if Greater than If a unique N cannot be found in the above expression, then the mixed-signal LDO is unstable.

[0058] To increase the slew rate, this invention designs a slew rate enhancement circuit. This circuit can be viewed as adding two additional digital LDOs in parallel to the existing digital LDO. These two digital LDOs have larger power transistors, each with a higher current draw, resulting in a greater slew rate. During severe transient responses, this circuit works in conjunction with the original digital LDOs to improve the slew rate and suppress fluctuations in the output voltage VOUT. Simultaneously, all power transistors in the slew rate enhancement circuit are slowly turned off before the transient response ends, ensuring no impact on system stability. The slow turn-off function of the power transistors is implemented through a gate drive circuit. This gate drive circuit adds a small current source to the CMOS push-pull structure, thereby limiting the discharge current of the gate parasitic capacitance when the power transistor is turned off, achieving a slow turn-off effect without affecting the turn-on speed of the power transistor. The specific working process is as follows:

[0059] When the load current increases sharply, the output voltage When the voltage drops below 1.44 V, comparator CMP5 outputs a low level. Subsequently, the shift register controls the PMOS power transistor to turn on, supplying power to... Node injection current is used to offset changes in load current. Due to the presence of a 30 mV hysteresis voltage, when When the voltage rises above 1.47 V, the CMP5 outputs a high level, the shift register is asynchronously reset, and all power transistors in the PMOS power transistor array of the slew rate enhancement circuit are slowly turned off. Because the power transistors turn off slowly, it will not cause… To avoid significant fluctuations. The voltage dropped below 1.44 V again, causing the CMP5 to be falsely triggered. The operation is similar when the load current decreases sharply, except that the circuit will then draw power from the NMOS power transistor... The node draws current to offset changes in load current.

[0060] Evaluation of the present invention:

[0061] The present invention is compared with a circuit that also uses NMOS pre-filtering technology, and the comparison results are shown in Table 1.

[0062] Table 1 Performance Comparison of the Invention and the Comparative Method

[0063]

[0064] As can be seen from Table 1, the present invention exhibits superior performance in differential pressure, transient response speed, and PSR. The PSR and transient response performance of the circuit of the present invention are shown below. Figure 8 andFigure 9 As shown. From Figure 8 It can be seen that the LDO exhibits good PSR performance at a load current of 1mA (light load), indicating that the FVF-based analog LDO can effectively improve the PSR performance degradation of the NMOS pre-filter circuit under light load. Furthermore, under different load current conditions, the LDO designed in this invention maintains good PSR performance across the entire frequency range. This demonstrates that this invention achieves good PSR performance across the entire frequency range without using large off-chip capacitors. Figure 9 It can be seen that the load step voltage also changes from 1 mA to 50 mA within a 100 ns rise time. The overshoot voltage is 110 mV, and the undershoot voltage is 87 mV. The slew rate enhancement circuit effectively suppresses the overshoot. The voltage fluctuations were measured, and the recovery times were 1.43 μs and 1.37 μs, respectively. These recovery times demonstrate that the loop control circuit can effectively shorten the transient response recovery time. Therefore, the loop control circuit and slew rate enhancement circuit designed in this invention can significantly improve transient response performance.

[0065] In summary, to achieve high PSR performance across the entire frequency band, this invention employs NMOS pre-filtering technology. Addressing the three shortcomings of NMOS pre-filtering technology, this invention first utilizes a hybrid digital-analog LDO structure (digitally assisted analog LDO) to improve the large voltage drop and limited maximum load current inherent in NMOS pre-filtering technology. Simultaneously, it uses a flip-flop voltage follower (FVF) analog LDO structure to mitigate the PSR performance degradation under light load conditions. To achieve fast transient response, this invention designs two transient enhancement circuits—a loop control circuit and a slew rate enhancement circuit—to increase stability during transient response, accelerate response speed, and reduce output voltage fluctuations, taking into account the specific structure of the hybrid digital-analog LDO used.

[0066] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A capacitorless hybrid digital-analog LDO with high power supply rejection and transient enhancement, characterized in that, include: NMOS pre-filter circuit, FVF-based analog LDO, digital-assisted LDO, and slew rate enhancement circuit; The output of the NMOS pre-filter circuit is connected to an FVF-based analog LDO, a digital auxiliary LDO, and a slew rate enhancement circuit; the output of the FVF-based analog LDO is connected to a digital auxiliary LDO, a slew rate enhancement circuit, and a capacitor. One end of the capacitor The other end is grounded.

2. The capacitorless hybrid digital-analog LDO with high power supply rejection and transient enhancement according to claim 1, characterized in that, The NMOS pre-filter circuit includes a charge pump, an operational transconductance amplifier OTA, and a capacitor. NMOS transistor NMOS transistor and resistance One input of the charge pump is connected to the power supply, the other input is connected to the digital auxiliary LDO, and the output is connected to the charge pump input of the operational transconductance amplifier OTA; the negative input of the operational transconductance amplifier OTA is connected to an NMOS transistor. source and resistor One end; the output of the operational transconductance amplifier OTA is connected to a capacitor. One end and NMOS transistor At one end of the gate, the NMOS transistor The other end of the gate is connected to the NMOS transistor. Gate of NMOS transistor drain and NMOS transistor The drains of the capacitors are all connected to the power supply; The other end is connected to the resistor The other end is grounded; NMOS transistor The source connection is based on an analog LDO, a digital-assisted LDO, and a slew rate enhancement circuit using an FVF.

3. A capacitorless hybrid digital-analog LDO with high power supply rejection and transient enhancement according to claim 1, characterized in that, The FVF-based analog LDO includes a super source follower and a PMOS transistor. Error amplifier EA, NOR gate, NMOS transistor ,capacitance and PMOS transistor ; The input terminal of the super source follower is connected to the power supply, and the output terminal of the super source follower is connected to the PMOS transistor. The gate of the LDO is connected to a digital auxiliary LDO, and the other output is connected to a PMOS transistor. Drain of PMOS transistor The source is connected to the power supply, PMOS transistor The drain of the error amplifier EA is connected to the negative input terminal of the PMOS transistor. The source of the PMOS transistor. The drain of the gate is also connected to a digital auxiliary LDO and a slew rate enhancement circuit; the two inputs of the NOR gate are connected to the digital auxiliary LDO, and the output of the NOR gate is connected to an NMOS transistor. The gate of the error amplifier EA is connected to the NMOS transistor. Drain of NMOS transistor The source of the PMOS transistor is connected. gate and capacitor One end of the capacitor The other end is grounded; PMOS transistor The drain is also connected to a capacitor. One end.

4. A capacitorless hybrid digital-analog LDO with high power supply rejection and transient enhancement according to claim 1, characterized in that, The digital auxiliary LDO includes four comparators CMP1~CMP4, a 4MHz oscillator, a 100MHz oscillator, a control unit, and a digital LDO based on a bidirectional shift register. The outputs of the four comparators CMP1~CMP4, the 4MHz oscillator, and the 100MHz oscillator are all connected to the input of the control unit. The output of the 4MHz oscillator is also connected to the charge pump in the NMOS pre-filter circuit. The output of the control unit is connected to the input of the digital LDO based on the bidirectional shift register. The input of the digital LDO based on the bidirectional shift register is also connected to the NMOS transistor in the NMOS pre-filter circuit. The source of the LDO is connected to the slew rate enhancement circuit; the output of the digital LDO based on the bidirectional shift register is connected to the slew rate enhancement circuit; the outputs of comparators CMP1 and CMP2 are respectively connected to the two inputs of the NOR gate in the FVF-based analog LDO; the positive inputs of comparators CMP1 and CMP2 are connected to the PMOS transistor in the FVF-based analog LDO. The gate of the comparator; the positive input terminals of comparators CMP3 and CMP4 are connected to the PMOS transistor in an FVF-based analog LDO. The drain electrode.

5. A capacitorless hybrid digital-analog LDO with high power supply rejection and transient enhancement according to claim 1, characterized in that, The slew rate enhancement circuit includes hysteresis comparators CMP5 and CMP6, an injection circuit, and a decimation circuit; the positive input terminals of both hysteresis comparators CMP5 and CMP6 are connected to the PMOS transistors in an FVF-based analog LDO. The drain of the hysteresis comparator CMP5 is connected to one input of the injection circuit, and the other input of the injection circuit is connected to the NMOS transistor in the NMOS pre-filter circuit. The source pole; The output of the hysteresis comparator CMP6 is connected to one input of the decimation circuit, and the other input of the decimation circuit is connected to the output of the injection circuit and the PMOS transistor in the FVF-based analog LDO. The drain of the circuit is grounded at the output terminal of the extraction circuit.

6. A capacitorless hybrid digital-analog LDO with high power supply rejection and transient enhancement according to claim 5, characterized in that, The injection circuit includes a bidirectional shift register with asynchronous reset function, a PMOS power transistor driver circuit, and a PMOS power transistor array. The input of the bidirectional shift register with asynchronous reset function is connected to the output of the hysteresis comparator CMP5, the output of the bidirectional shift register with asynchronous reset function is connected to the input of the PMOS power transistor driver circuit, the output of the PMOS power transistor driver circuit is connected to one input of the PMOS power transistor array, and the other input of the PMOS power transistor array is connected to the NMOS transistor in the NMOS pre-filter circuit. The source of the PMOS power transistor array is connected to the injection circuit at its output terminal.

7. A capacitorless hybrid digital-analog LDO with high power supply rejection and transient enhancement according to claim 5, characterized in that, The extraction circuit includes a bidirectional shift register with asynchronous set function, an NMOS power transistor driver circuit, and an NMOS power transistor array. The input of the bidirectional shift register with asynchronous set function is connected to the output of the hysteresis comparator CMP6, the output of the bidirectional shift register with asynchronous set function is connected to the input of the NMOS power transistor driver circuit, the output of the NMOS power transistor driver circuit is connected to one input of the NMOS power transistor array, the other input of the NMOS power transistor array is connected to the output of the PMOS power transistor array in the injection circuit, and the output of the NMOS power transistor array is grounded.

Images