Rising edge flip-flop, flip-flop module and low noise amplifier

Abstract

This invention provides a rising-edge trigger, a trigger module, and a low-noise amplifier. The rising-edge trigger includes a first inverting circuit, a first field-effect transistor, a first inverter, an RC charging circuit, a second inverting circuit, a Schmitt trigger, and a third inverting circuit. The first inverting circuit shapes the input excitation signal. The RC charging circuit charges and gradually increases the charging voltage. The second inverting circuit generates a delay signal with a preset time width. The Schmitt trigger shapes the delay signal generated by the second inverting circuit with the preset time width. The third inverting circuit shapes the delay signal after it has been shaped by the Schmitt trigger. This invention reduces the number of rising-edge triggers in the trigger module, thereby reducing the overall area of ​​the trigger module, while also improving the power-on and switching response speed of the low-noise amplifier.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a rising edge trigger, trigger module, and low noise amplifier used in radio frequency modules. Background Technology

[0002] The low-noise amplifier (LNA) uses a source-degenerate inductor common-source architecture, such as... Figure 1 As shown, the related RF low-noise amplifier includes field-effect transistors (M1, M2, M3, M4, M5, M6, M7), inductors (LS, LD), resistors (R1, R2), and a current source (Iref). Field-effect transistors M1 and M4 form a common-gate transistor (CG), with the gates of M1 and M4 respectively connected to a first bias voltage VGcg. Field-effect transistors M2 and M5 form a common-source transistor (CRT). The gates of MOSFETs M2 and M5 are used to connect to the second bias voltage VGcs. One end of inductor LD is used to connect to the operating voltage Vdd. One end of inductor LS is grounded to Gnd. One end of current source Iref is used to connect to the operating voltage Vdd. The gates of the third MOSFET M3 and the seventh MOSFET M7 are used to connect to the enable signal EN. The source of the third MOSFET M3 is grounded to Gnd. The gate of the sixth MOSFET M6 is used to connect to the delay control signal (Burst Stop, BSTP).

[0003] The specifications of the aforementioned RF low-noise amplifiers generally require power-on and switching to be completed in about 1µs. The enable switch of the RF low-noise amplifier is used to control the power-on of the low-noise amplifier enable signal (LNAEN). However, the gate voltage power-on of the common-gate transistor and common-source transistor is relatively slow, requiring a delay module. At the same time as the low-noise amplifier enable signal is powered on, the delay module simultaneously provides a fast power-on and fast switching signal of about 1µs, enabling the common-gate transistor and common-source transistor of the RF low-noise amplifier to be powered on quickly at the same time, so as to ensure that the power-on time and switching time are within the specification range. After the fast power-on is completed, the delay signal output of the delay module is 0, and the RF low-noise amplifier enters the normal operating state. A resistor R2 is connected between the field-effect transistor M2 in the mirror branch and the switch for protection. The circuit that generates the delay signal is called a rising edge trigger or edge-triggered trigger.

[0004] like Figure 2As shown, for the switching time of multiple gain levels, in order to meet the specifications of the aforementioned RF low-noise amplifier, the trigger module of the related technology generates an excitation signal. This signal is first controlled by an n-bit edge trigger by an n-bit register that controls the gain switching, and then processed by an OR gate logic to finally generate a delay signal, so that a delay signal is generated during the switching process of each gain level.

[0005] Although the aforementioned trigger module can generate a delay signal during the switching process of each gain level, the large number of edge triggers increases the overall area of ​​the trigger module, making it unsuitable for small-area RF low-noise amplifiers.

[0006] Therefore, a new rising-edge trigger, trigger module, and low-noise amplifier are needed to solve the above problems. Summary of the Invention

[0007] To address the shortcomings of the aforementioned related technologies, this invention proposes a rising edge trigger, a trigger module, and a low-noise amplifier to solve the problem that the trigger module in the related technologies requires a large number of edge triggers to generate the delay signal required for each gain level during switching, resulting in an excessively large overall area of ​​the trigger module.

[0008] To solve the above-mentioned technical problems, in a first aspect, the present invention provides a rising edge trigger, which includes a first inverting circuit, a first field-effect transistor, a first inverter, an RC charging circuit, a second inverting circuit, a Schmitt trigger, and a third inverting circuit.

[0009] The input terminal of the first inverter circuit is used to receive a 1-bit excitation signal; the first inverter circuit is used to shape the received excitation signal.

[0010] The gate of the first field-effect transistor is connected to the output terminal of the first inverting circuit, and the source of the first field-effect transistor is grounded.

[0011] The input terminal of the first inverter is connected to the output terminal of the first inverter circuit;

[0012] The first input terminal of the RC charging circuit is connected to the output terminal of the first inverter, and the second input terminal of the RC charging circuit is used to connect to the first operating voltage; the RC charging circuit is used to charge and gradually increase the charging voltage.

[0013] The input terminal of the second inverter circuit is connected to the drain of the first field-effect transistor and the output terminal of the RC charging circuit, respectively; the second inverter circuit is used to generate a delay signal with a preset time width;

[0014] The input of the Schmitt trigger is connected to the output of the second inverting circuit; the Schmitt trigger is used to shape the delayed signal with a preset time width generated by the second inverting circuit.

[0015] The input terminal of the third inverting circuit is connected to the output terminal of the Schmitt trigger, and the output terminal of the third inverting circuit is used to output a delay control signal; the third inverting circuit is used to shape the delay signal after it has been shaped by the Schmitt trigger.

[0016] Preferably, the first inverter circuit includes a second inverter and a third inverter;

[0017] The input terminal of the second inverter serves as the input terminal of the first inverter circuit;

[0018] The input terminal of the third inverter is connected to the output terminal of the second inverter, and the output terminal of the third inverter serves as the output terminal of the first inverter circuit.

[0019] Preferably, the RC charging circuit includes a resistor, a first capacitor, and a second capacitor;

[0020] The first end of the resistor serves as the first input terminal of the RC charging circuit, and the second end of the resistor serves as the output terminal of the RC charging circuit.

[0021] The first terminal of the first capacitor serves as the second input terminal of the RC charging circuit, and the second terminal of the first capacitor is connected to the second terminal of the resistor.

[0022] The first terminal of the second capacitor is connected to the second terminal of the resistor, and the second terminal of the second capacitor is grounded.

[0023] Preferably, the second inverter circuit includes a fourth inverter and a fifth inverter;

[0024] The input terminal of the fourth inverter serves as the input terminal of the second inverter circuit;

[0025] The input terminal of the fifth inverter is connected to the output terminal of the fourth inverter, and the output terminal of the fifth inverter serves as the output terminal of the second inverter circuit.

[0026] Preferably, the Schmitt trigger includes a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, and a seventh field-effect transistor;

[0027] The gates of the second field-effect transistor, the third field-effect transistor, the fourth field-effect transistor, and the fifth field-effect transistor are connected and together serve as the input terminal of the Schmitt trigger;

[0028] The source of the second field-effect transistor is used to connect to the second operating voltage;

[0029] The source of the third field-effect transistor is connected to the drain of the second field-effect transistor;

[0030] The drain of the fourth field-effect transistor is connected to the drain of the third field-effect transistor and together they serve as the output terminal of the Schmitt trigger.

[0031] The drain of the fifth field-effect transistor is connected to the source of the fourth field-effect transistor, and the source of the fifth field-effect transistor is grounded.

[0032] The source of the sixth field-effect transistor is connected to the drain of the second field-effect transistor, and the drain of the sixth field-effect transistor is grounded.

[0033] The source of the seventh field-effect transistor is connected to the source of the fourth field-effect transistor, the drain of the seventh field-effect transistor is used to connect to the third operating voltage, and the gate of the seventh field-effect transistor and the gate of the sixth field-effect transistor are respectively connected to the drain of the third field-effect transistor.

[0034] Preferably, the third inverter circuit includes a sixth inverter and a seventh inverter;

[0035] The input terminal of the sixth inverter serves as the input terminal of the third inverter circuit;

[0036] The input terminal of the seventh inverter is connected to the output terminal of the sixth inverter, and the output terminal of the seventh inverter serves as the output terminal of the third inverter circuit.

[0037] Secondly, the present invention provides a trigger module, which includes a MIPI controller and a rising edge trigger as described above; the MIPI controller is used to generate a 1-bit excitation signal.

[0038] Thirdly, the present invention provides a low-noise amplifier comprising the trigger module described above.

[0039] Compared with related technologies, the rising edge trigger in this invention, by designing a first inverting circuit, a first field-effect transistor, a first inverter, an RC charging circuit, a second inverting circuit, a Schmitt trigger, and a third inverting circuit, and defining the connection method and function of each device, only requires a 1-bit register to control a 1-bit rising edge trigger to generate a delay signal, thereby reducing the number of rising edge triggers in the trigger module and reducing the overall area of ​​the trigger module. At the same time, it can also detect changes in the register and generate the delay signal required for each gain level of the low-noise amplifier during switching based on the changes in the register, thereby improving the response speed of the low-noise amplifier during power-on and switching. Attached Figure Description

[0040] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0041] Figure 1 Circuit diagram of a radio frequency low-noise amplifier provided for related technologies;

[0042] Figure 2 Schematic diagram of the trigger module provided for related technologies;

[0043] Figure 3 A circuit diagram of a rising-edge trigger provided for an embodiment of the present invention;

[0044] Figure 4 The circuit diagram of the Schmitt trigger in the rising edge trigger provided in the embodiment of the present invention;

[0045] Figure 5 Timing diagram of a rising edge trigger provided in an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram illustrating the working principle of the trigger module provided in an embodiment of the present invention. Detailed Implementation

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0048] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] Example 1

[0051] This invention provides a rising edge trigger 100, such as... Figure 3 As shown, it includes a first inverter circuit 1, a first field-effect transistor M1, a first inverter INV1, an RC charging circuit 2, a second inverter circuit 3, a Schmitt trigger SMT, and a third inverter circuit 4.

[0052] The input terminal of the first inverting circuit 1 serves as the input terminal VIN of the rising edge trigger 100 and is used to receive a 1-bit excitation signal. The first inverting circuit 1 is used to shape the received excitation signal and improve anti-interference performance. The 1-bit excitation signal is generated by an external MIPI controller.

[0053] The gate of the first field-effect transistor M1 is connected to the output terminal of the first inverting circuit 1, and the source of the first field-effect transistor M1 is grounded. The first field-effect transistor M1 is an N-channel transistor, also known as an N-channel field-effect transistor or an NMOS transistor.

[0054] The input terminal of the first inverter INV1 is connected to the output terminal of the first inverter circuit 1.

[0055] The first input terminal of the RC charging circuit 2 is connected to the output terminal of the first inverter INV1, and the second input terminal of the RC charging circuit 2 is used to connect to the first operating voltage VDD1; the RC charging circuit 2 is used to charge and gradually increase the charging voltage to form a smooth ramp waveform.

[0056] The input terminal of the second inverter circuit 3 is connected to the drain of the first field-effect transistor M1 and the output terminal of the RC charging circuit 2, respectively; the second inverter circuit 3 is used to generate a delay signal with a preset time width.

[0057] The input of the Schmitt trigger SMT is connected to the output of the second inverting circuit 3; the Schmitt trigger SMT is used to shape the delayed signal with a preset time width generated by the second inverting circuit 3, so as to shape the delayed signal into a steeper rising edge and falling edge.

[0058] The input of the third inverting circuit 4 is connected to the output of the Schmitt trigger SMT. The output of the third inverting circuit 4 serves as the output VOUT of the rising edge trigger 100 and is used to output the delay control signal. The third inverting circuit 4 is used to shape the delay signal after it has been shaped by the Schmitt trigger SMT, and the shaped signal is used to obtain the delay control signal.

[0059] In this embodiment, the first inverter circuit 1 includes a second inverter INV2 and a third inverter INV3.

[0060] The input terminal of the second inverter INV2 serves as the input terminal of the first inverter circuit 1.

[0061] The input terminal of the third inverter INV3 is connected to the output terminal of the second inverter INV2, and the output terminal of the third inverter INV3 serves as the output terminal of the first inverter circuit 1.

[0062] The RC charging circuit 2 includes a resistor R, a first capacitor C1, and a second capacitor C2.

[0063] The first end of resistor R serves as the first input terminal of RC charging circuit 2, and the second end of resistor R serves as the output terminal of RC charging circuit 2.

[0064] The first terminal of the first capacitor C1 serves as the second input terminal of the RC charging circuit 2, and the second terminal of the first capacitor C1 is connected to the second terminal of the resistor R.

[0065] The first terminal of the second capacitor C2 is connected to the second terminal of the resistor R, and the second terminal of the second capacitor C2 is grounded.

[0066] The second inverter circuit 3 includes a fourth inverter INV4 and a fifth inverter INV5.

[0067] The input terminal of the fourth inverter INV4 serves as the input terminal of the second inverter circuit 3.

[0068] The input terminal of the fifth inverter INV5 is connected to the output terminal of the fourth inverter INV4, and the output terminal of the fifth inverter INV5 serves as the output terminal of the second inverter circuit 3.

[0069] like Figure 4 As shown, the Schmitt trigger (SMT) includes a second field-effect transistor M2, a third field-effect transistor M3, a fourth field-effect transistor M4, a fifth field-effect transistor M5, a sixth field-effect transistor M6, and a seventh field-effect transistor M7.

[0070] The gates of the second field-effect transistor M2, the third field-effect transistor M3, the fourth field-effect transistor M4, and the fifth field-effect transistor M5 are connected and together serve as the input terminal Vin of the Schmitt trigger SMT.

[0071] The source of the second field-effect transistor M2 is used to connect to the second operating voltage VDD2.

[0072] The source of the third field-effect transistor M3 is connected to the drain of the second field-effect transistor M2.

[0073] The drain of the fourth field-effect transistor M4 is connected to the drain of the third field-effect transistor M3, and together they serve as the output terminal Vout of the Schmitt trigger SMT.

[0074] The drain of the fifth field-effect transistor M5 is connected to the source of the fourth field-effect transistor M4, and the source of the fifth field-effect transistor M5 is grounded.

[0075] The source of the sixth field-effect transistor M6 is connected to the drain of the second field-effect transistor M2, and the drain of the sixth field-effect transistor M6 is grounded.

[0076] The source of the seventh field-effect transistor M7 is connected to the source of the fourth field-effect transistor M4. The drain of the seventh field-effect transistor M7 is used to connect to the third operating voltage VDD3. The gate of the seventh field-effect transistor M7 and the gate of the sixth field-effect transistor M6 are respectively connected to the drain of the third field-effect transistor M3.

[0077] The third inverter circuit 4 includes a sixth inverter INV6 and a seventh inverter INV7;

[0078] The input terminal of the sixth inverter INV6 serves as the input terminal of the third inverter circuit 4;

[0079] The input terminal of the seventh inverter INV7 is connected to the output terminal of the sixth inverter INV6, and the output terminal of the seventh inverter INV7 serves as the output terminal of the third inverter circuit 4.

[0080] like Figure 5 As shown, the top line is the timing line of the input terminal VIN of the rising edge flip-flop 100, the middle line is the timing line of node A of the rising edge flip-flop 100, and the bottom line is the timing line of the output terminal VOUT of the rising edge flip-flop 100.

[0081] In this embodiment, the rising edge trigger 100 works as follows: The 1-bit excitation signal generated by the external MIPI controller is first shaped by the second inverter INV2 and the third inverter INV3 in the first inverter circuit 1, which also improves the anti-interference performance; the shaped signal passes through the first field-effect transistor M1. When the shaped signal is at a high potential, the first field-effect transistor M1 is turned on, pulling the voltage of node A down to zero; the shaped signal is then flipped by the first inverter INV1 and output to the RC charging circuit 2; for example, after the 52MHz frequency signal ends and becomes low potential, the potential of resistor R becomes high potential. At this time, the first capacitor C1 and the second capacitor C2 pass through... As resistor R gradually charges, the voltage across the first capacitor C1 and the second capacitor C2 gradually increases, forming a smooth rising waveform. This waveform then passes through the fourth inverter INV4 and the fifth inverter INV5 in the second inverter circuit 3, reaching node N and generating a delay signal with a certain or preset time width. Finally, the waveform edges at node N are shaped into steeper rising and falling edges by a Schmitt trigger SMT. This is then further shaped by the sixth inverter INV6 and the seventh inverter INV7 in the third inverter circuit 4 to output the final delay control signal. This signal controls the fast power-on switching of the common-gate transistor and common-source transistor in the low-noise amplifier, thus achieving the fast power-on and switching requirements of the low-noise amplifier.

[0082] Compared with related technologies, the rising edge trigger 100 in this invention is designed with a first inverting circuit 1, a first field-effect transistor M1, a first inverter INV1, an RC charging circuit 2, a second inverting circuit 3, a Schmitt trigger SMT, and a third inverting circuit 4, and the connection method and function of each device are defined. In this way, only 1 bit of register is needed to control 1 bit of rising edge trigger 100 to generate a delay signal, thereby reducing the number of rising edge triggers 100 in the trigger module and reducing the overall area of ​​the trigger module. At the same time, it can also detect changes in the register and generate the delay signal required for each gain level of the low noise amplifier during the switching process according to the changes in the register, so as to improve the response speed of the low noise amplifier during power-on and switching.

[0083] Example 2

[0084] This embodiment provides a trigger module 200, such as Figure 6 As shown, it includes a MIPI controller 201 and a rising edge trigger 100 as described in Embodiment 1.

[0085] The MIPI controller 201 is used to generate a 1-bit excitation signal.

[0086] In this embodiment, the working principle of the trigger module 200 is as follows: the MIPI controller 201 generates a 1-bit excitation signal to control the 1-bit rising edge trigger 100, so that the rising edge trigger 100 generates a delay signal. That is, the input terminal of the rising edge trigger 100 is controlled by a 1-bit register and generates a delay signal, thereby controlling the fast power-on switching of the common gate transistor and common source transistor of the low noise amplifier, so as to realize the fast power-on and switching requirements of the low noise amplifier.

[0087] Since the trigger module 200 in this embodiment includes the rising edge trigger 100 in embodiment one, it can also achieve the technical effect achieved by the rising edge trigger 100 in embodiment one, which will not be elaborated here.

[0088] Example 3

[0089] This embodiment provides a low-noise amplifier, which includes the trigger module 200 from Embodiment 2.

[0090] The low-noise amplifier also includes, for example, Figure 1 The RF low-noise amplifier circuit shown has an output terminal of rising edge trigger 100 connected to the gate of a fast-power-on switching field-effect transistor, so as to control the fast power-on and switching of the common-gate transistor and the common-source transistor through the delay control signal BSTP.

[0091] Since the low-noise amplifier in this embodiment includes the trigger module 200 in embodiment two, it can also achieve the technical effect achieved by the trigger module 200 in embodiment two, which will not be elaborated here.

[0092] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. A rising-edge trigger, characterized in that, The rising edge trigger includes a first inverting circuit, a first field-effect transistor, a first inverter, an RC charging circuit, a second inverting circuit, a Schmitt trigger, and a third inverting circuit; The input terminal of the first inverter circuit is used to receive a 1-bit excitation signal; the first inverter circuit is used to shape the received excitation signal. The gate of the first field-effect transistor is connected to the output terminal of the first inverting circuit, and the source of the first field-effect transistor is grounded. The input terminal of the first inverter is connected to the output terminal of the first inverter circuit; The first input terminal of the RC charging circuit is connected to the output terminal of the first inverter, and the second input terminal of the RC charging circuit is used to connect to the first operating voltage; the RC charging circuit is used to charge and gradually increase the charging voltage. The input terminal of the second inverter circuit is connected to the drain of the first field-effect transistor and the output terminal of the RC charging circuit, respectively; the second inverter circuit is used to generate a delay signal with a preset time width; The input of the Schmitt trigger is connected to the output of the second inverting circuit; the Schmitt trigger is used to shape the delayed signal with a preset time width generated by the second inverting circuit. The input terminal of the third inverting circuit is connected to the output terminal of the Schmitt trigger, and the output terminal of the third inverting circuit is used to output a delay control signal; the third inverting circuit is used to shape the delay signal after it has been shaped by the Schmitt trigger.

2. The rising-edge trigger as described in claim 1, characterized in that, The first inverter circuit includes a second inverter and a third inverter; The input terminal of the second inverter serves as the input terminal of the first inverter circuit; The input terminal of the third inverter is connected to the output terminal of the second inverter, and the output terminal of the third inverter serves as the output terminal of the first inverter circuit.

3. The rising-edge trigger as described in claim 1, characterized in that, The RC charging circuit includes a resistor, a first capacitor, and a second capacitor. The first end of the resistor serves as the first input terminal of the RC charging circuit, and the second end of the resistor serves as the output terminal of the RC charging circuit. The first terminal of the first capacitor serves as the second input terminal of the RC charging circuit, and the second terminal of the first capacitor is connected to the second terminal of the resistor. The first terminal of the second capacitor is connected to the second terminal of the resistor, and the second terminal of the second capacitor is grounded.

4. The rising-edge trigger as described in claim 1, characterized in that, The second inverter circuit includes a fourth inverter and a fifth inverter; The input terminal of the fourth inverter serves as the input terminal of the second inverter circuit; The input terminal of the fifth inverter is connected to the output terminal of the fourth inverter, and the output terminal of the fifth inverter serves as the output terminal of the second inverter circuit.

5. The rising-edge trigger as described in claim 1, characterized in that, The Schmitt trigger includes a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, and a seventh field-effect transistor; The gates of the second field-effect transistor, the third field-effect transistor, the fourth field-effect transistor, and the fifth field-effect transistor are connected and together serve as the input terminal of the Schmitt trigger; The source of the second field-effect transistor is used to connect to the second operating voltage; The source of the third field-effect transistor is connected to the drain of the second field-effect transistor; The drain of the fourth field-effect transistor is connected to the drain of the third field-effect transistor and together they serve as the output terminal of the Schmitt trigger. The drain of the fifth field-effect transistor is connected to the source of the fourth field-effect transistor, and the source of the fifth field-effect transistor is grounded. The source of the sixth field-effect transistor is connected to the drain of the second field-effect transistor, and the drain of the sixth field-effect transistor is grounded. The source of the seventh field-effect transistor is connected to the source of the fourth field-effect transistor, the drain of the seventh field-effect transistor is used to connect to the third operating voltage, and the gate of the seventh field-effect transistor and the gate of the sixth field-effect transistor are respectively connected to the drain of the third field-effect transistor.

6. The rising-edge trigger as described in claim 1, characterized in that, The third inverter circuit includes a sixth inverter and a seventh inverter; The input terminal of the sixth inverter serves as the input terminal of the third inverter circuit; The input terminal of the seventh inverter is connected to the output terminal of the sixth inverter, and the output terminal of the seventh inverter serves as the output terminal of the third inverter circuit.

7. A trigger module, characterized in that, The trigger module includes a MIPI controller and a rising-edge trigger as described in any one of claims 1 to 6; the MIPI controller is used to generate a 1-bit excitation signal.

8. A low-noise amplifier, characterized in that, The low-noise amplifier includes the trigger module as described in claim 7.

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