Multi-channel radio frequency signal source device and implementation method

Abstract

The invention relates to the technical field of radio frequency electronics, and discloses a multi-channel radio frequency signal source device and an implementation method, and the device comprises a satellite receiver, a frequency reference source, a clock signal source, a multi-channel radio frequency signal source, a frequency monitoring module and a phase monitoring module. The frequency reference source locks a satellite signal generation benchmark; the clock signal source generates a driving clock based on a reference; the multi-path radio frequency signal source generates multi-path radio frequency signals by using a driving clock based on a direct digital frequency synthesis principle; the phase monitoring module measures signal phase difference through IQ phase discrimination and feeds back the signal phase difference, and realizes closed-loop phase locking in cooperation with multiple paths of radio frequency signal sources. A two-stage driving framework is adopted, synchronous frequency modulation of multiple paths of signals can be achieved by adjusting a clock, the phase relation is not changed, and automatic phase recovery after independent frequency modulation can be achieved through phase compensation. The invention has the advantages of continuous frequency modulation phase, stable amplitude, no need of automatic level control, low phase noise, high phase resolution and the like.

Description

Technical Field

[0001] This invention relates to the field of radio frequency electronics technology, specifically to a multi-channel radio frequency signal source device and its implementation method. Background Technology

[0002] In large scientific facilities such as synchrotron radiation sources, electron beams are accelerated and replenished by the electric field established by a radio frequency resonant cavity. To maintain the stable operation of electrons in different subsystems such as linear accelerators, intensifiers, and storage rings, a master oscillator is required to generate multiple radio frequency signals of specific frequencies. These signals have specific technical requirements for frequency and phase stability and tuning resolution, typically requiring a frequency tuning resolution better than 10 MHz and a phase tuning resolution better than 0.1 degrees.

[0003] Currently, the technical solutions to meet the above-mentioned requirements for multiple radio frequency signals typically employ multiple independent commercial signal sources or use general-purpose multi-channel signal source equipment. These devices generally achieve frequency synchronization by connecting to the same external frequency reference source.

[0004] However, the aforementioned existing technical solutions have shortcomings in practical applications. When commercial signal sources based on the phase-locked loop (PLL) principle adjust the frequency, the phase and frequency often cannot maintain continuous change, easily resulting in phase jumps. Furthermore, to maintain stable output amplitude, these devices typically rely on automatic level control circuits, which introduce transient response overshoot, thus affecting system stability.

[0005] Furthermore, the existing architecture struggles to simultaneously accommodate the synchronous and independent frequency modulation requirements of multiple signals. During long-term operation of a synchrotron radiation source, it is sometimes necessary to synchronously adjust the frequencies of all signals to address orbital drift caused by changes in ambient temperature, and at other times, independent tuning of a single branch is required. In existing technologies, when a signal is individually adjusted and then restored to its original frequency, the lack of a closed-loop phase monitoring and feedback mechanism often results in the phase relationship between that signal and other signals becoming random, failing to automatically return to the locked state before adjustment. This increases the difficulty of system recovery. Simultaneously, general-purpose commercial equipment is often not optimized for specific frequencies, and achieving high-performance indicators such as low phase noise requires significant equipment costs. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a multi-channel radio frequency signal source device and implementation method, which solves the problems that existing commercial signal sources cannot simultaneously meet the requirements of independent frequency modulation and synchronous frequency modulation, the phase and frequency discontinuity during frequency modulation, and the inability to automatically recover and accurately lock the phase relationship between multiple channels after independent frequency modulation.

[0007] To achieve the above objectives, the first aspect of the present invention provides a multi-channel radio frequency signal source device, including a satellite receiver, a frequency reference source, a clock signal source, a multi-channel radio frequency signal source, a frequency monitoring module, and a phase monitoring module.

[0008] Among them, the satellite receiver is used to receive the frequency standard signal of the external satellite navigation system and output it to the frequency reference source;

[0009] The frequency reference source is used to lock onto the signal output by the satellite receiver and generate frequency reference signals, which are then output to the clock signal source and the frequency monitoring module respectively. The clock signal source is used to receive the frequency reference signal, generate a driving clock signal, and output it to multiple radio frequency signal sources. The multi-channel radio frequency signal source is based on the direct digital frequency synthesis principle and uses the driving clock signal to generate multiple radio frequency signals with adjustable frequency and phase. The radio frequency signals include a first signal and other signals. The frequency monitoring module uses the frequency reference signal as a reference to measure the frequency of the radio frequency signal; the phase monitoring module is independent of the signal output link of the multi-channel radio frequency signal source, and is used to measure the phase difference and amplitude information of the other signals relative to the first signal with the first signal as a reference, and feeds back the measurement results to the multi-channel radio frequency signal source for phase locking.

[0010] In one implementation, the frequency reference source is a rubidium atomic clock. This frequency reference source is configured with a hold mode, which, when the satellite receiver signal is interrupted, independently outputs a frequency reference signal with a frequency of 5MHz to 15MHz using an internal control loop.

[0011] In one implementation, the clock signal source is configured to adjust the frequency of the driving clock signal. Based on the direct digital frequency synthesis principle, the output signal frequency is determined by the frequency control word, the driving clock signal frequency, and the number of bits in the accumulator. By adjusting the frequency of the driving clock signal output by the clock signal source, the frequencies of all the radio frequency signals output by the multi-channel radio frequency signal sources are adjusted synchronously and proportionally, while maintaining the relative phase relationship between the signals.

[0012] In one implementation, the multi-channel RF signal source employs a separate architecture for the field-programmable gate array (FPGA) and the high-speed digital-to-analog converter (DAC). The functional module of the direct digital frequency synthesis principle is implemented in the FPGA, including a frequency control word, a phase control word, and a digital lookup table. The high-speed DAC uses the driving clock signal as the sampling clock, with a bit depth of at least 16 bits. Simultaneously, a clock chip controls the deterministic delay mechanism of the serial JESD204B protocol, the timing of the high-speed DAC, and the FPGA, ensuring that the functional module of the direct digital frequency synthesis principle is in a defined starting position during each power-on initialization.

[0013] In one implementation, the phase monitoring module includes an IQ phase detector, an analog-to-digital converter (ADC), and a microcontroller unit. The IQ phase detector receives the first signal and the other signals, and outputs a quadrature differential signal representing the in-phase and quadrature components of the phase-detection signal. The ADC digitizes the quadrature differential signal with a minimum of 24 bits and a sampling rate of no more than 1 MSPS. The microcontroller unit is internally configured with a digital low-pass filter for calculating the phase difference between the other signals and the first signal based on the quadrature differential signal.

[0014] A second aspect of the present invention provides a method for implementing a multi-channel radio frequency signal source device, the method being applied to the aforementioned multi-channel radio frequency signal source device, comprising the following steps: The system uses a satellite receiver to receive frequency standard signals from an external satellite navigation system and uses a frequency reference source to lock onto the frequency standard signals to provide a stable frequency reference signal. A driving clock signal is generated based on the frequency reference signal using a clock signal source; Driven by the driving clock signal, a multi-channel radio frequency signal source outputs multiple radio frequency signals with the same initial frequency and phase lock. The radio frequency signals include a first signal and other signals. Using the first signal as a reference, the phase monitoring module measures and records the initial phase difference of the other signals relative to the first signal; The multi-channel radio frequency signal source adjusts the frequency of one of the other signals, and after the frequency adjustment is completed, restores the frequency of one of the other signals to the initial frequency; The phase monitoring module measures the current phase difference of one of the other signals after frequency recovery relative to the first signal; Calculate the difference between the current phase difference and the initial phase difference, adjust the phase of the corresponding channel in the multi-channel radio frequency signal source until the measured phase difference is restored to the initial phase difference, and complete the phase locking.

[0015] In one implementation, the phase monitoring module measures the phase difference using the quadrature demodulation principle: acquiring the in-phase component data and quadrature component data of one of the other signals relative to the first signal; calculating the arctangent of the ratio of the quadrature component data to the in-phase component data to obtain the phase measurement value; and performing digital low-pass filtering on the phase measurement value to obtain the current phase difference.

[0016] In one implementation, the method further includes a synchronous frequency modulation step: when it is necessary to synchronously adjust the frequency of all the radio frequency signals output by the multi-channel radio frequency signal source, the frequency of the driving clock signal output by the clock signal source is adjusted so that the frequency of all the radio frequency signals changes synchronously in proportion, while maintaining the phase difference between each signal unchanged.

[0017] In one implementation, the method uses timing control to ensure that the functional module of the direct digital frequency synthesis principle is in a defined starting position each time it is powered on and initialized, thus guaranteeing the initial phase lock of the output RF signal. During frequency and phase adjustment, the output amplitude remains stable, and automatic level control is not executed.

[0018] This invention provides a multi-channel radio frequency signal source device and its implementation method. It has the following beneficial effects: 1. This invention employs a two-stage signal driving architecture. The first stage uses a clock signal source to provide an adjustable driving clock, while the second stage utilizes a multi-channel RF signal source built upon the principle of direct digital frequency synthesis. This allows the device to achieve proportional synchronous frequency modulation of multiple signals while maintaining their relative phase relationship by adjusting the first-stage driving clock frequency; and also to achieve independent frequency adjustment of a single signal by adjusting the digital parameters of the second stage. This solves the technical challenge of existing commercial signal source solutions being unable to simultaneously achieve the flexibility of independent frequency modulation and the consistency of synchronous frequency modulation.

[0019] 2. This invention introduces an independent phase monitoring module and feedback closed-loop control, utilizing an IQ phase detector in conjunction with a high-bit-value analog-to-digital converter for high-precision phase measurement. After a single signal undergoes independent frequency adjustment and recovers to its initial frequency, the system can accurately compensate in the digital domain by measuring the deviation between the current phase difference and the initial phase difference. This achieves automatic recovery and locking of phase relationships between multiple channels, eliminating the problem of random phase slippage caused by frequency adjustment and meeting the requirements of precise synchronous control.

[0020] 3. This invention employs direct digital frequency synthesis logic implemented within a field-programmable gate array (FPGA) in hardware, coupled with a high-speed digital-to-analog converter (DAC) of at least 16 bits. Timing control ensures the determinism of the initial phase upon each power-on startup. Compared to traditional phase-locked loop (PLL) architectures, it maintains phase continuity during frequency and phase modulation, and maintains stable output amplitude without the need for additional automatic level control circuitry. It also features low phase noise and low spurious spectral characteristics. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall structure of the multi-channel radio frequency signal source of the present invention; Figure 2 This is a schematic diagram of the multi-channel radio frequency signal source implementation method of the present invention; Figure 3 This is a schematic diagram of the phase monitoring module implementation method of the present invention; Figure 4 This is a schematic diagram of the automated process for restoring the original phase relationship of a signal after frequency modulation according to the present invention. Figure 5 The phase noise and spurious spectrum of the 499.8MHz signal output from the multi-channel radio frequency signal source of this invention; Figure 6 This is a test diagram showing the frequency and phase continuity of the multi-channel radio frequency signal source output signal during frequency modulation according to the present invention. Detailed Implementation

[0022] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] See attached document Figure 1 The multi-channel radio frequency signal source device provided by the present invention mainly includes: a satellite receiver, a frequency reference source, a clock signal source, a multi-channel radio frequency signal source, a frequency monitoring module, and a phase monitoring module.

[0024] The satellite receiver, as the system's external standard input unit, is used to receive frequency standards from external satellite navigation systems. These external satellite navigation systems include the BeiDou Navigation Satellite System or the Global Positioning System. The frequency standards received by the satellite receiver have long-term stability and are output to the subsequent frequency reference source.

[0025] The frequency reference source serves as the local frequency reference center for the entire device. Connected to the satellite receiver, it locks onto the signal output by the receiver, maintaining frequency synchronization through a disciplined local oscillator. The frequency reference source generates a highly stable frequency reference signal. This signal is split into two outputs: one to the clock signal source as a reference for clock synthesis, and the other to the frequency monitoring module as a gate reference for frequency measurement.

[0026] A clock signal source is connected between the frequency reference source and the multiple RF signal sources. The clock signal source receives the frequency reference signal output from the frequency reference source and uses this signal to synthesize a high-frequency drive clock signal. The frequency of the drive clock signal is higher than the frequency of the RF signals output from the multiple RF signal sources to meet the sampling theorem and spurious emission requirements. The clock signal source outputs the generated drive clock signal to the multiple RF signal sources.

[0027] The multi-channel RF signal source is the core signal generation unit of the device. Built on the principle of direct digital frequency synthesis, its input receives a driving clock signal from a clock signal source. Using this driving clock signal, the multi-channel RF signal source generates multiple RF signals with independently adjustable frequencies and phases. The RF signals include a first signal and other signals. In the system configuration, the first signal is defined as the phase reference, and the other signals are the signals whose phases are to be adjusted. All RF signals are generated by the internal digital logic of the multi-channel RF signal source and output after digital-to-analog conversion.

[0028] The frequency monitoring module is connected to the output terminals of both the multi-channel RF signal source and the frequency reference source. Using the frequency reference signal provided by the frequency reference source as a high-precision time base, the module performs real-time frequency counting measurements on the RF signals output from the multi-channel RF signal source. The measurement results are used to monitor the frequency accuracy of the output signals.

[0029] The phase monitoring module is independently located outside the signal generation link of the multi-channel RF signal source, forming part of the feedback control loop. The input terminals of the phase monitoring module are connected to the first signal and the other signals respectively. The phase monitoring module is used to measure the phase difference and amplitude information of the other signals relative to the first signal, using the first signal as a reference phase. The phase monitoring module feeds back the measured phase difference and amplitude data to the multi-channel RF signal source.

[0030] The above modules constitute a closed-loop control system. Based on the measurement results fed back by the phase monitoring module, the multiple RF signal sources adjust the phase control words within their corresponding channels to achieve precise phase control of other signals, thus achieving phase locking between the multiple signals. When frequency adjustment is required, the system coordinates the control of the clock signal source or the internal parameters of the multiple RF signal sources to achieve frequency change while maintaining the recoverable or unchanged phase relationship.

[0031] See attached document Figure 2 In the overall architecture of the aforementioned multi-channel radio frequency signal source device, the generation of the frequency reference and the construction of the clock signal adopt a two-stage driving architecture to balance long-term frequency stability and system frequency modulation flexibility.

[0032] As the first-level reference of the system, the frequency reference source is implemented using a rubidium atomic clock. This rubidium atomic clock is equipped with an external reference input interface, which connects to the preceding satellite receiver. The satellite receiver integrates a BeiDou Navigation Satellite System (BDS) receiver module and a Global Positioning System (GPS) receiver module, used to receive frequency standards from the satellite navigation systems and demodulate a frequency standard signal with long-term frequency stability better than 10E-15. The frequency reference source receives this frequency standard signal and uses an internal phase-locked loop to control the local temperature-controlled crystal oscillator and the rubidium physical packaging unit to discipline and lock the local output frequency to the satellite frequency standard.

[0033] To ensure system reliability under external environmental interference, the frequency reference source is configured with a hold mode. Specifically, when the satellite receiver output signal is normal, the frequency reference source is locked, and the output frequency tracks the external standard in real time. When the satellite receiver experiences signal interruption due to antenna obstruction or signal interference, the frequency reference source automatically switches to hold mode, using the digital control loop inside the rubidium atomic clock to maintain the frequency control voltage at the last moment, thereby independently and continuously outputting a 10MHz frequency reference signal. This configuration ensures that applications such as synchrotron radiation sources or phased array radars can maintain the continuity and accuracy of the system clock even when external timing signals are lost, achieving high-reliability reference redundancy.

[0034] The clock signal source constitutes the second-stage driver core of the system, with its input connected to the output of the frequency reference source. The clock signal source uses a received 10MHz low-phase-noise frequency reference signal as a reference and generates a drive clock signal with a frequency range between 3GHz and 12GHz through an internal wideband frequency synthesizer. In a specific embodiment of the invention, to meet the requirement of outputting a 499.8MHz RF signal, the frequency of the drive clock signal generated by the clock signal source is set to 4096MHz. This drive clock signal serves not only as the sampling clock for the high-speed digital-to-analog converter in the subsequent multi-channel RF signal source but also as the operating clock reference for the internal logic of the field-programmable gate array.

[0035] The clock signal source integrates a high-resolution fractional-division phase-locked loop circuit, enabling frequency fine-tuning, which is the hardware foundation for synchronous adjustment of multiple signals. When the multi-channel RF signal source operates based on the principle of direct digital frequency synthesis, its output signal frequency... With drive clock frequency and frequency control word Satisfying the relation ,in, This refers to the number of bits in the accumulator. When the system needs to synchronously change the frequency of all RF signals output from multiple RF signal sources (e.g., to adapt to changes in ambient temperature on the electronic track), it is not necessary to modify the frequency control word of each signal individually. Instead, it precisely changes the frequency of the driving clock signal by adjusting the division ratio or other control parameters of its internal phase-locked loop through the control of the clock signal source. Since all radio frequency signals share the same driving clock signal, changes in the driving clock signal frequency are proportionally transmitted to all output channels, thereby achieving synchronous adjustment of the frequencies of all signals while maintaining the relative phase relationship between each signal. For the specific phase-locked loop frequency synthesis circuit and frequency adjustment circuit within the clock signal source, those skilled in the art can implement them using existing low-noise frequency synthesizer solutions; the circuit details are well-known in the field and will not be elaborated upon here.

[0036] With the above configuration, the 10MHz signal provided by the frequency reference source is mainly used to ensure the reference transmission of frequency accuracy and phase noise performance, while the clock signal source provides the high-frequency sampling signal and synchronous frequency modulation mechanism required to drive the subsequent direct digital frequency synthesis core. Together, they constitute the high-precision time and frequency basic network of the multi-channel radio frequency signal source device.

[0037] See attached document Figure 2 The multi-channel RF signal source, as the core signal generation component of this system, adopts a hardware architecture that separates the field-programmable gate array (FPGA) from the high-speed digital-to-analog converter (DAC). This architecture mainly consists of a clock distribution network, an FPGA logic control unit, and a multi-channel high-speed DAC.

[0038] The multi-channel RF signal source operates based on the principle of direct digital frequency synthesis. To achieve precise control of the initial phase, the functional modules of the direct digital frequency synthesis principle do not use the numerically controlled oscillator integrated inside the digital-to-analog converter chip, but are all implemented in the internal logic of the field-programmable gate array.

[0039] Specifically, the field-programmable gate array (FPGA) is internally configured with multiple independent direct digital synthesis (DDS) modules, each corresponding to one radio frequency (RF) signal. These modules primarily include a frequency control word register, a phase control word register, a phase accumulator with at least 48 bits, and a digital lookup table.

[0040] During operation, the phase accumulator performs accumulation operations according to the frequency control word under the control of the driving clock. The accumulated result is added to the phase control word and used as an address index digital lookup table to output the corresponding digital sine wave data. This architecture, implemented inside the field-programmable gate array, allows the state of the phase accumulator to be controlled by a global reset signal, ensuring that the phase accumulators of all channels can be accurately reset to zero or other preset values ​​at the moment of system reset release.

[0041] In the digital-to-analog conversion stage, this embodiment employs a high-speed digital-to-analog converter with a bit depth of at least 16 bits and a sampling rate of at least 3 GSPS. In one specific embodiment, to meet the requirement of outputting a 499.8MHz RF signal, the sampling clock frequency of the high-speed digital-to-analog converter is set to 4096MHz. The high bit depth conversion accuracy significantly reduces quantization noise, resulting in spurious performance of the output signal that is superior to that of conventional commercial signal sources.

[0042] To ensure the deterministic timing of digital signals transmitted from the field-programmable gate array (FPGA) to the high-speed digital-to-analog converter (DAC), multiple RF signal sources utilize a clock chip to control the deterministic delay mechanism of the serial JESD204B protocol, the timing of the DAC, and the FPGA. The clock chip generates the reference clock and device clock required by the FPGA, using the signal output from the clock source as a reference. The system utilizes the deterministic delay mechanism defined in JESD204B protocol subclass 1 to align the local multi-frame clocks within the FPGA and DAC with the reference clock signal, establishing a fixed link delay. Combined with the FPGA's internal reset control of the phase accumulator, the functional modules based on the direct digital frequency synthesis principle are always in a defined starting position during each power-on initialization, ensuring that the initial phase of the output RF signal is always locked and consistent, eliminating the influence of power-on randomness on the phase relationship.

[0043] Furthermore, signal generation methods based on the principle of direct digital frequency synthesis possess inherent amplitude stability.

[0044] The amplitude of the output signal is directly determined by the digital code value sent from the field-programmable gate array to the high-speed digital-to-analog converter. During frequency or phase adjustment, as long as the digital amplitude setting remains unchanged, the amplitude of the analog signal output by the high-speed digital-to-analog converter remains stable, without relying on the automatic level control circuit of the feedback loop.

[0045] Actual measurements show that the output amplitude stability of this device is better than ±0.01dB during frequency and phase modulation, which simplifies the circuit structure and avoids the transient response problem introduced by analog automatic level control.

[0046] To achieve real-time monitoring of the output signal without affecting the main signal output, each RF output link of the multi-channel RF signal source is equipped with an RF power divider (or power distribution network). In this embodiment, the RF power divider adopts a three-way power divider structure, splitting each RF signal generated by the multi-channel RF signal source into three: one channel serves as the final output signal of the device, capable of carrying frequency and phase adjustment; the other two channels are transmitted to the frequency monitoring module and the phase monitoring module, respectively, for real-time frequency and phase measurement.

[0047] See attached document Figure 3 This embodiment details the implementation of the frequency monitoring module and the phase monitoring module. These two modules are independent of the signal generation links of the multiple radio frequency signal sources, forming a closed-loop monitoring feedback loop for the system.

[0048] The input terminals of the frequency monitoring module are connected to the RF output ports of the multiple RF signal sources and the output port of the frequency reference source, respectively. The frequency monitoring module uses the frequency reference signal output from the frequency reference source as the reference gate signal and employs a high-precision waveform counting circuit to measure the frequency of the RF signals. This module has a resolution better than 10 MHz and is used to monitor the frequency accuracy of each output signal in real time.

[0049] The phase monitoring module is used to measure the relative phase relationship between multiple signals. Its input signals include a first signal serving as a phase reference and the other signals being measured. In terms of hardware, the phase monitoring module mainly consists of an IQ phase detector, an analog-to-digital converter, and a microcontroller unit.

[0050] The input terminals of the IQ phase detector are connected to one of the first signal and one of the other signals.

[0051] The IQ phase detector performs quadrature demodulation on two input signals of the same frequency, and outputs two sets of quadrature differential signals representing the phase difference between the two signals, which correspond to the in-phase components of the phase detection signal, respectively. and orthogonal components Using orthogonal demodulation can preserve complete vector information, thus enabling accurate resolution of the full-cycle phase relationship from 0 to 360 degrees in subsequent processing.

[0052] The analog-to-digital converter is connected to the output of the IQ phase detector to acquire and digitize the quadrature differential signal.

[0053] To meet the high-resolution requirement of phase monitoring in this embodiment, the analog-to-digital converter uses a high-precision, low-speed conversion chip with a bit depth of at least 24 bits and a sampling rate of at least 1 MSPS. Since the first signal under test has the same or very close frequency to the other signals, the in-phase and quadrature components demodulated by the IQ phase detector exhibit DC levels or lower-frequency envelopes. Therefore, a lower sampling rate is sufficient to satisfy the Nyquist sampling theorem, while a quantization bit depth of at least 24 bits provides sufficient dynamic range, ensuring low quantization noise in the phase measurement.

[0054] The digitized in-phase and quadrature component data are transmitted to the micro control unit via an internal bus.

[0055] The microcontroller unit is the core of the data processing; it performs phase calculations based on the received data. Specifically, the microcontroller unit calculates the quadrature component data. In-phase component data The arctangent of the ratio, i.e., the calculation ,in, This represents the calculated original phase measurement value, which characterizes the phase difference angle between the other signals (the measured signal) and the first signal (the reference signal). The data representing the quadrature components are the digitized values ​​of the quadrature branches of the phase detection signal acquired by the analog-to-digital converter. The data representing the in-phase component is the digitized value of the in-phase branch of the phase detector signal acquired by the analog-to-digital converter. This represents the arctangent function operation, used to convert vector coordinates in the IQ plane rectangular coordinate system. Converting to angle values ​​in polar coordinates is typically performed in microcontroller units using a lookup table or CORDIC algorithm. This yields the original phase difference.

[0056] To support closed-loop phase locking, the microcontroller is equipped with a storage register to record and maintain the initial phase difference in the initial state of the system. After the frequency adjustment of a specific branch is completed, the micro control unit acquires the measured value at the current moment as the current phase difference. The logic unit inside the microcontroller performs a subtraction operation to calculate the difference between the current phase difference and the initial phase difference. ,in, This represents the difference between the current phase difference and the initial phase difference; The measured value at the current moment is used as the current phase difference. This represents the initial phase difference in the initial state of the system. Due to phase periodicity, the microcontroller performs a modulo operation on this difference to obtain the minimum phase deviation value.

[0057] To obtain stable, high-precision phase readings, the micro control unit is equipped with a digital low-pass filter. The raw phase measurement value is smoothed by this digital low-pass filter to remove high-frequency noise interference, thereby obtaining the final current phase difference.

[0058] In addition, the micro control unit also uses in-phase component data and quadrature component data to calculate amplitude information. ,in, It represents the amplitude information of the radio frequency signal, used to monitor the stability of the signal power intensity; This represents the squared value of the above in-phase component data; This represents the squared value of the above orthogonal component data; This represents the arithmetic square root operation. It enables synchronous monitoring of signal amplitude.

[0059] The phase monitoring module also utilizes the mathematical relationship between phase and frequency. ,in, This represents the amount of phase shift that accumulates over time due to frequency inconsistency. This indicates the frequency difference (i.e., frequency offset) between other signals and the first signal; The time variable representing the duration of the frequency difference; Twice the constant of pi, this is a proportionality coefficient used to convert frequency differences, measured in Hertz (Hz), into angular frequency differences, measured in radians per second (rad / s). This enables auxiliary frequency difference monitoring. When other signals exhibit slight frequency deviations from the first signal, the measured phase difference will linearly shift over time. The microcontroller unit monitors the rate of change of the phase difference per unit time to calculate the frequency difference between the two signals. This mechanism is used in subsequent phase recovery steps to determine whether the frequency has been accurately restored to match the reference signal.

[0060] The phase monitoring module feeds back the calculated precise phase difference and amplitude information to multiple RF signal sources via a communication interface for closed-loop phase locking. This module supports wideband input from 10MHz to 6GHz, with a measured phase resolution better than 0.01° and an amplitude resolution better than 0.01dB.

[0061] See attached document Figure 4 This embodiment elaborates on the multi-signal control strategy based on the above hardware architecture, mainly including system initialization, synchronous frequency modulation, and automatic phase recovery process after independent frequency modulation.

[0062] The system initialization phase is fundamental to establishing phase determinism. Through precise timing control, the multiple RF signal sources ensure that the functional modules based on the direct digital frequency synthesis principle are in a defined starting position each time the system starts. Specifically, the system uses a reference clock signal from the JESD204B protocol to synchronously reset the field-programmable gate arrays (FPGAs) and high-speed digital-to-analog converters (DACs) within the multiple RF signal sources. Within the same clock cycle after the reset signal is released, the phase accumulators of the direct digital frequency synthesis in all channels of the FPGA are simultaneously cleared or set to preset fixed initial values.

[0063] This hardware-level reset mechanism ensures that the initial phase of the RF signal is repeatable, rather than randomly generated, thus providing a unified physical reference for subsequent phase recovery operations.

[0064] During system operation, the device supports synchronous frequency modulation mode and independent frequency modulation and phase recovery mode to meet different application requirements.

[0065] When an application requires synchronous adjustment of the frequencies of all output signals (e.g., to accommodate the drift of electron orbits in a synchrotron radiation source due to changes in ambient temperature), the system executes a synchronous frequency modulation strategy. In this case, the control system keeps the frequency control word within the multi-channel RF signal source's field-programmable gate array unchanged, instead directly adjusting the frequency of the driving clock signal output by the clock signal source. Since all channels of the multi-channel RF signal source share the same driving clock signal, and the output frequency of the direct digital synthesis is linearly proportional to the driving clock frequency, a change in the driving clock frequency will cause the frequencies of all RF signals to change synchronously in the same proportion. During this process, because the digital logic state within the field-programmable gate array does not change relatively, the relative phase relationship between the signals remains unchanged, achieving a phase-slip-free overall frequency migration.

[0066] When it is necessary to perform independent testing or parameter adjustment for a specific branch, and restore the original phase synchronization state after adjustment, the system executes an independent frequency modulation and automatic phase recovery process. The specific steps are as follows: Step S1: Reference Establishment. An external frequency standard is received using a satellite receiver, and a disciplined frequency reference source is used to generate a highly stable frequency reference signal. This signal serves as the frequency and time reference for the entire system, ensuring consistency in telemetry and control.

[0067] Step S2: Clock generation. The clock signal source synthesizes a high-frequency drive clock signal based on the frequency reference signal and distributes it to multiple radio frequency signal sources.

[0068] Step S3: Initial Signal Output. Driven by the driving clock signal, the multi-channel RF signal source outputs multiple RF signals with consistent initial frequencies and phase locks according to preset frequency control words and phase control words. The RF signals include the first signal defined as the reference and the other signals to be measured.

[0069] Step S4: Initial State Recording. The phase monitoring module starts the measurement, using the first signal as a reference, and collects the in-phase and quadrature components of other signals in real time, calculates and records the initial phase difference of other signals relative to the first signal.

[0070] Step S5: Frequency Adjustment and Phase Sliding. Based on external commands, the multi-channel RF signal source modifies only the internal frequency control word of the field-programmable gate array (FPGA) corresponding to one of the other channels, changing its output frequency while keeping the frequency control words of the other channels unchanged. During the frequency change, because the frequency of this signal is inconsistent with the frequency of the first signal, the phase difference between them will accumulate linearly over time, resulting in phase slip. After the frequency adjustment operation is completed, the control system resets the frequency control word of this signal, restoring its frequency to the initial frequency consistent with the first signal.

[0071] Step S6: Residual Phase Measurement. Once the frequency returns to normal, phase slippage stops, but the phase difference between this signal and the first signal is now at a random current value. The phase monitoring module measures this signal again to obtain the current phase difference after frequency recovery. .

[0072] Step S7: Phase Compensation and Recovery. The control system or microcontroller calculates the difference between the current phase difference and the initial phase difference. Subsequently, the control system calculates the corresponding phase compensation amount based on this difference and then superimposes this compensation amount into the phase control word of the corresponding channel of the multiple RF signal sources. The update of the phase control word drives an instantaneous shift in the phase of the output signal until the measured value fed back by the phase monitoring module returns to equal the initial phase difference. This completes phase locking.

[0073] Throughout the frequency adjustment (step S5) and phase adjustment (step S7) processes described above, thanks to the technical characteristics of direct digital frequency synthesis, the amplitude of the output signal from the multi-channel RF signal source depends only on the digital amplitude control word. Therefore, without automatic level control, the amplitude of the output signal remains stable, avoiding amplitude fluctuations that occur when traditional analog signal sources are frequency- and phase-modulated, as well as overshoot or oscillation phenomena introduced by the automatic level control circuit.

[0074] See attached document Figure 5Thanks to the aforementioned high-precision clock source drive and the optimized direct digital frequency synthesis logic within the field-programmable gate array, the system maintains a low noise floor when outputting high-frequency RF signals. Testing and analysis show that the integral phase noise of the signal is low in the 10Hz to 10MHz integration range, and there are no significant spurious signals within the band. This indicates that the output signal of this device has high spectral purity, which can meet the requirements of applications with high time-frequency jitter requirements, such as synchrotron radiation sources.

[0075] See attached document Figure 6 During the test, a 1kHz frequency step command was executed on the output signal. At the instant the frequency modulation occurred, both the frequency change curve and the phase change curve of the output signal exhibited smooth and continuous transition characteristics, without any phase jumps or frequency overshoots caused by phase-locked loop loss or analog circuit switching. This excellent continuity proves that the direct digital frequency synthesis architecture used in this invention can maintain phase continuity during dynamic adjustment, thereby ensuring the stability of the electron beam during the frequency modulation process of the accelerating electric field.

Claims

1. A multi-channel radio frequency signal source device, characterized in that, include: A satellite receiver, used to receive frequency standard signals from external satellite navigation systems; A frequency reference source, which is used to lock onto the frequency standard signal and generate a frequency reference signal; A clock signal source, which receives the frequency reference signal and generates a driving clock signal; A multi-channel radio frequency signal source, based on the principle of direct digital frequency synthesis, uses the driving clock signal to generate multiple radio frequency signals with adjustable frequency and phase, the radio frequency signals including a first signal and other signals; The frequency monitoring module uses the frequency reference signal as a reference to measure the frequency of the radio frequency signal, thereby monitoring the frequency accuracy of the radio frequency signal. The phase monitoring module, which is independent of the signal output link of the multi-channel radio frequency signal source, is used to measure the phase difference and amplitude information of the other channels relative to the first channel signal with the first channel signal as a reference, and feeds back the phase difference and amplitude information to the multi-channel radio frequency signal source for phase locking.

2. The multi-channel radio frequency signal source device according to claim 1, characterized in that, The frequency reference source is a rubidium atomic clock, and the frequency reference source locks onto the frequency standard signal by controlling a local oscillator; Furthermore, the frequency reference source can independently output the frequency reference signal when the satellite receiver signal is interrupted, and the frequency reference signal has a frequency of 5MHz-15MHz.

3. The multi-channel radio frequency signal source device according to claim 1, characterized in that, The clock signal source receives the frequency reference signal and generates the frequency-adjustable drive clock signal. By adjusting the frequency of the drive clock signal, the frequency of all the radio frequency signals output by the multi-channel radio frequency signal source is synchronously adjusted.

4. The multi-channel radio frequency signal source device according to claim 1, characterized in that, The multi-channel radio frequency signal source includes a field-programmable gate array (FPGA) and a high-speed digital-to-analog converter (DAC). The FPGA and the DAC use the driving clock signal to generate multiple radio frequency signals with adjustable frequency and phase. The functional module of the direct digital frequency synthesis principle is implemented in the field programmable gate array. The functional module includes a frequency control word, a phase control word, and a digital lookup table. The high-speed digital-to-analog converter uses the driving clock signal as the sampling clock, with a bit depth of not less than 16 bits. The multi-channel radio frequency signal source uses a clock chip to control the deterministic delay mechanism of the serial JESD204B protocol, the timing of the high-speed digital-to-analog converter, and the field-programmable gate array, so that the functional module based on the direct digital frequency synthesis principle is in a determined starting position each time it is powered on and initialized.

5. The multi-channel radio frequency signal source device according to claim 1, characterized in that, The phase monitoring module includes an IQ phase detector, an analog-to-digital converter, and a micro control unit; The IQ phase detector is used to receive the first signal and the other signals, and outputs an orthogonal differential signal that characterizes the in-phase component and the quadrature component of the phase detection signal. The analog-to-digital converter is used to acquire and digitize the orthogonal differential signal and transmit it to the micro control unit via an internal bus. The micro control unit is used to calculate the phase difference and amplitude information of the other signals relative to the first signal based on the orthogonal differential signal, and feeds back the calculated phase difference and amplitude information to the multi-channel radio frequency signal source for phase locking.

6. The multi-channel radio frequency signal source device according to claim 5, characterized in that, The analog-to-digital converter has a bit depth of not less than 24 bits and a sampling rate of not more than 1 MSPS; The micro control unit is equipped with a digital low-pass filter to process the calculated phase difference in order to filter out noise interference.

7. A method for implementing a multi-channel radio frequency signal source device, characterized in that, The multi-channel radio frequency signal source device according to any one of claims 1-6 includes the following steps: The frequency standard signal of an external satellite navigation system is received using a satellite receiver, and the frequency standard signal is locked using a frequency reference source; A driving clock signal is generated based on the frequency reference signal using a clock signal source; Driven by the driving clock signal, a multi-channel radio frequency signal source outputs multiple radio frequency signals with the same initial frequency and phase lock. The radio frequency signals include a first signal and other signals. Using the first signal as a reference, the phase monitoring module measures and records the initial phase difference and amplitude information of the other signals relative to the first signal; The multi-channel radio frequency signal source adjusts the frequency of one of the other signals, and after the frequency adjustment is completed, restores the frequency of one of the other signals to the initial frequency; The phase monitoring module measures the current phase difference and amplitude information of one of the other signals after frequency recovery relative to the first signal; Calculate the difference between the current phase difference and the initial phase difference, adjust the phase of the corresponding channel in the multi-channel radio frequency signal source, and adjust the phase until the measured phase difference is restored to the initial phase difference, thus completing phase locking.

8. The method for implementing a multi-channel radio frequency signal source device according to claim 7, characterized in that, The specific measurement steps for measuring and recording the phase difference and amplitude information of the other signals relative to the first signal include: Using the first signal as a reference, obtain the in-phase component data and quadrature component data of one of the other signals relative to the first signal; Calculate the arctangent of the ratio of the quadrature component data to the in-phase component data to obtain the phase measurement value; The amplitude information is obtained by calculating the square root of the sum of the squares of the in-phase component data and the quadrature component data.

9. The method for implementing a multi-channel radio frequency signal source device according to claim 7, characterized in that, It also includes the synchronous frequency modulation step: When it is necessary to synchronously adjust the frequency of all the radio frequency signals output by the multi-channel radio frequency signal source, the frequency of the driving clock signal output by the clock signal source is adjusted so that the frequency of all the radio frequency signals changes synchronously in proportion, while maintaining the phase difference between each signal.

10. The method for implementing a multi-channel radio frequency signal source device according to claim 7, characterized in that, It also includes the multi-channel radio frequency signal source controlling the timing so that the functional module based on the direct digital frequency synthesis principle is in a determined starting position each time it is powered on and initialized, so that the initial phase of the radio frequency signal output is always locked. When the multi-channel radio frequency signal source performs frequency adjustment and phase adjustment, it maintains a stable output amplitude and does not perform automatic level control.

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