Clock synchronization methods

Abstract

This application provides a clock synchronization method, belonging to the field of computer technology. The method includes: sending multiple synchronization request messages to a second device; receiving a response message from the second device for any synchronization request message, and parsing the response message to obtain a calibration timestamp; acquiring a first timestamp of the synchronization request message sent to the second device and a second timestamp of the response message received by the first device; determining clock synchronization parameters corresponding to the synchronization request message based on the first timestamp, the second timestamp, and the calibration timestamp; and performing clock synchronization based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages. This improves the accuracy and stability of clock synchronization, solving the technical problem in existing technologies where timestamp acquisition and processing rely on the operating system protocol stack, making them susceptible to task scheduling and interrupt response delays, resulting in low synchronization accuracy and difficulty in meeting the high-precision requirements of clock synchronization.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a clock synchronization method. Background Technology

[0002] In a distributed system, multiple independent devices need to work together based on a unified time base, and the accuracy of their clock synchronization directly affects the reliability, consistency and performance of the distributed system.

[0003] In related technologies, existing clock synchronization methods mainly rely on network time protocols. However, the acquisition and processing of timestamps in this method depend on the operating system protocol stack, which is susceptible to the effects of task scheduling and interrupt response delays, resulting in low synchronization accuracy and making it difficult to meet the high-precision requirements of clock synchronization. Summary of the Invention

[0004] The purpose of this application is to provide a clock synchronization method to solve the technical problem that the acquisition and processing of timestamps rely on the operating system protocol stack, which is susceptible to the effects of task scheduling and interrupt response delays, resulting in low synchronization accuracy and difficulty in meeting the high-precision requirements of clock synchronization. The specific technical solution is as follows:

[0005] In a first aspect of this application, a clock synchronization method is provided, applied to a first device, the method comprising:

[0006] Send multiple synchronization request messages to the second device;

[0007] For any of the aforementioned synchronization request messages, a response message from the second device is received, and the response message is parsed to obtain a calibration timestamp;

[0008] Obtain the first timestamp of sending the synchronization request message to the second device and the second timestamp of the first device receiving the response message;

[0009] Based on the first timestamp, the second timestamp, and the calibration timestamp, determine the clock synchronization parameters corresponding to the synchronization request message;

[0010] Clock synchronization is performed based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages.

[0011] In an optional implementation, the first device includes a software layer and a hardware layer, and before sending multiple synchronization request messages to the second device, it further includes:

[0012] The software layer reads the current timestamp from the clock source and writes the current timestamp into the clock timing unit of the hardware layer;

[0013] When the hardware layer receives the write completion signal of the current timestamp, it uses the current timestamp as the start time.

[0014] Obtain the preset calibration period, and use the timestamp after the preset calibration period as the end timestamp:

[0015] The clock drift amount is determined based on the current timestamp, the preset calibration period, and the end timestamp;

[0016] Based on the clock drift, a frequency compensation value is generated, and the clock timing unit of the hardware layer is calibrated based on the frequency compensation value.

[0017] In an optional implementation, the response message is generated through the following steps:

[0018] The second device receives the synchronization request message sent by the first device and records the receiving timestamp;

[0019] Obtain the preset absolute time point corresponding to the synchronization request message, wherein the preset absolute time point is determined by the second device based on the clock driven by the local high-stability oscillator;

[0020] The difference between the preset absolute time point and the received timestamp is used as the calibration timestamp;

[0021] The calibration timestamp is encapsulated to generate the response message.

[0022] In an optional implementation, the method further includes:

[0023] Monitor the current processing load status;

[0024] Adjust the calibration timestamp based on the current processing load status.

[0025] In an optional implementation, determining the clock synchronization parameters corresponding to the synchronization request message based on the first timestamp, the second timestamp, and the calibration timestamp includes:

[0026] The difference between the first timestamp and the second timestamp is used as the total observation timestamp;

[0027] Based on the first timestamp, the total observation timestamp, and the calibration timestamp, the clock synchronization parameters corresponding to the synchronization request message are determined.

[0028] In an optional implementation, determining the clock synchronization parameters corresponding to the synchronization request message based on the first timestamp, the total observation timestamp, and the calibration timestamp includes:

[0029] The first timestamp, the total observation timestamp, and the calibration timestamp are input into the equivalent value formula to calculate the clock synchronization parameters corresponding to the synchronization request message. The equivalent value formula is as follows:

[0030] = ;

[0031] in, The clock synchronization parameters corresponding to the synchronization request message. This is the first timestamp. The total observation timestamp, The calibration timestamp.

[0032] In an optional implementation, the clock synchronization based on the clock synchronization parameters corresponding to each of the plurality of synchronization request messages includes:

[0033] The target synchronization time is determined based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages.

[0034] Clock synchronization is performed based on the target synchronization time.

[0035] In an optional implementation, determining the target synchronization time based on the clock synchronization parameters corresponding to each of the plurality of synchronization request messages includes:

[0036] Obtain the clock synchronization parameters corresponding to each of the multiple synchronization request messages, and form a synchronization parameter set;

[0037] Sort the clock synchronization parameters in the set of synchronization parameters.

[0038] The clock synchronization parameters that are sorted and located at the preset target position are taken as the target synchronization time.

[0039] In an optional implementation, before sorting the clock synchronization parameters in the synchronization parameter set, the method further includes:

[0040] Obtain the response time corresponding to each of the aforementioned synchronization request messages;

[0041] Based on the response time corresponding to each of the synchronization request messages, statistical characteristics are determined, including at least one of the mean, median, and quartiles.

[0042] The response time threshold is determined based on the statistical characteristics.

[0043] Synchronization request messages whose response time exceeds the response time threshold are marked as abnormal messages.

[0044] Remove the clock synchronization parameters corresponding to the abnormal message from the set of synchronization parameters.

[0045] In an optional implementation, the method further includes:

[0046] Monitor the historical clock deviation trend between the first device and the second device;

[0047] When the drift rate corresponding to the historical clock deviation trend exceeds a preset stability threshold, the step of sending multiple synchronization request messages to the second device is executed.

[0048] In a second aspect of this application, a clock synchronization device is also provided, applied to a first device, the device comprising:

[0049] The message sending module is used to send multiple synchronization request messages to the second device;

[0050] The message parsing module is used to receive a response message from the second device for any of the synchronization request messages, and to parse the response message to obtain a calibration timestamp;

[0051] The timestamp determination module is used to obtain a first timestamp of sending the synchronization request message to the second device and a second timestamp of the first device receiving the response message;

[0052] The clock synchronization parameter determination module is used to determine the clock synchronization parameters corresponding to the synchronization request message based on the first timestamp, the second timestamp, and the calibration timestamp.

[0053] The clock synchronization module is used to perform clock synchronization based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages.

[0054] In a third aspect of the embodiments of this application, an electronic device is also provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0055] Memory, used to store computer programs;

[0056] When a processor executes a program stored in memory, it implements the clock synchronization method described in any one of the first aspects above.

[0057] In a fourth aspect of the embodiments of this application, a storage medium is also provided, wherein the storage medium stores instructions that, when run on a computer, cause the computer to execute any of the clock synchronization methods described in the first aspect above.

[0058] In a fifth aspect of the embodiments of this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to perform any of the clock synchronization methods described in the first aspect above.

[0059] The technical solution provided in this application sends multiple synchronization request messages to a second device; for any synchronization request message, a response message from the second device is received, and the response message is parsed to obtain a calibration timestamp; a first timestamp of the synchronization request message sent to the second device and a second timestamp of the response message received by the first device are obtained; based on the first timestamp, the second timestamp, and the calibration timestamp, clock synchronization parameters corresponding to the synchronization request message are determined; and clock synchronization is performed based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages. By determining the clock synchronization parameters corresponding to each of the multiple synchronization request messages based on the first timestamp, the second timestamp, and the calibration timestamp for clock synchronization, the accuracy and stability of clock synchronization can be improved. This solves the technical problem in the prior art where timestamp acquisition and processing rely on the operating system protocol stack, which is susceptible to task scheduling and interrupt response delays, resulting in low synchronization accuracy and difficulty in meeting the high-precision requirements of clock synchronization. Attached Figure Description

[0060] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0061] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0062] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0063] Figure 1 A schematic diagram illustrating the implementation process of a clock synchronization method provided in this application embodiment;

[0064] Figure 2 A schematic diagram illustrating the implementation process of another clock synchronization method provided in this application embodiment;

[0065] Figure 3 A schematic diagram illustrating the implementation process of another clock synchronization method provided in this application embodiment;

[0066] Figure 4 A schematic diagram illustrating the implementation process of a method for determining a target synchronization time provided in an embodiment of this application;

[0067] Figure 5 This is a schematic diagram of the structure of a clock synchronization device provided in an embodiment of this application;

[0068] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0070] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0071] To address the technical problem that existing technologies rely on the operating system protocol stack for timestamp acquisition and processing, making them susceptible to task scheduling and interrupt response delays, resulting in low synchronization accuracy and difficulty in meeting the high-precision requirements of clock synchronization, this application provides a clock synchronization method. The method involves sending multiple synchronization request messages to a second device; receiving a response message from the second device for each synchronization request message and parsing the response message to obtain a calibration timestamp; acquiring the first timestamp of the synchronization request message sent to the second device and the second timestamp of the response message received by the first device; determining the clock synchronization parameters corresponding to the synchronization request message based on the first timestamp, the second timestamp, and the calibration timestamp; and performing clock synchronization based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages. This method of determining the clock synchronization parameters corresponding to each of the multiple synchronization request messages based on the first timestamp, the second timestamp, and the calibration timestamp for clock synchronization improves the accuracy and stability of clock synchronization.

[0072] like Figure 1 The diagram shown is a schematic representation of an implementation flow of a clock synchronization method provided in this application embodiment, applied to a first device, and specifically includes the following steps:

[0073] S101, send multiple synchronization request messages to the second device.

[0074] The aforementioned first device refers to the device that initiates a clock synchronization request and performs synchronization adjustments based on its local clock.

[0075] The second device mentioned above refers to the device that serves as a high-precision time reference source and responds to synchronization requests. Its local clock (driven by a high-stability oscillator) is considered as the target reference for synchronization.

[0076] The aforementioned synchronization request message refers to a network data packet generated by the first device and sent to the second device to initiate a bidirectional time measurement exchange. The synchronization request message contains information such as a unique sequence number, the first device identifier, and the time the request was sent, used to match the request and response.

[0077] In this embodiment of the application, multiple synchronization request messages are sent to the second device to obtain multiple time test samples, thereby suppressing random errors and improving the robustness and accuracy of synchronization estimation.

[0078] It should be noted that when sending multiple synchronization request messages to the second device, a uniform time interval (such as 10ms to 100ms, which can be dynamically adjusted according to network bandwidth) can be used to avoid delay jitter caused by congestion of synchronization request messages in a short period of time. At the same time, a message timeout threshold (such as 500ms) should be set. If the corresponding response message is not received within the threshold, the information corresponding to the synchronization request message should be discarded and not included in subsequent calculations to avoid invalid data affecting synchronization accuracy.

[0079] S102: For any synchronization request message, receive the response message from the second device, parse the response message, and obtain the calibration timestamp.

[0080] In this embodiment, for any synchronization request message, a response message from the second device is received, and the response message is parsed to obtain a calibration timestamp. The response message is a data packet sent by the second device according to its local high-precision clock plan after receiving the synchronization request message. The calibration timestamp refers to a parameter parsed from the second device's response message, representing the time interval between the moment the second device receives the synchronization request message and the future absolute moment when it plans to send the response message.

[0081] S103, obtain the first timestamp of sending the synchronization request message to the second device and the second timestamp of the first device receiving the response message.

[0082] In this embodiment, a first timestamp of sending a synchronization request message to the second device and a second timestamp of the first device receiving a response message are obtained. The first timestamp refers to the precise moment when the network interface controller of the first device actually sends the synchronization request message into the physical link at the data link layer. The second timestamp is generated by dedicated hardware, bypassing the latency caused by the operating system protocol stack and software scheduling, thus possessing nanosecond-level high precision and low jitter. The second timestamp refers to the precise moment when the network interface controller of the first device receives the response message from the second device at the physical layer.

[0083] S104, based on the first timestamp, the second timestamp, and the calibration timestamp, determine the clock synchronization parameters corresponding to the synchronization request message.

[0084] In this embodiment, clock synchronization parameters corresponding to the synchronization request message are determined based on the first timestamp, the second timestamp, and the calibration timestamp. The entity synchronization parameters are used to characterize the estimated value that maps the absolute time when the second device plans to send the response message to the local time coordinate system of the first device.

[0085] S105 performs clock synchronization based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages.

[0086] In this embodiment of the application, clock synchronization is performed based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages.

[0087] Based on the above description of the technical solution provided in the embodiments of this application, multiple synchronization request messages are sent to a second device; for any synchronization request message, a response message from the second device is received, and the response message is parsed to obtain a calibration timestamp; a first timestamp of the synchronization request message sent to the second device and a second timestamp of the response message received by the first device are obtained; based on the first timestamp, the second timestamp, and the calibration timestamp, clock synchronization parameters corresponding to the synchronization request message are determined; and clock synchronization is performed based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages. By determining the clock synchronization parameters corresponding to each of the multiple synchronization request messages based on the first timestamp, the second timestamp, and the calibration timestamp for clock synchronization, the accuracy and stability of clock synchronization can be improved. This solves the technical problem in the prior art where the acquisition and processing of timestamps rely on the operating system protocol stack, which is susceptible to the effects of task scheduling and interrupt response delays, resulting in low synchronization accuracy and difficulty in meeting the high-precision requirements of clock synchronization.

[0088] like Figure 2 The diagram shown illustrates the implementation flow of another clock synchronization method provided in this application, applied to a first device, and may specifically include the following:

[0089] S201, send multiple synchronization request messages to the second device.

[0090] In this embodiment of the application, this step is similar to step S101 above, and will not be described in detail here.

[0091] It should be noted that the first device includes a software layer and a hardware layer. The software layer refers to the operating system and applications running on the CPU (central processing unit) of the first device. It is responsible for executing the logic control of the synchronization protocol, message generation and parsing, and obtaining initial time information from the clock source. The hardware layer refers to the dedicated clock circuit (such as the timing module in a programmable gate array or a dedicated clock chip) in the first device, driven by a high-stability oscillator (such as a temperature-compensated crystal oscillator or a oven-controlled crystal oscillator). It is responsible for providing nanosecond-level resolution time counting, performing high-precision timestamp insertion and reading, and performing low-latency frequency / phase adjustment.

[0092] Before sending multiple synchronization request messages to the second device, it is also necessary to ensure that the clock source of the software layer in the first device is consistent with the timestamp of the clock timing unit of the hardware layer. This may also include the following steps:

[0093] Step 11: The software layer reads the current timestamp from the clock source and writes the current timestamp into the clock timing unit of the hardware layer.

[0094] In this embodiment, the software layer reads the current timestamp from the clock source and writes it to the clock timing unit of the hardware layer. The clock source refers to a highly authoritative time reference accessible to the software layer, which can be time information provided by an external high-precision clock card read through interfaces such as PCIe. The clock timing unit refers to the core register or counter circuit in the hardware layer used for continuous counting of time (such as seconds and nanoseconds).

[0095] It should be noted that the clock source supports priority mode and alternative mode selection. In priority mode, the timestamp of an external high-precision clock card (such as Keysight 53230A) can be read through the PCIe 4.0 interface with an accuracy of ≤1ns. In alternative mode, when there is no external clock card, the system's built-in raw monotonic clock (Linux system) can be used to avoid relying on network clocks.

[0096] The specific implementation process of writing to the hardware layer can be as follows: If memory-mapped I / O is used, the timestamp needs to be written to the pre-allocated address space of the hardware (such as 0x7F000000-0x7F000007, a total of 8 bytes, storing second-level (32-bit) and nanosecond-level (32-bit) data respectively); if register writing is used, the hardware's "time write control register" needs to be configured first (such as address 0x7F000008, writing 0x01 indicates that writing is allowed), then the timestamp data is written, and finally the 0x00 lock configuration is written.

[0097] Step 12: When the hardware layer receives the write completion signal of the current timestamp, it uses the current timestamp as the start time.

[0098] In this embodiment, when the hardware layer receives a write completion signal with the current timestamp, it uses the current timestamp as the start time. The write completion signal refers to a physical confirmation signal from a hardware interface (such as register writing or memory-mapped I / O). When this signal is valid, the hardware layer latches the time value written by the software layer and uses it as the starting point of its internal timing cycle to ensure the determinism of time base transmission and eliminate uncertainties such as bus latency during the software layer's write process.

[0099] Step 13: Obtain the preset calibration period and use the timestamp after the preset calibration period as the end timestamp.

[0100] In this embodiment, a preset calibration period is obtained, and the timestamp after the preset calibration period is used as the end timestamp. The preset calibration period refers to a configurable time interval used to define the frequency at which the software layer performs periodic calibration on the clock timing unit of the hardware layer.

[0101] Step 14: Determine the clock drift amount based on the current timestamp, preset calibration period, and end timestamp.

[0102] In this embodiment, the clock drift is determined based on the current timestamp, the preset calibration period, and the end timestamp. The clock drift refers to the difference between the actual running time and the ideal cycle time of the clock timing unit in the hardware layer within the preset calibration period, used to quantify the accumulated frequency error of the hardware oscillator due to factors such as temperature and aging.

[0103] Step 15: Generate a frequency compensation value based on the clock drift amount, and calibrate the clock timing unit of the hardware layer based on the frequency compensation value.

[0104] In this embodiment, a frequency compensation value is generated based on the clock drift, and the clock timing unit of the hardware layer is calibrated based on the frequency compensation value. The frequency compensation value refers to an adjustment amount determined based on the clock drift and a control algorithm (such as a PID controller), used to fine-tune the counting step frequency of the hardware layer clock timing unit.

[0105] For calibrating the hardware-layer clock timing unit based on the frequency compensation value, the frequency compensation value can be written into the control register of the hardware-layer phase-locked loop or direct clock generator, thereby speeding up or slowing down the counting speed of the hardware-layer timing unit in real time, so that its long-term average frequency is consistent with the time reference provided by the software layer, and the high stability of the internal clock of the device can be achieved.

[0106] S202: For any synchronization request message, receive the response message from the second device, parse the response message, and obtain the calibration timestamp.

[0107] In this embodiment of the application, this step is similar to step S102 above, and will not be described in detail here.

[0108] The response message can be generated using the following steps:

[0109] Step 21: The second device receives the synchronization request message sent by the first device and records the receiving timestamp.

[0110] In this embodiment, the second device receives a synchronization request message sent by the first device and records the reception timestamp. The reception timestamp refers to the moment when the second device's hardware accurately receives the synchronization request message bitstream at the physical layer.

[0111] Step 22: Obtain the preset absolute time point corresponding to the synchronization request message, wherein the preset absolute time point is determined by the second device based on the clock driven by the local high-stability oscillator.

[0112] In this embodiment, a preset absolute time point corresponding to the synchronization request message is obtained. This preset absolute time point is determined by the second device based on a clock driven by its local high-stability oscillator. The preset absolute time point refers to a future moment when the second device plans to send a response message, determined by its local high-stability, low-drift hardware clock, to avoid system scheduling delays or uneven processing loads that may occur due to immediate response.

[0113] Step 23: Use the difference between the preset absolute time point and the received timestamp as the calibration timestamp.

[0114] In this embodiment of the application, the difference between the preset absolute time point and the received timestamp is used as the calibration timestamp.

[0115] Step 24: Encapsulate the calibration timestamp and generate a response message.

[0116] In this embodiment, the calibration timestamp is encapsulated to generate a response message. Specifically, the calibration timestamp can be used as a payload field to fill in a network message (such as a User Datagram Protocol message) to construct a response message; however, this embodiment does not limit this approach.

[0117] In addition, the current processing load status can be monitored, and the calibration timestamp can be adjusted accordingly. The current processing load status refers to indicators such as the CPU utilization, interrupt busyness, or message queue depth of the second device. Adjusting the calibration timestamp based on the current processing load status ensures that the second device has sufficient and stable time to complete message processing, avoiding additional jitter caused by untimely processing at the scheduled transmission time, and further improving synchronization determinism.

[0118] S203, obtain the first timestamp of sending the synchronization request message to the second device and the second timestamp of the first device receiving the response message.

[0119] In this embodiment of the application, this step is similar to step S103 above, and will not be described in detail here.

[0120] S204, the difference between the first timestamp and the second timestamp is used as the total observation timestamp.

[0121] In this embodiment of the application, the difference between the first timestamp and the second timestamp is used as the total observation timestamp.

[0122] For example, if the first timestamp is 1000000000ns and the second timestamp is 1000015000ns, then the difference between the first and second timestamps is 15000ns, so the total observation timestamp is 15000ns.

[0123] S205, based on the first timestamp, the total observation timestamp, and the calibration timestamp, determines the clock synchronization parameters corresponding to the synchronization request message.

[0124] In this embodiment of the application, the clock synchronization parameters corresponding to the synchronization request message are determined based on the first timestamp, the total observation timestamp, and the calibration timestamp.

[0125] To determine the clock synchronization parameters corresponding to the synchronization request message based on the first timestamp, the total observation timestamp, and the calibration timestamp, the first timestamp, the total observation timestamp, and the calibration timestamp can be input into the equivalent value formula to calculate the clock synchronization parameters corresponding to the synchronization request message. The equivalent value formula is as follows:

[0126] = ;

[0127] in, To synchronize the clock synchronization parameters corresponding to the synchronization request message, As the first timestamp, This is the total observation timestamp. For calibrating timestamps.

[0128] For example, If the total observation timestamp is 15,000 ns and the calibration timestamp is 200,000 ns, then the clock synchronization parameter corresponding to the synchronization request message is 1,000,207,500 ns.

[0129] S206, clock synchronization is performed based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages.

[0130] In this embodiment of the application, this step is similar to step S105 above, and will not be described in detail here.

[0131] Based on the above description of the technical solution provided in the embodiments of this application, multiple synchronization request messages are sent to a second device; for any synchronization request message, a response message from the second device is received, and the response message is parsed to obtain a calibration timestamp; a first timestamp of the synchronization request message sent to the second device and a second timestamp of the response message received by the first device are obtained; based on the first timestamp, the second timestamp, and the calibration timestamp, clock synchronization parameters corresponding to the synchronization request message are determined; and clock synchronization is performed based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages. By determining the clock synchronization parameters corresponding to each of the multiple synchronization request messages based on the first timestamp, the second timestamp, and the calibration timestamp for clock synchronization, the accuracy and stability of clock synchronization can be improved. This solves the technical problem in the prior art where the acquisition and processing of timestamps rely on the operating system protocol stack, which is susceptible to the effects of task scheduling and interrupt response delays, resulting in low synchronization accuracy and difficulty in meeting the high-precision requirements of clock synchronization.

[0132] like Figure 3 The diagram shown illustrates the implementation flow of another clock synchronization method provided in this application, applied to a first device, and may specifically include the following:

[0133] S301 sends multiple synchronization request messages to the second device.

[0134] In this embodiment of the application, this step is similar to step S101 above, and will not be described in detail here.

[0135] S302: For any synchronization request message, receive a response message from the second device, parse the response message, and obtain the calibration timestamp.

[0136] In this embodiment of the application, this step is similar to step S102 above, and will not be described in detail here.

[0137] S303, obtain the first timestamp of sending a synchronization request message to the second device and the second timestamp of the first device receiving the response message.

[0138] In this embodiment of the application, this step is similar to step S103 above, and will not be described in detail here.

[0139] S304, based on the first timestamp, the second timestamp, and the calibration timestamp, determines the clock synchronization parameters corresponding to the synchronization request message.

[0140] In this embodiment of the application, this step is similar to step S104 above, and will not be described in detail here.

[0141] S305 determines the target synchronization time based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages.

[0142] In this embodiment, a target synchronization time is determined based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages. The target synchronization time is used as the target time for the first device to adjust its local clock, thereby eliminating the influence of random measurement noise.

[0143] For details on how to determine the target synchronization time based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages, please refer to [reference needed]. Figure 4 The method shown. (As illustrated) Figure 4 The diagram shown illustrates the implementation flow of a method for determining a target synchronization time according to an embodiment of this application, which may specifically include the following steps:

[0144] S401: Obtain the clock synchronization parameters corresponding to each of the multiple synchronization request messages and form a synchronization parameter set.

[0145] In this embodiment of the application, the clock synchronization parameters corresponding to each of the multiple synchronization request messages are obtained to form a synchronization parameter set.

[0146] It should be noted that for clock synchronization parameters in the synchronization parameter set, outlier detection based on statistical methods (such as interquartile range) or preset thresholds (such as exceeding three standard deviations of the average response time) can be used to remove clock synchronization parameters that significantly deviate from the normal range, thus avoiding their adverse effects on the synchronization results. Simultaneously, it is necessary to check whether each clock synchronization parameter originates from a complete request-response exchange process and verify whether its corresponding timestamp is generated by hardware, ensuring data reliability and consistency.

[0147] S402 sorts the clock synchronization parameters in the synchronization parameter set.

[0148] In this embodiment, the clock synchronization parameters in the synchronization parameter set are sorted. Specifically, this can mean arranging all clock synchronization parameters in the synchronization parameter set in ascending or descending order of their values; however, this embodiment does not limit this to that.

[0149] It should be noted that before sorting the clock synchronization parameters in the synchronization parameter set, unreliable clock synchronization parameters caused by network anomalies are removed. This can specifically include the following steps:

[0150] Step 31: Obtain the response time corresponding to each synchronization request message.

[0151] In this embodiment of the application, the response time corresponding to each synchronization request message is obtained. The response time refers to the total time elapsed from when the first device sends a synchronization request message to when it receives the corresponding response message returned by the second device, and its value is equal to the difference between the second timestamp and the first timestamp.

[0152] Step 32: Based on the response time corresponding to each synchronization request message, determine the statistical characteristics, which include at least one of the following: median and quartiles.

[0153] In this embodiment, statistical characteristics are determined based on the response time corresponding to each synchronization request message. These statistical characteristics include at least one of the mean, median, and quartiles. The statistical characteristics describe the distribution characteristics of the response times corresponding to each synchronization request message. The mean is the arithmetic mean of all response times, reflecting the overall average level. The median is the value in the middle after sorting the response times by numerical value; if the number of response times is even, the average of the two middle response times is taken. The median effectively resists the influence of extreme values. The quartiles divide the sorted response times into four equal parts; the value at the 25th percentile is called the lower quartile, and the value at the 75th percentile is called the upper quartile. The quartiles are used to measure the dispersion of the data.

[0154] Step 33: Determine the response time threshold based on statistical characteristics.

[0155] In this embodiment, the response time threshold is determined based on statistical characteristics. Specifically, the interquartile range method can be used: response time threshold = upper quartile + k × (upper quartile) The response time threshold is obtained by using the lower quartiles, where k is a configurable parameter (K ​​can be 1.5 or 3). Alternatively, a method based on the mean and standard deviation can be used: T = N + m × R, where T is the response time threshold, N is the mean, R is the standard deviation, and m is an adjustment coefficient (such as 0.1, 0.2, etc.).

[0156] Step 34: Mark synchronization request messages whose response time exceeds the response time threshold as abnormal messages.

[0157] In this embodiment of the application, if the response time of the synchronization request message exceeds the response time threshold, it indicates that the synchronization request message may be delayed due to network instantaneous congestion, routing jitter or device processing delay. Therefore, the synchronization request message can be marked as an abnormal message.

[0158] Step 35: Remove the clock synchronization parameters corresponding to the abnormal message from the synchronization parameter set.

[0159] In this embodiment of the application, the clock synchronization parameters corresponding to the abnormal message are removed from the synchronization parameter set.

[0160] S403, take the clock synchronization parameters that are sorted and located at the preset target position as the target synchronization time.

[0161] In this embodiment, the clock synchronization parameter that is sorted and located at a preset target position is taken as the target synchronization time. The preset target position can be a pre-set index position, such as the median position. If the number of clock synchronization parameters in the synchronization parameter set is an odd number N, the target position is (N+1) / 2. If the number of clock synchronization parameters in the synchronization parameter set is an even number M, the target position is the average of the positions M / 2 and M / 2+1.

[0162] It should be noted that choosing the median after sorting as the target synchronization time can effectively resist the effects of "impulse noise" or "long-tail delay".

[0163] In another embodiment of this application, weights can be assigned based on the response time (i.e., total observation timestamp) or other quality indicators (such as the stability of timestamp acquisition, historical synchronization error, etc.) corresponding to each clock synchronization parameter, and a weighted average value can be calculated as the target synchronization time.

[0164] In another embodiment of this application, extreme values ​​in the synchronization parameter set can be removed first, and then the arithmetic mean of the remaining data can be calculated to balance robustness and efficiency. Specifically, the clock synchronization parameters in the synchronization parameter set can be sorted by numerical value, and the K data points at the beginning and end of the sorted set can be removed (K can be a fixed number, such as k=1 or k=|N×P|, where p is the removal ratio, for example, 5%, and N is the number of clock synchronization parameters in the synchronization parameter set). For the remaining N... Calculate the arithmetic mean of 2k clock synchronization parameters.

[0165] In another embodiment of this application, the most suitable statistical algorithm can be dynamically selected based on real-time network conditions. Specifically, network metrics such as response time variance, packet loss rate, and latency distribution skewness can be monitored. If the network latency variance is small (e.g., below a threshold), an arithmetic mean or weighted average is used to fully utilize sample information. If the network latency variance is large or a significant heavy-tailed distribution appears, the median is switched to enhance robustness. Simultaneously, historical synchronization errors can be used as feedback to adaptively adjust the parameters of the statistical algorithm (e.g., weighting coefficients, elimination ratios, etc.).

[0166] S306 performs clock synchronization based on the target synchronization time.

[0167] In this embodiment of the application, clock synchronization is performed based on the target synchronization time.

[0168] Specifically, this can include phase adjustment, which directly sets the current time of the hardware clock timing unit as the target synchronization time; it can also include frequency compensation, which calculates the clock drift rate based on the trend of historical synchronization errors and generates a frequency compensation value through a PID control algorithm to dynamically adjust the counting frequency of the hardware clock, thereby achieving long-term stable synchronization. Meanwhile, to avoid the impact of time jumps, a gradual adjustment method can be used to gradually adjust the hardware clock timing unit to the target synchronization time.

[0169] In addition, it may include monitoring the historical clock deviation trend between the first device and the second device; when the drift rate corresponding to the historical clock deviation trend exceeds a preset stability threshold, the step of sending multiple synchronization request messages to the second device is executed, i.e., step S301. Here, the historical clock deviation trend refers to the pattern of clock deviation change over time obtained by recording and analyzing the clock error (or frequency offset) calculated in multiple past synchronization cycles. The preset stability threshold is a pre-set parameter value used to determine whether the stable state of the clock has been broken.

[0170] Corresponding to the above method embodiments, this application also provides a clock synchronization device, such as... Figure 5 As shown, the device may include a message sending module 501, a message parsing module 502, a timestamp determination module 503, a clock synchronization parameter determination module 504, and a clock synchronization module 505.

[0171] The message sending module 501 is used to send multiple synchronization request messages to the second device;

[0172] The message parsing module 502 is used to receive a response message from the second device for any synchronization request message, and parse the response message to obtain the calibration timestamp;

[0173] The timestamp determination module 503 is used to obtain the first timestamp of sending the synchronization request message to the second device and the second timestamp of the first device receiving the response message;

[0174] The clock synchronization parameter determination module 504 is used to determine the clock synchronization parameters corresponding to the synchronization request message based on the first timestamp, the second timestamp, and the calibration timestamp.

[0175] The clock synchronization module 505 is used to perform clock synchronization based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages.

[0176] This application also provides an electronic device, such as... Figure 6 As shown, it includes a processor 601, a communication interface 602, a memory 603, and a communication bus 604, wherein the processor 601, the communication interface 602, and the memory 603 communicate with each other through the communication bus 604.

[0177] Memory 603 is used to store computer programs;

[0178] In one embodiment of this application, when the processor 601 executes a program stored in the memory 603, it performs the following steps:

[0179] Multiple synchronization request messages are sent to the second device; for any synchronization request message, a response message is received from the second device, and the response message is parsed to obtain a calibration timestamp; the first timestamp of the synchronization request message sent to the second device and the second timestamp of the response message received by the first device are obtained; based on the first timestamp, the second timestamp, and the calibration timestamp, the clock synchronization parameters corresponding to the synchronization request message are determined; based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages, clock synchronization is performed.

[0180] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0181] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0182] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0183] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0184] In another embodiment provided in this application, a storage medium is also provided, which stores instructions that, when run on a computer, cause the computer to execute any of the clock synchronization methods described in the above embodiments.

[0185] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to perform any of the clock synchronization methods described in the above embodiments.

[0186] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a storage medium or transmitted from one storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0187] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0188] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0189] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the protection scope of this application.

Claims

1. A method of clock synchronization, characterized by, Applied to a first device, the method includes: Send multiple synchronization request messages to the second device; For any of the synchronization request messages, a response message is received from the second device, and the response message is parsed to obtain a calibration timestamp. The calibration timestamp is used to represent the time interval between the moment the second device receives the synchronization request message and the future absolute moment when it plans to send the response message. Obtain the first timestamp of sending the synchronization request message to the second device and the second timestamp of the first device receiving the response message; Based on the first timestamp, the second timestamp, and the calibration timestamp, determine the clock synchronization parameters corresponding to the synchronization request message; Clock synchronization is performed based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages; The first device includes a software layer and a hardware layer, and before sending multiple synchronization request messages to the second device, it further includes: The software layer reads the current timestamp from the clock source and writes the current timestamp into the clock timing unit of the hardware layer; When the hardware layer receives the write completion signal of the current timestamp, it uses the current timestamp as the start time. Obtain the preset calibration period, and use the timestamp after the preset calibration period as the end timestamp: The clock drift amount is determined based on the current timestamp, the preset calibration period, and the end timestamp; Based on the clock drift, a frequency compensation value is generated, and the clock timing unit of the hardware layer is calibrated based on the frequency compensation value.

2. The method of claim 1, wherein, The response message is generated through the following steps: The second device receives the synchronization request message sent by the first device and records the receiving timestamp; Obtain the preset absolute time point corresponding to the synchronization request message, wherein the preset absolute time point is determined by the second device based on the clock driven by the local high-stability oscillator; The difference between the preset absolute time point and the received timestamp is used as the calibration timestamp; The calibration timestamp is encapsulated to generate the response message.

3. The method according to claim 2, characterized in that, The method further includes: Monitor the current processing load status; Adjust the calibration timestamp based on the current processing load status.

4. The method according to claim 1, characterized in that, The step of determining the clock synchronization parameters corresponding to the synchronization request message based on the first timestamp, the second timestamp, and the calibration timestamp includes: The difference between the first timestamp and the second timestamp is used as the total observation timestamp; Based on the first timestamp, the total observation timestamp, and the calibration timestamp, the clock synchronization parameters corresponding to the synchronization request message are determined.

5. The method according to claim 4, characterized in that, The step of determining the clock synchronization parameters corresponding to the synchronization request message based on the first timestamp, the total observation timestamp, and the calibration timestamp includes: The first timestamp, the total observation timestamp, and the calibration timestamp are input into the equivalent value formula to calculate the clock synchronization parameters corresponding to the synchronization request message. The equivalent value formula is as follows: = ； in, The clock synchronization parameters corresponding to the synchronization request message. This is the first timestamp. The total observation timestamp, The calibration timestamp.

6. The method according to claim 1, characterized in that, The step of performing clock synchronization based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages includes: The target synchronization time is determined based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages. Clock synchronization is performed based on the target synchronization time.

7. The method according to claim 6, characterized in that, The step of determining the target synchronization time based on the clock synchronization parameters corresponding to each of the multiple synchronization request messages includes: Obtain the clock synchronization parameters corresponding to each of the multiple synchronization request messages, and form a synchronization parameter set; Sort the clock synchronization parameters in the set of synchronization parameters. The clock synchronization parameters that are sorted and located at the preset target position are taken as the target synchronization time.

8. The method according to claim 7, characterized in that, Before sorting the clock synchronization parameters in the synchronization parameter set, the method further includes: Obtain the response time corresponding to each of the aforementioned synchronization request messages; Based on the response time corresponding to each of the synchronization request messages, statistical characteristics are determined, including at least one of the mean, median, and quartiles. The response time threshold is determined based on the statistical characteristics. Synchronization request messages whose response time exceeds the response time threshold are marked as abnormal messages. Remove the clock synchronization parameters corresponding to the abnormal message from the set of synchronization parameters.

9. The method according to claim 1, characterized in that, The method further includes: Monitor the historical clock deviation trend between the first device and the second device; When the drift rate corresponding to the historical clock deviation trend exceeds a preset stability threshold, the step of sending multiple synchronization request messages to the second device is executed.

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