Pixel driving circuit, driving method thereof and display device

Abstract

The invention discloses a pixel driving circuit, a driving method thereof and a display device, and the pixel driving circuit comprises a driving sub-circuit which is configured to provide a driving signal for a third node (N3) under the control of signals of a first node (N1) and a second node (N2); the first initial sub-circuit is configured to provide a first input signal end (IN1) signal to a first node (N1) under the control of a first scanning signal end (Gate1) signal; the coupling sub-circuit is configured to couple a signal of a data signal end (Data) or a second input signal end (IN2) to a third node (N3) under the control of a signal of a second scanning signal end (Gate2) and a signal of a third scanning signal end (Gate3); the holding sub-circuit is configured to store a voltage difference between signals of the first node (N1) and the third node (N3); the light-emitting control sub-circuit is configured to provide a first power supply end (VDD1) signal to the second node (N2) and provide a third node (N3) signal to the fifth node (N5) under the control of a first light-emitting signal end (EM1) signal and a second light-emitting signal end (EM2) signal.

Description

Pixel driving circuit and its driving method, display device

[0001] This application claims priority to Chinese Patent Application No. 202411187376.8, filed on August 27, 2024, entitled "Pixel Driving Circuit and Driving Method Thereof, Display Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, specifically to a pixel driving circuit and its driving method, and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a pixel driving circuit and driving method thereof, as well as a display device.

[0006] In a first aspect, this disclosure provides a pixel driving circuit configured to drive a light-emitting device to emit light, wherein the pixel driving circuit includes: a driving sub-circuit, a coupling sub-circuit, a holding sub-circuit, a first initial sub-circuit, and a light-emitting control sub-circuit;

[0007] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node.

[0008] The first initial sub-circuit is electrically connected to the first input signal terminal, the first scan signal terminal, and the first node, respectively, and is configured to provide the signal from the first input signal terminal to the first node under the control of the signal from the first scan signal terminal;

[0009] The coupling sub-circuit is electrically connected to the second scan signal terminal, the third scan signal terminal, the data signal terminal, the second input signal terminal, and the third node, respectively, and is configured to couple the signal from the data signal terminal or the second input signal terminal to the third node under the control of the signals from the second scan signal terminal and the third scan signal terminal.

[0010] The holding sub-circuit, which is electrically connected to the first node and the third node respectively, is configured to store the voltage difference between the signals of the first node and the third node;

[0011] The light-emitting control sub-circuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fifth node, respectively. It is configured to provide the signal from the first power supply terminal to the second node and the signal from the third node to the fifth node under the control of the signals from the first light-emitting signal terminal and the second light-emitting signal terminal.

[0012] The light-emitting device is electrically connected to the fifth node.

[0013] Secondly, this disclosure also provides a display device, including: the aforementioned pixel driving circuits arranged in an array.

[0014] Thirdly, this disclosure also provides a method for driving a pixel driving circuit, configured to drive the aforementioned pixel driving circuit, the method comprising:

[0015] The driving sub-circuit provides driving signals to the third node under the control of the signals from the first and second nodes;

[0016] The first initial sub-circuit provides the first input signal terminal signal to the first node under the control of the signal at the first scanning signal terminal;

[0017] Under the control of the signals at the second scan signal terminal and the third scan signal terminal, the coupler circuit couples the signal at the data signal terminal or the second input signal terminal to the third node;

[0018] Maintain the voltage difference between the signals stored in the first and third nodes in the sub-circuit;

[0019] Under the control of the signals from the first and second light-emitting signal terminals, the light-emitting control sub-circuit provides the first power supply signal to the second node and the third node signal to the fifth node.

[0020] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0021] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0022] Overview of the attached figures

[0023] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0024] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0025] Figure 2 is the equivalent circuit diagram of the first initial sub-circuit;

[0026] Figure 3 shows the equivalent circuit diagram of the holding sub-circuit;

[0027] Figure 4 shows the equivalent circuit diagram of the driver sub-circuit.

[0028] Figure 5 shows the equivalent circuit diagram of the driver sub-circuit (II).

[0029] Figure 6 shows the equivalent circuit diagram of the coupling sub-circuit;

[0030] Figure 7 shows the equivalent circuit diagram of the coupler sub-circuit (II).

[0031] Figure 8 shows the equivalent circuit diagram of the light-emitting control sub-circuit.

[0032] Figure 9 shows the equivalent circuit diagram of the light-emitting control sub-circuit (II).

[0033] Figure 10 is a schematic diagram of a pixel driving circuit provided in an exemplary embodiment;

[0034] Figure 11 is the equivalent circuit diagram of the second initial sub-circuit in Figure 10;

[0035] Figure 12 is a schematic diagram of the pixel driving circuit provided in another exemplary embodiment;

[0036] Figure 13 is the equivalent circuit diagram of the second initial sub-circuit in Figure 12;

[0037] Figure 14 is the equivalent circuit diagram of the second initial sub-circuit in Figure 12.

[0038] Figure 15 is a schematic diagram of the pixel driving circuit provided in yet another exemplary embodiment;

[0039] Figure 16 is the equivalent circuit diagram of the third initial sub-circuit;

[0040] Figure 17 is an equivalent circuit diagram of a pixel driving circuit.

[0041] Figure 18 is an equivalent circuit diagram of a pixel driving circuit (II).

[0042] Figure 19 is the first driving timing diagram of the pixel driving circuit provided in Figure 18;

[0043] Figure 20 is the second driving timing diagram of the pixel driving circuit provided in Figure 18;

[0044] Figure 21 is an equivalent circuit diagram of a pixel driving circuit.

[0045] Figure 22 is an equivalent circuit diagram of a pixel driving circuit.

[0046] Figure 23 is the first driving timing diagram of the pixel driving circuit provided in Figure 22;

[0047] Figure 24 is the second driving timing diagram of the pixel driving circuit provided in Figure 22;

[0048] Figure 25 is the third driving timing diagram of the pixel driving circuit provided in Figure 22;

[0049] Figure 26 is the fourth driving timing diagram of the pixel driving circuit provided in Figure 22;

[0050] Figure 27 is the fifth driving timing diagram of the pixel driving circuit provided in Figure 22;

[0051] Figure 28 is the driving timing diagram of the pixel driving circuit provided in Figure 22.

[0052] Figure 29 is the driving timing diagram of the pixel driving circuit provided in Figure 22.

[0053] Figure 30 is the driving timing diagram of the pixel driving circuit provided in Figure 22.

[0054] Figure 31 is an equivalent circuit diagram of a pixel driving circuit.

[0055] Figure 32 is an equivalent circuit diagram of a pixel driving circuit.

[0056] Figure 33 is an equivalent circuit diagram of a pixel driving circuit.

[0057] Figure 34 is a driving timing diagram of the pixel driving circuit provided in Figures 32 and 33.

[0058] Figure 35 is the second driving timing diagram of the pixel driving circuit provided in Figures 32 and 33;

[0059] Figure 36 is an equivalent circuit diagram of a pixel driving circuit.

[0060] Figure 37 is an equivalent circuit diagram of a pixel driving circuit.

[0061] Figure 38 is an equivalent circuit diagram of a pixel driving circuit.

[0062] Figure 39 is an equivalent circuit diagram of a pixel driving circuit.

[0063] Figure 40 is an equivalent circuit diagram of a pixel driving circuit.

[0064] Figure 41 is the first driving timing diagram of the pixel driving circuit provided in Figures 39 and 40;

[0065] Figure 42 is the second driving timing diagram of the pixel driving circuit provided in Figures 39 and 40;

[0066] Figure 43 is the third driving timing diagram of the pixel driving circuit provided in Figures 39 and 40;

[0067] Figure 44 is the fourth driving timing diagram of the pixel driving circuit provided in Figures 39 and 40;

[0068] Figure 45 is the fifth driving timing diagram of the pixel driving circuit provided in Figures 39 and 40;

[0069] Figure 46 is the driving timing diagram of the pixel driving circuit provided in Figures 39 and 40.

[0070] Figure 47 is the driving timing diagram of the pixel driving circuit provided in Figures 39 and 40.

[0071] Figure 48 is the driving timing diagram of the pixel driving circuit provided in Figures 39 and 40.

[0072] Figure 49 is a schematic diagram of the pixel driving circuit provided in another embodiment of the present disclosure;

[0073] Figure 50 is an exemplary structural schematic diagram of the pixel driving circuit provided in Figure 49;

[0074] Figure 51 is another exemplary structural schematic diagram of the pixel driving circuit provided in Figure 49;

[0075] Figure 52 is another exemplary structural diagram of the pixel driving circuit provided in Figure 49;

[0076] Figure 53 is an equivalent circuit diagram of the pixel driving circuit provided in Figure 50.

[0077] Figure 54 is the driving timing diagram of the pixel driving circuit provided in Figure 53 in the refresh frame;

[0078] Figure 55 is the driving timing diagram of the pixel driving circuit provided in Figure 53 in the holding frame;

[0079] Figure 56A is the second equivalent circuit diagram of the pixel driving circuit provided in Figure 50;

[0080] Figure 56B is the equivalent circuit diagram of the pixel driving circuit provided in Figure 50.

[0081] Figure 57 is the driving timing diagram of the pixel driving circuit provided in Figure 56A in the refresh frame;

[0082] Figure 58 is the driving timing diagram of the pixel driving circuit provided in Figure 56A in the holding frame;

[0083] Figure 59 is the equivalent circuit diagram of the pixel driving circuit provided in Figure 50.

[0084] Figure 60 is a timing diagram of the pixel driving circuit provided in Figure 59 during the refresh frame.

[0085] Figure 61 is a timing diagram of the pixel driving circuit provided in Figure 59 in the holding frame;

[0086] Figure 62 is the equivalent circuit diagram of the pixel driving circuit provided in Figure 50.

[0087] Figure 63 is a timing diagram of the pixel driving circuit provided in Figure 62 in the refresh frame;

[0088] Figure 64 is the driving timing diagram of the pixel driving circuit provided in Figure 62 in the holding frame;

[0089] Figure 65 is an equivalent circuit diagram of the pixel driving circuit provided in Figure 51.

[0090] Figure 66 is a timing diagram of the pixel driving circuit provided in Figure 65 during the refresh frame.

[0091] Figure 67 is the driving timing diagram of the pixel driving circuit provided in Figure 65 in the holding frame;

[0092] Figure 68 is the second equivalent circuit diagram of the pixel driving circuit provided in Figure 51;

[0093] Figure 69 is a timing diagram of the pixel driving circuit provided in Figure 68 in the refresh frame;

[0094] Figure 70 is the driving timing diagram of the pixel driving circuit provided in Figure 68 in the holding frame;

[0095] Figure 71 is the equivalent circuit diagram of the pixel driving circuit provided in Figure 51.

[0096] Figure 72 is the equivalent circuit diagram of the pixel driving circuit provided in Figure 51.

[0097] Figure 73 is an equivalent circuit diagram of the pixel driving circuit provided in Figure 52.

[0098] Figure 74 is a timing diagram of the pixel driving circuit provided in Figure 73 in the refresh frame;

[0099] Figure 75 is the driving timing diagram of the pixel driving circuit provided in Figure 73 in the holding frame;

[0100] Figure 76 is the second equivalent circuit diagram of the pixel driving circuit provided in Figure 52;

[0101] Figure 77 is a timing diagram of the pixel driving circuit provided in Figure 76 in the refresh frame;

[0102] Figure 78 is a timing diagram of the pixel driving circuit provided in Figure 76 in the holding frame.

[0103] Detailed Explanation

[0104] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0105] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0106] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0107] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0108] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0109] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0110] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0111] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0112] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0113] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0114] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0115] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0116] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0117] The display product includes at least one sub-pixel, which comprises a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light. The pixel driving circuit includes a driving transistor. The gate electrode of the driving transistor is connected to multiple transistors, resulting in a large parasitic capacitance value coupled to the gate electrode of the driving transistor. This reduces the follow-up ratio of the gate electrode voltage and source electrode voltage of the pixel driving circuit, causing a deviation in the driving signal voltage maintained between the gate electrode and source electrode of the driving transistor. This reduces the consistency of the display brightness of the display product and affects the display effect of the display substrate.

[0118] Therefore, this disclosure provides a pixel driving circuit.

[0119] Figure 1 is a schematic diagram of the pixel driving circuit provided in an embodiment of this disclosure. As shown in Figure 1, the pixel driving circuit provided in an embodiment of this disclosure may include: a driving sub-circuit, a coupling sub-circuit, a holding sub-circuit, a first initial sub-circuit, and a light emission control sub-circuit.

[0120] The driving sub-circuit is electrically connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving signal to the third node N3 under the control of the signals of the first node N1 and the second node N2.

[0121] The first initial sub-circuit is electrically connected to the first input signal terminal IN1, the first scan signal terminal Gate1, and the first node N1, respectively, and is configured to provide the signal of the first input signal terminal IN1 to the first node N1 under the control of the signal of the first scan signal terminal Gate1.

[0122] The coupling sub-circuit is electrically connected to at least one scan signal terminal Gate, a data signal terminal Data, a second input signal terminal IN2, and a third node N3, respectively, and is configured to couple the signal of the data signal terminal Data or the signal of the second input signal terminal IN2 to the third node N3 under the control of the signal of at least one scan signal terminal Gate.

[0123] The holding sub-circuit, electrically connected to the first node N1 and the third node N3 respectively, is configured to store the voltage difference between the signals of the first node N1 and the third node N3.

[0124] The light-emitting control sub-circuit is electrically connected to the first light-emitting signal terminal EM1, the first power supply terminal VDD, and the second node N2, respectively. It is configured to provide the first power supply terminal VDD signal to the second node N2 under the control of the signal from the first light-emitting signal terminal EM1.

[0125] In an exemplary embodiment, the first power supply terminal VDD can continuously provide a high-level signal, and the signal of the first power supply terminal VDD is a DC signal.

[0126] In this disclosure, the first initial sub-circuit connected to the first node is only electrically connected to the first input signal terminal and the first scan signal terminal. This means that the number of transistors connected to the first node is relatively small. Furthermore, the setting of the coupling sub-circuit can couple the data from the data signal terminal to the third node connected to the driving sub-circuit, reducing the number of transistors directly coupled to the first node connected to the driving sub-circuit. It can also achieve normal data writing and threshold compensation. Therefore, the pixel driving circuit provided in this disclosure embodiment can reduce the parasitic capacitance coupled to the first node N1 while ensuring normal display. This makes it less likely for the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit to deviate, ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0127] In an exemplary embodiment, the pixel driving circuit is configured to drive the light-emitting device L to emit light.

[0128] In an exemplary embodiment, the light-emitting device may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. Exemplarily, the anode of the light-emitting device is electrically connected to a pixel driving circuit, and the cathode of the light-emitting device is electrically connected to a second power supply terminal VSS.

[0129] In an exemplary embodiment, the second power supply terminal VSS can continuously provide a low-level signal, and the signal of the second power supply terminal VSS is a DC signal.

[0130] In exemplary embodiments, the light-emitting device may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). Typical dimensions (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. Typical dimensions (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0131] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0132] Figure 2 is an equivalent circuit diagram of the first initial sub-circuit. As shown in Figure 2, in an exemplary embodiment, the first initial sub-circuit includes a first transistor T1. The control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1.

[0133] In an exemplary embodiment, the first input signal terminal IN1 can receive a first initial signal. The first transistor T1 can be referred to as the first initial transistor. Under the signal control of the first scan signal terminal Gate1, the first transistor T1 writes the first initial signal into the first node N1.

[0134] Figure 2 shows only one exemplary structure of the first initial sub-circuit. Those skilled in the art will readily understand that the implementation of the first initial sub-circuit is not limited to this.

[0135] Figure 3 is an equivalent circuit diagram of the holding sub-circuit. As shown in Figure 3, in an exemplary embodiment, the holding sub-circuit includes a first capacitor C1. The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3.

[0136] In an exemplary embodiment, the first capacitor C1 can ensure the stability of the signal of the first node N1 and improve the reliability of the pixel driving circuit.

[0137] Figure 3 shows only one exemplary structure of the hold sub-circuit, and those skilled in the art will readily understand that the implementation of the hold sub-circuit is not limited to this.

[0138] Figure 4 shows the equivalent circuit diagram of the driving sub-circuit. As shown in Figure 4, in an exemplary embodiment, the driving sub-circuit includes a third transistor T3. The third transistor T3 can be a single-gate transistor. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.

[0139] Figure 5 shows the equivalent circuit diagram of the driving sub-circuit. As shown in Figure 5, in an exemplary embodiment, the driving sub-circuit includes a third transistor T3. The third transistor T3 can be a dual-gate transistor. The third transistor T3 includes a first control electrode and a second control electrode. The first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.

[0140] In an exemplary embodiment, the third transistor T3 can be referred to as the driving transistor. The connection method of the third transistor in this disclosure can improve the output saturation characteristics of the third transistor T3.

[0141] Figures 4 and 5 show two exemplary structures of the driver sub-circuit. It will be readily understood by those skilled in the art that the implementation of the driver sub-circuit is not limited to these.

[0142] Figure 6 shows the equivalent circuit diagram of the coupling sub-circuit. As shown in Figure 6, in an exemplary embodiment, at least one scan signal terminal includes a second scan signal terminal Gate2 and a third scan signal terminal Gate3. The coupling sub-circuit may include a second transistor T2, a fourth transistor T4, and a second capacitor C2. Specifically, the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4. The first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0143] In an exemplary embodiment, the second input signal terminal IN2 can receive a second initial signal. The second transistor T2 can be referred to as the second initial transistor. Under the signal control of the second scan signal terminal Gate2, the second transistor T2 writes the second initial signal into the fourth node N4.

[0144] In an exemplary embodiment, the data signal terminal Data can receive data signals. The fourth transistor T4 can be referred to as the write transistor. Under the control of the signal at the third scan signal terminal Gate3, the fourth transistor T4 writes data signals to the fourth node N4.

[0145] Figure 7 shows the equivalent circuit diagram of the coupling sub-circuit. As shown in Figure 7, in an exemplary embodiment, at least one scan signal terminal includes a second scan signal terminal Gate2. The coupling sub-circuit may include a second transistor T2 and a second capacitor C2. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2; the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time period and to the second input signal terminal IN2 for a portion of the time period; the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0146] In an exemplary embodiment, the second input signal terminal IN2 can receive the second initial signal, and the data signal terminal Data can receive the data signal. Under the control of the signal from the second scan signal terminal Gate2, the second transistor T2 writes the data signal to the fourth node N4 for a portion of the time period and writes the second initial signal to the fourth node N4 for a portion of the time period.

[0147] Figures 6 and 7 show two exemplary structures of the coupler circuit. It will be readily understood by those skilled in the art that the implementation of the coupler circuit is not limited to these.

[0148] In an exemplary embodiment, the coupling sub-circuit provided in FIG7 includes fewer transistors than the coupling sub-circuit provided in FIG6, which can reduce the area occupied by the pixel driving circuit and the number of connected signal lines, and can achieve a high PPI of the display device.

[0149] Figure 8 is an equivalent circuit diagram of the light-emitting control sub-circuit. As shown in Figure 8, in an exemplary embodiment, the light-emitting control sub-circuit may include a fifth transistor T5. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2.

[0150] In an exemplary embodiment, the first power supply terminal VDD can receive a first power signal, and the fifth transistor T5 can be referred to as a light-emitting transistor. Under the signal control of the first light-emitting signal terminal EM1, the fifth transistor T5 writes the first power signal into the second node N2.

[0151] As shown in Figure 8, the light-emitting device L is electrically connected to the third node N3 and the second power supply terminal VSS.

[0152] Figure 9 shows the equivalent circuit diagram of the light-emitting control sub-circuit. As shown in Figure 9, in the exemplary embodiment, the light-emitting control sub-circuit is also electrically connected to the second light-emitting signal terminal EM2, the third node N3, and the fifth node N5. The light-emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5.

[0153] In an exemplary embodiment, the first power supply terminal VDD can receive a first power supply signal, and the fifth transistor T5 can be referred to as the first light-emitting transistor. Under the signal control of the first light-emitting signal terminal EM1, the fifth transistor T5 writes the first power supply signal into the second node N2. The sixth transistor T6 can be referred to as the second light-emitting transistor. Under the signal control of the second light-emitting signal terminal EM2, the sixth transistor T6 writes the drive signal output from the third node N3 into the fifth node N5.

[0154] As shown in Figure 9, the light-emitting device L is electrically connected to the fifth node N5 and the second power supply terminal VSS.

[0155] Figures 8 and 9 show two exemplary structures of the light-emitting control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the light-emitting control sub-circuit is not limited to these.

[0156] In an exemplary embodiment, the light-emitting control sub-circuit shown in FIG9 isolates the third node N3 from the light-emitting device L, thereby avoiding the influence of the parasitic capacitance of the light-emitting device on the signal of the third node N3.

[0157] Figure 10 is a schematic diagram of a pixel driving circuit provided in an exemplary embodiment. As shown in Figure 10, in the exemplary embodiment, when the light-emitting device is electrically connected to the third node N3, the pixel driving circuit may further include a second initial sub-circuit. The second initial sub-circuit is electrically connected to the fourth scan signal terminal Gate4, the third input signal terminal IN3, and the third node N3, and is configured to provide the signal of the third input signal terminal IN3 to the third node N3 under the control of the signal of the fourth scan signal terminal Gate4.

[0158] Figure 11 is an equivalent circuit diagram of the second initial sub-circuit in Figure 10. As shown in Figure 11, the second initial sub-circuit may include: a seventh transistor T7. The control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to the third node N3.

[0159] In an exemplary embodiment, the third input signal terminal IN3 can receive a third initial signal. The seventh transistor T7 can be referred to as the third initial transistor. Under the signal control of the fourth scan signal terminal Gate4, the seventh transistor T7 writes the third initial signal into the third node N3 to initialize the third node N3. Exemplarily, the seventh transistor T7 can be turned on once in a display frame, or it can be turned on multiple times, to initialize the anode of the light-emitting device, or to bias the third transistor T3.

[0160] Figure 12 is a schematic diagram of a pixel driving circuit provided in another exemplary embodiment. As shown in Figure 12, in the exemplary embodiment, when the light-emitting device is electrically connected to the fifth node N5, the pixel driving circuit may further include a second initial sub-circuit. The second initial sub-circuit is electrically connected to the fourth scan signal terminal Gate4, the third input signal terminal IN3, and one of the third node N3 and the fifth node N5, respectively, and is configured to provide the signal of the third input signal terminal IN3 to one of the third node N3 and the fifth node N5 under the control of the signal of the fourth scan signal terminal Gate4.

[0161] Figure 13 is an equivalent circuit diagram of the second initial sub-circuit in Figure 12 (Figure 11), and Figure 14 is an equivalent circuit diagram of the second initial sub-circuit in Figure 12 (Figure 14). As shown in Figures 13 and 14, in an exemplary embodiment, the second initial sub-circuit includes a seventh transistor T7. The control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to one of the third node N3 and the fifth node N5. Figure 13 illustrates the circuit with the second terminal of the seventh transistor electrically connected to the third node N3, and Figure 14 illustrates the circuit with the second terminal of the seventh transistor electrically connected to the fifth node N5.

[0162] In an exemplary embodiment, the third input signal terminal IN3 can receive a third initial signal. The seventh transistor T7 can be referred to as the third initial transistor. Under the signal control of the fourth scan signal terminal Gate4, the seventh transistor T7 writes the third initial signal into the third node N3 or the fifth node N5, thus initializing the third node N3 or the fifth node N5. Exemplarily, the seventh transistor T7 can be turned on once in a display frame, or it can be turned on multiple times; this disclosure does not limit this. When the second terminal of the seventh transistor T7 is electrically connected to the third node N3, the conduction of the seventh transistor T7 can initialize the second terminal of the third transistor T3, or bias the third transistor T3. When the second terminal of the seventh transistor T7 is electrically connected to the fifth node N5, the conduction of the seventh transistor T7 can initialize the anode of the light-emitting device.

[0163] Figures 11, 13 and 14 show an exemplary structure of the second initial sub-circuit, and it will be readily understood by those skilled in the art that the implementation of the second initial sub-circuit is not limited thereto.

[0164] Figure 15 is a schematic diagram of a pixel driving circuit provided in another exemplary embodiment. As shown in Figure 15, in the exemplary embodiment, the pixel driving circuit may further include a third initial sub-circuit. The third initial sub-circuit is electrically connected to the fifth scan signal terminal Gate5, the fourth input signal terminal IN4, and the second node N2, respectively, and is configured to provide the signal of the fourth input signal terminal IN4 to the second node N2 under the control of the signal from the fifth scan signal terminal Gate5.

[0165] Figure 16 is an equivalent circuit diagram of the third initial sub-circuit. As shown in Figure 16, in an exemplary embodiment, the third initial sub-circuit includes an eighth transistor T8. The control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2.

[0166] In an exemplary embodiment, the fourth input signal terminal IN4 can receive a fourth initial signal. The eighth transistor T8 can be referred to as the fourth initial transistor. Under the signal control of the fifth scan signal terminal Gate5, the eighth transistor T8 writes the fourth initial signal into the second node N2, thereby initializing or biasing the second node N2.

[0167] The second initial sub-circuit and the third initial sub-circuit in this disclosure can initialize the second node before the light-emitting device emits light, thereby ensuring the consistency of the light emission brightness in the display device.

[0168] Figure 16 shows an exemplary structure of the third initial sub-circuit. It will be readily understood by those skilled in the art that the implementation of the third initial sub-circuit is not limited to this.

[0169] In an exemplary embodiment, the signals received by the first input signal terminal IN1 and the first power supply terminal VDD connected to the same pixel driving circuit can be the same signal.

[0170] In an exemplary embodiment, the signals received by the first input signal terminal IN1 and the second input signal terminal IN2 connected to the same pixel driving circuit can be the same signal.

[0171] In an exemplary embodiment, the signals received by the second input signal terminal IN2 and the third input signal terminal IN3 connected to the same pixel driving circuit can be the same signal.

[0172] In an exemplary embodiment, the signals received by the second input signal terminal IN2 and the fourth input signal terminal IN4, which are connected to the same pixel driving circuit, can be the same signal.

[0173] In an exemplary embodiment, the voltage value of the third initial signal received by the third input signal terminal IN3 is less than the sum of the voltage value of the signal at the second power supply terminal and the voltage value between the two electrodes of the light-emitting device, so as to ensure that the light-emitting device does not emit light when the anode of the light-emitting device L is initialized.

[0174] In an exemplary embodiment, the first initial signal received by the first input signal terminal IN1 is a positive voltage signal to ensure that the third transistor T3 can be turned on normally, thereby improving the reliability of the pixel driving circuit.

[0175] In an exemplary embodiment, the voltage value of the first initial signal received by the first input signal terminal IN1 may be equal to the voltage value of the second initial signal received by the second input signal terminal IN2, the voltage value of the first initial signal received by the first input signal terminal IN1 may be greater than the voltage value of the third initial signal received by the third input signal terminal IN3, and the voltage value of the third initial signal received by the third input signal terminal IN3 may be greater than the voltage value of the fourth initial signal received by the fourth input signal terminal IN4.

[0176] In an exemplary embodiment, the signal received by the second scanning signal terminal Gate2 connected to the same pixel driving circuit and the signal received by the first light-emitting signal terminal EM1 are the same signal; or, the signal received by the second scanning signal terminal Gate2 connected to the i-th row pixel driving circuit and the first scanning signal terminal Gate1 of the (i-1)-th row pixel driving circuit are the same signal.

[0177] In an exemplary embodiment, when the pixel driving circuit is electrically connected to the fourth scanning signal terminal and the fifth scanning signal terminal respectively, the signals received by the fourth scanning signal terminal Gate4 and the fifth scanning signal terminal Gate5 connected to the same pixel driving circuit are the same signals.

[0178] In an exemplary embodiment, the signals received by the third scanning signal terminal Gate3 connected to the pixel driving circuit of the i-th row and the fourth scanning signal terminal Gate4 of the pixel driving circuit of the (i+K)-th row are the same signal, where K is a positive integer greater than 1.

[0179] In an exemplary embodiment, having at least two signal terminals connected to the pixel driving circuit receive the same signal can reduce the number of signal lines connected to the pixel driving circuit, thereby achieving a high PPI for the display device.

[0180] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0181] In an exemplary embodiment, the N-type transistor can be an oxide thin-film transistor. The active pattern of the oxide thin-film transistor uses oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current, which can reduce power consumption and improve display quality.

[0182] In an exemplary embodiment, any one of the first capacitors C1 to the second capacitor C2 can be a capacitor device manufactured through a process, for example, by fabricating dedicated capacitor electrodes. Multiple capacitor electrodes can be implemented using metal layers, semiconductor layers (e.g., doped polysilicon), etc. Alternatively, any one of the first capacitors C1 to the second capacitor C2 can be a parasitic capacitance between multiple devices, implemented using the transistor itself and other devices or circuits. The connection method of any one of the first capacitors C1 to the second capacitor C2 includes, but is not limited to, the methods described above; other applicable connection methods can be used, as long as the level of the corresponding node is stored. Here, the exemplary embodiments of this disclosure do not limit this.

[0183] Figure 17 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 17, the pixel driving circuit includes: a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, and a light emission control sub-circuit. The first initial sub-circuit includes: a first transistor T1; the holding sub-circuit includes: a first capacitor C1; the coupling sub-circuit includes: a second transistor T2 and a second capacitor C2; the driving sub-circuit includes: a third transistor T3; and the light emission control sub-circuit includes: a fifth transistor T5. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time, and to the second input signal terminal IN2 for a portion of the time. The second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Or... The first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0184] In an exemplary embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 in FIG17 is an N-type transistor. Exemplarily, the first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 are all N-type transistors, or the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0185] Figure 18 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 18, the pixel driving circuit includes: a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, a light emission control sub-circuit, and at least one of a second initial sub-circuit and a third initial sub-circuit. Figure 18 illustrates the pixel driving circuit with the second initial sub-circuit and the third initial sub-circuit as an example. Specifically, the first initial sub-circuit includes a first transistor T1, the holding sub-circuit includes a first capacitor C1, the coupling sub-circuit includes a second transistor T2 and a second capacitor C2, the driving sub-circuit includes a third transistor T3, the light emission control sub-circuit includes a fifth transistor T5, the second initial sub-circuit includes a seventh transistor T7, and the third initial sub-circuit includes an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2. The first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time and to the second input signal terminal IN2 for a portion of the time. The second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Alternatively, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, and the first electrode of the third transistor T3 is electrically connected to the second node N2. The second terminal of transistor T3 is electrically connected to the third node N3; the control terminal of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2; the control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to the third node N3; the control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0186] In an exemplary embodiment, at least one of the first transistor T1, second transistor T2, third transistor T3, fifth transistor T5, seventh transistor T7, and eighth transistor T8 in FIG18 is an N-type transistor. Exemplarily, the first transistor T1, second transistor T2, third transistor T3, fifth transistor T5, seventh transistor T7, and eighth transistor T8 are all N-type transistors, or the first transistor T1, second transistor T2, third transistor T3, seventh transistor T7, and eighth transistor T8 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0187] In Figure 18, the seventh transistor T7 initializes the third node N3, and the eighth transistor T8 resets the second node N2. The operation of the first transistor T1, second transistor T2, third transistor T3, and fifth transistor T5 in Figure 18 is the same as that in Figure 17. This disclosure only provides the operation process of the pixel driving circuit shown in Figure 18; the operation process of the pixel driving circuit shown in Figure 17 will not be described again here.

[0188] Figure 19 is a timing diagram of the pixel driving circuit provided in Figure 18. Figure 19 is illustrated using the example of N-type transistors in Figure 18. As shown in Figure 19, the operation of the pixel driving circuit provided in Figure 18 may include:

[0189] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signal at the first light-emitting signal terminal (EM1) is low-level. During this stage, the first terminal of the second transistor T2 is electrically connected to the second input signal terminal (IN2). The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fifth transistor T5 is turned off.

[0190] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where VIN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0191] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the fourth scan signal terminal Gate4 and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 or the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the seventh transistor T7 and the eighth transistor T8 are turned off.

[0192] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0193] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1-Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... data -V IN1 +Vth.

[0194] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1 and the second transistor T2 are turned on, while the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0195] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0196] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data(C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0197] In the fourth stage (S4), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the signal written to the first terminal of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0198] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0199] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1.

[0200] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage, and the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0201] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0202] I = K * (Vgs - Vth) 2

[0203] =K*(V1-V3-Vth) 2

[0204] =K*[(V IN2 -V data (C2 / C1+C2)]2

[0205] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0206] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the second stage, and the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0207] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies:

[0208] I = K * (Vgs - Vth) 2

[0209] =K*(V1-V3-Vth) 2

[0210] =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0211] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0212] Figure 20 is a second driving timing diagram of the pixel driving circuit provided in Figure 18. Figure 20 is illustrated using the example of all transistors in Figure 18 being N-type transistors. As shown in Figure 20, the operation of the pixel driving circuit provided in Figure 18 may include:

[0213] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), and the fourth scan signal terminal (Gate4) are high-level signals, while the signals at the first light emission signal terminal (EM1) and the fifth scan signal terminal (Gate5) are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the second input signal terminal (IN2). The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, while the fifth transistor T5 and the eighth transistor T8 are turned off.

[0214] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0215] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the fourth scan signal terminal Gate4 and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 or the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the seventh transistor T7 and the eighth transistor T8 are turned off.

[0216] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0217] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... data -V IN1 +Vth.

[0218] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1 and the second transistor T2 are turned on, while the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0219] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0220] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0221] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is high, while the signals at the first light emission signal terminal (EM1), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), and the fourth scan signal terminal (Gate4) are low. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal (IN2) and the data signal terminal (Data). The eighth transistor T8 is turned on, while the first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are turned off.

[0222] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0223] In the fifth stage (S5), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the signal written to the first terminal of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0224] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0225] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1.

[0226] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage, and the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0227] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0228] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0229] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the second stage, and the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0230] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0231] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0232] The difference between the pixel driving circuit shown in Figure 20 and the pixel driving circuit shown in Figure 19 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0233] Figure 21 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 21, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, and a light emission control sub-circuit. Specifically, the first initial sub-circuit includes a first transistor T1; the holding sub-circuit includes a first capacitor C1; the coupling sub-circuit includes a second transistor T2, a fourth transistor T4, and a second capacitor C2; the driving sub-circuit includes a third transistor T3; and the light emission control sub-circuit includes a fifth transistor T5. Wherein, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or, the first control electrode of the third transistor T3 is electrically connected to the first node N1, and the second control electrode of the third transistor T3 is electrically connected to the third node N3. The first terminal of transistor T3 is electrically connected to the second node N2, and the second terminal of transistor T3 is electrically connected to the third node N3; the control terminal of transistor T4 is electrically connected to the third scan signal terminal Gate3, the first terminal of transistor T4 is electrically connected to the data signal terminal Data, and the second terminal of transistor T4 is electrically connected to the fourth node N4; the control terminal of transistor T5 is electrically connected to the first light emission signal terminal EM1, the first terminal of transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of transistor T5 is electrically connected to the second node N2; the first terminal of capacitor C1 is electrically connected to the first node N1, and the second terminal of capacitor C1 is electrically connected to the third node N3; the first terminal of capacitor C2 is electrically connected to the fourth node N4, and the second terminal of capacitor C2 is electrically connected to the third node N3.

[0234] In an exemplary embodiment, at least one of the first transistors T1 to the fifth transistor T5 in FIG21 is an N-type transistor. Exemplarily, all of the first transistors T1 to the fifth transistor T5 are N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0235] Figure 22 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 22, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, a light emission control sub-circuit, and at least one of a second initial sub-circuit and a third initial sub-circuit. Figure 22 illustrates the pixel driving circuit with the second initial sub-circuit and the third initial sub-circuit as an example. Specifically, the first initial sub-circuit includes: a first transistor T1; the holding sub-circuit includes: a first capacitor C1; the coupling sub-circuit includes: a second transistor T2, a fourth transistor T4, and a second capacitor C2; the driving sub-circuit includes: a third transistor T3; the light emission control sub-circuit includes: a fifth transistor T5; the second initial sub-circuit includes: a seventh transistor T7; and the third initial sub-circuit includes: an eighth transistor T8. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3. The first terminal of transistor T4 is electrically connected to the data signal terminal Data; the second terminal of transistor T4 is electrically connected to the fourth node N4; the control terminal of transistor T5 is electrically connected to the first light-emitting signal terminal EM1; the first terminal of transistor T5 is electrically connected to the first power supply terminal VDD; the second terminal of transistor T5 is electrically connected to the second node N2; the control terminal of transistor T7 is electrically connected to the fourth scan signal terminal Gate4; the first terminal of transistor T7 is electrically connected to the third input signal terminal IN3; the second terminal of transistor T7 is electrically connected to the third node N3; the control terminal of transistor T8 is electrically connected to the fifth scan signal terminal Gate5; the first terminal of transistor T8 is electrically connected to the fourth input signal terminal IN4; the second terminal of transistor T8 is electrically connected to the second node N2; the first terminal of capacitor C1 is electrically connected to the first node N1; the second terminal of capacitor C1 is electrically connected to the third node N3; the first terminal of capacitor C2 is electrically connected to the fourth node N4; the second terminal of capacitor C2 is electrically connected to the third node N3.

[0236] In an exemplary embodiment, at least one of the first transistors T1 to T5, the seventh transistor T7, and the eighth transistor T8 in FIG22 is an N-type transistor. Exemplarily, the first transistors T1 to T5, the seventh transistor T7, and the eighth transistor T8 are all N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are N-type transistors, and the fifth transistor T5 is a P-type transistor.

[0237] In Figure 22, the seventh transistor T7 initializes the third node N3, and the eighth transistor T8 resets the second node N2. The operation of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, and fifth transistor T5 in Figure 22 is the same as that in Figure 21. This disclosure only provides the operation process of the pixel driving circuit shown in Figure 22; the operation process of the pixel driving circuit shown in Figure 21 will not be described again here.

[0238] Figure 23 is a timing diagram of the pixel driving circuit provided in Figure 22. Figure 23 is illustrated using the example of N-type transistors in Figure 22. Figure 23 is illustrated using the example of the second scan signal terminal connected to the pixel driving circuit in row i and the first scan signal terminal connected to the pixel driving circuit in row (i-1) receiving the same signal, and the fifth scan signal terminal (Gate5) and the fourth scan signal terminal (Gate4) receiving the same signal. As shown in Figure 23, the operation of the pixel driving circuit provided in Figure 22 can include:

[0239] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are high-level signals, while the signals at the first light emission signal terminal EM1 and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fifth transistor T5 is turned off.

[0240] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0241] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals at the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0242] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0243] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0244] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = VIN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0245] In the fourth stage (S4), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0246] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0247] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0248] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2-V data (C2 / C1+C2)] 2

[0249] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0250] Figure 24 is the second driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 24 is illustrated using the example that all transistors in Figure 22 are N-type transistors. Figure 24 is illustrated using the example that the second scan signal terminal connected to the pixel driving circuit in the i-th row and the first scan signal terminal connected to the pixel driving circuit in the (i-1)-th row receive the same signal, and the time when the fifth scan signal terminal Gate5 receives the valid level signal is later than the time when the fourth scan signal terminal Gate4 receives the valid level signal. As shown in Figure 24, the operation process of the pixel driving circuit provided in Figure 22 may include:

[0251] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light emission signal terminal EM1, the third scan signal terminal Gate3, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, while the fifth transistor T5 is turned off.

[0252] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0253] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals at the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0254] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0255] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0256] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2(C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0257] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light emission signal terminal (EM1), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fifth transistor (T5), and the seventh transistor (T7) are turned off.

[0258] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0259] In the fifth stage (S5), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0260] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0261] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0262] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0263] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0264] The difference between the pixel driving circuit shown in Figure 24 and the pixel driving circuit shown in Figure 23 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0265] Figure 25 is the third driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 25 is illustrated using the example that all transistors in Figure 22 are N-type transistors. Figure 25 is illustrated using the example that the second scan signal terminal and the first light emission signal terminal connected in the same pixel driving circuit receive the same signal, and the fifth scan signal terminal Gate5 and the fourth scan signal terminal Gate4 receive the same signal. As shown in Figure 25, the operation process of the pixel driving circuit provided in Figure 22 may include:

[0266] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are high-level signals, while the signals at the first light emission signal terminal EM1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, while the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0267] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0268] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals at the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0269] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0270] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0271] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0272] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second scanning signal terminal Gate2 are high-level signals, while the signals at the first scanning signal terminal Gate1, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The second transistor T2 and the fifth transistor T5 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0273] The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The voltage value of the signal at the first input signal terminal IN2. When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0274] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0275] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -Vdata (C2 / C1+C2)] 2

[0276] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0277] Figure 26 is the fourth driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 26 is illustrated using the example of all transistors in Figure 22 being N-type transistors. Figure 26 is illustrated using the example of the second scan signal terminal and the first light emission signal terminal connected in the same pixel driving circuit receiving the same signal, and the fifth scan signal terminal Gate5 receiving the valid level signal later than the fourth scan signal terminal Gate4 receiving the valid level signal. As shown in Figure 26, the operation process of the pixel driving circuit provided in Figure 22 may include:

[0278] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1 and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light emission signal terminal EM1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, while the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0279] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0280] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light emission signal terminal EM1 are high-level signals, while the signals at the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0281] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0282] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0283] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0284] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light emission signal terminal (EM1), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fifth transistor (T5), and the seventh transistor (T7) are turned off.

[0285] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0286] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second scanning signal terminal Gate2 are high-level signals, while the signals at the first scanning signal terminal Gate1, the third scanning signal terminal Gate3, the fourth scanning signal terminal Gate4, and the fifth scanning signal terminal Gate5 are low-level signals. The second transistor T2 and the fifth transistor T5 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0287] The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The voltage value of the signal at the first input signal terminal IN2. When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0288] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0289] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0290] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0291] The difference between the pixel driving circuit shown in Figure 26 and the pixel driving circuit shown in Figure 25 is that the initialization of the second node N2 occurs during the biasing stage after the data writing stage and before the light emission stage, in order to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0292] Figure 27 is the fifth driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 27 is illustrated using the example that all transistors in Figure 22 are N-type transistors. Figure 27 is illustrated using the example that the fifth scan signal terminal Gate5 and the fourth scan signal terminal Gate4 receive the same signal. As shown in Figure 27, the operation process of the pixel driving circuit provided in Figure 22 may include:

[0293] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are high-level signals, while the signals at the first light emission signal terminal EM1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, while the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0294] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where VIN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0295] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light emission signal terminal EM1 are high-level signals, while the signals at the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0296] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0297] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0298] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(VIN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0299] In the fourth stage (S4), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0300] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0301] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0302] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0303] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0304] Figure 28 is the driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 28 is illustrated using the example of all transistors in Figure 22 being N-type transistors. Figure 28 is illustrated with the example of the fifth scan signal terminal Gate5 receiving the valid level signal later than the fourth scan signal terminal Gate4 receiving the valid level signal. As shown in Figure 28, the operation of the pixel driving circuit provided in Figure 22 may include:

[0305] In the first stage S1, the initialization stage, the signals at the first scan signal terminal Gate1 and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light emission signal terminal EM1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the seventh transistor T7 are turned on, while the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are turned off.

[0306] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0307] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light emission signal terminal EM1 are high-level signals, while the signals at the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0308] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1-Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0309] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0310] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0311] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light emission signal terminal (EM1), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), and the seventh transistor (T7) are turned off.

[0312] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0313] In the fifth stage (S5), the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0314] When the fifth transistor T5 is turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5 and the turned-on third transistor T3, thereby driving the light-emitting device L to emit light.

[0315] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0316] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0317] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0318] The difference between the pixel driving circuit shown in Figure 28 and the pixel driving circuit shown in Figure 27 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0319] Figure 29 is the driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 29 is illustrated using the example of N-type transistors in Figure 22. The driving timing diagram provided in Figure 29 differs from that provided in Figure 23 only in the duration of the effective level signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2. However, the signals at the multiple signal terminals connected to the pixel driving circuit are the same at different stages. Therefore, the operation process of the pixel driving circuit provided in Figure 29 is exactly the same as that of the pixel driving circuit provided in Figure 23, and will not be described again here.

[0320] Figure 30 is a driving timing diagram of the pixel driving circuit provided in Figure 22. Figure 30 is illustrated using the example of N-type transistors in Figure 22. The driving timing diagram provided in Figure 30 differs from that provided in Figure 24 only in the duration of the effective level signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2. However, the signals at the multiple signal terminals connected to the pixel driving circuit are the same at different stages. Therefore, the operation process of the pixel driving circuit provided in Figure 30 is exactly the same as that of the pixel driving circuit provided in Figure 24, and will not be described again here.

[0321] Figure 31 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 31, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, and a light emission control sub-circuit. The first initial sub-circuit includes: a first transistor T1; the holding sub-circuit includes: a first capacitor C1; the coupling sub-circuit includes: a second transistor T2 and a second capacitor C2; the driving sub-circuit includes: a third transistor T3; and the light emission control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2. The first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time and to the second input signal terminal IN2 for a portion of the time. The second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Alternatively, the first control electrode of the third transistor T3 is electrically connected to the first node N1, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fifth node N5. The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3. The first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0322] In an exemplary embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 in FIG31 is an N-type transistor. Exemplarily, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are all N-type transistors, or the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors, and the fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0323] Figure 32 is an equivalent circuit diagram of a pixel driving circuit (Figure 6), and Figure 33 is an equivalent circuit diagram of a pixel driving circuit (Figure 7). As shown in Figures 32 and 33, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, a light emission control sub-circuit, and at least one of a second initial sub-circuit and a third initial sub-circuit. Figures 32 and 33 are illustrated using the example of a pixel driving circuit including a second initial sub-circuit and a third initial sub-circuit. Specifically, the first initial sub-circuit includes a first transistor T1, the holding sub-circuit includes a first capacitor C1, the coupling sub-circuit includes a second transistor T2 and a second capacitor C2, the driving sub-circuit includes a third transistor T3, the light emission control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, the second initial sub-circuit includes a seventh transistor T7, and the third initial sub-circuit includes an eighth transistor T8.Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2. The first electrode of the second transistor T2 is electrically connected to the data signal terminal Data for a portion of the time and to the second input signal terminal IN2 for a portion of the time. The second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Alternatively, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1. The first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2; the control terminal of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fifth node N5; the control terminal of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first terminal of the seventh transistor T7 is electrically connected to the third input signal terminal IN3, and the second terminal of the seventh transistor T7 is electrically connected to one of the nodes N3 and N5; the control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3. Figure 32 illustrates the connection between the second terminal and the third node of the seventh transistor, and Figure 33 illustrates the connection between the second terminal and the fifth node of the seventh transistor.

[0324] In an exemplary embodiment, at least one of the first transistor T1, second transistor T2, third transistor T3, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 in Figures 32 and 33 is an N-type transistor. Exemplarily, the first transistor T1, second transistor T2, third transistor T3, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 are all N-type transistors, or the first transistor T1, second transistor T2, third transistor T3, seventh transistor T7, and eighth transistor T8 are N-type transistors, and the fifth transistor T5 and sixth transistor T6 are P-type transistors.

[0325] In Figures 32 and 33, the seventh transistor T7 initializes the third node N3, and the eighth transistor T8 resets the second node N2. The operation of the first transistor T1, second transistor T2, third transistor T3, fifth transistor T5, and sixth transistor T6 in Figures 27 and 28 is the same as that in Figure 26. This disclosure only provides the operation of the pixel driving circuit shown in Figures 27 and 28; the operation of the pixel driving circuit shown in Figure 26 will not be described again here.

[0326] Figure 34 is a timing diagram of the pixel driving circuit provided in Figures 32 and 33. Figure 34 is illustrated using the example of N-type transistors in all transistors in Figures 32 and 33. Figure 34 is also illustrated using the example of the fourth scan signal terminal Gate4 and the fifth scan signal terminal Gate5 receiving the same signal. As shown in Figure 34, the operation of the pixel driving circuit provided in Figures 32 and 33 may include:

[0327] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first light-emitting signal terminal (EM1) and the second light-emitting signal terminal (EM2) are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the second input signal terminal (IN2). The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fifth transistor T5 and the sixth transistor T6 are turned off.

[0328] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node). The voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0329] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the fourth scan signal terminal Gate4, the fifth scan signal terminal Gate5, and the second light-emitting signal terminal EM2 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 or the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0330] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0331] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... data -V IN1 +Vth.

[0332] In the third stage, S3, the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1 and the second transistor T2 are turned on, while the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0333] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0334] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0335] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the signal written to the first terminal of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0336] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0337] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1.

[0338] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage, and the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -VIN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0339] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0340] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0341] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the second stage, and the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0342] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0343] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0344] Figure 35 is a second timing diagram of the pixel driving circuit provided in Figures 32 and 33. Figure 35 is illustrated using the example of N-type transistors in all transistors in Figures 32 and 33. Figure 35 is illustrated using the example of the effective level signal received at the fifth scan signal terminal Gate5 being received later than the effective level signal received at the fourth scan signal terminal Gate4. As shown in Figure 35, the operation of the pixel driving circuit provided in Figures 32 and 33 may include:

[0345] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, while the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned off.

[0346] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node). The voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0347] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the fourth scan signal terminal Gate4, the fifth scan signal terminal Gate5, and the second light-emitting signal terminal EM2 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to one of the second input signal terminal IN2 or the data signal terminal Data. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0348] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0349] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... data -V IN1 +Vth.

[0350] In the third stage, S3, the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the first terminal of the second transistor T2 is electrically connected to the other signal terminal of the second input signal terminal IN2 and the data signal terminal Data. The first transistor T1 and the second transistor T2 are turned on, while the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0351] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0352] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2, the first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0353] In the fourth stage, the bias stage, the signal at the fifth scan signal terminal Gate5 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, the first light emission signal terminal EM1, and the second light emission signal terminal EM2 are low-level signals. The eighth transistor T8 is turned on, while the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0354] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0355] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. During this stage, the signal written to the first terminal of the second transistor T2 has no effect on the signal at the fourth node N4. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0356] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0357] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1.

[0358] When the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the second stage, and the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0359] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0360] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0361] When the first terminal of the second transistor T2 is electrically connected to the data signal terminal Data in the second stage, and the first terminal of the second transistor T2 is electrically connected to the second input signal terminal IN2 in the third stage, the voltage value V1 of the signal at the first node N1 is V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0362] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0363] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0364] Figure 36 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 36, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, and a light emission control sub-circuit. The first initial sub-circuit includes a first transistor T1; the holding sub-circuit includes a first capacitor C1; the coupling sub-circuit includes a second transistor T2, a fourth transistor T4, and a second capacitor C2; the driving sub-circuit includes a third transistor T3; and the light emission control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. Alternatively, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N4. Node N3 is electrically connected; the control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0365] In an exemplary embodiment, at least one of the first transistors T1 to the sixth transistor T6 in FIG36 is an N-type transistor. Exemplarily, all of the first transistors T1 to the sixth transistor T6 are N-type transistors, or the first transistor T1 and the first transistors T1 to the fourth transistor T4 are N-type transistors, and the fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0366] Figure 37 is an equivalent circuit diagram of a pixel driving circuit (Figure 9), Figure 38 is an equivalent circuit diagram of a pixel driving circuit (Figure 10), Figure 39 is an equivalent circuit diagram of a pixel driving circuit (Figure 11), and Figure 40 is an equivalent circuit diagram of a pixel driving circuit (Figure 12). As shown in Figures 37 to 40, the pixel driving circuit includes: a first initial sub-circuit, a driving sub-circuit, a holding sub-circuit, a coupling sub-circuit, a light emission control sub-circuit, and at least one of a second initial sub-circuit and a third initial sub-circuit. Figures 37 and 38 are illustrated using the example of a pixel driving circuit including a second initial sub-circuit. Figures 39 and 40 are illustrated using the example of a pixel driving circuit including both a second and a third initial sub-circuit. The first initial sub-circuit includes a first transistor T1, the holding sub-circuit includes a first capacitor C1, the coupling sub-circuit includes a second transistor T2, a fourth transistor T4, and a second capacitor C2, the driving sub-circuit includes a third transistor T3, the light-emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, the second initial sub-circuit includes a seventh transistor T7, and the third initial sub-circuit includes an eighth transistor T8.Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; or, the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4. Connections: The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, and the first electrode of the seventh transistor T7 is electrically connected to the third input signal terminal IN. 3. Electrical connections: The second terminal of the seventh transistor T7 is electrically connected to either the third node N3 or the fifth node N5; the control terminal of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor T8 is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3. Figures 37 and 39 illustrate the connection of the second terminal of the seventh transistor T7 to the third node N3 as an example, while Figures 38 and 40 illustrate the connection of the second terminal of the seventh transistor T7 to the fifth node N5 as an example.

[0367] In an exemplary embodiment, at least one of the first transistors T1 to the eighth transistor T8 in Figures 39 and 40 is an N-type transistor. Exemplarily, all of the first transistors T1 to the eighth transistor T8 are N-type transistors, or the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are N-type transistors, and the fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0368] In Figures 37 to 40, the seventh transistor T7 initializes the third node N3, and the eighth transistor T8 resets the second node N2. The operation of the first transistors T1 to the sixth transistor T6 in Figures 37 to 40 is the same as that in Figure 36. Compared to Figure 37, Figure 39 only adds the eighth transistor T8. The operation of the first transistors T1 to the seventh transistor T7 in Figure 39 is the same as that in Figure 37. Compared to Figure 38, Figure 40 only adds the eighth transistor T8. The operation of the first transistors T1 to the seventh transistor T7 in Figure 40 is the same as that in Figure 38.

[0369] This disclosure only provides the operation process of the pixel driving circuits shown in Figures 39 and 40; the operation process of the pixel driving circuits shown in Figures 36, 37 and 39 will not be described in detail here.

[0370] Figure 41 is a timing diagram of the pixel driving circuits provided in Figures 39 and 40. Figure 41 is illustrated using the example of N-type transistors in Figures 39 and 40. Figure 41 is illustrated using the example of the second scan signal terminal connected to the pixel driving circuit in the i-th row receiving the same signal as the first scan signal terminal connected to the pixel driving circuit in the (i-1)-th row, and the fourth scan signal terminal (Gate4) and the fifth scan signal terminal (Gate5) receiving the same signal. As shown in Figure 41, the operation of the pixel driving circuits provided in Figures 39 and 40 can include:

[0371] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), and the third scan signal terminal (Gate3) are low-level signals. The first transistor (T1), the second transistor (T2), the seventh transistor (T7), and the eighth transistor (T8) are turned on, while the fifth transistor (T5) and the sixth transistor (T6) are turned off.

[0372] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0373] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0374] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0375] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0376] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0377] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0378] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0379] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = VIN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0380] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0381] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0382] Figure 42 is a second driving timing diagram of the pixel driving circuits provided in Figures 39 and 40. Figure 42 is illustrated using the example of N-type transistors in all transistors in Figures 39 and 40. Figure 42 illustrates the case where the second scan signal terminal connected to the pixel driving circuit in the i-th row receives the same signal as the first scan signal terminal connected to the pixel driving circuit in the (i-1)-th row, and the effective level signal received by the fifth scan signal terminal Gate5 is received later than the effective level signal received by the fourth scan signal terminal Gate4. As shown in Figure 42, the operation of the pixel driving circuits provided in Figures 39 and 40 may include:

[0383] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), and the fourth scan signal terminal (Gate4) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the third scan signal terminal (Gate3), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1), the second transistor (T2), and the seventh transistor (T7) are turned on, while the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are turned off.

[0384] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node). The voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0385] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0386] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0387] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0388] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0389] In the fourth stage, the bias stage, the signal at the fifth scan signal terminal Gate5 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, the first light emission signal terminal EM1, and the second light emission signal terminal EM2 are low-level signals. The eighth transistor T8 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0390] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0391] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0392] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0393] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0394] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0395] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0396] The difference between the pixel driving circuit shown in Figure 42 and the pixel driving circuit shown in Figure 42 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0397] Figure 43 is the third driving timing diagram of the pixel driving circuit provided in Figures 39 and 40. Figure 43 is illustrated using the example of all transistors in Figures 39 and 40 being N-type transistors. Figure 43 is illustrated using the example of the second scan signal terminal and the first light emission signal terminal connected in the same pixel driving circuit receiving the same signal, and the fifth scan signal terminal Gate5 and the fourth scan signal terminal Gate4 receiving the same signal. As shown in Figure 43, the operation process of the pixel driving circuit provided in Figures 39 and 40 can include:

[0398] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the second scan signal terminal (Gate2), and the third scan signal terminal (Gate3) are low-level signals. The first transistor (T1), the seventh transistor (T7), and the eighth transistor (T8) are turned on, while the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) are turned off.

[0399] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node). The voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0400] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0401] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1-Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0402] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0403] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0404] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0405] The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2The voltage value of the signal at the first input signal terminal IN2. When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0406] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0407] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0408] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0409] Figure 44 is the fourth driving timing diagram of the pixel driving circuit provided in Figures 39 and 40. Figure 44 is illustrated using the example that all transistors in Figures 39 and 40 are N-type transistors. Figure 44 is illustrated using the example that the second scan signal terminal and the first light emission signal terminal connected in the same pixel driving circuit receive the same signal, and the time when the fifth scan signal terminal Gate5 receives the valid level signal is later than the time when the fourth scan signal terminal Gate4 receives the valid level signal. As shown in Figure 44, the operation process of the pixel driving circuit provided in Figures 39 and 40 can include:

[0410] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1) and the fourth scan signal terminal (Gate4) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the seventh transistor (T7) are turned on, while the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are turned off.

[0411] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0412] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0413] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1-Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0414] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0415] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0416] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) are turned off.

[0417] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0418] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the second scan signal terminal Gate2 are high-level signals, while the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned on, while the first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0419] The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written into the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 The voltage value of the signal at the first input signal terminal IN2. When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0420] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0421] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0422] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0423] The difference between the pixel driving circuit shown in Figure 44 and the pixel driving circuit shown in Figure 43 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0424] Figure 45 is the driving timing diagram of the pixel driving circuit provided in Figures 39 and 40. Figure 45 is illustrated using the example that all transistors in Figures 39 and 40 are N-type transistors. Figure 45 is illustrated with the fifth scan signal terminal Gate5 and the fourth scan signal terminal Gate4 receiving the same signal. As shown in Figure 45, the operation of the pixel driving circuit provided in Figures 39 and 40 may include:

[0425] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the second scan signal terminal (Gate2), and the third scan signal terminal (Gate3) are low-level signals. The first transistor (T1), the seventh transistor (T7), and the eighth transistor (T8) are turned on, while the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) are turned off.

[0426] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0427] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0428] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0429] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the second light emission signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0430] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -Vdata (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0431] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0432] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0433] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0434] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0435] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0436] Figure 46 is a timing diagram of the pixel driving circuits provided in Figures 39 and 40. Figure 46 is illustrated using the example of N-type transistors in Figures 39 and 40. Figure 46 illustrates the process with the fifth scan signal terminal (Gate5) receiving the valid level signal later than the fourth scan signal terminal (Gate4). As shown in Figure 46, the operation of the pixel driving circuits provided in Figures 39 and 40 can include:

[0437] In the first stage (S1), the initialization stage, the signals at the first scan signal terminal (Gate1) and the fourth scan signal terminal (Gate4) are high-level signals, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the seventh transistor (T7) are turned on, while the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are turned off.

[0438] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node), and the voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0439] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on, while the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0440] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V dataWhen the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0441] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are high-level signals, while the signals at the first light emission signal terminal EM1, the second light emission signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0442] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. data Jump to V IN2 Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V IN2 -V data (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0443] In the fourth stage (S4), the bias stage, the signal at the fifth scan signal terminal (Gate5) is a high-level signal, while the signals at the first light-emitting signal terminal (EM1), the second light-emitting signal terminal (EM2), the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the third scan signal terminal (Gate3), and the fourth scan signal terminal (Gate4) are low-level signals. The eighth transistor (T8) is turned on, while the first transistor (T1), the second transistor (T2), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) are turned off.

[0444] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = VIN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0445] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0446] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0447] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V IN2 -V data (C2 / C1+C2)]=Vss+V OLED +Vth-(V IN2 -V data (C2 / C1+C2)

[0448] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V data -V IN2 (C2 / C1+C2)] 2

[0449] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0450] The difference between the pixel driving circuit shown in Figure 46 and the pixel driving circuit shown in Figure 45 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0451] Figure 47 is the driving timing diagram of the pixel driving circuit provided in Figures 39 and 40. Figure 47 is illustrated using the example of all transistors in Figures 39 and 40 being N-type transistors. Figure 47 is illustrated using the example of the fifth scan signal terminal Gate5 and the fourth scan signal terminal Gate4 receiving the same signal. The driving timing diagram provided in Figure 47 differs from the driving timing diagram provided in Figure 41 in that the duration of the valid level signals at the first scan signal terminal Gate1 and the second scan signal terminal Gate2 is different; the duration of the valid level signal at the second scan signal terminal Gate2 is longer than the duration of the valid level signal at the first scan signal terminal Gate1.

[0452] As shown in Figure 47, the operation of the pixel driving circuits provided in Figures 39 and 40 may include:

[0453] In the first stage (S1), the initialization stage, the signals of the second light-emitting signal terminal EM2, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are high-level signals, while the signals of the first light-emitting signal terminal EM1 and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on, while the fourth transistor T4 and the fifth transistor T5 are turned off.

[0454] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node). The voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where V IN3This is the voltage value of the signal at the third input signal terminal IN3. The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written to the second node N2. The voltage value of the signal at the second node N2 is V2 = V... IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3. The sixth transistor T6 is turned on, connecting the signals at the fifth node N5 and the third node N3.

[0455] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0456] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0457] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0458] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0459] In the fourth stage (S4), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0460] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0461] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0462] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth)2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0463] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0464] Figure 48 is the driving timing diagram for the pixel driving circuits provided in Figures 39 and 40. Figure 48 is illustrated using the example of N-type transistors in Figures 39 and 40. Figure 48 is illustrated using the example of the fifth scan signal terminal, Gate 5, receiving an effective level signal later than the fourth scan signal terminal, Gate 4. The driving timing diagram provided in Figure 48 differs from that provided in Figure 42 in that the duration of the effective level signals at the first scan signal terminal, Gate 1, and the second scan signal terminal, Gate 2, is different; the duration of the effective level signal at the second scan signal terminal, Gate 2, is longer than the duration of the effective level signal at the first scan signal terminal, Gate 1.

[0465] As shown in Figure 48, the operation of the pixel driving circuits provided in Figures 39 and 40 may include:

[0466] In the first stage (S1), the initialization stage, the signals of the second light-emitting signal terminal EM2, the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the fourth scan signal terminal Gate4 are high-level signals, while the signals of the first light-emitting signal terminal EM1, the third scan signal terminal Gate3, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are turned on, while the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are turned off.

[0467] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = V IN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to one of the nodes N3 (third node) and N5 (fifth node). The voltage value of the signal at one of the nodes N3 and N5 is V. IN3 , where VIN3 This is the voltage value of the signal at the third input signal terminal IN3. The sixth transistor T6 is turned on, connecting the signal at the fifth node N5 with the signal at the third node N3.

[0468] In the second stage, S2, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the first light-emitting signal terminal EM1 are high-level signals, while the signals at the second light-emitting signal terminal EM2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, while the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0469] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth.

[0470] In the third stage (S3), the data writing stage, the signals at the first scan signal terminal (Gate1) and the third scan signal terminal (Gate3) are high-level signals, while the signals at the first light emission signal terminal (EM1), the second light emission signal terminal (EM2), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the fifth scan signal terminal (Gate5) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0471] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V dataUnder the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1 and C2 is the capacitance of the second capacitor C2.

[0472] In the fourth stage, the bias stage, the signal at the fifth scan signal terminal Gate5 is a high-level signal, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, the first light emission signal terminal EM1, and the second light emission signal terminal EM2 are low-level signals. The eighth transistor T8 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0473] The eighth transistor T8 is turned on, and the signal at the fourth input signal terminal IN4 is written into the second node N2. The voltage value of the signal at the second node N2 is V2 = V IN2 , where V IN2 This is the voltage value of the signal at the second input signal terminal IN3.

[0474] In the fifth stage (S5), the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0475] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0476] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(Vdata -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(V data -V IN2 (C2 / C1+C2)

[0477] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0478] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0479] The difference between the pixel driving circuit shown in Figure 48 and the pixel driving circuit shown in Figure 47 is that the initialization of the second node N2 occurs after the data writing stage and before the light emission stage, so as to bias the driving transistor and thus improve the hysteresis effect after the driving transistor has been in operation for a long time.

[0480] In the exemplary embodiment, the control electrode (i.e., the first node) of the third transistor (driving transistor) in the pixel driving circuit provided in Figures 17, 18, 21, 22, 31, 32, 33, 36 to 40 is only electrically connected to the first transistor T1. That is, during the light-emitting stage, the capacitance value of the parasitic capacitance coupled to the control electrode of the third transistor is small, so that the parasitic capacitance of the first transistor has little impact on the signal of the first node N1. This makes it less likely for the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit to deviate, ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0481] In the exemplary embodiment, the control electrode (i.e., the first node) of the third transistor (driving transistor) in the pixel driving circuit provided in Figures 17, 18, 21, 22, 31, 32, 33, 36 to 40 is only electrically connected to the first transistor T1. That is, during the light-emitting stage, the capacitance value of the parasitic capacitance coupled to the control electrode of the third transistor is small, so that the parasitic capacitance of the first transistor has little impact on the signal of the first node N1. This makes it less likely for the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit to deviate, ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0482] In an exemplary embodiment, all transistors in the pixel driving circuit can be N-type transistors; or some transistors can be N-type transistors and some transistors can be P-type transistors. N-type transistors can be made of semiconductor oxide materials, while P-type transistors can be made of low-temperature polycrystalline silicon. P-type transistors have a higher MOB (Mean Optical Bound) and Ion (Ion) than N-type transistors, allowing for rapid switching on and off in scenarios with high light emission and anode reset frequencies. For example, the fifth transistor T5 can be a P-type transistor, meaning it is off when the signal at the first light emission signal terminal EM1 is high and on when the signal is low. Alternatively, the fifth and sixth transistors can be P-type transistors, or the fifth, sixth, and seventh transistors can be P-type transistors, which is beneficial for high-frequency refresh and suitable for PWM dimming scenarios. Alternatively, the fourth transistor can be a P-type transistor, which can improve data writing speed. In this case, the second scan signal terminal Gate2 and the third scan signal terminal Gate3 can receive the same signal.

[0483] In the exemplary embodiment, in the pixel driving circuits provided in Figures 17, 18, 21, and 22, before and after the signal of the fourth node N4 undergoes a transition, the variables related to the fourth node N4 satisfy the charge conservation equation of the third node N3.

[0484] [V3-(V IN1 -Vth)]*(C1+C OLED )+{(V3-Vdata)-[(V IN1 -Vth)-V IN2 ]}*C2=0, where C OLED Let V be the parasitic capacitance of the light-emitting device L. V3 = [C2 / (C1+C2+C...] OLED )]*(V IN2 -Vdata)+V IN1 -Vth

[0485] Since the signal of the first node N1 before the light-emitting stage is the signal of the first input signal terminal IN1, that is, V1 = V IN1 Therefore, Vgs = V1 - V3 = [C2 / (C1 + C2 + C OLED )]*(V IN2 -Vdata)+Vth

[0486] In an exemplary embodiment, in the pixel driving circuits provided in Figures 31, 32, 33, 36 to 40, before and after the signal of the fourth node N4 undergoes a transition, the variables related to the fourth node N4 satisfy the charge conservation equation of the third node N3 [V3-(V IN1 -Vth)]*C1+{(V3-Vdata)-[(V IN1 -Vth)-V IN2]}*C2=0 V3=[C2 / (C1+C2)]*(V IN2 -Vdata)+V IN1 -Vth

[0487] Since the signal of the first node N1 before the light-emitting stage is the signal of the first input signal terminal IN1, that is, V1 = V IN1 Therefore, Vgs = V1 - V3 = [C2 / (C1 + C2)] * (V IN2 -Vdata)+Vth

[0488] Regarding the driving timing mentioned above, for embodiments including transistor T7: S1-S4 can be a refresh period. At the first driving frequency, a display frame can include one refresh period. The first driving frequency can be a frequency in high-frequency driving mode. At the second driving frequency, a display frame can include one refresh period and at least one hold period. The hold period can be defined as a self-scanning period where no data signal is written, the data signal written in the refresh period is held, and the pixel emits light. The second driving frequency can be a frequency in low-frequency driving mode. The hold period can include a first hold period and a second hold period. In the first hold period, only the seventh transistor T7 is turned on, and all other transistors are turned off to reset the anode of the light-emitting device, i.e., the signal at the fourth scan signal terminal Gate4 is an effective level signal. The seventh transistor T7 can be turned on multiple times, and the number of times is not limited. In the second hold period, the seventh transistor T7 is turned off, and the fifth transistor T5 and the sixth transistor T6 are turned on, and the light-emitting device L emits light.

[0489] When the embodiment further includes an eighth transistor T8, the eighth transistor T8 may also be turned on during the first holding phase, writing the fourth initial signal into the second node N2 to bias the driving transistor; the turn-on time of the eighth transistor T8 may occur after the turn-on time of the seventh transistor T7, or it may be at the same time as the turn-on time of the seventh transistor T7. This disclosure does not limit this. The eighth transistor T8 may be turned on multiple times, and the number of times is not limited.

[0490] This disclosure also provides a method for driving a pixel driving circuit, configured to drive the pixel driving circuit provided in any of the foregoing embodiments. The method for driving the pixel driving circuit may include:

[0491] Step 100: Under the control of the signal from the first node, the driving sub-circuit provides a driving signal to the third node;

[0492] Step 200: Under the control of the signal at the first scanning signal terminal, the first initial sub-circuit provides the signal at the first input signal terminal to the first node;

[0493] Step 300: Under the control of the signal at at least one scanning signal terminal, the coupling sub-circuit couples the signal at the data signal terminal or the second input signal terminal to the third node;

[0494] Step 400: Maintain the voltage difference between the signals of the first node and the third node stored in the sub-circuit;

[0495] Step 500: Under the control of the signal at the first light-emitting signal terminal, the light-emitting control sub-circuit provides the signal at the first power supply terminal to the second node.

[0496] This disclosure also provides a display device, including: any one of the aforementioned pixel driving circuits arranged in an array.

[0497] The display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, multiple scan signal terminals, multiple data signal lines, multiple light-emitting signal lines, and a pixel array. The timing controller is connected to the data driver, scan driver, and light-emitting driver. The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit. The first and second light-emitting signal terminals connected to the pixel driving circuit are electrically connected to the light-emitting signal lines. At least one scan signal terminal connected to the pixel driving circuit is electrically connected to the scan signal line, and the data signal terminal connected to the pixel driving circuit is electrically connected to the data signal line.

[0498] The data driver is connected to multiple data signal lines, the scan driver is connected to multiple scan signal lines, and the light-emitting driver is connected to multiple light-emitting signal lines. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines. For example, the data driver can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines on a pixel-by-pixel basis. The scan driver can generate scan signals to be provided to the scan signal lines by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to the scan signal lines. For example, a scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. An LED driver can generate transmit signals to be provided to the LED signal lines by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, an LED driver can sequentially provide transmit signals with off-level pulses to the LED signal lines. For example, an LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of off-level pulses, to the next stage circuit under the control of a clock signal.

[0499] The display device may include a plurality of pixel units arranged in a matrix. At least one of the plurality of pixel units includes a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. Each of the first, second, and third sub-pixels includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first, second, and third sub-pixels are respectively connected to a gate signal line and a data signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the gate signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first, second, and third sub-pixels are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0500] In an exemplary embodiment, the first sub-pixel can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light.

[0501] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side or in a triangular pattern, which is not limited in this disclosure.

[0502] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement, etc., and this disclosure does not limit the arrangement. In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement, etc., and this disclosure does not limit the arrangement.

[0503] In an exemplary embodiment, the display device can be any product or component with display function, such as a wearable device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0504] Figure 49 is a schematic diagram of a pixel driving circuit provided in another embodiment of this disclosure. As shown in Figure 49, the pixel driving circuit provided in this embodiment of the disclosure is configured to drive a light-emitting device to emit light. The pixel driving circuit includes: a driving sub-circuit, a coupling sub-circuit, a holding sub-circuit, a first initial sub-circuit, and a light-emitting control sub-circuit. The driving sub-circuit is electrically connected to a first node N1, a second node N2, and a third node N3, and is configured to provide a driving signal to the third node N3 under the control of the signals from the first node N1 and the second node N2. The first initial sub-circuit is electrically connected to a first input signal terminal IN1, a first scan signal terminal Gate1, and the first node N1, and is configured to provide a signal from the first input signal terminal IN1 to the first node N1 under the control of the signal from the first scan signal terminal Gate1. The coupling sub-circuit is electrically connected to a second scan signal terminal Gate2, a third scan signal terminal Gate3, a data signal terminal Data, a second input signal terminal IN2, and the third node N3, and is configured to provide a driving signal to the third node N3 under the control of the signals from the second scan signal terminal Gate2 and the third scan signal terminal Data. Under the control of the signal at Gate3, the signal at Data terminal or the signal at IN2 terminal is coupled to the third node N3; the holding sub-circuit, which is electrically connected to the first node N1 and the third node N3 respectively, is configured to store the voltage difference between the signals at the first node N1 and the third node N3; the light emission control sub-circuit, which is electrically connected to the first light emission signal terminal EM1, the second light emission signal terminal EM2, the first power supply terminal VDD, the second node N2, the third node N3 and the fifth node N5 respectively, is configured to provide the first power supply terminal VDD signal to the second node N2 and the third node N3 signal to the fifth node N5 under the control of the signals at the first light emission signal terminal EM1 and the second light emission signal terminal EM2; the light emission device L is electrically connected to the fifth node N5.

[0505] Figure 50 is an exemplary structural diagram of the pixel driving circuit provided in Figure 49. As shown in Figure 50, in the exemplary embodiment, the pixel driving circuit further includes a second initial sub-circuit. The second initial sub-circuit is electrically connected to the fourth scan signal terminal Gate4, the third input signal terminal IN3, and the third node N3, and is configured to provide the signal of the third input signal terminal IN3 to the third node N3 under the control of the signal of the fourth scan signal terminal Gate4; or, the second initial sub-circuit is electrically connected to the fourth scan signal terminal Gate4, the third input signal terminal IN3, and the fifth node N5, and is configured to provide the signal of the third input signal terminal IN3 to the fifth node N5 under the control of the signal of the fourth scan signal terminal Gate4.

[0506] Figure 51 is another exemplary structural diagram of the pixel driving circuit provided in Figure 49. As shown in Figure 51, in the exemplary embodiment, when the second initial sub-circuit is electrically connected to the fifth node N5, the pixel driving circuit further includes a third initial sub-circuit. The third initial sub-circuit is electrically connected to the fifth scan signal terminal Gate5, the fourth input signal terminal IN4, and the second node N2, respectively, and is configured to provide the signal of the fourth input signal terminal IN4 to the second node N2 under the control of the signal of the fifth scan signal terminal Gate5; or, it is electrically connected to the fifth scan signal terminal Gate5, the fourth input signal terminal IN4, and the third node N3, respectively, and is configured to provide the signal of the fourth input signal terminal IN4 to the third node N3 under the control of the signal of the fifth scan signal terminal Gate5.

[0507] Figure 52 is another exemplary structural diagram of the pixel driving circuit provided in Figure 49. As shown in Figure 52, in the exemplary embodiment, when the second initial sub-circuit is electrically connected to the third node N3, the pixel driving circuit further includes a third initial sub-circuit. The third initial sub-circuit is electrically connected to the fifth scan signal terminal Gate5, the fourth input signal terminal IN4, and the second node N2, respectively, and is configured to provide the signal of the fourth input signal terminal IN4 to the second node N2 under the control of the signal of the fifth scan signal terminal Gate5.

[0508] Figure 53 is an equivalent circuit diagram of the pixel driving circuit provided in Figure 50. As shown in Figure 53, the first initial sub-circuit includes: a first transistor T1; the holding sub-circuit includes: a first capacitor C1; the driving sub-circuit includes: a third transistor T3, which includes: a first control electrode and a second control electrode; the coupling sub-circuit includes: a second transistor T2, a fourth transistor T4, and a second capacitor C2; the light emission control sub-circuit includes: a fifth transistor T5 and a sixth transistor T6; and the second initial sub-circuit includes: a seventh transistor T7.

[0509] As shown in Figure 53, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first input signal terminal IN1, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the second input signal terminal IN2, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the first control electrode of the third transistor T3 is electrically connected to the first node N1, the second control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data. The control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the fourth scan signal terminal Gate4, the first electrode of the seventh transistor T7 is electrically connected to the third input signal terminal INI3, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5; the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the third node N3; the first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0510] In an exemplary embodiment, the fifth transistor T5 is a P-type transistor, and the other transistors besides the fifth transistor T5 (the first transistor T1 to the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7) are N-type transistors.

[0511] If the fifth transistor T5 is an N-type transistor, since the signal of the first power supply terminal VDD connected to the fifth transistor T5 is a high-level signal, the conduction voltage of the fifth transistor T5 is greater than the voltage value of the signal of the first power supply terminal VDD, resulting in a large power consumption of the display device where the pixel driving circuit is located. Therefore, this disclosure uses a P-type transistor for the fifth transistor. In this case, the conduction signal of the fifth transistor is a low-level signal, and the high-level signal of the first power supply terminal VDD will not affect the conduction signal of the fifth transistor. This not only reduces the threshold loss of the fifth transistor T5, but also reduces the power consumption of the display device where the pixel driving circuit is located.

[0512] In an exemplary embodiment, a pixel driving circuit is disposed in a display device. The content displayed by the display device includes multiple display frames. The driving modes of different display frames may include a first driving mode and a second driving mode. The first driving mode may be referred to as a low-frequency driving mode, and the second driving mode may be referred to as a high-frequency driving mode.

[0513] In an exemplary embodiment, refresh rate refers to the number of times the display substrate refreshes data per second. The refresh rate of the first driving mode set for the same display substrate is fixed, while the refresh rate of the first driving mode set for different display substrates may be different. The refresh rate of the display substrate in the first driving mode can range from 1Hz to 60Hz; for example, the refresh rate in the first driving mode can be approximately 10Hz.

[0514] In an exemplary embodiment, in a first driving mode, the display substrate refreshes display data in a refresh frame and holds the refreshed display data in a hold frame. In a second driving mode, a display frame may include a refresh frame but not a hold frame. In the second driving mode, the display substrate refreshes display data in a refresh frame. The refresh rate of the display substrate in the second driving mode can range from 60Hz to 480Hz; exemplaryly, the refresh rate in the first driving mode can be approximately 120Hz.

[0515] In one exemplary embodiment, the display substrate employs an alternating display function of a first driving mode and a second driving mode to reduce product power consumption.

[0516] Figure 54 is a timing diagram of the pixel driving circuit provided in Figure 53 during the refresh frame. As shown in Figure 54, the operation of the pixel driving circuit provided in Figure 53 during the refresh frame may include the following stages:

[0517] In the first stage (P11), the initialization stage, the signals at the first scan signal terminal (Gate1), the second scan signal terminal (Gate2), the fourth scan signal terminal (Gate4), and the first light-emitting signal terminal (EM1) are high-level signals, while the signals at the second light-emitting signal terminal (EM2) and the third scan signal terminal (Gate3) are low-level signals. The first transistor (T1), the second transistor (T2), and the seventh transistor (T7) are turned on, while the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) are turned off.

[0518] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is written into the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 , where V IN1 This represents the voltage value of the signal at the first input signal terminal IN1. When the second transistor T2 is turned on, the signal at the second input signal terminal IN2 is written to the fourth node N4, and the voltage value of the signal at the fourth node N4 is V4 = VIN2 , where V IN2 This represents the voltage value of the signal at the first input signal terminal IN2. With the seventh transistor T7 turned on, the signal at the third input signal terminal IN3 is written to the fifth node N5, and the voltage value of the signal at the fifth node N5 is V5 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0519] In the second stage, P12, the threshold compensation stage, the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light emission signal terminal EM1, the second light emission signal terminal EM2, and the third scan signal terminal Gate3 are low-level signals. The first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are turned on, while the fourth transistor T4 and the sixth transistor T6 are turned off.

[0520] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is continuously written to the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The second transistor T2 is turned on, and the signal at the second input signal terminal IN2 is continuously written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V IN2 When the fifth transistor T5 is turned on, the first power supply terminal VDD charges the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3 until the voltage value V3 of the signal at the third node N3 equals V. IN1 -Vth, where Vth is the threshold voltage of the third transistor. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is V... IN2 -V IN1 +Vth. The seventh transistor T7 is turned on, and the signal at the third input signal terminal IN3 is written to the fifth node N5. The voltage value of the signal at the fifth node N5 is V5 = V. IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0521] In the third stage (P13), the data writing stage, the signals of the first light-emitting signal terminal EM1, the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the fourth scan signal terminal Gate4 are high-level signals, while the signals of the second light-emitting signal terminal EM2 and the second scan signal terminal Gate2 are low-level signals. The first transistor T1, the fourth transistor T4, and the seventh transistor T7 are turned on, while the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0522] The first transistor T1 is turned on, and the signal at the first input signal terminal IN1 is continuously written to the first node N1. The voltage value of the signal at the first node N1 is V1 = V IN1 The fourth transistor T4 is turned on, and the data signal at the Data terminal is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = V data The voltage value of the signal at the fourth node N4 is changed from V in the previous stage. IN2 Jump to V data Under the coupling effect of the second capacitor C2, the voltage value V3 of the signal at the third node N3 also changes abruptly, V3 = V IN1 -Vth+(V data -V IN2 (C2 / C1+C2), where C1 is the capacitance of the first capacitor C1, and C2 is the capacitance of the second capacitor C2. The seventh transistor T7 is turned on, and the signal at the third input signal terminal IN3 is written to the fifth node N5. The voltage value of the signal at the fifth node N5 is V5 = V IN3 , where V IN3 This is the voltage value of the signal at the third input signal terminal IN3.

[0523] In the fourth stage (P14), the light-emitting stage, the signal at the second light-emitting signal terminal EM2 is a high-level signal, while the signals at the first light-emitting signal terminal EM1, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, and the fourth scan signal terminal Gate4 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned off.

[0524] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0525] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is V3 = Vss + V OLED The signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is V1 = V IN1 +Vss+V OLED -[V IN1 -Vth+(V data -V IN2 (C2 / C1+C2)]=Vss+V OLED +Vth-(Vdata -V IN2 (C2 / C1+C2)

[0526] At this time, the driving current I flowing through the third transistor T3 (which is also the driving current driving the light-emitting device L) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(V IN2 -V data (C2 / C1+C2)] 2

[0527] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0528] In the fifth stage (P15), the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 are low-level signals. The sixth transistor T6 and the seventh transistor T7 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0529] The sixth transistor T6 and the seventh transistor T7 are turned on, and the signal at the third input signal terminal IN3 is written to the third node N3 and the fifth node N5, thus resetting the third node N3 and the fifth node N5.

[0530] The pixel driving circuit in the refresh frame includes: multiple fourth stages P14 and multiple fifth stages P15, which are executed alternately.

[0531] Figure 55 is a timing diagram of the pixel driving circuit provided in Figure 53 during frame refresh. As shown in Figure 55, the pixel driving circuit provided in Figure 53 can include the following stages during frame refresh:

[0532] In stage six (P21), the signals at the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 are low-level signals. The sixth transistor T6 and the seventh transistor T7 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0533] The sixth transistor T6 and the seventh transistor T7 are turned on, and the signal at the third input signal terminal IN3 is written to the third node N3 and the fifth node N5, thus resetting the third node N3 and the fifth node N5.

[0534] In stage seven (P22), the light-emitting stage, the signal at the second light-emitting signal terminal EM2 is a high-level signal, while the signals at the first light-emitting signal terminal EM1, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, and the fourth scan signal terminal Gate4 are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned off.

[0535] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the first power supply terminal VDD provides driving current to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0536] The pixel driving circuit in the holding frame includes: multiple sixth stages P21 and multiple seventh stages P22, which are executed alternately.

[0537] Figure 56A is the second equivalent circuit diagram of the pixel driving circuit provided in Figure 50, and Figure 56B is the third equivalent circuit diagram of the pixel driving circuit provided in Figure 50. The pixel driving circuit provided in Figure 56A differs from that provided in Figure 56B in that the signal terminal connected to the control electrode of the sixth transistor T6 is different. In the pixel driving circuit provided in Figure 56B, the control electrode of the sixth transistor T6 is electrically connected to the first scan signal terminal Gate1. In the pixel driving circuit provided in Figure 56A, the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2. The pixel driving circuit provided in Figure 56A differs from that provided in Figure 53 in that, in the pixel driving circuit provided in Figure 56A, the sixth transistor T6 is a P-type transistor.

[0538] In an exemplary embodiment, when the fifth transistor T5 and the sixth transistor T6 are P-type transistors, the signal received by the second light-emitting signal terminal EM2 connected to the same pixel driving circuit is the same signal received by the first scanning signal terminal Gate1.

[0539] In this disclosure, the signal received by the second light-emitting signal terminal EM2 connected to the same pixel driving circuit is the same signal received by the first scanning signal terminal Gate1. This can reduce the number of signal terminals connected to the pixel driving circuit, reduce the area occupied by the pixel driving circuit, and achieve a high PPI in the display device.

[0540] In the exemplary embodiment, since the signal received by the second light-emitting signal terminal EM2 connected to the same pixel driving circuit is the same signal received by the first scanning signal terminal Gate1, the operation process of the pixel driving circuit provided in FIG56A is the same as that of the pixel driving circuit provided in FIG56B. The operation process of the pixel driving circuit provided in FIG56B will not be described again here.

[0541] Figure 57 shows the driving timing diagram of the pixel driving circuit provided in Figure 56A during the refresh frame. The driving timing diagram provided in Figure 57 differs from that provided in Figure 54 in that the signal timing of the second light-emitting signal terminal EM2 is different. The operation process of the pixel driving circuit provided in Figure 56A under the driving timing diagram provided in Figure 57 is the same as the operation process of the pixel driving circuit provided in Figure 53 under the driving timing diagram provided in Figure 54, and will not be described again here.

[0542] Figure 58 is the driving timing diagram of the pixel driving circuit provided in Figure 56A in the holding frame. The driving timing diagram provided in Figure 58 differs from that provided in Figure 56A in that the signal timing of the second light-emitting signal terminal EM2 is different. The operation process of the pixel driving circuit provided in Figure 56A in the driving timing diagram provided in Figure 58 is the same as the operation process of the pixel driving circuit provided in Figure 53 in the driving timing diagram provided in Figure 55, and will not be described again here.

[0543] Figure 59 is the equivalent circuit diagram of the pixel driving circuit provided in Figure 50. The pixel driving circuit provided in Figure 59 differs from the pixel driving circuit provided in Figure 53 in the connection method of the second terminal of the seventh transistor T7. In the pixel driving circuit provided in Figure 53, the second terminal of the seventh transistor T7 is electrically connected to the fifth node N5, while in the pixel driving circuit provided in Figure 59, the second terminal of the seventh transistor T7 is electrically connected to the third node N3.

[0544] Figure 60 is the driving timing diagram of the pixel driving circuit provided in Figure 59 during the refresh frame. The driving timing diagram provided in Figure 60 differs from that provided in Figure 54 in the signals of the fourth scan signal terminal in the third and fifth stages. The time for the Gate4 signal of the fourth scan signal terminal in the fifth stage of the driving timing diagram provided in Figure 60 to be an effective level signal is shorter than the time for the Gate4 signal of the fourth scan signal terminal in the fifth stage of the driving timing diagram provided in Figure 54 to be an effective level signal. The Gate4 signal of the fourth scan signal terminal in the third stage of the driving timing diagram provided in Figure 60 is a low level signal. The operation of the transistors other than the seventh transistor T7 in the pixel driving circuit provided in Figure 53 under the driving timing diagram provided in Figure 54 is the same as that of the transistors other than the seventh transistor T7 in the pixel driving circuit provided in Figure 59 under the driving timing diagram provided in Figure 60, and will not be repeated here. The following only describes the operation of the seventh transistor T7 in the pixel driving circuit provided in Figure 59 under the driving timing diagram provided in Figure 60.

[0545] The seventh transistor T7 is turned on in the first stage (P11) and the second stage (P12), and partially turned on in the fifth stage (P15). The signal at the third input signal terminal IN3 is written into the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 The seventh transistor T7 is disconnected in stage three (P13) and stage four (P14).

[0546] Figure 61 is the driving timing diagram of the pixel driving circuit provided in Figure 59 in the holding frame. The driving timing diagram provided in Figure 61 is different from the signal of the fourth scan signal terminal in the sixth stage in the driving timing diagram provided in Figure 55. The time for the signal of the fourth scan signal terminal Gate4 in the fifth stage of the driving timing diagram provided in Figure 61 to be an effective level signal is shorter than the time for the signal of the fourth scan signal terminal Gate4 in the fifth stage of the driving timing diagram provided in Figure 55 to be an effective level signal. The operation of the transistors other than the seventh transistor T7 in the pixel driving circuit provided in Figure 53 under the driving timing diagram provided in Figure 55 is the same as the operation of the transistors other than the seventh transistor T7 in the pixel driving circuit provided in Figure 59 under the driving timing diagram provided in Figure 61, and will not be repeated here. The following only describes the operation of the seventh transistor T7 in the pixel driving circuit provided in Figure 59 under the driving timing diagram provided in Figure 61.

[0547] The seventh transistor T7 is turned on for a portion of the time in stage 6 (P21), and the signal at the third input signal terminal IN3 is written into the third node N3. The voltage value of the signal at the third node N3 is V3 = V IN3 The seventh transistor T7 is disconnected at P22 in the seventh stage.

[0548] Figure 62 is the equivalent circuit diagram of the pixel driving circuit provided in Figure 50. The pixel driving circuit provided in Figure 62 differs from the pixel driving circuit provided in Figure 56A in the connection method of the second terminal of the seventh transistor T7. In the pixel driving circuit provided in Figure 56A, the second terminal of the seventh transistor T7 is electrically connected to the fifth node N5, while in the pixel driving circuit provided in Figure 62, the second terminal of the seventh transistor T7 is electrically connected to the third node N3.

[0549] Figure 63 is the driving timing diagram of the pixel driving circuit provided in Figure 62 during the refresh frame. The driving timing diagram provided in Figure 63 differs from that provided in Figure 57 in the signals of the fourth scan signal terminal in the third and fifth stages. The time for the Gate4 signal of the fourth scan signal terminal in the fifth stage of the driving timing diagram provided in Figure 63 to be an effective level signal is shorter than the time for the Gate4 signal of the fourth scan signal terminal in the fifth stage of the driving timing diagram provided in Figure 57 to be an effective level signal. The Gate4 signal of the fourth scan signal terminal in the driving timing diagram provided in Figure 63 is a low level signal. The operation of the transistors other than the seventh transistor T7 in the pixel driving circuit provided in Figure 56A under the driving timing diagram provided in Figure 57 is the same as that of the transistors other than the seventh transistor T7 in the pixel driving circuit provided in Figure 62 under the driving timing diagram provided in Figure 63, and will not be repeated here. The following only describes the operation of the seventh transistor T7 in the pixel driving circuit provided in Figure 62 under the driving timing diagram provided in Figure 63.

[0550] The seventh transistor T7 is turned on in the first stage (P11) and the second stage (P12), and partially turned on in the fifth stage (P15). The signal at the third input signal terminal IN3 is written into the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN3 The seventh transistor T7 is disconnected in stage three (P13) and stage four (P14).

[0551] Figure 64 is a timing diagram of the pixel driving circuit provided in Figure 62 in the holding frame. The driving timing diagram provided in Figure 64 differs from the signal of the fourth scan signal terminal in the sixth stage in the driving timing diagram provided in Figure 58. The time for the signal of the fourth scan signal terminal Gate4 in the fifth stage of the driving timing diagram provided in Figure 64 to be an effective level signal is shorter than the time for the signal of the fourth scan signal terminal Gate4 in the fifth stage of the driving timing diagram provided in Figure 58 to be an effective level signal. The operation of the transistors other than the seventh transistor T7 in the pixel driving circuit provided in Figure 56A under the driving timing diagram provided in Figure 58 is the same as the operation of the transistors other than the seventh transistor T7 in the pixel driving circuit provided in Figure 62 under the driving timing diagram provided in Figure 64, and will not be repeated here. The following only describes the operation of the seventh transistor T7 in the pixel driving circuit provided in Figure 62 under the driving timing diagram provided in Figure 64.

[0552] The seventh transistor T7 is turned on for a portion of the time in stage 6 (P21), and the signal at the third input signal terminal IN3 is written into the third node N3. The voltage value of the signal at the third node N3 is V3 = V IN3 The seventh transistor T7 is disconnected at P22 in the seventh stage.

[0553] Figure 65 is an equivalent circuit diagram of the pixel driving circuit provided in Figure 51. The pixel driving circuit in Figure 65 differs from that in Figure 53 in that it further includes an eighth transistor T8. The control terminal of the eighth transistor is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor is electrically connected to the second node N2.

[0554] Figure 66 is the driving timing diagram of the pixel driving circuit provided in Figure 65 during the refresh frame. The driving timing diagram in Figure 66 differs from that in Figure 54 in that it includes the timing of the signal at the fifth scan signal terminal, Gate5. The operation of the first transistor T1 to the seventh transistor T7 in the driving timing diagram provided in Figure 66 is the same as the operation of the remaining transistors (excluding the first transistor T1 to the seventh transistor T7) in the pixel driving circuit provided in Figure 53 under the driving timing diagram provided in Figure 54, and will not be repeated here. The following only describes the operation of the eighth transistor T8 in the pixel driving circuit provided in Figure 65 under the driving timing diagram provided in Figure 66.

[0555] The eighth transistor T8 is turned on in the first stage P11 and the second stage P12. The signal at the fourth input signal terminal IN4 is written into the second node N2, and the voltage value of the signal at the second node N2 is V2 = V IN4 , where V IN4 This is the voltage value of the signal at the fourth input signal terminal IN4. The eighth transistor T8 is turned off from stage 3 (P13) to stage 5 (P15).

[0556] Figure 67 is the driving timing diagram of the pixel driving circuit provided in Figure 65 in the holding frame. The driving timing diagram provided in Figure 67 differs from that provided in Figure 55 in that the driving timing diagram in Figure 67 includes the timing of the signal at the fifth scan signal terminal, Gate5. The operation of the first transistor T1 to the seventh transistor T7 in the driving timing diagram provided in Figure 67 of the pixel driving circuit provided in Figure 65 is the same as the operation of the remaining transistors other than the first transistor T1 to the seventh transistor T7 in the pixel driving circuit provided in Figure 53 under the driving timing diagram provided in Figure 55, and will not be repeated here. The following only describes the operation of the eighth transistor T8 in the pixel driving circuit provided in Figure 65 under the driving timing diagram provided in Figure 67.

[0557] The eighth transistor T8 is disconnected in stage 6 P21 and stage 7 P22.

[0558] Figure 68 is a second equivalent circuit diagram of the pixel driving circuit provided in Figure 51. The pixel driving circuit in Figure 68 differs from the pixel driving circuit in Figure 56A in that it further includes an eighth transistor T8. The control terminal of the eighth transistor is electrically connected to the fifth scan signal terminal Gate5, the first terminal of the eighth transistor is electrically connected to the fourth input signal terminal IN4, and the second terminal of the eighth transistor is electrically connected to the second node N2.

[0559] In an exemplary embodiment, when the fifth transistor T5 and the sixth transistor T6 are P-type transistors, the signal received by the second light-emitting signal terminal EM2 connected to the same pixel driving circuit is the same signal received by the first scanning signal terminal Gate1.

[0560] In this disclosure, the signal received by the second light-emitting signal terminal EM2 connected to the same pixel driving circuit is the same signal received by the first scanning signal terminal Gate1. This can reduce the number of signal terminals connected to the pixel driving circuit, reduce the area occupied by the pixel driving circuit, and achieve a high PPI in the display device.

[0561] Figure 69 is the driving timing diagram of the pixel driving circuit provided in Figure 68 during the refresh frame. The driving timing diagram provided in Figure 69 differs from that provided in Figure 57 in that it includes the timing of the signal at the fifth scan signal terminal, Gate5. The operation of the first transistor T1 to the seventh transistor T7 in the driving timing diagram provided in Figure 69 is the same as the operation of the remaining transistors (excluding the first transistor T1 to the seventh transistor T7) in the pixel driving circuit provided in Figure 56A under the driving timing diagram provided in Figure 57, and will not be repeated here. The following only describes the operation of the eighth transistor T8 in the pixel driving circuit provided in Figure 68 under the driving timing diagram provided in Figure 69.

[0562] The eighth transistor T8 is turned on in the first stage P11 and the second stage P12. The signal at the fourth input signal terminal IN4 is written into the second node N2, and the voltage value of the signal at the second node N2 is V2 = V IN4 , where V IN4 This is the voltage value of the signal at the fourth input signal terminal IN4. The eighth transistor T8 is turned off from stage 3 (P13) to stage 5 (P15).

[0563] Figure 70 is a timing diagram of the pixel driving circuit provided in Figure 68 in the holding frame. The driving timing diagram provided in Figure 70 differs from that provided in Figure 58 in that it includes the timing of the signal at the fifth scan signal terminal, Gate5. The operation of the first transistor T1 to the seventh transistor T7 in the pixel driving circuit provided in Figure 68 under the driving timing diagram provided in Figure 70 is the same as the operation of the remaining transistors (excluding the first transistor T1 to the seventh transistor T7) in the pixel driving circuit provided in Figure 56A under the driving timing diagram provided in Figure 58, and will not be repeated here. The following only describes the operation of the eighth transistor T8 in the pixel driving circuit provided in Figure 68 under the driving timing diagram provided in Figure 70.

[0564] The eighth transistor T8 is disconnected in stage 6 P21 and stage 7 P22.

[0565] Figure 71 is the equivalent circuit diagram of the pixel driving circuit provided in Figure 51. The pixel driving circuit provided in Figure 71 differs from the pixel driving circuit provided in Figure 65 in that the second terminal of the eighth transistor T8 in the pixel driving circuit provided in Figure 71 is electrically connected to the third node N3.

[0566] The driving timing sequences provided in Figure 66 and Figure 67 can be applied to the pixel driving circuit provided in Figure 71. The operation of the first transistor T1 to the seventh transistor T7 in the driving timing sequence provided in Figure 66 is the same as the operation of the remaining transistors (excluding the first transistor T1 to the seventh transistor T7) in the pixel driving circuit provided in Figure 65 under the driving timing sequence provided in Figure 66, and will not be repeated here. The following only describes the operation of the eighth transistor T8 in the pixel driving circuit provided in Figure 71 under the driving timing sequence provided in Figure 66.

[0567] The eighth transistor T8 is turned on in the first stage P11 and the second stage P12. The signal at the fourth input signal terminal IN4 is written into the third node N3, and the voltage value of the signal at the third node N3 is V3 = V IN4 , where V IN4 This is the voltage value of the signal at the fourth input signal terminal IN4. The eighth transistor T8 is turned off from stage 3 (P13) to stage 5 (P15).

[0568] The operation of the first transistor T1 to the eighth transistor T8 in the driving timing provided in Figure 67 of the pixel driving circuit shown in Figure 71 is the same as that of the first transistor T1 to the eighth transistor T8 in the driving timing provided in Figure 67 of the pixel driving circuit shown in Figure 65, and will not be described again here.

[0569] Figure 72 is the equivalent circuit diagram of the pixel driving circuit provided in Figure 51. The difference between the pixel driving circuit in Figure 72 and the pixel driving circuit provided in Figure 68 is that the second terminal of the eighth transistor T8 in the pixel driving circuit provided in Figure 72 is electrically connected to the third node N3.

[0570] In an exemplary embodiment, when the fifth transistor T5 and the sixth transistor T6 are P-type transistors, the signal received by the second light-emitting signal terminal EM2 connected to the same pixel driving circuit is the same signal received by the first scanning signal terminal Gate1.

[0571] In this disclosure, the signal received by the second light-emitting signal terminal EM2 connected to the same pixel driving circuit is the same signal received by the first scanning signal terminal Gate1. This can reduce the number of signal terminals connected to the pixel driving circuit, reduce the area occupied by the pixel driving circuit, and achieve a high PPI in the display device.

[0572] The driving timing sequences provided in Figure 69 and Figure 70 can be applied to the pixel driving circuit provided in Figure 72. The operation of the first transistor T1 to the seventh transistor T...

Claims

A pixel driving circuit is configured to drive a light-emitting device to emit light, wherein, The pixel driving circuit includes: a driving sub-circuit, a coupling sub-circuit, a holding sub-circuit, a first initialization sub-circuit, and a light emission control sub-circuit; The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node. The first initial sub-circuit is electrically connected to the first input signal terminal, the first scan signal terminal, and the first node, respectively, and is configured to provide the signal from the first input signal terminal to the first node under the control of the signal from the first scan signal terminal; The coupling sub-circuit is electrically connected to the second scan signal terminal, the third scan signal terminal, the data signal terminal, the second input signal terminal, and the third node, respectively, and is configured to couple the signal from the data signal terminal or the second input signal terminal to the third node under the control of the signals from the second scan signal terminal and the third scan signal terminal. The holding sub-circuit, which is electrically connected to the first node and the third node respectively, is configured to store the voltage difference between the signals of the first node and the third node; The light-emitting control sub-circuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fifth node, respectively. It is configured to provide the signal from the first power supply terminal to the second node and the signal from the third node to the fifth node under the control of the signals from the first light-emitting signal terminal and the second light-emitting signal terminal. The light-emitting device is electrically connected to the fifth node. According to the pixel driving circuit of claim 1, wherein, The light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the second light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fifth node. The fifth transistor is a P-type transistor. According to the pixel driving circuit of claim 2, wherein, The pixel driving circuit includes multiple transistors, all of which except for the fifth transistor are N-type transistors. According to the pixel driving circuit of claim 2, wherein, The pixel driving circuit includes multiple transistors, with the sixth transistor being a P-type transistor and the remaining transistors, excluding the fifth and sixth transistors, being N-type transistors. According to the pixel driving circuit of claim 4, wherein, The signal received by the second light-emitting signal terminal connected to the same pixel driving circuit is the same signal as the signal received by the first scanning signal terminal. The pixel driving circuit according to any one of claims 1 to 5, wherein, The signal received by the first input signal terminal connected to the same pixel driving circuit and the signal received by the second input signal terminal are the same signal. The pixel driving circuit according to any one of claims 3 to 5 further comprises: Second initial sub-circuit; The second initial sub-circuit is electrically connected to the fourth scan signal terminal, the third input signal terminal, and the third node, respectively, and is configured to provide the signal from the third input signal terminal to the third node under the control of the signal from the fourth scan signal terminal. According to the pixel driving circuit of claim 7, wherein, The second initial sub-circuit includes: a seventh transistor; The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the third node. The pixel driving circuit according to any one of claims 3 to 5 further comprises: Second initial sub-circuit; The second initial sub-circuit is electrically connected to the fourth scan signal terminal, the third input signal terminal, and the fifth node, respectively, and is configured to provide the signal from the third input signal terminal to the fifth node under the control of the signal from the fourth scan signal terminal. According to the pixel driving circuit of claim 9, wherein, The second initial sub-circuit includes: a seventh transistor; The control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the third input signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node. The pixel driving circuit according to claim 8 or 10 further includes: Third initial sub-circuit; The third initial sub-circuit is electrically connected to the fifth scan signal terminal, the fourth input signal terminal, and the second node, respectively, and is configured to provide the signal from the fourth input signal terminal to the second node under the control of the signal from the fifth scan signal terminal. According to the pixel driving circuit of claim 11, wherein, The third initial sub-circuit includes: an eighth transistor; The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth input signal terminal, and the second electrode of the eighth transistor is electrically connected to the second node. The pixel driving circuit according to claim 10 further includes: Third initial sub-circuit; The third initial sub-circuit is electrically connected to the fifth scan signal terminal, the fourth input signal terminal, and the third node, respectively, and is configured to provide the signal from the fourth input signal terminal to the third node under the control of the signal from the fifth scan signal terminal. According to the pixel driving circuit of claim 13, wherein, The third initial sub-circuit includes: an eighth transistor; The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the fourth input signal terminal, and the second electrode of the eighth transistor is electrically connected to the third node. According to the pixel driving circuit of claim 1, wherein, The first initial sub-circuit includes: a first transistor; the holding sub-circuit includes: a first capacitor; the driving sub-circuit includes: a third transistor, the third transistor includes: a first control electrode and a second control electrode; and the coupling sub-circuit includes: a second transistor, a fourth transistor and a second capacitor. The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first input signal terminal, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the second input signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node. The first control electrode of the third transistor is electrically connected to the first node, the second control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the third node. The first terminal of the second capacitor is electrically connected to the fourth node, and the second terminal of the second capacitor is electrically connected to the third node. A display device, comprising: The pixel driving circuit of any one of claims 1 to 15 is arranged in an array. The display device according to claim 16 further includes: The first data unit and the second data unit, the content displayed by the display device includes: multiple display frames, at least one display frame including: a refresh frame and a hold frame; The first data unit provides an effective level signal to the first light-emitting signal terminal during the refresh frame and the hold frame, and the second data unit provides an effective level signal to the second light-emitting signal terminal during the refresh frame and the hold frame; In the refresh frame and hold frame, the time period during which the first data unit provides an effective level signal to the first light-emitting signal terminal includes: multiple first time periods; the time period during which the second data unit provides an effective level signal to the second light-emitting signal terminal includes: a second time period. In the refresh frame, the first time interval occurs before the second time interval, and all other time intervals except the first time interval are within the second time interval. The duration of the first time interval is shorter than the duration of all other time intervals except the first time interval. In the hold frame, multiple first time periods are all located within the second time period. The display device according to claim 17 further includes: The third data unit, the fourth data unit, and the fifth data unit are configured such that the third data unit provides a valid level signal to the first scan signal terminal during the refresh frame and an invalid level signal to the first scan signal terminal during the hold frame; the fourth data unit provides a valid level signal to the second scan signal terminal during the refresh frame and an invalid level signal to the second scan signal terminal during the hold frame; and the fifth data unit provides a valid level signal to the third scan signal terminal during the refresh frame and an invalid level signal to the third scan signal terminal during the hold frame. In at least one refresh frame, the time period during which the third data unit provides an effective level signal to the first scan signal terminal includes: the third time period; the time period during which the fourth data unit provides an effective level signal to the second scan signal terminal includes: the fourth time period; and the time period during which the fifth data unit provides an effective level signal to the third scan signal terminal includes: the fifth time period. The third time period occurs before the second time period. The first time period is located within the third and fourth time periods and occurs before the fifth time period. The fourth time period overlaps with the third time period and occurs before the fifth time period. The fifth time period is located within the third time period. The display device according to claim 18 further includes: The sixth data unit provides a valid level signal to the fourth scan signal terminal during refresh and hold frames; The sixth data unit provides a valid level signal to the fourth scan signal terminal during the refresh frame and hold frame, including multiple sixth time periods; In the refresh frame, the first sixth time period is located within the third time period, and the nth sixth time period is located between the nth first time period and the (n+1)th first time period. n is a positive integer greater than 1 and less than or equal to N, and N is the total number of sixth time periods. While maintaining the frame, multiple first time periods and multiple sixth time periods are arranged alternately. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as described in any one of claims 1 to 15, the method comprising: The driving sub-circuit provides a driving signal to the third node under the control of the signals from the first and second nodes; The first initial sub-circuit provides the first input signal terminal signal to the first node under the control of the first scan signal terminal signal; Under the control of the signals at the second scan signal terminal and the third scan signal terminal, the coupler circuit couples the signal at the data signal terminal or the second input signal terminal to the third node; Maintain the voltage difference between the signals stored in the first and third nodes in the sub-circuit; Under the control of the signals from the first and second light-emitting signal terminals, the light-emitting control sub-circuit provides the first power supply signal to the second node and the third node signal to the fifth node.

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