Invalid power consumption analysis method, electronic device and storage medium

Abstract

This invention belongs to the field of electronic design automation (EDA) technology and proposes an ineffective power consumption analysis method, electronic device, and storage medium. The method includes: performing an analyzability check on an instance in a circuit design to determine if the instance is an analyzable device, whereby an analyzable device performs a preset function by responding to control signals; if the instance is an analyzable device, acquiring the control signal waveform of the instance and determining the mapping relationship between each signal state contained in the control signal waveform and each data pin of the instance; traversing the control signal waveform to determine the ineffective period of each data pin according to the mapping relationship within the time interval of the control signal waveform, whereby switching events of each data pin during its respective ineffective period do not affect the circuit function, thus causing ineffective power consumption. This invention can determine ineffective power consumption based on the ineffective periods of the device, allowing users to reduce the occurrence of ineffective power consumption by improving signal frequency, etc.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to an ineffective power consumption analysis method, electronic device, and storage medium. Background Technology

[0002] With the advancement of manufacturing and design technologies, the design methods of electronic systems have undergone profound changes, from Computer-Aided Design (CAD) and Computer-Aided Engineering (CAE) to Electronic Design Automation (EDA). The degree of automation in design is increasing, and the complexity of design is also increasing.

[0003] Integrated circuit (IC) EDA refers to the design method that uses electronic design automation software to complete the functional design, synthesis, verification, and physical design (including placement, routing, layout, and design rule checking) of very large-scale integrated circuit (VLSI) chips. Currently, EDA technology has become a powerful tool in modern electronic design. Without the support of EDA technology, it would be unimaginable to design and manufacture VLSI. IC designers need to use EDA tools to develop complex integrated circuits with hundreds of thousands to tens of billions of transistors to reduce design deviations, improve tape-out success rates, and save tape-out costs.

[0004] For decades, the primary goal of chip design has been to pursue higher performance (faster computing speed). However, with the continuous advancement of semiconductor processes (such as moving to 28nm, 7nm, 5nm, and even lower nodes), power consumption has replaced area and performance as the most critical and challenging metric in chip design. Besides the power required to achieve the target function, modern chips also contain a significant amount of ineffective power consumption that does not substantially contribute to the output of the target function. This not only increases the overall energy consumption of the chip but can also lead to heat dissipation issues and reliability problems.

[0005] While EDA tools for related technologies can analyze the overall power consumption of a chip or the power consumption of local modules, they lack the ability to identify and characterize invalid power consumption with finer granularity. This makes it difficult to accurately locate the source of invalid power consumption, limits the targeting of subsequent low-power optimization, and exposes problems such as outdated methodology, insufficient accuracy, and poor efficiency. Therefore, a more accurate and efficient way to analyze invalid power consumption is needed. Summary of the Invention

[0006] This invention provides a method for analyzing ineffective power consumption, an electronic device, and a storage medium, to at least solve the problems of low efficiency and insufficient accuracy in the analysis of ineffective power consumption in related technologies. The technical solution of this invention is as follows:

[0007] According to a first aspect of the present invention, an ineffective power consumption analysis method is provided, applied to electronic design automation software. The method includes: performing an analyzability check on an instance in a circuit design to determine whether the instance is an analyzable device, wherein the analyzable device implements a preset function by responding to a control signal; if the instance is an analyzable device, acquiring the control signal waveform of the instance, and determining a mapping relationship between each signal state contained in the control signal waveform and each data pin of the instance; traversing the control signal waveform to determine an ineffective period of each data pin according to the mapping relationship within the time interval of the control signal waveform, wherein a switching event of each data pin in its respective ineffective period does not affect the circuit function, such that the switching event causes ineffective power consumption.

[0008] According to a second aspect of the present invention, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions, wherein, when executed by the processor, the processor causes the processor to perform an ineffective power consumption analysis method according to the present invention.

[0009] According to a third aspect of the present invention, a computer-readable storage medium is provided, wherein when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the ineffective power consumption analysis method according to the present invention.

[0010] The technical solution provided by this invention brings at least the following beneficial effects:

[0011] This invention can determine the invalid time period corresponding to the invalid switching event on the data pin of the device that does not affect the circuit function based on the input waveform of the analyzable device in the circuit design. Thus, it can determine the invalid power consumption caused by the invalid switching event based on the invalid time period of the device. This allows users to reduce invalid power consumption by improving signal frequency, device switching state, etc., based on the invalid power consumption analysis results, thereby optimizing the power consumption of the entire circuit design.

[0012] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention, but do not constitute an undue limitation of the invention.

[0014] Figure 1 This is a flowchart illustrating an ineffective power consumption analysis method according to an exemplary embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram illustrating a 2-to-1 multiplexer according to an exemplary embodiment of the present invention;

[0016] Figure 3 This is a diagram showing the input waveform of a 2-to-1 multiplexer according to an exemplary embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram illustrating a D flip-flop according to an exemplary embodiment of the present invention;

[0018] Figure 5 This is a diagram showing the input waveform of a D flip-flop according to an exemplary embodiment of the present invention;

[0019] Figure 6 This is a block diagram illustrating an electronic device according to an exemplary embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0021] It should be noted that the steps in the specification and drawings of this invention are not limited to the specific order or sequence described. It should be understood that the steps used in this way can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in a sequence other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0022] As mentioned earlier, power consumption has become the most critical and challenging metric in chip design. The total power consumption of a chip mainly consists of three parts: dynamic power consumption, static power consumption, and surge power consumption. Dynamic power consumption refers to the power consumed by the switching activity of logic gates during chip operation, i.e., the power consumption generated when a signal transitions from 0 to 1 or from 1 to 0. Dynamic power consumption is the primary source of power consumption in circuit design. Furthermore, dynamic power consumption is composed of switching power consumption and short-circuit power consumption. Switching power consumption refers to the energy consumed in charging and discharging the load capacitor. Short-circuit power consumption refers to the power consumption caused by the short-circuit current generated when a direct conductive path is formed between the power supply and ground during the brief instant of transistor switching. In a well-designed system, this power consumption is usually relatively small.

[0023] It is evident that switching power consumption is one of the main sources of chip power consumption; therefore, optimizing switching power consumption helps reduce the overall power consumption of the chip. However, not all switching events contribute to the actual implementation of circuit functions. Power consumption caused by switching events that do not have a practical effect on circuit functionality can be called ineffective power consumption. Specifically, when a switching event does not affect the circuit function, the power consumption corresponding to that switching event can be considered ineffective power consumption. Since switching power consumption includes effective switching power consumption and ineffective switching power consumption, by analyzing the causes of ineffective power consumption and identifying the corresponding ineffective switching events, switching power consumption can be reduced in a targeted manner, thereby reducing the overall power consumption of the chip.

[0024] Static detection EDA tools for related technologies (such as Synopsys' Spyglass) lack finer-grained identification and characterization capabilities for invalid power consumption, which is not conducive to accurately locating the source of invalid power consumption, limiting the targeted nature of subsequent low-power optimization, and exposing problems such as outdated methodology, insufficient accuracy, and poor efficiency. They are gradually failing to meet the increasingly agile development needs of today.

[0025] In view of the above problems, exemplary embodiments of the present invention provide an ineffective power consumption analysis method, an electronic device, and a computer-readable storage medium, which can solve or at least alleviate the above problems.

[0026] In a first aspect of an exemplary embodiment of the present invention, an ineffective power consumption analysis method is provided, which will be referred to below. Figures 1 to 5Provide a detailed description.

[0027] According to an exemplary embodiment of the present invention, the ineffective power consumption analysis method is applicable to electronic design automation (EDA) software. The user terminal can load the EDA software, enabling it to perform analyzable checks on instances in the circuit design to determine whether an instance is an analyzable component. Here, an analyzable component implements a preset function by responding to a control signal. If the instance is an analyzable component, the control signal waveform of the instance is acquired, and the mapping relationship between each signal state contained in the control signal waveform and each data pin of the instance is determined. The control signal waveform is traversed to determine the ineffective time interval (ITI) of each data pin within the time interval of the control signal waveform based on the mapping relationship. Here, the switching events of each data pin during its respective ineffective time interval do not affect the circuit function, causing ineffective power consumption.

[0028] This method can determine the invalid periods corresponding to invalid switching events on the data pins of analyzable devices that do not affect the circuit function based on the input waveform of the analyzable devices in the circuit design. This allows the invalid power consumption caused by invalid switching events to be determined based on the invalid periods of the devices. Users can then reduce invalid power consumption by improving signal frequency, device switching states, etc., based on the results of invalid power consumption analysis, thereby optimizing the power consumption of the entire circuit design.

[0029] The aforementioned user terminal can be such as a tablet computer, laptop computer, digital assistant, wearable device, etc. However, the implementation scenario of the invalid power consumption analysis method described above is only an example scenario. The invalid power consumption analysis method according to the exemplary embodiment of the present invention can also be applied to other application scenarios. For example, it can also be that the user requests access to relevant data from the server via the network on the user terminal (e.g., mobile phone, desktop computer, tablet computer, etc.). The server can access the data by executing the invalid power consumption analysis method according to the exemplary embodiment of the present invention and return the result to the user terminal. Here, the server can be an independent server, a server cluster, a cloud computing platform, or a virtualization center, etc.

[0030] The following will refer to Figure 1 The specific steps of an ineffective power consumption analysis method according to an exemplary embodiment of the present invention are described below. For example... Figure 1 As shown, the ineffective power consumption analysis method may include the following steps:

[0031] In step S110, an analyzability check can be performed on instances in the circuit design to determine whether an instance is an analyzable device.

[0032] According to an exemplary embodiment of the present invention, designers typically use HDL (Hardware Description Language) to complete integrated circuit design. HDL describes the structure and behavior of digital system hardware in text form and can represent logic circuit diagrams, logic expressions, and the logic functions performed by the digital logic system. Thus, it can model multiple abstract design levels such as algorithm level, register transfer level, gate level, and switch level.

[0033] According to an exemplary embodiment of the present invention, invalid power consumption mainly originates from invalid switching events, thus allowing for targeted analysis of these events. For the entire circuit design, most invalid switching power consumption is caused by specific types of components. Therefore, it is unnecessary to analyze the invalid switching events of each individual component; analysis of the invalid switching events of a specific set of components is sufficient to achieve significant optimization of overall power consumption. Here, components can be categorized into analyzable and non-analyzable components based on whether the switching event triggers a downstream signal event. Analyzable components can implement preset functions by responding to control signals. By classifying components into analyzable and non-analyzable components, analysis can be focused on components that trigger downstream signal events, thereby narrowing the analysis scope, reducing analysis complexity and computational overhead, and avoiding redundant processing of components that lack effective analytical value.

[0034] Furthermore, analyzable devices may include combinational logic devices with control signals, such as multiplexers (MUX), and / or sequential logic devices, such as flip-flops (FF). Here, the output of a combinational logic device is determined solely by the current input, independent of past input / output states; the circuit contains no memory elements, and signals are transmitted unidirectionally from input to output. In contrast, the output of a sequential logic device depends not only on the current input but also on the circuit's historical states; the circuit contains memory elements capable of storing state information. It should be understood that, in addition to the above non-limiting examples, several specifications can be made for the analyzable devices in the circuit design according to the actual needs of the analysis, designating specified devices as analyzable devices and unspecified devices as non-analyzable devices, thereby further improving analysis efficiency. This invention does not limit this.

[0035] Next, in step S120, if the instance is an analyzable device, the control signal waveform of the instance can be obtained, and the mapping relationship between each signal state contained in the control signal waveform and each data pin of the instance can be determined.

[0036] According to an exemplary embodiment of the present invention, input waveforms related to a target instance can be obtained from a waveform file. Here, the input waveforms include at least one control signal waveform. Further, the control signal waveform can be used to characterize the control state of the target instance at a corresponding time and serve as the basis for determining the validity of the target instance's input signals and analyzing the validity of switching events. In some possible implementations, the input waveforms of the target instance can be obtained from a waveform file. These input waveforms can include the state changes of each input terminal of the target instance in the time dimension. Here, the target instance includes control input terminals, such as control signal pins and / or clock signal pins, so the input waveforms can include the control signal waveforms corresponding to the control input terminals. Further, the control signal waveforms can be used to characterize the control state of the target instance in different time intervals to further determine which inputs among the target instance's data pins are valid inputs and which are invalid inputs, and thereby analyze the validity of the corresponding switching events.

[0037] According to an exemplary embodiment of the present invention, the control signal waveform can be characterized using multi-valued logic states, such as logic 0, logic 1, unknown state X, and high-impedance state Z. Here, logic 0 indicates that the control signal is in a low-level state, and logic 1 indicates that the control signal is in a high-level state; unknown state X indicates that the current logic value of the control signal cannot be determined, for example, due to uninitialized signal, conflict of multiple drive sources, or simulation propagation, making it impossible to determine whether it is logic 0 or logic 1; high-impedance state Z indicates that the node corresponding to the control signal is in a high-impedance state, that is, the node is not effectively driven or is in a tri-state disconnected state. Based on the above different signal states, the control state of the target instance and its corresponding switching behavior in different time intervals can be further analyzed. It should be understood that unknown state X and high-impedance state Z are mainly used to describe the signal states during simulation, verification, or waveform analysis.

[0038] According to an exemplary embodiment of the present invention, the analyzable device may include a combinational logic device with control signals. The combinational logic device can use a functional expression to characterize the logical relationship between its output signals and each input signal. Each variable in the functional expression corresponds to a different input pin (including control signal pins and data pins) of the combinational logic device. Based on the functional expression, it is possible to determine the data pins that actually affect the output result and the data pins that do not have an actual effect under different values ​​of the target variable corresponding to the control signal pin. Therefore, in response to the instance being a combinational logic device, the functional expression of the instance can be determined, where the control signal pin of the instance corresponds to the target variable in the functional expression. Then, the state value (e.g., 0 or 1) of each signal state can be assigned to the target variable, and the assigned functional expression can be logically simplified to determine the mapping relationship between each signal state and each data pin of the instance based on the data pin corresponding to the simplification result. Establishing the mapping relationship between each signal state and the data pin based on the functional expression of the combinational logic device can fully utilize the logical functional characteristics of the device itself, distinguish the validity of data paths under different control states, and avoid misjudgments caused by relying solely on waveform statistics or empirical rules.

[0039] Furthermore, after determining the control signal pins and their corresponding target variables, a mapping relationship between each control signal state and an invalid data pin can be established based on the functional expression of the combinational logic device. Here, for different control signal states, such as logic 0, logic 1, unknown state X, and high-impedance state Z, data pins that do not actually affect the output result in the corresponding signal state can be determined, and these data pins can be designated as invalid data pins corresponding to that signal state, thus forming a mapping relationship from control signal states to invalid data pins.

[0040] In one possible implementation, for any signal state within each signal state, the state value of that signal state can be assigned to a target variable, and the assigned functional expression can be logically simplified to obtain a simplified result. Then, the data pins corresponding to the simplified result are excluded from the instance's data pins to obtain the instance's target data pins, and these target data pins are mapped to any signal state. This creates a mapping table from each signal state to the target data pins. When analyzing control signal waveforms, the corresponding target data pins can be directly determined from the mapping table based on the current state of the control signal within the target time period, and switching events generated by the target data pins within the target time period can be identified as invalid switching events. By using an exclusion method to determine the target data pins after simplification of the functional expression, the original process of identifying data pins through sequential confirmation can be transformed into a process of eliminating non-target data pins, thereby simplifying the mapping relationship establishment process and improving processing efficiency.

[0041] According to an exemplary embodiment of the present invention, the analyzable device may further include a sequential logic device, and the control signal waveform may include a clock signal waveform. For a sequential logic device, whether its data input can be sampled and applied to the output depends on whether the clock signal satisfies the triggering mode of the sequential logic device. Here, the triggering mode may be rising edge triggering, falling edge triggering, active high, or active low. When the clock signal is in a state that conforms to the triggering mode, the signal on the data pin can be sampled or transmitted to the output; when the clock signal is in a state that does not conform to the triggering mode, changes in the signal on the data pin generally do not cause an output update.

[0042] For example, for a rising-edge triggered flip-flop, data on the data pin is sampled only when the clock signal transitions from logic 0 to logic 1, thus the data pin can be mapped as an invalid data pin in the non-rising-edge state. For a falling-edge triggered flip-flop, data on the data pin is sampled only when the clock signal transitions from logic 1 to logic 0, thus the data input pin can be mapped as an invalid data pin in the non-falling-edge state. For a high-active latch, data on the data pin can be transmitted to the output only when the clock signal is high, thus the data pin can be mapped as an invalid data pin in the low-level state. For a low-active latch, data on the data pin can be transmitted to the output only when the clock signal is low, thus the data input pin can be mapped as an invalid data pin in the high-level state.

[0043] Based on this, a mapping relationship can be established between clock signal states that do not conform to the triggering mode and data pins, and the mapped data pins can be identified as invalid data pins in the corresponding signal states. In one possible implementation, in response to the instance being a sequential logic device, the triggering mode of the instance can be determined. Here, the triggering mode includes at least one of rising edge triggering, falling edge triggering, active high, and active low. Then, the target signal states that do not conform to the triggering mode in each signal state can be mapped to the data pins of the instance. By establishing a mapping relationship between target signal states and data pins based on the triggering mode of the sequential logic device, data pins that do not cause output updates can be accurately identified, thereby improving the accuracy and efficiency of invalid switch event analysis.

[0044] Next, in step S130, the control signal waveform can be traversed to determine the invalid period of each data pin according to the mapping relationship within the time interval of the control signal waveform.

[0045] According to an exemplary embodiment of the present invention, the switching events of each data pin during its respective invalid period do not affect the circuit function, thus causing invalid power consumption due to the switching events during the invalid period (i.e., invalid switching events). Here, an invalid period refers to a specific time period in which the signal of the relevant data pin undergoes a state transition, but this state transition does not affect the output result, state update, or actual function of the instance. Since the switching events occurring during this period do not actually contribute to the implementation of the circuit function, this period can be regarded as an invalid period (i.e., an invalid switching period). Switching events generated during the invalid period can be further identified as invalid switching events, and the power consumption caused by the invalid switching events can be determined as invalid power consumption.

[0046] In one possible implementation, if the instance is a combinational logic device with control signals, then for any signal state in each signal state of the instance, a first time period corresponding to any signal state can be determined within the time interval of the control signal waveform. Given the mapping relationship between any signal state and the target data pin, the first time period can be used as the invalid time period of the target data pin. By determining the invalid time period of the target data pin within the time interval of the control signal waveform based on the mapping relationship of each signal state, the activity of data pins that do not affect the output can be accurately identified from the time dimension, thereby improving the accuracy of invalid switching event identification and the efficiency of invalid power consumption analysis.

[0047] In another possible implementation, if the instance is a sequential logic device, for each signal state of the instance that does not conform to the triggering method, a second time period corresponding to the target signal state can be determined within the time interval of the clock signal waveform. Given the mapping relationship between the target signal state and the instance's data pins, this second time period can be used as the invalid time period for the instance's data pins. For sequential logic devices, determining the invalid time period of data pins within the time interval of the clock signal waveform based on the mapping relationship of the target signal state allows for pre-screening of time ranges that will not participate in output updates, reducing analysis complexity and computational overhead, while improving the efficiency of invalid power consumption location.

[0048] Although the example steps for determining the invalid period of a data pin within the time interval of a control signal waveform by means of the mapping relationship between the signal state and the data pin are described above, the exemplary embodiments of the present invention are not limited thereto. As another example, in the case of a sequential logic device, the invalid period of the data pin may not be determined by means of the mapping relationship, but may be determined directly according to the triggering method of the instance to improve the analysis efficiency.

[0049] According to an exemplary embodiment of the present invention, in response to the instance being a sequential logic device, the clock signal waveform of the instance can be acquired, and the triggering mode of the instance can be determined. Here, the triggering mode includes at least one of rising edge triggering, falling edge triggering, active high level, and active low level. Then, the clock signal waveform is traversed to determine the invalid period of the data pin of the instance within a preset time interval of the clock signal waveform according to the triggering mode. For sequential logic devices, directly determining the invalid period of the data pin within the time interval of the clock signal waveform according to its triggering mode can utilize the operating characteristic of sequential logic devices that respond to input data only at specific edges or specific active levels. It can directly identify from the time dimension when the data pin will not be sampled, will not be transmitted to the output, or will not cause an output update, thereby simplifying the determination process of the invalid period and reducing the processing overhead caused by intermediate mapping analysis.

[0050] Furthermore, the trigger time or trigger period corresponding to the trigger mode can be determined within a preset time interval of the clock signal waveform. By excluding the trigger time or trigger period, a third period within the preset time interval is obtained, and this third period is used as the invalid period of the data pin in the example. Here, rising edge triggering and falling edge triggering correspond to the trigger time, and high level active and low level active correspond to the trigger period. By using the method of excluding the trigger time or trigger period to determine the invalid period of the data pin, the process that originally required forward segment-by-segment identification of valid periods can be transformed into direct screening of non-trigger time intervals. This simplifies the invalid period identification process of data pins in sequential logic devices, improves processing efficiency, and enhances the stability and interpretability of the invalid period division results.

[0051] The following will refer to Figure 2 and Figure 3 This describes a process for determining invalid periods of data pins for combinational logic devices with control signals, according to exemplary embodiments of the present invention. Figure 2 This is a schematic diagram illustrating a 2-to-1 multiplexer according to an exemplary embodiment of the present invention. Figure 3 This is a waveform diagram showing the input waveform of a 2-to-1 multiplexer according to an exemplary embodiment of the present invention.

[0052] like Figure 2 As shown, the example device is a 2-to-1 multiplexer (MUX), including data pins A and B, control signal pin C, and output pin O. (As shown...) Figure 3 As shown, the input waveforms of the multiplexer MUX include the control signal waveform corresponding to the control signal pin C and the data signal waveforms corresponding to the data pins A and B. The time range of the input waveforms is (0-50), and the time unit is, for example, but not limited to, nanoseconds (ns).

[0053] As an example, the invalid periods of data pins A and B can be determined through the following main steps to achieve invalid power consumption analysis of a multiplexer (MUX).

[0054] Step 1: Obtain the function expression of the multiplexer MUX, for example, (C*A) | (!C*B).

[0055] Step 2, obtain the control signal pin C.

[0056] Step 3: Arrange and combine all the signal states of the control signal to obtain the valid input under each signal state. For example, the signal states of C are 0 and 1. Substituting C=0 and C=1 into the function expression, we get that the valid input is B when C=0 and A when C=1.

[0057] Step 4: Traverse the waveform of C, obtain the waveform state, and determine the invalid inputs and time ranges. For example, in the 0-10 time period, C=0, B is a valid input, then A is an invalid input, so 0-10 is an invalid time period for A; in the 10-20 time period, C=1, A is a valid input, then B is an invalid input, so 10-20 is an invalid time period for B; and so on, the invalid time periods for data pin A are (0-10), (20-30), and (40-50), and the invalid time periods for data pin B are (10-20) and (30-40).

[0058] The following will refer to Figure 4 and Figure 5 This describes a process for determining invalid periods of data pins for sequential logic devices according to exemplary embodiments of the present invention. Figure 4 This is a schematic diagram illustrating a D flip-flop according to an exemplary embodiment of the present invention. Figure 5 This is a diagram showing the input waveform of a D flip-flop according to an exemplary embodiment of the present invention.

[0059] like Figure 4 As shown, the example device is a D flip-flop (DFF), including a data pin (D), a clock signal pin (CK), and an output pin (Q). Figure 5 As shown, the input waveform of the flip-flop DFF includes the clock signal waveform corresponding to the clock signal pin CK and the data signal waveform corresponding to the data pin D. The time range of the input waveform is (0-50), and the time unit is, for example, but not limited to, nanoseconds.

[0060] As an example, the invalid periods of data pin D can be determined through the following main steps to achieve invalid power consumption analysis of the flip-flop DFF.

[0061] Step 1: Obtain the clock signal pin CK and the trigger mode of the flip-flop DFF. Here, we assume that the trigger mode of the flip-flop DFF is rising edge triggered.

[0062] Step 2: Traverse the waveform of CK and obtain the trigger times of all rising edges of CK as 10 and 30. Then the signal on the data pin D will be sampled on the output pin Q at the trigger times of 10 and 30.

[0063] Step 3, the time periods other than the two trigger times in Step 2: (0-10), (10-30), and (30-50) are all invalid time periods for data pin D.

[0064] According to the exemplary embodiment of the present invention, the invalid power consumption analysis method can determine the invalid time period corresponding to the invalid switching event on the data pin of the device that does not affect the circuit function based on the input waveform of the analyzable device in the circuit design. Thus, it is possible to determine the invalid power consumption caused by the invalid switching event based on the invalid time period of the device. This allows users to reduce invalid power consumption by improving signal frequency, device switching state, etc., based on the invalid power consumption analysis results, thereby optimizing the power consumption of the entire circuit design.

[0065] In a second aspect of an exemplary embodiment of the present invention, an electronic device is provided, the electronic device comprising: a processor; and a memory for storing processor-executable instructions, wherein the processor-executable instructions, when executed by the processor, cause the processor to perform an ineffective power consumption analysis method according to an exemplary embodiment of the present invention.

[0066] Figure 6 This is a block diagram illustrating an electronic device according to an exemplary embodiment of the present invention. Figure 6 As shown, the electronic device 10 includes a processor 101 and a memory 102 for storing processor-executable instructions. Here, when executed by the processor, the processor-executable instructions cause the processor to perform an ineffective power consumption analysis method according to an exemplary embodiment of the present invention.

[0067] As an example, electronic device 10 is not necessarily a single device, but can be a collection of any means or circuits capable of executing the aforementioned instructions (or instruction sets) individually or in combination. Electronic device 10 can also be part of an integrated control system or system manager, or can be configured to interface with a server locally or remotely (e.g., via wireless transmission).

[0068] In electronic device 10, processor 101 may include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller, or a microprocessor. By way of example and not limitation, processor 101 may also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc.

[0069] The processor 101 can execute instructions or code stored in the memory 102, which can also store data. Instructions and data can also be sent and received over a network via a network interface device, which can employ any known transmission protocol.

[0070] The memory 102 may be integrated with the processor 101, for example, by placing RAM or flash memory within an integrated circuit microprocessor. Alternatively, the memory 102 may include a separate device, such as an external disk drive, a storage array, or other storage device that can be used by any database system. The memory 102 and the processor 101 may be operatively coupled, or may communicate with each other, for example, via I / O ports, network connections, etc., enabling the processor 101 to read files stored in the memory 102.

[0071] In addition, the electronic device 10 may also include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, mouse, touch input device, etc.). All components of the electronic device 10 can be connected to each other via a bus and / or network.

[0072] In an exemplary embodiment, a computer-readable storage medium may also be provided, which, when executed by a processor of an electronic device, enables the electronic device to perform the ineffective power consumption analysis method as described in the exemplary embodiment above. The computer-readable storage medium may be, for example, a memory including instructions. Optionally, the computer-readable storage medium may be: a read-only memory (ROM), a random access memory (RAM), a random access programmable read-only memory (PROM), an electrically erasable programmable read-only memory (EEPROM), a dynamic random access memory (DRAM), a static random access memory (SRAM), flash memory, non-volatile memory, a CD-ROM, a CD-R, a CD+R, a CD-RW, a CD+RW, a DVD-ROM, a DVD-R, a DVD+R, a DVD-RW, a DVD+RW, a DVD-RAM, a BD-ROM, a BD-R, or a BD-R... LTH, BD-RE, Blu-ray or optical disc storage, hard disk drive (HDD), solid-state drive (SSD), card storage (such as multimedia cards, secure digital (SD) cards, or ultra-fast digital (XD) cards), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state drive, and any other device configured to store a computer program and any associated data, data files, and data structures in a non-transitory manner and to provide the computer program and any associated data, data files, and data structures to a processor or computer so that the processor or computer can execute the computer program. The computer program in the aforementioned computer-readable storage medium can run in an environment deployed in computer devices such as clients, hosts, agent devices, servers, etc. Furthermore, in one example, the computer program and any associated data, data files, and data structures are distributed across a networked computer system, such that the computer program and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner through one or more processors or computers.

[0073] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0074] Furthermore, it should be noted that although several examples of each step have been described above with reference to the specific accompanying drawings, it should be understood that the embodiments of the present invention are not limited to the combinations given in the examples, and the steps appearing in different drawings can be combined, which will not be exhaustive here.

[0075] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the claims.

Claims

1. A method of nullity power consumption analysis, characterized by, The method, applied to electronic design automation software, includes: An analyzability check is performed on an instance of a circuit design to determine whether the instance is an analyzable device, wherein the analyzable device performs a preset function in response to a control signal; In the case where the instance is an analyzable device, the control signal waveform of the instance is acquired, and the mapping relationship between each signal state contained in the control signal waveform and each data pin of the instance is determined. The control signal waveform is traversed to determine the invalid period of each data pin according to the mapping relationship within the time interval of the control signal waveform. The switching events of each data pin in their respective invalid periods do not affect the circuit function, so that the switching events cause invalid power consumption.

2. The method of claim 1, wherein, The analyzable device includes a combinational logic device with control signals, wherein determining the mapping relationship between each signal state included in the control signal waveform and each data pin of the instance includes: In response to the instance being a combinational logic device, a functional expression for the instance is determined, wherein the control signal pins of the instance correspond to the target variable in the functional expression; The state value of each signal state is assigned to the target variable, and the functional expression after assignment is logically simplified to determine the mapping relationship based on the data pin corresponding to the simplification result.

3. The method of claim 2, wherein, The state value of each signal state is assigned to the target variable, and the functional expression after assignment is logically simplified to determine the mapping relationship based on the data pin corresponding to the simplification result, including: For any signal state in each of the signal states, the state value of any signal state is assigned to the target variable, and the functional expression after assignment is logically simplified to obtain the simplified result; Exclude the data pins corresponding to the simplification result from the data pins of the example to obtain the target data pins of the example, and map the target data pins to any of the signal states.

4. The ineffective power consumption analysis method according to claim 3, characterized in that, Within the time interval of the control signal waveform, determining the invalid period of each data pin according to the mapping relationship includes: determining a first period corresponding to any signal state within the time interval, and using the first period as the invalid period of the target data pin.

5. The method of claim 2, wherein, The analyzable device further includes a timing logic device, and the control signal waveform includes a clock signal waveform. Determining the mapping relationship between each signal state included in the control signal waveform and each data pin of the instance further includes: In response to the fact that the instance is a sequential logic device, the triggering mode of the instance is determined, wherein the triggering mode includes at least one of rising edge triggering, falling edge triggering, active high level, and active low level; Map the target signal state that does not conform to the triggering method in each signal state to the data pin of the instance.

6. The method of claim 5, wherein, Within the time interval of the control signal waveform, the invalid time period for each data pin is determined according to the mapping relationship, including: Within the time interval, a second time period corresponding to the target signal state is determined, and the second time period is used as the invalid time period for the data pin of the instance.

7. The method of claim 2, wherein, The analyzable device further includes a sequential logic device, wherein, in the case where the instance is an analyzable device, it further includes: In response to the fact that the instance is a sequential logic device, the clock signal waveform of the instance is acquired, and the triggering mode of the instance is determined, wherein the triggering mode includes at least one of rising edge triggering, falling edge triggering, active high level, and active low level; The clock signal waveform is traversed to determine the invalid period of the data pin of the instance within a preset time interval of the clock signal waveform according to the triggering method.

8. The method of claim 7, wherein, Within a preset time interval of the clock signal waveform, the invalid period of the data pin of the instance is determined according to the triggering method, including: Within the preset time interval, determine the trigger time or trigger period corresponding to the triggering method. By excluding the trigger time or trigger period, obtain the third period within the preset time interval, and use the third period as the invalid period of the data pin of the instance. Rising edge triggering and falling edge triggering correspond to the trigger time, and high level active and low level active correspond to the trigger period.

9. An electronic device, comprising: include: processor; Memory used to store processor-executable instructions. Wherein, when the processor executes the processor, it causes the processor to perform the ineffective power consumption analysis method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is able to perform the ineffective power consumption analysis method according to any one of claims 1 to 8.

Images