A high frame rate scheduling synchronization method and system for a multi-channel infrared digital prototype

Abstract

The application discloses a kind of high frame frequency scheduling synchronization method and system of multichannel infrared digital prototype, belong to infrared imaging simulation and digital prototype technical field, including: using producer-consumer mode decouples data preprocessing with core calculation;Efficient zero-copy data transmission from host to GPU is realized using lock page memory and DMA technology, and the switching overhead of page table of non-real-time operating system is avoided;Geometry imaging and sparse point spread function calculation are executed in parallel at the GPU end;Finally, lock-free output of image data and multichannel frame synchronization are realized through double-buffer read-write separation mechanism.The application can effectively solve the problems of multichannel frame number misalignment caused by thread scheduling jitter, IO blocking and CPU computation overload under traditional CPU architecture, significantly reduce the whole link delay, and realize the stable operation of multichannel infrared digital prototype at a high frame rate of 100Hz or above.

Description

Technical Field

[0001] This invention relates to the field of infrared imaging simulation and digital prototyping technology, and in particular to a high frame rate scheduling and synchronization method and system for a multi-channel infrared digital prototype. Background Technology

[0002] With the development of space remote sensing and infrared detection technologies, infrared payloads are widely used in tasks such as Earth observation, deep space exploration, and target identification. To reduce the cost of physical testing and improve the efficiency of system development, infrared digital prototype technology has gradually become an important supporting means for payload development, verification, and performance evaluation.

[0003] For example, Chinese patent document CN120219546A discloses a space-based infrared imaging simulation platform based on CUDA, which enables the rapid generation of imaging simulation data of joint observation targets of space platforms in multi-observation orbit scenarios, and uses modular data and development to improve the versatility of the platform.

[0004] Chinese patent document CN114898040A discloses a real-time infrared imaging simulation method and system based on hardware pipeline acceleration. By using pre-calculated infrared data as input and accelerating it with real-time ray tracing technology in the rendering pipeline, infrared images of a scene can be generated in real time.

[0005] In existing technologies, traditional infrared digital prototypes mostly employ CPU serial computing technology, but they face the following problems in high frame rate scenarios: First, operating system scheduling jitter. The non-real-time thread scheduling mechanism of the general operating system Windows can easily cause core computing threads to be suspended under high load, resulting in uncontrollable fluctuations in processing latency. Second, I / O transmission bottlenecks. Conventional methods use pageable memory allocated by malloc. When transferring data between the host and the device, the CPU needs to participate in multiple data copies and handle page faults, leading to severe I / O blocking and CPU resource consumption. Third, ineffective computational redundancy. Traditional radiation models usually perform convolution calculations on the entire focal plane, while targets in infrared scenes often occupy only a very small area, resulting in a large amount of computing power being wasted in the background zero-value region. Fourth, multi-channel synchronization failure. When processing multiple channels in parallel, if each channel maintains its own frame count, it is very easy for thread competition to cause frame number misalignment or screen tearing, which seriously affects the timing reliability of the simulation data.

[0006] Therefore, there is an urgent need for an optimization method that can systematically solve the aforementioned bottlenecks in computing, transmission, and synchronization. Summary of the Invention

[0007] To address the shortcomings of existing technologies in terms of computational efficiency, data transmission, and multi-channel synchronization, this invention provides a high frame rate scheduling and synchronization method and system for a multi-channel infrared digital prototype. Through heterogeneous computing, memory optimization, and read-write separation architecture, stable, low-latency high frame rate real-time simulation is achieved through hardware and software co-optimization.

[0008] A high frame rate scheduling and synchronization method for a multi-channel infrared digital prototype includes the following steps:

[0009] Data preprocessing and scheduling steps: The front-end preprocessing thread reads the motion trajectory, target information and environmental background information of the infrared payload mounting platform, generates a simulation request and pushes it into the thread-safe data preparation queue;

[0010] Heterogeneous data transmission steps: The backend computing thread obtains simulation requests from the data preparation queue and uses paged memory to copy the simulation requests to the GPU memory in a centralized manner via direct memory access (DMA);

[0011] Parallel core computing steps: Geometric imaging calculation and radiation model calculation are performed in parallel on the GPU to generate infrared image data; The radiation model calculation adopts an on-demand sparse computing strategy, performing convolution calculation only on the pixels of the target point projected onto the focal plane of the infrared detector and within its preset neighborhood.

[0012] Double-buffered synchronous output steps: The infrared image data generated by the GPU is sent back to the image double buffer pool on the CPU. Using the read-write pointer separation mechanism, while the front-end preprocessing thread reads the current frame, the back-end calculation thread writes the next frame to achieve lock-free synchronous output.

[0013] Multi-channel frame synchronization steps: For multi-channel infrared image data, before data transmission, check the consistency of the current infrared image data frame ID of each channel, and handle abnormal frames based on the queue length control strategy.

[0014] This invention establishes a full-link collaborative system through the above steps, encompassing data preprocessing and scheduling, heterogeneous data transmission, parallel core computing, double-buffered synchronous output, and multi-channel frame synchronization. Through this multi-level collaborative mechanism, a stable real-time operation of the multi-channel infrared digital prototype is achieved under high frame rates of 100Hz and above.

[0015] Furthermore, the data preprocessing and scheduling steps adopt a producer-consumer model, separating data preprocessing from core computation and eliminating serial waiting. The front-end preprocessing thread acts as the producer, preprocessing data and placing it into a queue; the back-end computation thread acts as the consumer, retrieving data from the queue. This decoupled design maximizes the utilization of CPU resources and improves throughput.

[0016] In the heterogeneous data transmission step, the page-locked memory is requested through a preset memory allocation interface and configured to support the DMA engine to directly access physical memory without CPU intervention, thus opening up a high-speed data channel between the host and the device, improving transmission efficiency by 30%-50%.

[0017] The default memory allocation interface adopts the cudaMallocHost interface under the CUDA architecture, which is compatible with the paged memory allocation interface of the OpenCL / ROCm standard; the heterogeneous data transfer steps avoid multiple data copies and page faults caused by the operating system's paging memory mechanism.

[0018] In the parallel core computing steps, the on-demand sparse computing strategy specifically includes:

[0019] Calculate the center of the target's projection on the focal plane of the infrared detector based on the target's spatial coordinates;

[0020] Using the projection center as a reference, the diffusion radius is determined according to the preset point diffusion function. Define the region of interest (ROI); the size of the truncated local window is... ;

[0021] For coordinates within the window Calculate the discretized PSF weight matrix The formula is:

[0022] ;

[0023] in, This represents the normalization coefficient, ensuring that the total energy of the point light source is conserved after integration over the entire plane, with a total energy of 1. ; This represents the standard deviation of the Gaussian distribution and the radius coefficient of the speckle.

[0024] Only GPU thread blocks covering the region of interest are activated to perform radiative energy integration calculations; radiative calculations are not performed on regions outside the region of interest. The input is the ideal target energy map. Discrete convolution with the PSF kernel generates the final infrared image with optical blurring effect. :

[0025] ;

[0026] in, This indicates the coordinates of the pixel whose radiation energy needs to be calculated.

[0027] In the double-buffered synchronous output step, the image double-buffer pool includes two independent physical buffers; the read / write pointer separation mechanism specifically includes:

[0028] Set mutually exclusive write and read pointers; when a frame of infrared image data is written, trigger the mutual exclusion operation switching logic to mutually exclude the target buffers of the write and read pointers, so that the write and read operations are isolated in physical memory space.

[0029] In the multi-channel frame synchronization step, the queue length control strategy is as follows:

[0030] If frame numbers are found to be misaligned or the backlog of data in the data preparation queue exceeds a preset threshold, a strategy of discarding old data or skipping frames is executed until the frame numbers of each channel are aligned and the queue length is restored to a safe range.

[0031] A high frame rate scheduling and synchronization system for a multi-channel infrared digital prototype, used to implement the above-mentioned high frame rate scheduling and synchronization method, includes:

[0032] The preprocessing module, configured as the runtime data preparation thread, is responsible for reading the motion trajectory, target information, and environmental background information of the infrared payload mounting platform and encapsulating them into a structured simulation request.

[0033] The scheduling and transmission module includes a thread-safe data preparation queue and paged memory, which are used to cache simulation request data and transmit simulation request data to GPU memory through direct memory access mechanism;

[0034] The GPU computing module is equipped with parallel geometric imaging units and radiation imaging units, which are used to receive simulation request data and generate infrared images.

[0035] The synchronous output module includes an image double buffer pool and a read / write switching logic unit, configured to switch between writing images and reading sent images;

[0036] The frame synchronization control module is configured to monitor the consistency of multi-channel infrared image data frame IDs and perform exception handling.

[0037] Preferably, it also includes a performance monitoring module, which uses a high-precision timer to segment and embed data at key nodes of the computation link. When the segment time or cumulative time exceeds a preset simulation cycle threshold, an anomaly log is recorded.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] 1. Improved Real-Time Performance: By employing heterogeneous computing and pipelined scheduling mechanisms, the critical path processing time for a single frame is reduced, enabling the system to support multi-channel operation at frame rates of 100Hz and above. After optimization, the geometric imaging time is reduced to less than 0.1ms, the PSF calculation is stabilized at less than 1ms, and the core algorithm calculation time is reduced from over 20ms to less than 2ms, resulting in a significant reduction in total time and meeting the requirements for 100Hz real-time output.

[0040] 2. Improved transmission stability: The paged memory and DMA collaborative mechanism reduces page faults and CPU copying intervention, eliminates the uncertainty caused by thread scheduling jitter and IO blocking, and improves the stability of large-scale image data transmission.

[0041] 3. Reduced computational load: The sparse PSF computation strategy based on ROI reduces invalid convolution operations in non-target regions, thereby reducing the consumption of GPU computing resources.

[0042] 4. Enhanced output consistency: The double buffering and single-threaded frame ID management mechanism completely solves the problems of frame number misalignment and frame skipping, ensuring the consistency of multi-channel data. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the overall architecture and data flow of the digital prototype model in an embodiment of the present invention.

[0045] Figure 2 This is a flowchart illustrating the design of a 100Hz frame rate performance optimization scheme in an embodiment of the present invention.

[0046] Figure 3 This is a data flow separation and optimization architecture diagram based on the producer-consumer model in an embodiment of the present invention.

[0047] Figure 4 This is a schematic diagram illustrating the principle of the double-buffered read-write separation mechanism in an embodiment of the present invention.

[0048] Figure 5 This is a comparison chart of traditional CPU serial computing and the CPU-GPU heterogeneous parallel computing of this invention. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] It should be noted that, unless otherwise specified, the features in the following embodiments and implementation methods can be combined with each other.

[0051] like Figure 1 As shown, a high frame rate scheduling and synchronization method for a multi-channel infrared digital prototype includes the following steps:

[0052] Data preprocessing and scheduling steps: Using a producer-consumer model, the front-end preprocessing thread reads the platform's motion trajectory, target information, and environmental background information, generates simulation requests, and pushes them into a thread-safe data preparation queue.

[0053] Heterogeneous data transfer steps: The backend computing thread obtains a request from the data preparation queue and uses pinned memory to copy the simulation data to the GPU memory in a centralized manner via direct memory access (DMA). The pinned memory is requested through a preset memory allocation interface and configured to support the DMA engine to directly access physical memory without CPU intervention.

[0054] Parallel core computing steps: Geometric imaging calculation and radiation model calculation are performed in parallel on the GPU to generate infrared image data; the radiation model calculation adopts an on-demand sparse computing strategy, performing convolution calculation only on the pixels of the target point at the focal plane projection position and its preset neighborhood range.

[0055] Double-buffered synchronous output steps: The image data generated by the GPU is sent back to the double buffer pool on the CPU side. Using the read-write pointer separation mechanism, the front-end transmission thread reads the current frame while the back-end calculation thread writes the next frame, thus achieving lock-free synchronous output.

[0056] Multi-channel frame synchronization steps: For multi-channel infrared data, the frame ID update logic is converged to single-threaded management at the sending end, and consistency checks and abnormal frame handling are performed based on the queue length control strategy.

[0057] A high frame rate scheduling and synchronization system for a multi-channel infrared digital prototype includes:

[0058] The preprocessing module, configured as the runtime data preparation thread, is responsible for reading external simulation data and encapsulating it into structured requests;

[0059] The scheduling and transmission module includes a thread-safe data preparation queue and a paged memory pool, which are used to cache request data and transmit it to acceleration hardware via DMA mechanism;

[0060] The GPU computing module is equipped with a parallel geometric imaging unit and a radiation imaging unit, which are used to receive data and generate infrared images.

[0061] The synchronous output module includes an image dual buffer pool and a read / write switching logic unit, configured to perform ping-pong switching between writing the image and reading the sent image.

[0062] The frame synchronization control module is configured to monitor the consistency of multi-channel frame IDs and perform exception handling.

[0063] The performance monitoring module uses a high-precision timer to segment and embed data at key nodes in the computation link. When the segmented time or the cumulative time exceeds the preset simulation cycle threshold, an anomaly log is recorded.

[0064] When the multi-channel infrared digital prototype is running, the collaborative relationships between the modules are as follows:

[0065] The preprocessing module generates simulation requests, the scheduling and transmission module completes buffering and DMA transfer, the GPU computing module performs parallel imaging, the synchronization output module completes double buffer switching, the frame synchronization control module performs frame alignment, and the performance monitoring module records the total latency of the entire process.

[0066] The hardware environment of this embodiment of the invention consists of a Xeon® W-3335 processor and an NVIDIA RTX 3070Ti graphics card. The software environment comprises a C++ program compiled based on MSVC, with OpenCV 4.8.0, CUDA 11.6, Visual C++ Redistributable runtime library, and other related dependent libraries installed. Each module uses a unified scheduling clock for cycle control, forming a highly efficient and stable pipelined processing architecture.

[0067] like Figure 2 The diagram shown is a design flowchart for the 100Hz frame rate performance optimization scheme in this embodiment of the invention. To address the stringent requirements of some infrared payload platforms—namely, high dynamics, large maneuverability, and fast closed-loop operation—traditional CPU serial computing systems struggle to meet the system's stringent 10ms time window. Therefore, this embodiment designs a system-level optimization process consisting of "baseline assessment - bottleneck identification - heterogeneous optimization - closed-loop verification":

[0068] First, we move on to the baseline performance assessment and bottleneck identification phase.

[0069] After setting an optimization target of 100Hz (equivalent to a single frame period of 10ms), the system first performs a baseline evaluation of the existing conventional simulation architecture. If the 100Hz requirement is not met, the system attributes the core latency to three major physical bottlenecks:

[0070] (1) CPU computational overload: The imaging field of infrared digital prototypes usually contains complex infrared and high-speed deformable targets, which makes traditional full-plane radiation calculation extremely time-consuming;

[0071] (2) IO / Memory Blocking: Frequent copying of multi-channel high-resolution images between host memory and video memory severely congests the PCIe bus;

[0072] (3) Thread scheduling jitter: Unpredictable scheduling of non-real-time operating systems causes a phase difference between the input of flight trajectory data and the output of images.

[0073] Secondly, in response to the aforementioned bottlenecks, we proceed to the stage of developing and implementing heterogeneous parallel optimization solutions.

[0074] This is the core execution stage of the invention, employing a three-line parallel optimization strategy to solve the data link problem:

[0075] Branch 1: Software Architecture Optimization. Introducing a producer-consumer decoupling model and multi-threaded parallel design. Separating the high-dynamic six-DOF trajectory data calculation and preprocessing process of the infrared payload platform from the heavy-load image rendering core calculation process, thus absorbing and smoothing out scheduling jitter caused by the operating system.

[0076] Branch 2: Computational Acceleration Optimization. Develop a GPU CUDA kernel to fully migrate the geometric imaging and point spread function (PSF) algorithms to the GPU device, and adopt an on-demand sparse computing strategy based on the region of interest to solve the computational pressure of complex radiation within the imaging field of view of the infrared digital prototype.

[0077] Branch 3: Data Transmission Optimization. Paging memory and DMA technology are introduced to achieve zero-copy transmission, while a double-buffered read / write separation mechanism ensures that the generated infrared images can be transmitted to the subsequent signal processing unit without tearing and with low latency.

[0078] Finally, we move on to the system integration and end-to-end performance verification phase.

[0079] After integrating the three optimization branches mentioned above, the system's full-link imaging performance was verified in a semi-physical simulation experiment. A critical decision node was set at the end of the process: whether it was stable at 10ms / frame. If occasional timeouts occurred, the process returned to the "bottleneck localization" stage for iterative optimization through a feedback mechanism; if the test passed, it demonstrated a stable 100Hz real-time output, thus ensuring that the multi-channel infrared digital prototype could operate stably without time delay deviation.

[0080] The main steps are explained in more detail below.

[0081] In the data preprocessing and scheduling steps, such as Figure 3 As shown, in order to address the problems of unstable thread scheduling in non-real-time operating systems and mutual blocking between "data preparation" and "core computing" in traditional serial architectures, this invention designs a software architecture based on the producer-consumer pattern.

[0082] Front-end preprocessing thread (producer): This thread reads platform motion trajectory data, target data, and environmental information data every 10ms cycle. It does not perform time-consuming calculations; it is only responsible for data preprocessing, assembly, and validity verification. The generated structured requests are pushed into a thread-safe data preparation queue. If the baseline data is not ready (e.g., the platform motion trajectory data queue is empty), the cycle is skipped, achieving input error tolerance.

[0083] Backend computing thread (consumer): Focuses on retrieving requests from the queue and triggering the core algorithm. The computing thread retrieves requests from the queue Pop and invokes the GPU kernel. This thread is decoupled from the frontend preprocessing thread, and the queue buffer smooths out system jitter. This process does not participate in subsequent data transmission; it focuses solely on image generation.

[0084] Queue decoupling: The two interact through thread-safe queues, enabling "data preparation" and "core computing" to proceed in parallel, reducing the concentration of single-threaded load.

[0085] In the heterogeneous data transmission step, this invention optimizes the memory management strategy to address the PCIe transmission bottleneck.

[0086] Traditional methods use paged memory allocated by malloc, requiring multiple CPU copies during data transfer. This embodiment calls the CUDA API cudaMallocHost to request a locked paged memory pool on the host side. This memory region is locked in physical RAM, allowing the GPU's DMA engine to directly read and write. Tests show that with this strategy, when data transfer begins, the GPU's DMA engine directly reads this physical memory address via the PCIe bus, eliminating the need for CPU intervention. This significantly reduces CPU utilization, stabilizes transfer latency from milliseconds to microseconds, and eliminates the maximum latency peak caused by page faults, greatly improving I / O stability.

[0087] In the parallel core computing steps, to address the computational bottleneck, this invention migrates geometric imaging and PSF radiation calculation to the GPU (e.g., Figure 5 (As shown on the right).

[0088] Geometric imaging, utilizing CUDA multithreading for parallel processing of geometric matrix transformations, reduced the processing time from 2.92ms to less than 0.1ms.

[0089] Traditional methods for sparse PSF calculation involve PSF convolution across the entire focal plane, resulting in enormous computational costs. This invention proposes an "on-demand sparse computation" strategy, performing convolution calculations only on the pixel region containing the target. Specifically: calculating the target center... Projection onto the detector array; based on the PSF energy distribution characteristics, 3 times. Principles, defining the radius ; only for the scope The pixels within the kernel trigger the GPU kernel to perform convolution integration.

[0090] Tested on an NVIDIA RTX 3070Ti graphics card, this strategy reduced redundant calculations by more than 70%, lowering radiation calculation time from 8.64ms to less than 1ms.

[0091] In the double-buffered synchronous output step, such as Figure 4 As shown, a double buffering mechanism is introduced to resolve read / write conflicts at high frame rates.

[0092] A dual-buffer pool is used, with Buffer A and Buffer B configured for read / write separation. While the backend computing thread's image generation module is writing the current frame (frame N) data to Buffer A, the frontend sending thread reads the previous frame (frame N-1) data from Buffer B. After writing is complete, the pointer is switched. This process eliminates lock contention, preventing screen tearing.

[0093] In the multi-channel frame synchronization step, the main focus is on addressing the issue of inconsistent frame numbers across multiple channels. This invention abandons the mechanism of updating frame IDs separately by multiple threads, and instead maintains frame IDs uniformly by a single thread at the sending end. Before each transmission, the frame IDs in the queue are checked. If discontinuities or misalignments between channels are found, a frame dropping strategy is immediately executed to ensure strict consistency in the timing of the output data.

[0094] The embodiments described above provide a detailed explanation of the technical solutions and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, additions, and equivalent substitutions made within the scope of the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high frame rate scheduling and synchronization method for a multi-channel infrared digital prototype, characterized in that, Includes the following steps: Data preprocessing and scheduling steps: The front-end preprocessing thread reads the motion trajectory, target information and environmental background information of the infrared payload mounting platform, generates a simulation request and pushes it into the thread-safe data preparation queue; Heterogeneous data transmission steps: The backend computing thread obtains simulation requests from the data preparation queue and uses paged memory to copy the simulation requests to the GPU memory in a centralized manner through direct memory access; Parallel core computing steps: Geometric imaging calculation and radiation model calculation are performed in parallel on the GPU to generate infrared image data; The radiation model calculation adopts an on-demand sparse computing strategy, performing convolution calculation only on the pixels of the target point projected onto the focal plane of the infrared detector and within its preset neighborhood. Double-buffered synchronous output steps: The infrared image data generated by the GPU is sent back to the image double buffer pool on the CPU. Using the read-write pointer separation mechanism, while the front-end preprocessing thread reads the current frame, the back-end calculation thread writes the next frame to achieve lock-free synchronous output. Multi-channel frame synchronization steps: For multi-channel infrared image data, before data transmission, check the consistency of the current infrared image data frame ID of each channel, and handle abnormal frames based on the queue length control strategy.

2. The high frame rate scheduling and synchronization method for a multi-channel infrared digital prototype according to claim 1, characterized in that, In the heterogeneous data transmission step, the page-locked memory is requested through a preset memory allocation interface and configured to support the DMA engine to directly access physical memory without CPU intervention.

3. The high frame rate scheduling and synchronization method for a multi-channel infrared digital prototype according to claim 2, characterized in that, The default memory allocation interface uses the cudaMallocHost interface under the CUDA architecture.

4. The high frame rate scheduling and synchronization method for a multi-channel infrared digital prototype according to claim 1, characterized in that, In the parallel core computing steps, the on-demand sparse computing strategy specifically includes: Calculate the center of the target's projection on the focal plane of the infrared detector based on the target's spatial coordinates; Using the projection center as a reference, the diffusion radius is determined according to the preset point diffusion function. Define the region of interest; the size of the truncated local window is... ; For coordinates within the window Calculate the discretized PSF weight matrix ; Only GPU thread blocks covering the region of interest are activated to perform radiative energy integration calculations; radiative calculations are not performed on regions outside the region of interest. The input is the ideal target energy map. Discrete convolution with the PSF kernel generates the final infrared image with optical blurring effect. : ； in, This indicates the coordinates of the pixel whose radiation energy needs to be calculated.

5. The high frame rate scheduling and synchronization method for a multi-channel infrared digital prototype according to claim 4, characterized in that, Calculate the discretized PSF weight matrix The formula is: ； in, Represents the normalization coefficient. This represents the standard deviation of the Gaussian distribution and the radius coefficient of the speckle.

6. The high frame rate scheduling and synchronization method for a multi-channel infrared digital prototype according to claim 1, characterized in that, In the double-buffered synchronous output step, the image double-buffer pool includes two independent physical buffers; the read / write pointer separation mechanism specifically includes: Set mutually exclusive write and read pointers; when a frame of infrared image data is written, trigger the mutual exclusion operation switching logic to mutually exclude the target buffers of the write and read pointers, so that the write and read operations are isolated in physical memory space.

7. The high frame rate scheduling and synchronization method for a multi-channel infrared digital prototype according to claim 1, characterized in that, In the multi-channel frame synchronization step, the queue length control strategy is as follows: If frame numbers are found to be misaligned or the backlog of data in the data preparation queue exceeds a preset threshold, a strategy of discarding old data or skipping frames is executed until the frame numbers of each channel are aligned and the queue length is restored to a safe range.

8. A high frame rate scheduling and synchronization system for a multi-channel infrared digital prototype, used to implement the high frame rate scheduling and synchronization method according to any one of claims 1 to 7, comprising: The preprocessing module, configured as the runtime data preparation thread, is responsible for reading the motion trajectory, target information, and environmental background information of the infrared payload mounting platform and encapsulating them into a structured simulation request. The scheduling and transmission module includes a thread-safe data preparation queue and paged memory, which are used to cache simulation request data and transmit simulation request data to GPU memory through direct memory access mechanism; The GPU computing module is equipped with parallel geometric imaging units and radiation imaging units, which are used to receive simulation request data and generate infrared images. The synchronous output module includes an image double buffer pool and a read / write switching logic unit, configured to switch between writing images and reading sent images; The frame synchronization control module is configured to monitor the consistency of multi-channel infrared image data frame IDs and perform exception handling.

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