Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device, the display panel comprises a plurality of data lines, a plurality of scanning lines and a plurality of pixel units, and the pixel units are used for receiving scanning signals from the scanning lines, receiving data signals from the data lines under the control of the scanning signals and executing image display according to the data signals. Each pixel unit comprises a driving module, an adjusting module, a light-emitting module, an initialization module and a preset node, the driving module is electrically connected to the adjusting module, the light-emitting module, the initialization module and the preset node, the preset node is further electrically connected to the adjusting module and the initialization module, and the initialization module is used for initializing the preset node; the adjusting module is used for receiving the power supply voltage and charging the preset node to the preset potential so as to adjust the threshold voltage of a driving switch tube in the driving module to a preset value, so that the problem of different luminance caused by different threshold voltages between adjacent pixels is solved; and the image display effect is effectively improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to display panels and display devices. Background Technology

[0002] Organic light-emitting diode (OLED) displays possess numerous advantages, including self-illumination, low driving current, high luminous efficiency, short response time, high clarity and contrast, near 180° viewing angle, wide operating temperature range, and the ability to achieve flexible displays and large-area full-color displays. They are considered by the industry to be the most promising display device. However, because OLED light-emitting materials are driven by current, as panel sizes increase, the current driving the OLED light-emitting material needs to be as small as possible to reduce heat generation in large OLED panels. This can easily lead to threshold voltage variations in the transistors controlling the driving current. Consequently, for the same data voltage control, different driving currents flow through the transistors, resulting in varying OLED luminous intensity and ultimately, poor display performance.

[0003] Therefore, how to adjust and compensate for the threshold voltage variation of the driving transistor to improve the display effect is an urgent problem to be solved. Summary of the Invention

[0004] In view of the shortcomings of the above-mentioned technical problems, this application provides a display panel and display device that can effectively adjust the threshold voltage of the driving transistor.

[0005] This application discloses a display panel including multiple data lines, multiple scan lines, and multiple pixel units arranged in an array. Each pixel unit receives scan signals from the scan lines and, under the control of the scan signals, receives data signals from the data lines, and performs image display based on the data signals. Each pixel unit includes a driving module, an adjustment module, a light-emitting module, an initialization module, and a preset node. The driving module is electrically connected to the adjustment module, the light-emitting module, the initialization module, and the preset node. The preset node is also electrically connected to the adjustment module and the initialization module. The initialization module initializes the preset node to control it at an initial potential. The adjustment module receives power supply voltage to charge the preset node to a preset potential, thereby adjusting the threshold voltage of the driving switch in the driving module to a preset value. The driving module drives the light-emitting module to emit light based on the data signals.

[0006] Optionally, the pixel unit further includes a first node, a second node, and a third node, wherein the third node is the preset node. The driving module includes a driving switch transistor, wherein the first control terminal of the driving switch transistor is electrically connected to the first node, the second control terminal of the driving switch transistor is electrically connected to the third node, the first conductive terminal of the driving switch transistor is electrically connected to a power supply voltage terminal, and the second conductive terminal of the driving switch transistor is electrically connected to the second node. When the third node is at the initial potential, the driving switch transistor is turned on, and the power supply voltage terminal charges the third node to the preset potential through the driving switch transistor and the adjustment module, thereby controlling the driving switch transistor to turn off and adjusting the threshold voltage of the driving switch transistor to a preset value.

[0007] Optionally, the pixel unit further includes a first signal receiving module and a second signal receiving module. The first signal receiving module is electrically connected to the first node and the data line, and the second signal receiving module is electrically connected to the reference voltage terminal and the second node. The first signal receiving module is used to receive an adjustment signal or the data signal from the data line and transmit it to the first node. The adjustment signal is used to adjust the threshold voltage of the driving switch in conjunction with the adjustment module, and the data signal is used to control the driving module to drive the light-emitting module to emit light. The second signal receiving module is used to receive a reference signal from the reference voltage terminal and to control the second node to the initial potential.

[0008] Optionally, the pixel unit further includes a first storage module and a second storage module. The first storage module is electrically connected to the first node and the power supply voltage terminal, and the second storage module is electrically connected to the third node and the power supply voltage terminal. The first storage module is used to store and maintain the voltage of the first node, and the second storage module is used to store and maintain the voltage of the third node.

[0009] Optionally, the pixel unit further includes an emissive control module and a fourth node. The emissive control module is electrically connected to the second node and the fourth node and is electrically connected to the emissive module through the fourth node. The emissive control module is used to control the second node to be electrically connected to the fourth node.

[0010] Optionally, the adjustment module includes a first switching transistor, and the initialization module includes a second switching transistor. The control terminal of the first switching transistor is electrically connected to the first adjustment terminal, the first conductive terminal of the first switching transistor is electrically connected to the second node, and the second conductive terminal of the first switching transistor is electrically connected to the third node. The first switching transistor is used to conduct under the control of the first adjustment terminal to control the second node to be electrically connected to the third node. The control terminal of the second switching transistor is electrically connected to the second adjustment terminal, the first conductive terminal of the second switching transistor is electrically connected to the reference voltage terminal, and the second conductive terminal of the second switching transistor is electrically connected to the third node. The second switching transistor is used to conduct under the control of the second adjustment terminal to receive a reference signal from the reference voltage terminal and transmit it to the third node, thereby controlling the third node to be at the initial potential.

[0011] Optionally, the first signal receiving module includes a third switch, and the second signal receiving module includes a fourth switch. The control terminal of the third switch is electrically connected to the scan line, the first conductive terminal of the third switch is electrically connected to the data line, the second conductive terminal of the third switch is electrically connected to the first node, the control terminal of the fourth switch is electrically connected to the second adjustment terminal, the first conductive terminal of the fourth switch is electrically connected to the reference voltage terminal, and the second conductive terminal of the fourth switch is electrically connected to the second node. The third switch is turned on under the control of the scan signal to receive the data signal or the adjustment signal from the data line and transmit it to the first node. The fourth switch is turned on under the control of the second adjustment terminal to receive the reference signal from the reference voltage terminal and transmit it to the second node, thereby controlling the second node to be at the initial potential.

[0012] Optionally, the first storage module includes a first capacitor, the second storage module includes a second capacitor, and the light-emitting control module includes a fifth switching transistor. The first capacitor is electrically connected between the first node and the power supply voltage terminal, and the second capacitor is electrically connected between the third node and the power supply voltage terminal. The first capacitor is used to maintain the voltage difference between the first node and the power supply voltage terminal, and the second capacitor is used to maintain the voltage difference between the third node and the power supply voltage terminal. The control terminal of the fifth switching transistor is electrically connected to the light-emitting control terminal, the first conductive terminal of the fifth switching transistor is electrically connected to the second node, and the second conductive terminal of the fifth switching transistor is electrically connected to the fourth node. The fifth switching transistor is used to conduct under the control of the light-emitting control terminal to control the second node to be electrically connected to the fourth node.

[0013] Optionally, in the first time period, which is the initialization phase, the second, third, fourth, and fifth switches are turned on, the first switch is turned off, the data line outputs an adjustment signal to the first node through the third switch, and the reference voltage terminal transmits a reference signal to the second and third nodes through the fourth and second switches and to the fourth node through the fifth switch, for initializing the second, third, and fourth nodes; in the second time period, which is the compensation phase, the second, fourth, and fifth switches are turned off, the drive switch and the first switch are turned on, and the power supply voltage terminal outputs an adjustment signal to the first node through the drive switch and the first switch. The third node is charged by the switch. When the third node rises to a preset potential, the driving switch is turned off to adjust the threshold voltage of the driving switch to the preset value. The second capacitor maintains the voltage of the third node. In the third time period, which is the data writing stage, the third switch is turned on, and the first, second, fourth, and fifth switches are turned off. The data signal is transmitted to the first node through the third switch, and the first capacitor maintains the voltage of the first node. In the fourth time period, the first, second, third, and fourth switches are turned off, and the driving switch and the fifth switch are turned on. The power supply voltage terminal drives the light-emitting module to emit light through the driving switch and the fifth switch.

[0014] Optionally, the first and second time periods are performed during the non-image display phase, while the third and fourth time periods are performed during the image display phase, wherein the non-display phase is the power-on non-display period.

[0015] Optionally, the first time period and the second time period are performed during the non-image display phase, and the third time period and the fourth time period are performed during the image display phase, wherein the non-image display phase is a vertical blanking phase; the vertical blanking phase is located between the image display phases of two adjacent frames; the display panel executes the first time period and the second time period in the vertical blanking phase of each frame; or, the display panel executes the first time period and the second time period once in the vertical blanking phase of every a frames, where a is an integer greater than 1.

[0016] Optionally, during each frame image display phase, the pixel unit sequentially executes the first time period, the second time period, the third time period, and the fourth time period.

[0017] This application also provides a display device, including a power module and a display panel as described above, wherein the power module is used to provide driving power to the display panel to drive the display panel to perform image display.

[0018] This application also provides a display device, including a power module and the aforementioned display panel. The power module is used to provide driving power to the display panel to drive the display panel to perform image display.

[0019] Compared to the problems of existing technologies, this application adjusts the threshold voltage in the driving module to a preset range by setting the adjustment module, thereby eliminating the difference in luminous intensity between adjacent pixel units caused by the different threshold voltages of the driving module, thus avoiding the brightness difference between adjacent pixel units and effectively improving the display effect. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of this application;

[0022] Figure 2 for Figure 1 A schematic diagram of the floor plan layout of the central display panel;

[0023] Figure 3 for Figure 2 A schematic diagram of the equivalent circuit of a mid-pixel unit;

[0024] Figure 4 for Figure 3 Timing diagram of the signal output;

[0025] Figure 5 for Figure 3 A schematic diagram showing the conduction curve changes of the first switching transistor in the circuit.

[0026] Figure 6 This is the signal output timing diagram for the first compensation mode;

[0027] Figure 7 This is the signal output timing diagram for the second compensation mode.

[0028] Explanation of reference numerals in the attached figures:

[0029] Display device-100, display panel-10, power supply module-20, m data lines-S1~Sm, n scan lines-G1~Gn, first direction-F1, second direction-F2, timing control circuit-11, data driving circuit-12, scan driving circuit-13, pixel unit-15, driving module-151, adjustment module-152, light emission module-153, initialization module-154, first signal receiving module-155, second signal receiving module-156, first storage module-157, second storage module-158, light emission control module-159, first node-N1, the... Node 2 - N2, Node 3 - N3, Node 4 - N4, Driver Switch - DT, First Switch - T1, Second Switch - T2, Third Switch - T3, Fourth Switch - T4, Fifth Switch - T5, First Capacitor - C1, Second Capacitor - C2, Light Emitting Element - E, Scan Line - G, Data Line - S, Light Emitting Control Terminal - EM, First Adjustment Terminal - K1, Second Adjustment Terminal - K2, Reference Voltage Terminal - ER, Drive Voltage Terminal - VDD, Low Voltage Terminal - VSS, First Time Period - t1, Second Time Period - t2, Third Time Period - t3, Fourth Time Period - t4, Data Signal - Data, V TG_S -V voltage difference between the first control terminal and the first conductive terminal of the drive switch transistor MG_S -Voltage difference between the second control terminal and the first conductive terminal of the drive switch transistor, I DS - The current driving the switching transistor. Detailed Implementation

[0030] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0031] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0032] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order.

[0033] Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding functions, operations, elements, etc., disclosed, but do not limit the inclusion of one or more other functions, operations, elements, etc. Additionally, the terms "comprising" or "include" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. Furthermore, when describing embodiments of this application, "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0035] Please see Figure 1 , Figure 1 This is a schematic diagram of a display device 100 according to the first embodiment of this application. The display device 100 includes a display panel 10 and a power module 20, which is disposed on the back of the display panel 10, i.e., the non-display surface of the display panel 10. The power module 20 is used to provide driving current for the display panel 10 to display images.

[0036] Please see Figure 2 , Figure 2 for Figure 1 A schematic diagram of the floor plan layout of the central display panel.

[0037] like Figure 2As shown, the display panel 10 includes a plurality of matrix-arranged pixel units 15 disposed in the display area 10a of the array substrate 10c, m data lines S1 to Sm and n scan lines G1 to Gn, where m and n are natural numbers greater than 1, and a timing control circuit 11, a data driving circuit 12 and a scan driving circuit 13 disposed in the non-display area of ​​the array substrate 10c. The n scan lines G1 to Gn extend along a first direction F1 and are mutually insulated and arranged parallel to each other along a second direction F2. The m data lines S1 to Sm extend along the second direction F2 and are mutually insulated and arranged parallel to each other along the first direction F1. The first direction F1 and the second direction F2 are perpendicular to each other.

[0038] The timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13, and is used to control the working timing of the data driving circuit 12 and the scan driving circuit 13. That is, the timing control circuit 11 is used to output corresponding timing control signals to the data driving circuit 12 and the scan driving circuit 13 respectively, so as to control the data driving circuit 12 to output data signals and control the scan driving circuit 13 to output scan signals. The pixel unit 15 receives the data signal for image display according to the scan signal and performs image display.

[0039] The data driving circuit 12 is electrically connected to the m data lines S1 to Sm, and is used to transmit the data signal (Data) to be displayed to the plurality of pixel units 15 in the form of data voltage through the m data lines S1 to Sm.

[0040] The scan driving circuit 13 is electrically connected to the n scan lines G1 to Gn, and outputs scan signals through the n scan lines G1 to Gn to control when the pixel unit 15 receives data signals. In some embodiments, the scan driving circuit 13 can output scan signals from the n scan lines G1 to Gn in sequence according to the scan cycle to control the pixel unit 15 to receive data signals for image display. Of course, the scan signals can also be output in other timing sequences as needed, and this application does not limit this.

[0041] Please see Figure 3 , Figure 3 for Figure 2 A schematic diagram of the equivalent circuit of a mid-pixel unit.

[0042] like Figure 3As shown, the pixel unit 15 includes a driving module 151, an adjustment module 152, an emissive module 153, an initialization module 154, and a preset node. The driving module 151 is electrically connected to the adjustment module 152, the emissive module 153, the initialization module 154, and the preset node. The preset node is also electrically connected to the adjustment module 152 and the initialization module 154. The initialization module 154 is used to initialize the preset node to control the preset node to be at an initial potential. The adjustment module 152 is used to receive the power supply voltage from the driving module 151 to charge the preset node to a preset potential, thereby adjusting the threshold voltage of the driving switch in the driving module 151 to a preset value. The driving module 151 is used to drive the emissive module 153 to emit light according to the data signal during the image display stage.

[0043] By controlling the power supply voltage terminal VDD, the driving module 151 and the adjustment module 152 to form a conductive path, the threshold voltage of the driving switch in the driving module 151 is adjusted to a preset range during the charging process of the preset node at the power supply voltage terminal VDD. This can effectively eliminate the difference in light intensity between adjacent pixel units due to the different threshold voltages of the driving module 151, thereby avoiding the brightness difference between adjacent pixel units 15 and effectively improving the display effect.

[0044] In this embodiment, the pixel unit 15 further includes a first node N1, a second node N2, and a third node N3, wherein the third node N3 is a preset node. The driving module 151 includes a driving switch DT, wherein the first control terminal of the driving switch DT is electrically connected to the first node N1 and then electrically connected to the first signal receiving module 155 through the first node N1; the second control terminal of the driving switch DT is electrically connected to the third node N3 and then electrically connected to the initialization module 154 through the third node N3; the first conductive terminal of the driving switch DT is electrically connected to the power supply voltage terminal VDD; and the second conductive terminal of the driving switch DT is electrically connected to the second node N2. That is, the driving switch DT is a dual-gate transistor with a first control terminal and a second control terminal. The driving switch DT is used to conduct under the control of the first control terminal and / or the second control terminal. The adjustment module 152 is electrically connected to the second node N2 and the third node N3. When the second node N2 and the third node N3 are electrically connected through the adjustment module 152, the power supply voltage terminal VDD, the drive switch DT, the second node N2, the adjustment module 152 and the third node N3 can form a conductive path. The power supply voltage terminal VDD can charge the second node N2 through the drive switch DT and the adjustment module 152. When the second node N2 is charged to the preset voltage, the drive switch DT is turned off. At this time, the threshold voltage of the drive switch DT is adjusted to the preset value.

[0045] The pixel unit 15 also includes a first signal receiving module 155 and a second signal receiving module 156. The first signal receiving module 155 is electrically connected to the data line S and the first node N1. During the initialization and compensation phases, the first signal receiving module 155 receives an adjustment signal from the data line S and transmits it to the first node N1 to cooperate with the adjustment module 152 to adjust the threshold voltage of the driving switch transistor DT. During the data writing phase, the first signal receiving module 155 receives a data signal from the data line S and transmits it to the first node N1. The driving module 151 is used to control the light-emitting module 153 to emit light according to the data signal.

[0046] The second signal receiving module 156 is electrically connected to the reference voltage terminal ER and the second node N2, and is used to receive a reference signal from the reference voltage terminal ER and transmit it to the second node N2. The reference signal is used to initialize the second node N2 to adjust the second node N2 to its initial potential.

[0047] The pixel unit 15 also includes a first storage module 157 and a second storage module 158. The first storage module 157 is electrically connected between the first node N1 and the power supply voltage terminal VDD, and the second storage module 158 is electrically connected between the third node N3 and the power supply voltage terminal VDD. The first storage module 157 is used to store and maintain the voltage of the first node N1, and the second storage module 158 is used to store and maintain the voltage of the third node N3.

[0048] The pixel unit 15 also includes a light emission control module 159, which is electrically connected to the second node N2 and the fourth node N4, and is electrically connected to the light emission module 153 through the fourth node N4. During the initialization phase, the light emission control module 159 controls the transmission of the reference signal of the second node N2 to the fourth node. During the light emission phase, the light emission control module 159 receives the power supply voltage from the self-driving switch DT and transmits it to the light emission module 153 to drive the light emission module 153 to emit light.

[0049] Specifically, the adjustment module 152 includes a first switch transistor T1. The control terminal of the first switch transistor T1 is electrically connected to the first adjustment terminal K1. The first conductive terminal of the first switch transistor T1 is electrically connected to the second node N2. The second conductive terminal of the first switch transistor T1 is electrically connected to the third node N3, and through the third node N3, it is electrically connected to the second control terminal of the drive switch transistor DT. The first switch transistor T1 is used to turn on under the control of the first adjustment terminal K1 to control the second node N2 to be electrically connected to the third node N3. That is, during the compensation phase, it receives the power supply voltage from the second node N2 and transmits it to the third node N3 to charge the third node N3 to a preset potential so as to control the drive switch transistor DT to turn off.

[0050] The light-emitting module 153 includes a light-emitting element E, which can be an organic light-emitting diode. The anode of the light-emitting element E is electrically connected to the second node N2, and the cathode of the light-emitting element E is electrically connected to the low-voltage terminal VSS. The light-emitting module 153 emits light according to the driving current transmitted by the driving switch DT to display images.

[0051] The initialization module 154 includes a second switch T2. The control terminal of the second switch T2 is electrically connected to the second adjustment terminal K2. The first conductive terminal of the second switch T2 is electrically connected to the reference voltage terminal ER. The second conductive terminal of the second switch T2 is electrically connected to the third node N3. The second switch T2 is turned on under the control of the second adjustment terminal K2 to receive a reference signal from the reference voltage terminal ER and transmit it to the third node N3 to initialize the third node N3 and control the third node N3 to be at the initial potential.

[0052] The first signal receiving module 155 includes a third switch transistor T3, and the second signal receiving module 156 includes a fourth switch transistor T4. The control terminal of the third switch transistor T3 is electrically connected to the scan line G, the first conductive terminal of the third switch transistor T3 is electrically connected to the data line S, and the second conductive terminal of the third switch transistor T3 is electrically connected to the first node N1. The third switch transistor T3 is used to be turned on under the control of the scan signal to receive adjustment signals or data signals from the data line and transmit them to the first node N1.

[0053] The control terminal of the fourth switch T4 is electrically connected to the second adjustment terminal K2, the first conductive terminal of the fourth switch T4 is electrically connected to the reference voltage terminal ER, and the second conductive terminal of the fourth switch T4 is electrically connected to the second node N2. The fourth switch T4 is used to conduct under the control of the second adjustment terminal K2 to receive the reference signal from the reference voltage terminal and transmit it to the second node N2.

[0054] The first storage module 157 includes a first capacitor C1, and the second storage module 158 includes a second capacitor C2. The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the power supply voltage terminal VDD. That is, the first capacitor C1 is electrically connected between the first control terminal and the first conductive terminal of the driving switch DT. The first capacitor C1 is used to store the charge of the first node N1 to maintain the voltage of the first node N1.

[0055] The first terminal of the second capacitor C2 is electrically connected to the third node N3, and the second terminal of the second capacitor C2 is electrically connected to the power supply voltage terminal VDD. That is, the second capacitor C2 is electrically connected between the second control terminal and the first conductive terminal of the driving switch DT. The second capacitor C2 is used to store the charge of the third node N3 to maintain the voltage of the third node N3.

[0056] The light-emitting control module 159 includes a fifth switch T5. The control terminal of the fifth switch T5 is electrically connected to the light-emitting control terminal EM. The first conductive terminal of the fifth switch T5 is electrically connected to the second node N2. The second conductive terminal of the fifth switch T5 is electrically connected to the fourth node N4. The fifth switch T5 is turned on under the control of the light-emitting control terminal EM to receive driving current from the second node N2 and transmit it to the source of the light-emitting element E to drive the light-emitting element E to emit light.

[0057] Please see Figure 4 , Figure 4 for Figure 3 Timing diagram of the signal output.

[0058] like Figure 4 As shown,

[0059] During the first time period t1, which is the initialization phase, the second switch T2, the third switch T3, the fourth switch T4, and the fifth switch T5 are turned on, while the first switch T1 is turned off. Data line S transmits an adjustment signal to the first node N1 via the third switch T3. The first capacitor C1 maintains the potential of the first node N1. The reference voltage terminal ER transmits a reference signal to the third node N3 and the second node N2 via the second switch T2 and the fourth switch T4, respectively, and to the fourth node N4 via the fifth switch T5. This is used to initialize the second node N2, the third node N3, and the fourth node N4. The second capacitor C2 is used to maintain the voltage of the third node N3, and V... ER <VSS+Vel, where Vel is the turn-on voltage of the light-emitting element E, meaning the reference signal transmitted to the second node N2 and the third node N3 is insufficient to drive the light-emitting element E to emit light. By transmitting the power supply voltage to the first node N1, the voltage difference across the first capacitor C1 is made zero, which also means the voltage difference between the first control terminal and the first conductive terminal of the control switch DT is zero.

[0060] During the second time period t2, which is the compensation phase, the second switch T2, the fourth switch T4, and the fifth switch T5 are turned off, while the first switch T1 and the third switch T3 are turned on. The driving switch DT is turned on under the control of the first node N1 and the third node N3. The power supply voltage terminal VDD, the driving switch DT, the first switch T1, and the third node N3 form a charging path to charge the third node N3. When the third node N3 is charged to the preset potential, the driving switch DT is turned off. At this time, the threshold voltage of the driving switch DT is adjusted to the preset value.

[0061] like Figure 5 As shown, Figure 5 for Figure 3A schematic diagram of the conduction curve of the driving switch DT. Here, TG represents the first control terminal of the driving switch DT, MG represents the second control terminal of the driving switch DT, and V... TG_S To drive the voltage difference between the first control terminal and the first conductive terminal of the switching transistor DT, i.e., the voltage difference between the first gate and the source, V MG_S This is the voltage difference between the second control terminal and the first conductive terminal of the driving switch DT, i.e., the voltage difference between the second gate and the source. DS This represents the magnitude of the current flowing through the drive switch DT.

[0062] The following will be based on V MG_S The charging process is explained in detail using a curve of -2.5V. At the beginning of the second time period t2, the voltage is V... MG_S = -2.5V (V N3 -VDD=-2.5V), V TG_S =0V(V N1 Taking -VDD=0V as an example, at this time I DS >0, the driving switch DT is in the conducting state. As the second time period t2 progresses, the power supply voltage VDD charges the third node N3 through the driving switch DT and the first switch T1, causing the voltage of the third node N3 to gradually increase. Since the voltage of the power supply voltage VDD is greater than the voltage of the third node N3, the voltage difference (V) between the third node N3 and the power supply voltage VDD at this time... MG-_S The voltage gradually decreases, and after the voltage at the third node N3 exceeds the voltage at the power supply terminal VDD, the voltage difference (V) between the third node N3 and the power supply terminal VDD gradually decreases. MG_S ) gradually increases, that is, V MG-_S The change in V is that it first decreases and then increases. In other words, the entire charging process can be referenced by the arrow symbol on the vertical axis. TG_S V remains unchanged MG_S During the process of first decreasing and then increasing, I DS Gradually decrease, until the voltage at the third node N3 rises to the preset voltage V. MG At that time, I DS This can be ignored, and at this point, the driving switch DT can be considered to be off. The critical voltage for the driving switch DT to turn on and off is the threshold voltage Vth, that is, when the voltage at the third node N3 or the second control terminal of the driving switch DT rises to the preset voltage Vth... MG At that time, the voltage difference (V) between the first control terminal and the source of the driving switch DT TG_S The threshold voltage Vth that drives the switching transistor DT is equal to the threshold voltage Vth. In this embodiment, Vth = V TG_S =0. In some other embodiments, the first time period t1 can make V TG_S (V N1-VDD) is set to other values ​​because V in the second time period t2 TG_S While remaining unchanged, the threshold voltage Vth can also be other values. That is, the threshold voltage Vth can be set according to specific needs, and this application does not impose any restrictions on it.

[0063] During the third time period t3, which is the data writing phase, the third switch T3 is turned on, while the first switch T1, the second switch T2, the fourth switch T4, and the fifth switch T5 are turned off. The second capacitor C2 stores charge and maintains the voltage at the third node N3. The data line S outputs the data voltage V through the third switch T3. Data The data signal is transmitted to the first node N1. The first capacitor C1 is used to maintain the voltage of the first node N1. At this time, the voltage difference between the first control terminal of the driving switch DT and the power supply voltage terminal VDD is the difference between the data voltage and the power supply voltage, that is, V TG_S =V N1 -VDD=V Data -VDD.

[0064] During the fourth time period t4, the first switch T1, the second switch T2, the third switch T3, and the fourth switch T4 are off, while the fifth switch T5 and the driver switch DT are on. A path is formed between the power supply voltage terminal VDD and the low voltage terminal VSS. The driver switch DT and the light-emitting element E divide the voltage, and the voltage at the fourth node N4 rises to V. E +VSS, to drive the light-emitting element E to emit light, V E Let V be the voltage used to drive the light-emitting element E to emit light. As the voltage increases at node 4 N4, the current through the light-emitting element is I = (k / 2)(V). TG_S -Vth) 2 =(k / 2)[(1-α)(V Data -V DD )] 2 Among them, due to V th =V TG_S =0, such that I = (k / 2)[(1-α)(V Data -V ER )] 2 Where, k = W·Cox·μ eff / L; W represents the channel width of the DTFT device, L represents the channel length of the DTFT device, Cox represents the capacitance per unit area of ​​the gate dielectric layer, μ eff This indicates the mobility of the semiconductor material in the channel region.

[0065] During the initialization phase (first time period t1) and the compensation phase (second time period t2), the adjustment signal written to the first node N1 by the data line S can be set according to specific needs. If the written voltage is Vx, then the final voltage will be V.MG Under the control of [the controller], the threshold voltage V of the driving switch is [driven]. th =Vx-V DD That is, by adjusting the voltage Vx written to the first node N1 during the initialization and compensation phases, and controlling the charging process of the third node N3 during the compensation phase, the IDVG curve of the driving switch DT can be adjusted. Figure 5 This offset allows for the setting of the threshold voltage. If Vx = V... DD If Vx is set to a value other than 0, then Vth = 0. In other embodiments, Vx can also be set to other values, thereby setting the threshold voltage Vth to other values.

[0066] In this embodiment, by setting the second switch T2 to initialize and adjust the third node N3 during the initialization phase, or in other words, resetting the third node N3, the third node N3 can be accurately reset to the initial potential, avoiding the influence of the power supply voltage VDD, and effectively ensuring the compensation adjustment effect of the threshold voltage of the driving switch during the compensation phase.

[0067] In this embodiment, the driving switch DT and the first to fifth switches T1 are P-type transistors, used to conduct under the control of a low-level signal. Of course, the first to fifth switches T5 can also be set to other types of transistors according to specific needs, and this application does not limit this. By setting the driving switch DT and the first switch T1 as P-type transistors, the charging speed of the power supply voltage VDD through the driving switch DT and the first switch T1 to the third node N3 during the compensation stage can be effectively improved, thereby improving the response speed of the driving switch DT, reducing the time occupied by the compensation stage, and optimizing the overall compensation effect. Furthermore, by electrically connecting one end of the first capacitor C1 and the second capacitor C2 to the power supply voltage VDD, since the power supply voltage VDD is a constant voltage, the coupling effect of the first capacitor C1 on the first node N1 and the coupling effect of the second capacitor C2 on the third node N3 can be effectively eliminated, thereby effectively maintaining the voltage stability of the first node N1 and the third node N3.

[0068] Please see Figure 6 , Figure 6 for Figure 3 Timing diagram of signal output in the first compensation mode of the middle pixel unit.

[0069] like Figure 6 As shown, when the display panel 10 executes the first compensation mode, during each frame of image display, n scan lines sequentially output scan signals. Simultaneously, the first adjustment terminal K1, the second adjustment terminal K2, and the light emission control terminal EM output signals according to a preset timing sequence to control the threshold voltage V of the first switching transistor T1 in the pixel unit 15. th Adjustments are made, that is, adjustments are made to the threshold voltage V.th Compensation is performed, and then data signals are received for image display. That is, pixel unit 15 sequentially executes the process from the first time period t1 to the fourth time period t4 during each frame of image display. The first compensation mode can be performed line by line, that is, the first time period t1 to the fourth time period t4 is sequentially performed on all row sub-pixels.

[0070] Please see Figure 7 , Figure 7 This is the signal output timing diagram for the second compensation mode.

[0071] like Figure 7 As shown, in the second compensation mode, during the non-image display phase, pixel unit 15 executes a first time period t1 and a second time period t2 to adjust the threshold voltage of the driving switch transistor DT. During each frame image display phase (display frame), pixel unit 15 executes a third time period t3 and a fourth time period t4 to receive data signals and display images. The non-image display phase can be the non-display period when the display panel 10 is powered on and the vertical blanking phase between any two adjacent frames.

[0072] Specifically, during the non-display period, when executing the first time period t1 and the second time period t2, the entire pixel unit 15 of the display panel can be compensated simultaneously, i.e., the entire panel is compensated. Alternatively, the first time period t1 and the second time period t2 can be executed for the entire panel during the vertical blanking phase of each frame, or the first time period t1 and the second time period t2 can be executed once for the entire panel during the vertical blanking phase of every 'a' frames, where 'a' is an integer greater than 1. In other words, the first time period t1 and the second time period t2 can be executed during the non-image display phase to complete the process of setting the threshold voltage of the driving switch DT. Thus, during the display phase, it is not necessary to execute the above two time periods, but to execute the third time period t3 and the fourth time period t4 to complete the data writing and light emission process.

[0073] The embodiments of this application also have the effect of increasing the threshold voltage compensation range. The specific principle is as follows: As can be seen from the aforementioned current formula, I=(k / 2)(V TG_S -Vth) 2 After the compensation phase and data writing phase in this embodiment of the application, V TG_S =V Data -V ER In other words, V TG_S Excluding Vth. For traditional schemes where the driving transistor is a single-gate transistor, after the compensation and data writing stages, V... TG_S =V Data+Vth-Vint, where Vint can be understood as a reference voltage similar to VER, and VTG_S (voltage difference between gate and source) includes Vth. Due to the presence of Vth, the write range of the data signal Data is compressed, so the compensation range of Vth is limited to avoid affecting the Data range. However, in this embodiment, VTG_S does not include Vth, so even if the range of Vth is set very large, it will not encroach on the write range of VData. Furthermore, since this embodiment can compensate for pixel units 15 during non-image display stages, it reduces the occupation of the image display stage, and can adjust and compensate the threshold voltage of the driving module 151 when displaying multiple frames of images at intervals, it does not require frame-by-frame compensation, avoiding the problem of compressing compensation time to ensure refresh rate, thereby increasing the compensation time and making the compensation of the threshold voltage of the driving switch more sufficient.

[0074] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A display panel, comprising multiple data lines, multiple scan lines, and multiple pixel units arranged in an array, wherein the pixel units are configured to receive scan signals from the scan lines and receive data signals from the data lines under the control of the scan signals, and perform image display based on the data signals; Its features are, The pixel unit includes a driving module, an adjustment module, a light-emitting module, an initialization module, and a preset node. The driving module is electrically connected to the adjustment module, the light-emitting module, the initialization module, and the preset node. The preset node is also electrically connected to the adjustment module and the initialization module. The initialization module is used to initialize the preset node to control the preset node to be at an initial potential. The adjustment module is used to receive power supply voltage to charge the preset node to a preset potential, thereby adjusting the threshold voltage of the driving switch in the driving module to a preset value. The driving module is used to drive the light-emitting module to emit light according to the data signal.

2. The display panel as described in claim 1, characterized in that, The pixel unit further includes a first node, a second node, and a third node, wherein the third node is the preset node. The driving module includes a driving switch transistor, wherein the first control terminal of the driving switch transistor is electrically connected to the first node, the second control terminal of the driving switch transistor is electrically connected to the third node, the first conductive terminal of the driving switch transistor is electrically connected to the power supply voltage terminal, and the second conductive terminal of the driving switch transistor is electrically connected to the second node. When the third node is at the initial potential, the driving switch transistor is turned on, and the power supply voltage terminal charges the third node to the preset potential through the driving switch transistor and the adjustment module, thereby controlling the driving switch transistor to be turned off, and adjusting the threshold voltage of the driving switch transistor to the preset value.

3. The display panel as described in claim 2, characterized in that, The pixel unit further includes a first signal receiving module and a second signal receiving module. The first signal receiving module is electrically connected to the first node and the data line, and the second signal receiving module is electrically connected to the reference voltage terminal and the second node. The first signal receiving module is used to receive an adjustment signal or the data signal from the data line and transmit it to the first node. The adjustment signal is used to adjust the threshold voltage of the driving switch in conjunction with the adjustment module. The data signal is used to control the driving module to drive the light-emitting module to emit light. The second signal receiving module is used to receive a reference signal from the reference voltage terminal and to control the second node to be at the initial potential.

4. The display panel as described in claim 3, characterized in that, The pixel unit further includes a first storage module and a second storage module. The first storage module is electrically connected to the first node and the power supply voltage terminal, and the second storage module is electrically connected to the third node and the power supply voltage terminal. The first storage module is used to store and maintain the voltage of the first node, and the second storage module is used to store and maintain the voltage of the third node.

5. The display panel as described in claim 4, characterized in that, The pixel unit further includes a light emission control module and a fourth node. The light emission control module is electrically connected to the second node and the fourth node, and is electrically connected to the light emission module through the fourth node. The light emission control module is used to control the second node to be electrically connected to the fourth node.

6. The display panel as described in claim 5, characterized in that, The adjustment module includes a first switching transistor, and the initialization module includes a second switching transistor. The control terminal of the first switching transistor is electrically connected to the first adjustment terminal, the first conductive terminal of the first switching transistor is electrically connected to the second node, and the second conductive terminal of the first switching transistor is electrically connected to the third node. The first switching transistor is used to be turned on under the control of the first adjustment terminal to control the second node to be electrically connected to the third node. The control terminal of the second switch is electrically connected to the second adjustment terminal, the first conductive terminal of the second switch is electrically connected to the reference voltage terminal, and the second conductive terminal of the second switch is electrically connected to the third node. The second switch is used to conduct under the control of the second adjustment terminal to receive a reference signal from the reference voltage terminal and transmit it to the third node, so as to control the third node to be located at the initial potential.

7. The display panel as described in claim 6, characterized in that, The first signal receiving module includes a third switching transistor, and the second signal receiving module includes a fourth switching transistor. The control terminal of the third switching transistor is electrically connected to the scan line, the first conductive terminal of the third switching transistor is electrically connected to the data line, the second conductive terminal of the third switching transistor is electrically connected to the first node, the control terminal of the fourth switching transistor is electrically connected to the second adjustment terminal, the first conductive terminal of the fourth switching transistor is electrically connected to the reference voltage terminal, and the second conductive terminal of the fourth switching transistor is electrically connected to the second node. The third switch is turned on under the control of the scan signal to receive the data signal or the adjustment signal from the data line and transmit it to the first node. The fourth switch is turned on under the control of the second adjustment terminal to receive the reference signal from the reference voltage terminal and transmit it to the second node, thereby controlling the second node to be at the initial potential.

8. The display panel as described in claim 7, characterized in that, The first storage module includes a first capacitor, the second storage module includes a second capacitor, and the light-emitting control module includes a fifth switching transistor. The first capacitor is electrically connected between the first node and the power supply voltage terminal, and the second capacitor is electrically connected between the third node and the power supply voltage terminal. The first capacitor is used to maintain the voltage difference between the first node and the power supply voltage terminal, and the second capacitor is used to maintain the voltage difference between the third node and the power supply voltage terminal. The control terminal of the fifth switch is electrically connected to the light-emitting control terminal, the first conductive terminal of the fifth switch is electrically connected to the second node, and the second conductive terminal of the fifth switch is electrically connected to the fourth node. The fifth switch is used to conduct under the control of the light-emitting control terminal to control the second node to be electrically connected to the fourth node.

9. The display panel as described in claim 8, characterized in that, In the first time period, which is the initialization phase, the second, third, fourth, and fifth switches are turned on, the first switch is turned off, the data line outputs an adjustment signal to the first node through the third switch, and the reference voltage terminal transmits a reference signal to the second and third nodes through the fourth and second switches and to the fourth node through the fifth switch, for initializing the second, third, and fourth nodes; In the second time period, which is the compensation phase, the second, fourth, and fifth switches are turned off, the driving switch and the first switch are turned on, and the power supply voltage terminal charges the third node through the driving switch and the first switch. When the third node rises to a preset potential, the driving switch is turned off to adjust the threshold voltage of the driving switch to the preset value, and the second capacitor maintains the voltage of the third node. In the third time period, which is the data writing stage, the third switch is turned on, and the first, second, fourth and fifth switches are turned off. The data signal is transmitted to the first node through the third switch, and the first capacitor maintains the voltage of the first node. In the fourth time period, which is the light-emitting stage, the first, second, third, and fourth switching transistors are turned off, while the driving switching transistor and the fifth switching transistor are turned on. The power supply voltage terminal drives the light-emitting module to emit light through the driving switching transistor and the fifth switching transistor.

10. The display panel as claimed in claim 9, characterized in that, The first and second time periods are conducted during the non-image display phase, while the third and fourth time periods are conducted during the image display phase. The non-image display phase is the power-on non-display period.

11. The display panel as claimed in claim 9, characterized in that, The first and second time periods are performed during the non-image display phase, while the third and fourth time periods are performed during the image display phase. The non-image display phase is a vertical blanking phase, which is located between the image display phases of two adjacent frames. The display panel executes the first time period and the second time period in the vertical blanking phase of each frame; or, the display panel executes the first time period and the second time period once in the vertical blanking phase of every a frames, where a is an integer greater than 1.

12. The display panel as claimed in claim 9, characterized in that, During each frame of image display, the pixel unit sequentially executes the first time period, the second time period, the third time period, and the fourth time period.

13. A display device, characterized in that, It includes a power module and a display panel as described in any one of claims 1-12, wherein the power module is used to provide driving power to the display panel to drive the display panel to perform image display.

Images