Display device and electronic device including the same

Abstract

The invention discloses a display device and an electronic device including the same. The display device includes: a display panel including sub-pixels; a scan driver connected to the sub-pixels through scan lines; a data driver connected to the sub-pixels through data lines; and a timing controller configured to control the scan driver and the data driver, in which the timing controller is configured to transmit pre-stored register values to the processor, receive image data arranged in an order corresponding to the register values from the processor, and control the data driver based on the image data.

Description

Cross-reference to applications related to display devices and electronic devices including display devices

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0151086, filed on October 30, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Some aspects of embodiments of this disclosure relate to display devices and electronic devices including display devices. Background Technology

[0003] With the development of information technology, the importance of display devices, which serve as the connection medium between users and information, has become increasingly apparent. Due to the importance of display devices, the use of various display devices, such as liquid crystal displays, organic light-emitting diode displays, and plasma displays, has increased.

[0004] The display device may include a display panel comprising pixels and a driver configured to drive the display panel. The driver may include a scan driver configured to sequentially provide scan signals to scan lines and a data driver configured to provide data signals to data lines. Each pixel may emit light with a brightness corresponding to the data signal provided through the corresponding data line in response to a scan signal provided through the corresponding scan line.

[0005] Recently, with the increase in resolution, data drivers can include demultiplexers added to the output lines to output data signals in a time-division manner to a larger number of data lines than the number of output lines. As a result, the number of switching operations required to output data signals increases, leading to increased power consumption.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore, the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0007] Some aspects of embodiments of this disclosure include display devices with relatively improved efficiency and electronic devices including display devices. For example, the display device can receive image data arranged in an order corresponding to the display panel from a processor and drive the display panel, which makes it possible to relatively reduce the power consumption of the data driver and the size of the memory.

[0008] Some embodiments of this disclosure include a display device comprising: a display panel including sub-pixels; a scan driver connected to the sub-pixels via scan lines; a data driver connected to the sub-pixels via data lines; and a timing controller configured to control the scan driver and the data driver. According to some embodiments, the timing controller may send pre-stored register values ​​to a processor, receive image data arranged in an order corresponding to the register values ​​from the processor, and control the data driver based on the image data.

[0009] According to some embodiments, the register value can indicate one of a first logic level and a second logic level.

[0010] According to some embodiments, subpixels can form pixel rows. According to some embodiments, at least one pixel row may include a first subpixel and a second subpixel. According to some embodiments, the first subpixel may be connected to a first scan line in the scan lines, the second subpixel may be connected to a second scan line in the scan lines, and the register value may include a first logic level.

[0011] According to some embodiments, subpixels can form pixel rows. According to some embodiments, pixel rows can be connected to corresponding scan lines, and register values ​​can have a second logic level.

[0012] According to some embodiments, subpixels can form a first pixel column and a second pixel column arranged alternately with the first pixel column. According to some embodiments, the first pixel column and the second pixel column can be connected to a data driver via data lines. According to some embodiments, based on a register value having a first logic level, a first image dataset corresponding to the first pixel column can be received from the processor during a first time period, and a second image dataset corresponding to the second pixel column can be received from the processor during a second time period after the first time period. According to some embodiments, the first image dataset and the second image dataset can be included in image data.

[0013] According to some embodiments, the first image dataset and the second image dataset can be received sequentially during a single frame period.

[0014] According to some embodiments, each of the sub-pixels can be configured to emit light of any one of a first color, a second color, and a third color. According to some embodiments, in each of the first pixel columns, sub-pixels emitting light of the first color and sub-pixels emitting light of the second color can be arranged alternately. According to some embodiments, in each of the second pixel columns, sub-pixels emitting light of the third color can be arranged.

[0015] According to some embodiments, the first image dataset may include first sub-pixel data corresponding to both sub-pixels emitting light of a first color and sub-pixels emitting light of a second color, and the second image dataset may include second sub-pixel data corresponding to sub-pixels emitting light of a third color.

[0016] According to some embodiments, the data driver can output a data voltage corresponding to image data to the data lines. According to some embodiments, a first pixel column can be connected to a first sub-data line. According to some embodiments, a second pixel column can be connected to a second sub-data line. According to some embodiments, the display device may further include a demultiplexer configured to selectively transmit the data voltage output through the data lines to the first and second sub-data lines.

[0017] According to some embodiments, the demultiplexer can transmit the data voltage corresponding to the first image dataset to the first sub-data line and the data voltage corresponding to the second image dataset to the second sub-data line.

[0018] According to some embodiments, subpixels can form pixel rows. According to some embodiments, pixel rows can be connected to a scan driver via scan lines. According to some embodiments, an image dataset corresponding to a pixel row can be received from a processor based on a register value at a second logic level, and the image dataset is included in image data. According to some embodiments, the image dataset can include subpixel data sequentially corresponding to the subpixels arranged in each of the pixel rows.

[0019] According to some embodiments, the image dataset can be received during a single frame period.

[0020] According to some embodiments, the timing controller may include registers configured to store register values. According to some embodiments, the register values ​​may be pre-stored based on the display panel's driving mode.

[0021] According to some embodiments of this disclosure, the electronic device may include: a display device including sub-pixels; and a processor configured to control the display device. According to some embodiments, the display device may send pre-stored register values ​​to the processor, receive image data arranged in an order corresponding to the register values ​​from the processor, and drive the sub-pixels based on the image data.

[0022] According to some embodiments, the register value may include one of a first logic level and a second logic level.

[0023] According to some embodiments, the display device may further include: a scan driver connected to the sub-pixels via scan lines. According to some embodiments, the sub-pixels may form pixel rows. According to some embodiments, at least one of the pixel rows may include a first sub-pixel and a second sub-pixel. According to some embodiments, the first sub-pixel may be connected to a first scan line in the scan lines, the second sub-pixel may be connected to a second scan line in the scan lines, and the register value may have a first logic level.

[0024] According to some embodiments, the display device may further include: a scan driver connected to the sub-pixels via scan lines. According to some embodiments, the sub-pixels may form pixel rows. According to some embodiments, pixel rows may be connected to corresponding scan lines, and register values ​​may have a second logic level.

[0025] According to some embodiments, the display device further includes: a data driver connected to the sub-pixels via data lines. According to some embodiments, the sub-pixels may form a first pixel column and a second pixel column arranged alternately with the first pixel column. According to some embodiments, the first pixel column and the second pixel column may be connected to the data driver via data lines. According to some embodiments, based on a register value having a first logic level, a first image dataset corresponding to the first pixel column may be received from the processor during a first time period, and a second image dataset corresponding to the second pixel column may be received from the processor during a second time period after the first time period, and the first and second image datasets may be included in image data.

[0026] According to some embodiments, the first image dataset and the second image dataset can be received sequentially during a single frame period. Attached Figure Description

[0027] Figure 1 is a block diagram illustrating examples of a display device and a processor included in an electronic device according to some embodiments of the present disclosure.

[0028] Figure 2 is a block diagram illustrating one aspect of the display device shown in Figure 1.

[0029] Figure 3 is a circuit diagram of any one of the sub-pixels in Figure 2.

[0030] Figure 4 is a block diagram of aspect A of Figure 2.

[0031] Figure 5 is a block diagram illustrating the data transmitting unit (or data transmitter) and data receiving unit (or data receiver) of Figure 4 according to some embodiments of the present disclosure.

[0032] Figure 6 is a flowchart illustrating aspects of the transmit and receive operations between the display device and the processor shown in Figure 1.

[0033] Figure 7 is a plan view of a display device that illustrates the transmit / receive operation of Figure 6.

[0034] Figure 8 is a timing diagram illustrating aspects of the image data received from the processor in Figure 6.

[0035] Figure 9 illustrates a timing diagram of the operation of the display device in Figure 7 based on the image data in Figure 8.

[0036] Figure 10 is a flowchart illustrating aspects of the transmit and receive operations between the display device and the processor shown in Figure 1.

[0037] Figure 11 is a plan view of a display device that illustrates the transmit / receive operation of Figure 10.

[0038] Figure 12 is a timing diagram illustrating aspects of the image data received from the processor in Figure 10.

[0039] Figure 13 illustrates a timing diagram of the operation of the display device of Figure 11 based on the image data of Figure 12.

[0040] Figure 14 is a schematic block diagram illustrating an example of an electronic device including a display device according to some embodiments of the present disclosure. Detailed Implementation

[0041] In the following description, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the following description, only the parts necessary for understanding operation according to some embodiments of the present disclosure will be described, and descriptions of other parts will be omitted so as not to obscure the essential points of the disclosure. Accordingly, the present disclosure is not limited to the embodiments set forth herein, but may be implemented in other types. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the technical spirit of the present disclosure to those skilled in the art.

[0042] It will be understood that when an element is referred to as “coupled” or “connected” to another element, it may be directly coupled or directly connected to that other element, or indirectly coupled or indirectly connected to that other element, with an intermediary element in between. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. In the specification, when an element is referred to as “comprising” or “including” a component, it does not exclude another component, but may further include other components, unless the context clearly indicates otherwise. “At least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more selected from the group consisting of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). As used herein, the term “and / or” can include any and all combinations of one or more of the associated listed items.

[0043] Although the terms “first” or “second” may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0044] Figure 1 is a block diagram illustrating an example of a display device DD and a processor 10 included in an electronic device ED according to some embodiments of the present disclosure.

[0045] Referring to Figure 1, the electronic device ED may include a processor 10 and a display device DD.

[0046] Electronic devices (EDs) can include computers (e.g., laptop computers), cellular phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital TVs, digital cameras, portable game consoles, navigation devices (e.g., vehicle navigation systems), wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, videophones, monitoring systems, autofocus systems, tracking systems, or motion sensor systems, etc.

[0047] The processor 10 can execute software to control the display device DD connected to the processor 10, and can perform various data processing or computational operations. For example, the processor 10 can output image data IDATA in response to external input (or user input or user command). The image data IDATA can be converted to match the subpixel arrangement and driving mode of the display panel, and then output. The processor 10 can be implemented as at least one of an application processor (AP), a graphics processing unit (GPU), and a central processing unit (CPU).

[0048] According to some embodiments, processor 10 can receive register value RD from display device DD. Processor 10 can send image data IDATA and control signal CS to display device DD. For example, processor 10 can generate image data IDATA arranged in an order corresponding to register value RD, and can send image data IDATA to display device DD. Furthermore, processor 10 can send control signal CS including vertical synchronization signal, horizontal synchronization signal, and clock signal, etc. The vertical synchronization signal can indicate the start of frame data (i.e., data corresponding to a frame period in which a single frame of image is displayed). The horizontal synchronization signal can indicate the start of a data line (i.e., one of a plurality of data lines included in frame data).

[0049] The display device DD can send a pre-stored register value RD to the processor 10. For example, depending on the driving mode of the display panel, the display device DD can send a pre-stored register value RD at a first logic level or a second logic level to the processor 10.

[0050] The display device DD can receive image data IDATA and corresponding control signals CS from the processor 10. The image data IDATA received from the processor 10 can be data arranged in an order corresponding to register values ​​RD. The display device DD can be controlled to display an image (e.g., a frame image) corresponding to the received image data IDATA without rearranging (or remapping) the image data IDATA. For example, the display device DD can transmit data voltages corresponding to the received image data IDATA to subpixels without rearranging the image data IDATA to match the subpixel arrangement and driving mode of the display panel. Therefore, the display device DD can be implemented without a separate controller for performing various data processing or calculation operations to rearrange the image data IDATA. Furthermore, the display device DD can be controlled to display an image without storing the image data IDATA. Accordingly, the display device DD can be implemented with a smaller memory configured to store the image data IDATA, preset commands, or processing results. As a result, the size and manufacturing cost of the display device DD can be reduced. In addition, since there is no power consumption caused by a separate controller and memory for rearranging the image data IDATA, the power consumption of the display device DD can be reduced.

[0051] Figure 2 is a block diagram of one aspect of the display device DD shown in Figure 1.

[0052] Referring to Figure 2, the display device DD may include a display panel DP, a scan driver 120 (or a gate driver), a data driver 130 (or a source driver), a timing controller 140, a transmit driver 150, and a demultiplexer 160.

[0053] The display panel DP may include sub-pixels SP. Sub-pixels SP can be connected to scan driver 120 via first scan lines SL1 to the nth scan line SLn (where n is an integer equal to or greater than 1). Sub-pixels SP can be connected to data driver 130 via first data lines DL1 to the mth data line DLm (where m is an integer equal to or greater than 1). Sub-pixels SP can be connected to transmit driver 150 via first transmit control lines EL1 to the nth transmit control line ELn.

[0054] Subpixels (SPs) can produce two or more colors of light. For example, each subpixel SP can produce light in colors such as red, green, blue, cyan, magenta, or yellow.

[0055] Two or more subpixels SP can form a single pixel PXL. For example, as shown in Figure 2, pixel PXL can include three subpixels SP. Therefore, depending on the combination of light emitted from the subpixels SP included in pixel PXL, pixel PXL can emit light of various colors and brightness levels.

[0056] A first power voltage VDD and a second power voltage VSS can be provided to the display panel DP. The first power voltage VDD and the second power voltage VSS can be the voltages required for the operation of the sub-pixels SP. The first power voltage VDD can have a higher voltage level than the second power voltage VSS. Furthermore, an initialization power voltage VINT can be provided to the display panel DP. The first power voltage VDD, the second power voltage VSS, and the initialization power voltage VINT can be provided by an external device to the display device DD.

[0057] The timing controller 140 can control the overall operation of the display device DD. The timing controller 140 can receive image data IDATA and the corresponding control signal CS from the processor 10 (refer to FIG. 1). In response to the control signal CS, the timing controller 140 can provide a scan control signal SCS, a transmit drive control signal ECS, a data control signal DCS, and a multiplexer control signal DMCS.

[0058] The timing controller 140 can correct the image data IDATA and output the corrected image data DATA. For example, the timing controller 140 can correct the image data IDATA based on the degradation of sub-pixel SP, grayscale value, and color temperature, and output the corrected image data DATA.

[0059] Scan driver 120 can generate scan signals based on scan control signal SCS. Scan driver 120 can sequentially provide scan signals to scan lines SL1 to SLn. Scan control signal SCS may include start signal and clock signal, etc., and may be provided from timing controller 140. For example, scan driver 120 may include shift register (or stage) that uses clock signal to sequentially generate and output pulse-type scan signals corresponding to pulse-type start signals.

[0060] The scan driver 120 may be located on one side of the display panel DP. However, the embodiments are not limited to the foregoing examples. For example, the scan driver 120 may be divided into two or more drivers that are physically and / or logically separated from each other. The drivers may be located on a first side of the display panel DP and a second side of the display panel DP opposite to the first side. Therefore, depending on the embodiment, the scan driver 120 may be located around the display panel DP in various forms.

[0061] Transmit driver 150 can generate transmit control signals based on transmit drive control signals ECS. Transmit driver 150 can provide transmit control signals sequentially or simultaneously (or concurrently) to transmit control lines EL1 to ELn. Transmit drive control signals ECS may include transmit start signals and transmit clock signals, etc., and may be provided from timing controller 140. For example, transmit driver 150 may include a shift register that sequentially generates and outputs pulse-type transmit control signals corresponding to pulse-type transmit start signals using transmit clock signals.

[0062] The data driver 130 can generate a data signal based on the corrected image data DATA and the data control signal DCS provided from the timing controller 140. The data driver 130 can provide the data signal to the display panel DP (or sub-pixel SP). The data control signal DCS can be a signal used to control the operation of the data driver 130, and includes a load signal (or data enable signal) indicating that a valid data signal is output. For example, the data driver 130 can generate a gamma voltage, select a gamma voltage from the gamma voltages that corresponds to the grayscale value in the corrected image data DATA, and output a data signal (or data voltage).

[0063] Demultiplexer 160 can be connected between data lines DL1 to DLm and sub-data lines DA1 to DAm and DB1 to DBm. Demultiplexer 160 can, based on demultiplexer control signal DMCS, provide the data voltage input from data driver 130 via data lines DL1 to DLm to sub-pixels SP included in display panel DP via sub-data lines DA1 to DAm and DB1 to DBm.

[0064] Two or more of the components, including the data driver 130, the timing controller 140, and the transmit driver 150, can be mounted on a single integrated circuit. According to some embodiments, the data driver 130 and the timing controller 140 can be included in a single driver integrated circuit. In this case, the integrated circuit can be referred to as a timing controller embedded data driver (TED). According to some embodiments, the data driver 130 and the timing controller 140 can each be implemented as separate integrated circuits.

[0065] Figure 3 is a circuit diagram illustrating an aspect of any of the subpixel SPs of Figure 2. Although Figure 3 illustrates various components in the subpixel SP according to some embodiments, the embodiments of this disclosure are not limited thereto, and the subpixel SP may include additional or fewer components according to various embodiments without departing from the spirit and scope of the embodiments of this disclosure.

[0066] Figure 3 illustrates the sub-pixel SPij located in the i-th row (where i is an integer equal to or greater than 1 and less than or equal to n) and the j-th column (where j is an integer equal to or greater than 1 and less than or equal to m) of the sub-pixel SP in Figure 2.

[0067] Referring to Figure 3, the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0068] The sub-pixel circuit SPC can be connected to the i-th scan line SLi, the (i-1)-th scan line SLi-1, the i-th emission control line ELi, and the j-th data line DLj.

[0069] The sub-pixel circuit SPC may include a first transistor TR1 through a seventh transistor TR7 and a storage capacitor Cst.

[0070] The first electrode of the first transistor TR1 can be connected to the second node N2, or it can be connected to the first power node VDDN via the fifth transistor TR5. The second electrode of the first transistor TR1 can be connected to the first node N1, or it can be connected to the anode electrode AE ​​of the light-emitting element LD via the sixth transistor TR6. The gate electrode of the first transistor TR1 can be connected to the third node N3. The first transistor TR1 can control the amount of current flowing from the first power node VDDN through the light-emitting element LD to the second power node VSSN in response to the voltage of the third node N3. The first transistor TR1 can be referred to as the driving transistor.

[0071] The second transistor TR2 can be connected between the j-th data line DLj and the second node N2. The gate electrode of the second transistor TR2 can be connected to the i-th scan line SLi. When a scan signal is supplied to the i-th scan line SLi, the second transistor TR2 can be turned on to electrically connect the first electrode of the first transistor TR1 to the j-th data line DLj. The second transistor TR2 can be referred to as a switching transistor.

[0072] The third transistor TR3 can be connected between the first node N1 and the third node N3. The gate electrode of the third transistor TR3 can be connected to the i-th scan line SLi. When the scan signal is supplied to the i-th scan line SLi, the third transistor TR3 can be turned on to electrically connect the first node N1 to the third node N3.

[0073] The storage capacitor Cst can be connected between the first power node VDDN and the third node N3. The storage capacitor Cst can store a voltage corresponding to both the data signal and the threshold voltage of the first transistor TR1.

[0074] The fourth transistor TR4 can be connected between the third node N3 and the initialization power node VINTN. The gate electrode of the fourth transistor TR4 can be connected to the (i-1)th scan line SLi-1, which is the preceding scan line. When the scan signal is supplied to the (i-1)th scan line SLi-1, the fourth transistor TR4 can be turned on to supply the initialization power voltage VINT (refer to Figure 2) to the third node N3. The initialization power voltage VINT can be set to a voltage level lower than the voltage level of the data signal.

[0075] The fifth transistor TR5 can be connected between the first power node VDDN and the second node N2. The gate electrode of the fifth transistor TR5 can be connected to the i-th emitter control line ELi. The fifth transistor TR5 can be turned on when the emitter control signal is supplied to the i-th emitter control line ELi, and can be turned off under other conditions.

[0076] The sixth transistor TR6 can be connected between the first node N1 and the light-emitting element LD. The gate electrode of the sixth transistor TR6 can be connected to the i-th emitter control line ELi. When the emitter control signal is supplied to the i-th emitter control line ELi, the sixth transistor TR6 can be turned on, and under other conditions it can be turned off.

[0077] The seventh transistor TR7 can be connected between the initialization power node VINTN and the anode electrode AE ​​of the light-emitting element LD. The gate electrode of the seventh transistor TR7 can be connected to the i-th scan line SLi. When the scan signal is supplied to the i-th scan line SLi, the seventh transistor TR7 can be turned on to supply the initialization power voltage VINT to the anode electrode AE ​​of the light-emitting element LD.

[0078] Therefore, the sub-pixel circuit SPC may include first transistors TR1 through seventh transistors TR7 and a storage capacitor Cst. However, the embodiments are not limited to the above. The sub-pixel circuit SPC can be implemented in any of various types of circuits, each including multiple transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and two capacitors. Depending on the embodiment of the sub-pixel circuit SPC, the number of sub-data lines included in the j-th data line DLj and the number of sub-emission control lines included in the i-th emission control line ELi may vary.

[0079] The first transistor TR1 through the seventh transistor TR7 can be P-type transistors. Each of the first transistor TR1 through the seventh transistor TR7 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). However, embodiments according to this disclosure are not limited to the above. For example, at least one of the first transistor TR1 through the seventh transistor TR7 can be replaced with an N-type transistor.

[0080] According to some embodiments, the first transistor TR1 to the seventh transistor TR7 may include amorphous silicon semiconductor, monocrystalline silicon semiconductor, polycrystalline silicon semiconductor, or oxide semiconductor, etc.

[0081] The light-emitting element (LD) may include an anode electrode AE, a cathode electrode CE, and an emitting layer. The emitting layer may be located between the anode electrode AE ​​and the cathode electrode CE. When the data signal transmitted via the j-th data line DLj is reflected in the voltage of the second node N2, and the emission control signal of the i-th emission control line ELi is enabled to a low level, the fifth transistor TR5 and the sixth transistor TR6 can be turned on. Furthermore, the first transistor TR1 may be turned on depending on the voltage of the third node N3, allowing current to flow from the first power node VDDN to the second power node VSSN. The light-emitting element LD can emit light corresponding to the amount of current.

[0082] Figure 4 is a block diagram of aspect A of Figure 2.

[0083] Referring to Figures 1, 2, and 4, the processor 10 may include a data transmission unit (or data transmitter) 111. The timing controller 140 of the display device DD may include a data receiving unit (or data receiver) 141, a register 142, a data processing unit 143, and a memory 144.

[0084] The data transmission unit 111 can transmit image data IDATA through the channel connected between the processor 10 and the display device DD. The data transmission unit 111 can send the image data IDATA arranged by the processor 10 in a specific order to the display device DD. For example, the data transmission unit 111 can send the image data IDATA arranged as frame data based on the sub-pixel arrangement and driving mode of the display panel DP (refer to FIG. 2).

[0085] Data receiving unit 141 can be connected to a channel to receive image data IDATA provided by processor 10. Before receiving the image data IDATA, data receiving unit 141 can pre-send a register value RD to processor 10 to determine the arrangement order of the image data IDATA. Data receiving unit 141 can receive image data IDATA arranged in the order corresponding to the register value RD from processor 10.

[0086] Data transmission unit 111 and data reception unit 141 may correspond to the physical layer of the Mobile Industry Processor Interface (MIPI) protocol. However, embodiments are not limited to the foregoing examples. For example, data transmission unit 111 and data reception unit 141 may correspond to the physical layer and data link layer of the Open Systems Interconnection (OSI) 7-layer model or the network interface of Transmission Control Protocol / Internet Protocol (TCP / IP).

[0087] Register 142 can store register values ​​RD sent to processor 10. For example, when processor 10 requests register value RD to send image data IDATA, the register value RD stored in register 142 can be sent to processor 10. Register value RD can be preset to a first logic level or a second logic level corresponding to the sub-pixel arrangement and driving mode of display panel DP. For example, register value RD can be preset to "0" or "1", but the embodiment is not limited to this.

[0088] The data processing unit 143 can correct the image data IDATA received through the data receiving unit 141, thereby generating corrected image data DATA. The data processing unit 143 can output the generated corrected image data DATA to the data driver 130. The data processing unit 143 can be connected to the memory 144 and can be supplied with data stored in the memory 144. For example, the data processing unit 143 can correct the received image data IDATA based on the image data of a previous frame stored in the memory 144, thereby generating corrected image data DATA. The corrected image data DATA can be generated from the image data IDATA using various known methods.

[0089] The corrected image data DATA can be transmitted to the data driver 130 and provided to the display panel DP (or sub-pixel SP). For example, the data driver 130 can provide the data voltage VDATA corresponding to the corrected image data DATA to the data lines DL1 to DLm.

[0090] Figure 5 is a block diagram illustrating the data transmitting unit (or data transmitter) 111 and the data receiving unit (or data receiver) 141 of Figure 4 according to some embodiments.

[0091] Referring to Figures 4 and 5, the data transmission unit 111 of the processor 10 and the data receiving unit 141 of the timing controller 140 are illustrated.

[0092] The data transmission unit 111 may include a transmitter controller 501, an encoder 502, and a transmitter 503. According to some embodiments, the transmitter controller 501 may provide payload image data pIDATA (or payload data) to the encoder 502. The encoder 502 may encode the payload image data pIDATA and generate encoded image data eIDATA, and may provide the encoded image data eIDATA to the transmitter 503. The transmitter 503 may add other data before and after the encoded image data eIDATA according to a preset protocol, thereby generating image data IDATA. The transmitter 503 may transmit the image data IDATA.

[0093] The data receiving unit 141 may include a receiver 504, a decoder 505, and a receiver controller 506. According to some embodiments, the receiver 504 may generate a clock signal using image data IDATA, and may sample the image data IDATA (or encoded payload image data epIDATA) based on the generated clock signal. The receiver 504 may provide the encoded payload image data epIDATA to the decoder 505. The decoder 505 may decode the encoded payload image data epIDATA to generate payload image data pIDATA', and may provide the payload image data pIDATA' to the receiver controller 506.

[0094] The data transmitting unit 111 and the data receiving unit 141 can be connected via a first line DCL1 and a second line DCL2. The transmitter 503, the first line DCL1, the second line DCL2, and the receiver 504 can form a single channel. For example, the data transmitting unit 111 can receive the register value RD via the first line DCL1 and can transmit image data IDATA to the data receiving unit 141 via the second line DCL2.

[0095] Figure 6 is a flowchart illustrating aspects of the transmit and receive operations between the display device DD and the processor 10 of Figure 1.

[0096] Referring to Figures 1 and 6, at operation S110, the display device DD can send a register value RD1 having a first logic level to the processor 10. According to some embodiments, when the sub-pixels of the display panel DP operate in a driving mode (e.g., alternating data drive (ADD) mode) where the data lines are alternately driven every half cycle during a single frame period, the register value RD1 can have a first logic level. For example, the display device DD can send a value "1" corresponding to a pre-stored register value RD1. In ADD mode, sub-pixels in odd-numbered pixel columns can be driven during a first sub-frame period, while sub-pixels in even-numbered pixel columns are driven during a second sub-frame period following the first sub-frame period. The first and second sub-frame periods can be included within a single frame period. A detailed description of the structure and operation of the display panel DP driven in ADD mode will be provided later with reference to Figures 7 and 9.

[0097] At operation S120, processor 10 can send image data IDATA1 arranged in an order corresponding to register value RD1 to display device DD. According to some embodiments, upon receiving register value RD1 having a first logic level, processor 10 can align the input image data to correspond to the ADD mode, thereby generating image data IDATA1. Processor 10 can send image data IDATA1 arranged in an order corresponding to the ADD mode as frame data to display device DD. A detailed description of the arrangement of image data IDATA1 will be provided later with reference to FIG8.

[0098] At operation S130, the display device DD can control the data driver 130 (refer to FIG. 2) based on the image data IDATA1. According to some embodiments, the timing controller 140 (refer to FIG. 2) can provide the image data IDATA1 to the data driver 130. The data driver 130 can convert the digital data signal image data IDATA1 into an analog data signal data voltage VDATA (refer to FIG. 4) in response to the data control signal DCS, and can provide the data voltage VDATA to the data lines DL1 to DLm.

[0099] Figure 7 is a plan view of a display device DD that illustrates the transmit / receive operation of Figure 6.

[0100] Referring to Figure 7, a pentilet is illustrated. ® A display panel DP with a specific structure. According to some embodiments, the display panel DP may have a structure in which first pixels PXL1 and second pixels PXL2 are alternately arranged in the extension direction of data lines DL1 to DLm and in a direction perpendicular to the extension direction. Each of the first pixels PXL1 includes a sub-pixel configured to emit red (R) light and a sub-pixel configured to emit green (G) light, and each of the second pixels PXL2 includes a sub-pixel configured to emit blue (B) light and a sub-pixel configured to emit green (G) light.

[0101] The display panel DP may have a structure in which sub-pixels configured to emit red light and sub-pixels configured to emit blue light are alternately arranged in the extension direction of data lines DL1 to DLm, and sub-pixels configured to emit green light are continuously arranged in the extension direction of data lines DL1 to DLm.

[0102] The display panel DP may include a first pixel column COL1, a second pixel column COL2, a third pixel column COL3, a fourth pixel column COL4, ..., a 2m-1 pixel column COL2m-1, and a 2m pixel column COL2m. According to some embodiments, in the first pixel column COL1, subpixels configured to emit red light and subpixels configured to emit blue light may be alternately arranged along the extension direction of data lines DL1 to DLm. The first pixel column COL1 may include a first subpixel R1, a seventh subpixel B7, a thirteenth subpixel R13, a nineteenth subpixel B19, ..., a twenty-fifth subpixel R25, and a thirty-first subpixel B31. The subpixels of the first pixel column COL1 may be connected to the A1 sub-data line DA1.

[0103] In the second pixel column COL2, subpixels configured to emit green light can be continuously arranged along the extension direction of data lines DL1 to DLm. The second pixel column COL2 may include the second subpixel G2, the eighth subpixel G8, the fourteenth subpixel G14, the twentieth subpixel G20, ..., the twenty-sixth subpixel G26, and the thirty-second subpixel G32. The subpixels of the second pixel column COL2 can be connected to the B1 sub-data line DB1.

[0104] In the third pixel column COL3, subpixels configured to emit blue light and subpixels configured to emit red light can be alternately arranged along the extension direction of data lines DL1 to DLm. The third pixel column COL3 may include the third subpixel B3, the ninth subpixel R9, the fifteenth subpixel B15, the twenty-first subpixel R21, ..., the twenty-seventh subpixel B27, and the thirty-third subpixel R33. The subpixels of the third pixel column COL3 can be connected to the A2 sub-data line DA2.

[0105] In the fourth pixel column COL4, subpixels configured to emit green light can be arranged continuously along the extension direction of data lines DL1 to DLm. The fourth pixel column COL4 may include the fourth subpixel G4, the tenth subpixel G10, the sixteenth subpixel G16, the twenty-second subpixel G22, ..., the twenty-eighth subpixel G28, and the thirty-fourth subpixel G34. The subpixels of the fourth pixel column COL4 can be connected to the B2 sub-data line DB2.

[0106] Pixel column COL2m-1 (2m-1) may include sub-pixels B5 (5th), R11 (11th), B17 (17th), R23 (23rd), ..., B29 (29th), and R35 (35th). The sub-pixels of pixel column COL2m-1 can be connected to sub-data line DAm. Pixel column COL2m (2m) may include sub-pixels G6 (6th), G12 (12th), G18 (18th), G24 (24th), ..., G30 (30th), and G36 (36th). The sub-pixels of pixel column COL2m (2m) can be connected to sub-data line DBm (Bm).

[0107] In other words, in odd-numbered pixel columns, subpixels configured to emit red light and subpixels configured to emit blue light can be arranged alternately. In even-numbered pixel columns, subpixels configured to emit green light can be arranged consecutively.

[0108] The display panel DP may include a first pixel row RW1, a second pixel row RW2, a third pixel row RW3, a fourth pixel row RW4, ..., an (n-1)th pixel row RWn-1, and an nth pixel row RWn. According to some embodiments, in the first pixel row RW1, sub-pixels configured to emit red light and sub-pixels configured to emit blue light can be connected to a first scan line SL1. In the first pixel row RW1, sub-pixels configured to emit green light can be connected to a second scan line SL2. First sub-pixel R1, third sub-pixel B3, and fifth sub-pixel B5 can be connected to the first scan line SL1. Second sub-pixel G2, fourth sub-pixel G4, and sixth sub-pixel G6 can be connected to the second scan line SL2.

[0109] According to some embodiments, in the second pixel row RW2, subpixels configured to emit red light and subpixels configured to emit blue light can be connected to the third scan line SL3. In the second pixel row RW2, subpixels configured to emit green light can be connected to the fourth scan line SL4. The seventh subpixel B7, the ninth subpixel R9, and the eleventh subpixel R11 can be connected to the third scan line SL3. The eighth subpixel G8, the tenth subpixel G10, and the twelfth subpixel G12 can be connected to the fourth scan line SL4.

[0110] In the third pixel row RW3, the subpixel configured to emit red light and the subpixel configured to emit blue light can be connected to the fifth scan line SL5. In the third pixel row RW3, the subpixel configured to emit green light can be connected to the sixth scan line SL6. The thirteenth subpixel R13, the fifteenth subpixel B15, and the seventeenth subpixel B17 can be connected to the fifth scan line SL5. The fourteenth subpixel G14, the sixteenth subpixel G16, and the eighteenth subpixel G18 can be connected to the sixth scan line SL6.

[0111] In the fourth pixel row RW4, the subpixel configured to emit red light and the subpixel configured to emit blue light can be connected to the seventh scan line SL7. In the fourth pixel row RW4, the subpixel configured to emit green light can be connected to the eighth scan line SL8. The nineteenth subpixel B19, the twenty-first subpixel R21, and the twenty-third subpixel R23 can be connected to the seventh scan line SL7. The twentieth subpixel G20, the twenty-second subpixel G22, and the twenty-fourth subpixel G24 can be connected to the eighth scan line SL8.

[0112] The 25th sub-pixel R25, the 27th sub-pixel B27, and the 29th sub-pixel B29 can be connected to the 2k-3 scan line SL2k-3 (where k is an integer equal to or greater than 2 and less than or equal to n). The 26th sub-pixel G26, the 28th sub-pixel G28, and the 30th sub-pixel G30 can be connected to the 2(k-1) scan line SL2(k-1). The 31st sub-pixel B31, the 33rd sub-pixel R33, and the 35th sub-pixel R35 can be connected to the 2k-1 scan line SL2k-1. The 32nd sub-pixel G32, the 34th sub-pixel G34, and the 36th sub-pixel G36 can be connected to the 2k scan line SL2k.

[0113] In other words, in each pixel column, subpixels emitting red light and subpixels emitting blue light can be connected to odd-numbered scan lines, while subpixels emitting green light can be connected to even-numbered scan lines.

[0114] The demultiplexer 160 may include selection transistors M1 to M6 connected between data lines DL1 to DLm and sub-data lines DA1 to DAm and DB1 to DBm. For example, a first selection transistor M1 may be connected between the first data line DL1 and the A1 sub-data line DA1. A second selection transistor M2 may be connected between the first data line DL1 and the B1 sub-data line DB1. A third selection transistor M3 may be connected between the second data line DL2 and the A2 sub-data line DA2. A fourth selection transistor M4 may be connected between the second data line DL2 and the B2 sub-data line DB2. A fifth selection transistor M5 may be connected between the m-th data line DLm and the Am-th sub-data line DAm. A sixth selection transistor M6 may be connected between the m-th data line DLm and the Bm sub-data line DBm.

[0115] Selecting transistors M1 through M6 can be PMOS transistors. The turn-on voltage of a PMOS transistor can be a low-level voltage, and its turn-off voltage can be a high-level voltage. However, the embodiments are not limited to the foregoing examples. For instance, at least one of the selecting transistors M1 through M6 can be an NMOS transistor.

[0116] Figure 8 is a timing diagram illustrating aspects of the image data received from the processor 10 of Figure 6.

[0117] Referring to Figures 6, 7 and 8, the image data IDATA1 is shown as frame data when the processor 10 receives a register value RD1 with a first logic level.

[0118] The image data IDATA1 corresponding to a single frame period 1FP may include a first image dataset IDS1 and a second image dataset IDS2. The display device DD may sequentially receive the first image dataset IDS1 and the second image dataset IDS2 from the processor 10 during the single frame period 1FP. The display device DD may receive the first image dataset IDS1 during the first sub-frame period 1SFP of the single frame period 1FP, and may receive the second image dataset IDS2 during the second sub-frame period 2SFP of the single frame period 1FP.

[0119] According to some embodiments, during the first subframe period 1SFP, the display device DD can receive from the processor 10 a first image dataset IDS1 corresponding to the first pixel column COL1, the third pixel column COL3, ... and the 2m-1 pixel column COL2m-1. During the second subframe period 2SFP following the first subframe period 1SFP, the display device DD can receive from the processor 10 a second image dataset IDS2 corresponding to the second pixel column COL2, the fourth pixel column COL4, ... and the 2m pixel column COL2m. In other words, the display device DD can sequentially receive from the processor 10 the first image dataset IDS1 corresponding to odd-numbered pixel columns and the second image dataset IDS2 corresponding to even-numbered pixel columns.

[0120] The first image dataset IDS1 may include subpixel data corresponding to subpixels emitting red light and subpixels emitting blue light. For example, the first image dataset IDS1 may include first subpixel data DRW1_1 corresponding to the subpixels emitting red and blue light in the first pixel row RW1. The first subpixel data DRW1_1 may include subpixel data DR1, DB3, and DB5 corresponding to the first subpixel R1, the third subpixel B3, and the fifth subpixel B5, respectively. The first image dataset IDS1 may include second subpixel data DRW2_1 corresponding to the subpixels emitting red and blue light in the second pixel row RW2. The second subpixel data DRW2_1 may include subpixel data DB7, DR9, and DR11 corresponding to the seventh subpixel B7, the ninth subpixel R9, and the eleventh subpixel R11, respectively. The first image dataset IDS1 may include n_1 subpixel data DRWn_1 corresponding to the subpixels emitting red and blue light in the nth pixel row RWn. The n_1th subpixel data DRWn_1 may include subpixel data DB31, DR33, and DR35, which correspond to the thirty-first subpixel B31, the thirty-third subpixel R33, and the thirty-fifth subpixel R35, respectively.

[0121] The second image dataset IDS2 may include sub-pixel data corresponding to sub-pixels emitting green light. For example, the second image dataset IDS2 may include DRW1_2, the first-second sub-pixel data corresponding to the sub-pixel emitting green light in the first pixel row RW1. DRW1_2 may include sub-pixel data DG2, DG4, and DG6, respectively, corresponding to the second sub-pixel G2, the fourth sub-pixel G4, and the sixth sub-pixel G6. The second image dataset IDS2 may include DRW2_2, the second-second sub-pixel data corresponding to the sub-pixel emitting green light in the second pixel row RW2. DRW2_2 may include sub-pixel data DG8, DG10, and DG12, respectively, corresponding to the eighth sub-pixel G8, the tenth sub-pixel G10, and the twelfth sub-pixel G12. The second image dataset IDS2 may include DRWn_2, the n-second sub-pixel data corresponding to the sub-pixel emitting green light in the nth pixel row RWn. The n_2nd sub-pixel data DRWn_2 may include sub-pixel data DG32, DG34, and DG36, which correspond to the thirty-second sub-pixel G32, the thirty-fourth sub-pixel G34, and the thirty-sixth sub-pixel G36, respectively.

[0122] As described above, image data IDATA1 can be data in which sub-pixel data are arranged in an order corresponding to the ADD pattern.

[0123] Figure 9 illustrates a timing diagram of the operation of the display device DD in Figure 7 based on the image data in Figure 8.

[0124] Referring to Figures 7, 8, and 9, a single frame period 1FP may include a first subframe period 1SFP and a second subframe period 2SFP. The first subframe period 1SFP may be from T0 to T3, and the second subframe period 2SFP may be from T3 to T6. The first subframe period 1SFP may be a period in which data voltages for subpixels arranged in odd-numbered pixel columns and emitting red and blue light are output from data driver 130. For example, during the first subframe period 1SFP, data driver 130 may output data voltages corresponding to the first image dataset IDS1. The second subframe period 2SFP may be a period in which data voltages for subpixels arranged in even-numbered pixel columns and emitting green light are output from data driver 130. For example, during the second subframe period 2SFP, data driver 130 may output data voltages corresponding to the second image dataset IDS2.

[0125] According to some embodiments, the demultiplexer control signal DMCS may include a first selection signal CLA and a second selection signal CLB.

[0126] During the time period from T1 to T2, the first selection signal CLA can be enabled to a low level. The first selection transistor M1, the third selection transistor M3, ..., and the fifth selection transistor M5, respectively connected to the odd-numbered pixel columns COL1, COL3, ..., and COL2m-1, can be turned on in response to the first selection signal CLA. During the time period from T1 to T2, the first data voltage VDATA1 input via the first data line DL1 can be transmitted to the sub-pixels of the first pixel column COL1 via the A1 sub-data line DA1. The first data voltage VDATA1 may include voltages corresponding to sub-pixels emitting red light and sub-pixels emitting blue light. For example, during the time period from T1 to T2, the first data voltage VDATA1 may include voltages corresponding to the first sub-pixel data DR1, the seventh sub-pixel data DB7, the thirteenth sub-pixel data DR13, the nineteenth sub-pixel data DB19, ..., the twenty-fifth sub-pixel data DR25, and the thirty-first sub-pixel data DB31.

[0127] During the time period from T1 to T2, the second data voltage VDATA2, input via the second data line DL2, can be transmitted to the sub-pixels of the third pixel column COL3 via the A2 sub-data line DA2. The second data voltage VDATA2 may include voltages corresponding to sub-pixels emitting blue light and sub-pixels emitting red light. For example, during the time period from T1 to T2, the second data voltage VDATA2 may include voltages corresponding to the third sub-pixel data DB3, the ninth sub-pixel data DR9, the fifteenth sub-pixel data DB15, the twenty-first sub-pixel data DR21, ..., the twenty-seventh sub-pixel data DB27, and the thirty-third sub-pixel data DR33.

[0128] During the time period from T4 to T5, the second selection signal CLB can be enabled to a low level. The second selection transistors M2, M4, ..., and M6, respectively connected to even-numbered pixel columns COL2, COL4, ..., and COL2m, can be turned on in response to the second selection signal CLB. During the time period from T4 to T5, the first data voltage VDATA1 input via the first data line DL1 can be transmitted to the sub-pixels of the second pixel column COL2 via the B1 sub-data line DB1. The first data voltage VDATA1 may include the voltage corresponding to the sub-pixel emitting green light. For example, during the time period from T4 to T5, the first data voltage VDATA1 may include the voltage corresponding to the second sub-pixel data DG2, the eighth sub-pixel data DG8, the fourteenth sub-pixel data DG14, the twentieth sub-pixel data DG20, ..., the twenty-sixth sub-pixel data DG26, and the thirty-second sub-pixel data DG32.

[0129] During the time period from T4 to T5, the second data voltage VDATA2, input via the second data line DL2, can be transmitted to the sub-pixels of the fourth pixel column COL4 via the B2 sub-data line DB2. The second data voltage VDATA2 may include voltages corresponding to the sub-pixels emitting green light. For example, during the time period from T4 to T5, the second data voltage VDATA2 may include voltages corresponding to the fourth sub-pixel data DG4, the tenth sub-pixel data DG10, the sixteenth sub-pixel data DG16, the twenty-second sub-pixel data DG22, ..., the twenty-eighth sub-pixel data DG28, and the thirty-fourth sub-pixel data DG34.

[0130] The data voltage applied to the sub-pixel via the corresponding sub-data line in response to the first selection signal CLA and the second selection signal CLB can have the same configuration as the first data voltage and the second data voltage, so some redundant descriptions can be omitted.

[0131] Therefore, within a single frame period 1FP, the data voltage received during the first subframe period 1SFP may include data voltages corresponding to the red and blue subpixels in odd-numbered pixel columns. Accordingly, the first selection transistor M1, the third selection transistor M3, ..., and the fifth selection transistor M5 in the demultiplexer 160 may remain on during the first subframe period 1SFP. The data voltage received during the second subframe period 2SFP may include data voltages corresponding to the green subpixels in even-numbered pixel columns. Accordingly, the second selection transistor M2, the fourth selection transistor M4, ..., and the sixth selection transistor M6 in the demultiplexer 160 may remain on during the second subframe period 2SFP.

[0132] Therefore, the display device DD can reduce the number of switching operations (or conduction operations) per unit time of the first selection transistor M1 to the sixth selection transistor M6 in the demultiplexer 160, thereby minimizing or reducing power consumption.

[0133] Figure 10 is a flowchart illustrating aspects of the transmit and receive operations between the display device DD and the processor 10 of Figure 1.

[0134] Referring to Figures 1 and 10, at operation S210, the display device DD can send a register value RD2 having a second logic level to the processor 10. According to some embodiments, in a driving mode (e.g., normal driving mode) where the subpixels of the display panel DP are driven sequentially during a single frame period, the register value RD2 can have a second logic level. For example, the display device DD can send a value "0" corresponding to a pre-stored register value RD2. A detailed description of the structure and operation of the display panel DP driven in normal driving mode will be provided later with reference to Figures 11 and 13.

[0135] At operation S220, processor 10 can send image data IDATA2 arranged in an order corresponding to register value RD2 to display device DD. According to some embodiments, upon receiving register value RD2 with a second logic level, processor 10 can align the input image data to correspond to a normal driving mode, thereby generating image data IDATA2. Processor 10 can send image data IDATA2 arranged in an order corresponding to a normal driving mode as frame data to display device DD. A detailed description of the arrangement of image data IDATA2 will be provided later with reference to FIG12.

[0136] At operation S230, the display device DD can control the data driver 130 (refer to FIG. 2) based on the image data IDATA2. According to some embodiments, the timing controller 140 (refer to FIG. 2) can provide the image data IDATA2 to the data driver 130. The data driver 130 can convert the digital data signal image data IDATA2 into an analog data signal data voltage VDATA (refer to FIG. 4) in response to the data control signal DCS, and can provide the data voltage VDATA to the data lines DL1 to DLm.

[0137] Figure 11 is a plan view of a display device DD that illustrates the transmit / receive operation of Figure 10.

[0138] Referring to Figure 11, the display panel DP may include a first pixel column COL1, a second pixel column COL2, a third pixel column COL3, a fourth pixel column COL4, ..., a 2m-1 pixel column COL2m-1, and a 2m pixel column COL2m. According to some embodiments, in each of the first pixel column COL1, the third pixel column COL3, ..., and the 2m-1 pixel column COL2m-1, subpixels configured to emit red light and subpixels configured to emit blue light can be alternately arranged in the extension direction of data lines DL1 to DLm. In each of the second pixel column COL2, the fourth pixel column COL4, ..., and the 2m pixel column COL2m, subpixels configured to emit green light can be continuously arranged in the extension direction of data lines DL1 to DLm. The display panel DP can be configured in the same manner as described with reference to Figure 7. Therefore, some redundant descriptions can be omitted.

[0139] The display panel DP may include a first pixel row RW1, a second pixel row RW2, a third pixel row RW3, a fourth pixel row RW4, ..., a (n-1)th pixel row RWn-1, and an nth pixel row RWn. According to some embodiments, sub-pixels in the first pixel row RW1 may be connected to a first scan line SL1. First sub-pixel R1, second sub-pixel G2, third sub-pixel B3, fourth sub-pixel G4, ..., fifth sub-pixel B5, and sixth sub-pixel G6 may be connected to the first scan line SL1.

[0140] The subpixels in the second pixel row RW2 can be connected to the second scan line SL2. The seventh subpixel B7, the eighth subpixel G8, the ninth subpixel R9, the tenth subpixel G10, ..., the eleventh subpixel R11 and the twelfth subpixel G12 can be connected to the second scan line SL2.

[0141] The subpixels in the third pixel row RW3 can be connected to the third scan line SL3. The thirteenth subpixel R13, the fourteenth subpixel G14, the fifteenth subpixel B15, the sixteenth subpixel G16, ..., the seventeenth subpixel B17 and the eighteenth subpixel G18 can be connected to the third scan line SL3.

[0142] The subpixels in the fourth pixel row RW4 can be connected to the fourth scan line SL4. The nineteenth subpixel B19, the twentieth subpixel G20, the twenty-first subpixel R21, the twenty-second subpixel G22, ..., the twenty-third subpixel R23 and the twenty-fourth subpixel G24 can be connected to the fourth scan line SL4.

[0143] The 25th sub-pixel R25, the 26th sub-pixel G26, the 27th sub-pixel B27, the 28th sub-pixel G28, ..., the 29th sub-pixel B29 and the 30th sub-pixel G30 can be connected to the (n-1)th scan line SLn-1. The 31st sub-pixel B31, the 32nd sub-pixel G32, the 33rd sub-pixel R33, the 34th sub-pixel G34, ..., the 35th sub-pixel R35 and the 36th sub-pixel G36 can be connected to the nth scan line SLn.

[0144] In other words, within a single pixel row, subpixels configured to emit red light, blue light, and green light can be connected to a single scan line.

[0145] Demultiplexer 160 may include selection transistors M1 to M6 connected between data lines DL1 to DLm and sub-data lines DA1 to DAm and DB1 to DBm. Demultiplexer 160 may be configured in the same manner as described with reference to FIG7. Therefore, some redundant descriptions may be omitted.

[0146] Figure 12 is a timing diagram illustrating aspects of image data received from processor 10 of Figure 10.

[0147] Referring to Figures 10, 11 and 12, the image data IDATA2 is shown as frame data when the processor 10 receives a register value RD2 with a second logic level.

[0148] The image data IDATA2 corresponding to a single frame period 1FP may include an image dataset IDS. The display device DD may sequentially receive the image dataset IDS from the processor 10 during a single frame period 1FP.

[0149] According to some embodiments, during a single frame period 1FP, the display device DD can receive from the processor 10 an image dataset IDS that corresponds sequentially to the first pixel row RW1, the second pixel row RW2, the third pixel row RW3, the fourth pixel row RW4, ..., the (n-1)th pixel row RWn-1 and the nth pixel row RWn.

[0150] An image dataset IDS may include multiple subpixel data corresponding sequentially to subpixels arranged in each of the pixel rows. For example, an image dataset IDS may include first subpixel data DRW1 corresponding to subpixels in a first pixel row RW1. First subpixel data DRW1 may include subpixel data DR1, DG2, DB3, DG4, ..., DB5, and DG6 corresponding to first subpixel R1, second subpixel G2, third subpixel B3, fourth subpixel G4, ..., fifth subpixel B5, and sixth subpixel G6, respectively. An image dataset IDS may include second subpixel data DRW2 corresponding to subpixels in a second pixel row RW2. Second subpixel data DRW2 may include subpixel data DB7, DG8, DR9, DG10, ..., DR11, and DG12 corresponding to seventh subpixel B7, eighth subpixel G8, ninth subpixel R9, tenth subpixel G10, ..., eleventh subpixel R11, and twelfth subpixel G12, respectively. The image dataset IDS may include the nth sub-pixel data DRWn corresponding to the sub-pixels in the nth pixel row RWn. The nth sub-pixel data DRWn may include the sub-pixel data DB31, DG32, DR33, DG34, ..., DR35 and DG36 corresponding to the thirty-first sub-pixel B31, thirty-second sub-pixel G32, thirty-third sub-pixel R33, thirty-fourth sub-pixel G34, ..., thirty-fifth sub-pixel R35 and thirty-sixth sub-pixel G36, respectively.

[0151] As mentioned above, image data IDATA2 can be data in which sub-pixel data are arranged in an order corresponding to the normal driving mode.

[0152] Figure 13 illustrates a timing diagram of the operation of the display device DD in Figure 11 based on the image data in Figure 12.

[0153] Referring to Figures 11, 12, and 13, the range of a single frame period 1FP can be from T0 to T7. A single frame period 1FP can be a time period in which the data driver 130 outputs the data voltages of the sub-pixels from the first pixel row RW1 to the nth pixel row RWn. For example, during a single frame period 1FP, the data driver 130 can output data voltages corresponding to the image dataset IDS.

[0154] During a single frame period 1FP, each of the first selection signal CLA and the second selection signal CLB may include multiple pulses. For example, when the first selection signal CLA is enabled to a low level (or a high level), the second selection signal CLB may be enabled to a high level (or a low level).

[0155] According to some embodiments, during a time period ranging from T1 to T2, the first selection signal CLA can be enabled to a low level. First selection transistors M1, third selection transistors M3, ..., and fifth selection transistors M5, respectively connected to odd-numbered pixel columns COL1, COL3, ..., COL2m-1, can be turned on in response to the first selection signal CLA. During the time period ranging from T1 to T2, a first data voltage VDATA1 input via the first data line DL1 can be transmitted to the sub-pixels of the first pixel column COL1 via the A1 sub-data line DA1. During the time period ranging from T1 to T2, a second data voltage VDATA2 input via the second data line DL2 can be transmitted to the sub-pixels of the third pixel column COL3 via the A2 sub-data line DA2. Each of the first data voltage VDATA1 and the second data voltage VDATA2 may include a voltage corresponding to a sub-pixel emitting blue light and a sub-pixel emitting red light.

[0156] During the time period from T2 to T3, the second selection signal CLB can be enabled to a low level. The second selection transistor M2, the fourth selection transistor M4, ..., and the sixth selection transistor M6, respectively connected to even-numbered pixel columns COL2, COL4, ..., COL2m, can be turned on in response to the second selection signal CLB. During the time period from T2 to T3, the first data voltage VDATA1 input via the first data line DL1 can be transmitted to the sub-pixels of the second pixel column COL2 via the B1 sub-data line DB1. During the time period from T2 to T3, the second data voltage VDATA2 input via the second data line DL2 can be transmitted to the sub-pixels of the fourth pixel column COL4 via the B2 sub-data line DB2. Each of the first data voltage VDATA1 and the second data voltage VDATA2 may include a voltage corresponding to the sub-pixel emitting green light.

[0157] During the time period from T3 to T4, the first selection signal CLA can be enabled to a low level. During the time period from T3 to T4, the first data voltage VDATA1 can be transmitted to the sub-pixel of the first pixel column COL1 via the A1 sub-data line DA1, and the second data voltage VDATA2 can be transmitted to the sub-pixel of the third pixel column COL3 via the A2 sub-data line DA2.

[0158] During the time period from T4 to T5, the second selection signal CLB can be enabled to a low level. During the time period from T4 to T5, the first data voltage VDATA1 can be transmitted to the sub-pixel of the second pixel column COL2 via the B1 sub-data line DB1, and the second data voltage VDATA2 can be transmitted to the sub-pixel of the fourth pixel column COL4 via the B2 sub-data line DB2.

[0159] As described above, the data voltage received during a single frame period 1FP can include data voltages corresponding to the red and blue sub-pixels of odd-numbered pixel columns and data voltages corresponding to the green sub-pixels of even-numbered pixel columns. For example, the first data voltage VDATA1 can include voltages corresponding to the first sub-pixel data DR1, the second sub-pixel data DG2, the seventh sub-pixel data DB7, the eighth sub-pixel data DG8, ..., the thirty-first sub-pixel data DB31 and the thirty-second sub-pixel data DG32. The second data voltage VDATA2 can include voltages corresponding to the third sub-pixel data DB3, the fourth sub-pixel data DG4, the ninth sub-pixel data DR9, the tenth sub-pixel data DG10, ..., the thirty-third sub-pixel data DR33 and the thirty-fourth sub-pixel data DG34.

[0160] Figure 14 is a schematic block diagram illustrating an example of an electronic device 1000 including a display device DD according to some embodiments of the present disclosure.

[0161] Referring to FIG14, the electronic device 1000 according to some embodiments of the present disclosure can output various types of information through the display module 1140. If the processor 1110 executes an application stored in the memory 1120, the display module 1140 can provide application information to the user through the display panel 1141.

[0162] Processor 1110 can acquire external input via input module 1130 or sensor module 1161 and execute applications corresponding to the external input. For example, if the user selects a camera icon (or camera application icon) displayed on display panel 1141, processor 1110 can acquire user input via input sensor 1161-2 and activate camera module 1171. Processor 1110 can then transmit image data corresponding to the image captured by camera module 1171 to display module 1140. Display module 1140 can then display the image corresponding to the captured image on display panel 1141.

[0163] As another example, when performing personal information authentication via display module 1140, fingerprint sensor 1161-1 can acquire the input fingerprint information as input data. Processor 1110 can compare the input data acquired by fingerprint sensor 1161-1 with authentication data stored in memory 1120, and can execute an application based on the comparison result. Display module 1140 can display information executed according to the application logic on display panel 1141. Fingerprint sensor 1161-1 can be positioned such that it is possible to acquire fingerprint information over the entire area of ​​display module 1140 (or display panel 1141).

[0164] As another example, when a music stream icon displayed on display module 1140 is selected, processor 1110 can acquire user input via input sensor 1161-2 and activate the music stream application stored in memory 1120. If a music playback command is entered in the music stream application, processor 1110 can activate sound output module 1163 and provide the user with sound information corresponding to the music playback command.

[0165] A brief description of the operation of the electronic device 1000 has been provided to date. The construction of the electronic device 1000 will be described in detail below. Some of the components of the electronic device 1000 described below may be integrated into a single component, or a component may be separated into two or more components.

[0166] Electronic device 1000 can communicate with external electronic device 2000 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to some embodiments, electronic device 1000 may include a processor 1110, a memory 1120, an input module 1130, a display module 1140, a power module 1150, an embedded module 1160, and an external mounting module 1170. According to some embodiments, at least one of the aforementioned components may be omitted from electronic device 1000, or one or more other components may be added. According to some embodiments, some of the aforementioned components (e.g., sensor module 1161, antenna module 1162, or audio output module 1163) may be integrated into another component (e.g., display module 1140).

[0167] Processor 1110 can execute software to control at least one other component (e.g., hardware or software component) of electronic device 1000 connected to processor 1110 and perform various data processing or computational operations. According to some embodiments, as at least part of the data processing or computational operation, processor 1110 can store commands or data received from another component (e.g., input module 1130, sensor module 1161, or communication module 1173) in volatile memory 1121, process the commands or data stored in volatile memory 1121, and store the result data in non-volatile memory 1122. Processor 1110 may include processor 10 of FIG. 1.

[0168] Processor 1110 may include a main processor 1111 and an auxiliary processor 1112. The main processor 1111 may include one or more of a central processing unit (CPU) 1111-1 and an application processor (AP). The main processor 1111 may further include any one of a graphics processing unit (GPU) 1111-2, a communication processor (CP), and an image signal processor (ISP). The main processor 1111 may further include a neural processing unit (NPU) 1111-3. NPU 1111-3 may be a processor dedicated to processing artificial intelligence models. The artificial intelligence model can be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the aforementioned networks, but is not limited thereto. The artificial intelligence model may include not only hardware architectures but also additional or alternative software architectures. At least two of the aforementioned processing units and processors can be implemented as a single integrated component (e.g., a single chip). Alternatively, the processing units and processors can be implemented as separate components (e.g., multiple chips).

[0169] The auxiliary processor 1112 may include a controller 1112-1. The controller 1112-1 may include interface conversion circuitry and timing control circuitry. For example, the controller 1112-1 may include the timing controller 140 shown in FIG. 2. The controller 1112-1 may send register values ​​to the main processor 1111 and may receive image data from the main processor 1111. The controller 1112-1 may output various control signals required to drive the display module 1140.

[0170] The auxiliary processor 1112 may further include a data conversion circuit 1112-2, a gamma correction circuit 1112-3, a rendering circuit 1112-4, and a touch control circuit, etc. The data conversion circuit 1112-2 can receive image data from the controller 1112-1, compensate the image data based on the characteristics of the electronic device 1000 or user settings to display the image at the desired brightness, or it can convert the image data to reduce power consumption or compensate for afterimages.

[0171] The gamma correction circuit 1112-3 can convert image data or gamma reference voltage, etc., so that the image to be displayed on the electronic device 1000 can have the desired gamma characteristics. The rendering circuit 1112-4 can receive image data from the controller 1112-1 and render the image data taking into account the pixel arrangement, etc., applied to the display panel 1141 of the electronic device 1000.

[0172] The touch control circuit can supply touch signals to the input sensor 1161-2 and receive sensing signals from the input sensor 1161-2 in response to the touch signals.

[0173] At least one of the data conversion circuit 1112-2, gamma correction circuit 1112-3, rendering circuit 1112-4, and touch control circuit can be integrated into another component (e.g., main processor 1111 or controller 1112-1). At least one of the data conversion circuit 1112-2, gamma correction circuit 1112-3, and rendering circuit 1112-4 can be integrated into the data driver 1143, which will be described below.

[0174] The memory 1120 may store various data to be used in at least one component of the electronic device 1000 (e.g., processor 1110 or sensor module 1161), as well as input or output data of commands regarding various data. Furthermore, the memory 1120 may store various setting data corresponding to user settings. The memory 1120 may include at least one of volatile memory 1121 and non-volatile memory 1122.

[0175] The input module 1130 can receive commands or data from an external device (e.g., a user or external electronic device 2000) provided outside the electronic device 1000, which will be used in components of the electronic device 1000 (e.g., processor 1110, sensor module 1161, or voice output module 1163).

[0176] Input module 1130 may include a first input module 1131 configured to receive commands or data from a user and a second input module 1132 configured to receive commands or data from an external electronic device 2000. The first input module 1131 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 1132 may support a specified protocol that allows wired or wireless connection to the external electronic device 2000. According to some embodiments, the second input module 1132 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, an SD card interface, or an audio interface. The second input module 1132 may include a connector for physical connection to the external electronic device 2000, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0177] Display module 1140 can provide visual information to the user. Display module 1140 may include display panel 1141, scan driver 1142, and data driver 1143.

[0178] The display panel 1141 (or display) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel. The type of display panel 1141 is not limited to a specific type. The display panel 1141 may be a rigid panel or a flexible panel that can be rolled up or folded. The display module 1140 may further include a support, bracket, or heat sink for supporting the display panel 1141.

[0179] Display panel 1141 can receive image data from auxiliary processor 1112 and display an image while controlling the amount of current flowing from the line for transmitting the first power voltage (or first power supply) VDD through pixel PXL to the line for transmitting the second power voltage (or second power supply) VSS in accordance with the image data. Display panel 1141 may correspond to display panel DP illustrated in FIG2.

[0180] The scan driver 1142 can be mounted as a driver chip on the display panel 1141. The scan driver 1142 can be integrated into the display panel 1141. For example, the scan driver 1142 may include an amorphous silicon TFT gate (ASG) driving circuit, a low-temperature polycrystalline silicon (LTPS) TFT gate driving circuit, or an oxide semiconductor TFT gate (OSG) driving circuit embedded in the display panel 1141. The scan driver 1142 can receive control signals from the controller 1112-1 and output scan signals to the display panel 1141 in response to the control signals. The scan driver 1142 may include the scan driver 120 illustrated in FIG. 2.

[0181] The display module 1140 may further include a transmit driver. The transmit driver may output a transmit control signal to the display panel 1141 in response to a control signal received from the controller 1112-1. The transmit driver may be formed separately from the scan driver 1142, or it may be integrated into the scan driver 1142.

[0182] Data driver 1143 can receive control signals from controller 1112-1, convert image data into analog voltages (e.g., data signals) in response to the control signals, and output the data signals to display panel 1141. Data driver 1143 may include data driver 130 illustrated in FIG2.

[0183] The data driver 1143 can be integrated into another component (e.g., controller 1112-1). The functions of the interface conversion circuit and timing control circuit of controller 1112-1 can be integrated into the data driver 1143.

[0184] The display module 1140 may further include a voltage generation circuit 1144. The voltage generation circuit 1144 can output various voltages required to drive the display panel 1141.

[0185] According to some embodiments, the data driver 1143 can convert data included in the image data received from the processor 1110 and corresponding to red (R), green (G) and blue (B) into red data signals (or data voltages), green data signals and blue data signals, and provide the data signals to a plurality of pixel columns included in the display panel 1141 during a single horizontal time period.

[0186] Power module 1150 can supply power to components of electronic device 1000. Power module 1150 may include a battery for storing electrical voltage. The battery may include a non-rechargeable primary battery and a rechargeable secondary battery or fuel cell. Power module 1150 may include a power management integrated circuit (PMIC). The PMIC can supply optimized power to each of the aforementioned modules and the modules described below. Power module 1150 may include a wireless power transceiver electrically connected to the battery. The wireless power transceiver may include multiple coiled antenna radiators. Voltage generation circuitry 1144 may be integrated with power module 1150.

[0187] The electronic device 1000 may further include an embedded module 1160 and an external mounting module 1170. The embedded module 1160 may include a sensor module 1161, an antenna module 1162, and a sound output module 1163. The external mounting module 1170 may include a camera module 1171, an optical module 1172, and a communication module 1173.

[0188] Sensor module 1161 can sense input from the user's body or from the pen of the first input module 1131, and generate an electrical signal or data value corresponding to the input. Sensor module 1161 may include at least one of fingerprint sensor 1161-1, input sensor 1161-2, and digitizer 1161-3.

[0189] The fingerprint sensor 1161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 1161-1 can include either an optical fingerprint sensor or a capacitive fingerprint sensor.

[0190] Input sensor 1161-2 can generate data values ​​corresponding to coordinate information from input from the user's body or from input from a pen. Input sensor 1161-2 can generate data values ​​corresponding to the amount of capacitance change caused by input. Input sensor 1161-2 can sense input from a passive pen, or send data to or receive data from an active pen.

[0191] Input sensor 1161-2 can measure biosignals about biological information such as blood pressure, body fluids, or body fat. For example, if a user brings a part of his / her body into contact with the sensor layer or sensing panel and keeps it still for a period of time, input sensor 1161-2 can sense biosignals based on changes in the electric field caused by that part of his / her body and output the information desired by the user to display module 1140.

[0192] The digitizer 1161-3 can generate data values ​​corresponding to coordinate information from input from a pen. The digitizer 1161-3 can also generate data values ​​corresponding to electromagnetic changes caused by the input. The digitizer 1161-3 can sense input from a passive pen, or send data to or receive data from an active pen.

[0193] At least one of the fingerprint sensor 1161-1, input sensor 1161-2, and digitizer 1161-3 can be implemented as a sensor layer formed on the display panel 1141 by a continuous process. At least one of the fingerprint sensor 1161-1, input sensor 1161-2, and digitizer 1161-3 can be located above the display panel 1141. Any one of the fingerprint sensor 1161-1, input sensor 1161-2, and digitizer 1161-3 (e.g., digitizer 1161-3) can be located below the display panel 1141.

[0194] At least two of the fingerprint sensor 1161-1, input sensor 1161-2, and digitizer 1161-3 can be formed into a single sensing panel using the same process. When at least two of the fingerprint sensor 1161-1, input sensor 1161-2, and digitizer 1161-3 are integrated into a single sensing panel, the sensing panel can be located between the display panel 1141 and a window located above the display panel 1141. According to some embodiments, the sensing panel can be located on the window, and the position of the sensing panel is not particularly limited.

[0195] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 can be embedded in the display panel 1141. In other words, during the process of forming components (e.g., light-emitting elements and transistors) included in the display panel 1141, at least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 can be formed simultaneously (or concurrently) with said components.

[0196] Additionally, sensor module 1161 can generate electrical signals or data values ​​corresponding to the internal or external conditions of electronic device 1000. Sensor module 1161 may further include, for example, a gesture sensor, gyroscope sensor, atmospheric sensor, magnetic sensor, accelerometer, grip sensor, proximity sensor, color sensor, infrared (IR) sensor, biosensor, temperature sensor, humidity sensor, or illuminance sensor.

[0197] Antenna module 1162 may include one or more antennas for transmitting or receiving signals or power to or from an external device. According to some embodiments, communication module 1173 may transmit or receive signals from external electronic device 2000 via an antenna suitable for a communication scheme. The antenna pattern of antenna module 1162 may be integrated into components of display module 1140 (e.g., display panel 1141 of display module 1140) or input sensors 1161-2.

[0198] The sound output module 1163 may be a means for outputting sound signals to a device provided external to the electronic device 1000, and may include, for example, a speaker for typical purposes such as reproducing multimedia or recording data, and a receiver for telephone reception only. According to some embodiments, the receiver may be integrated with or separate from the speaker. The sound output pattern of the sound output module 1163 may be integrated into the display module 1140.

[0199] Camera module 1171 can capture still images or video. According to some embodiments, camera module 1171 may include one or more lenses, an image sensor, or an image signal processor. Camera module 1171 may further include an infrared camera capable of sensing the presence of a user, the user's position, or the user's line of sight.

[0200] The optical module 1172 can provide light. The optical module 1172 may include a light-emitting diode or a xenon lamp. The optical module 1172 can be interlocked with the camera module 1171 or operate independently of the camera module 1171.

[0201] Communication module 1173 can form a wired or wireless communication channel between electronic device 1000 and external electronic device 2000, and support the execution of communication through the formed communication channel. Communication module 1173 may include any one or two of the following: a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module; and a wired communication module such as a Local Area Network (LAN) communication module or a power line communication module. Communication module 1173 can communicate with external electronic device 2000 through short-range communication networks such as Bluetooth, WiFi Direct, or Infrared Data Association (IrDA), or long-range communication networks such as cellular networks, the Internet, or computer networks (e.g., LAN or WAN). The various types of communication modules 1173 described above can be implemented as a single chip or as separate chips.

[0202] The input module 1130, sensor module 1161, and camera module 1171, which are interlocked with the processor 1110, can be used to control the operation of the display module 1140.

[0203] The processor 1110 can output commands or data to the display module 1140, the sound output module 1163, the camera module 1171, or the optical module 1172 based on input data received from the input module 1130. For example, the processor 1110 can generate image data and output the image data to the display module 1140 in response to input data applied via a mouse or active pen, or it can generate command data and output the command data to the camera module 1171 or the optical module 1172 in response to input data. When no input data is received from the input module 1130, the processor 1110 can switch the operating mode of the electronic device 1000 to a low-power mode or a sleep mode, thereby reducing the power consumption of the electronic device 1000.

[0204] The processor 1110 can output commands or data to the display module 1140, the sound output module 1163, the camera module 1171, or the optical module 1172 based on the sensing data received from the sensor module 1161. For example, the processor 1110 can compare the authentication data applied from the fingerprint sensor 1161-1 with the authentication data stored in the memory 1120, and execute an application based on the comparison result. The processor 1110 can execute commands or output corresponding image data to the display module 1140 based on the sensing data sensed by the input sensor 1161-2 or the digitizer 1161-3. If the sensor module 1161 includes a temperature sensor, the processor 1110 can receive temperature data of the measured temperature from the sensor module 1161, and further perform brightness correction operations on the image data based on the temperature data.

[0205] Processor 1110 can receive measurement data from camera module 1171 regarding the presence of a user, the user's position, or the user's gaze. Processor 1110 can further perform brightness correction operations on the image data based on the measurement data. For example, processor 1110, having already determined the presence of a user through input from camera module 1171, can output image data whose brightness has been corrected by data conversion circuit 1112-2 or gamma correction circuit 1112-3 to display module 1140.

[0206] Some of the aforementioned components can be connected to each other via communication schemes that can be used between peripheral devices, such as buses, general purpose input / output (GPIO), serial peripheral interfaces (SPI), mobile industry processor interfaces (MIPI), or ultrapath interconnect (UPI) links, and thus can exchange signals (e.g., commands or data). Processor 1110 can communicate with display module 1140 via an interface (e.g., a configuration or predefined interface). For example, any of the aforementioned communication schemes can be used, and the interface is not limited to the aforementioned communication schemes.

[0207] In display devices and electronic devices including display devices according to some embodiments of the present disclosure, the display device can receive image data arranged in an order corresponding to the driving mode of the display panel from a processor, and control a data driver based on the received image data. Accordingly, the display device may not include a separate controller or memory for performing various data processing or operations to rearrange the image data. As a result, because no additional space or power is required for a separate controller or memory to rearrange the image data, the size and manufacturing cost of the display device can be reduced, and power consumption can be reduced, thereby relatively improving efficiency.

[0208] Various embodiments of this disclosure can provide display devices with relatively improved efficiency and electronic devices including display devices.

[0209] The effects of this disclosure are not limited to the foregoing, and various other effects are contemplated herein.

[0210] Electronic or electrical devices and / or any other related devices or components according to embodiments of the invention described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on a single integrated circuit (IC) chip or on multiple separate IC chips. Furthermore, various components of these devices can be implemented on flexible printed circuit films, tape-on-a-carrier packages (TCPs), or rigid printed circuit boards (PCBs), or formed on a substrate. Additionally, various components of these devices can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. The computer program instructions are stored in memory that can be implemented in the computing device using standard memory devices such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media such as CD-ROMs or flash drives. Furthermore, those skilled in the art will recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the spirit and scope of exemplary embodiments of the invention.

[0211] Although specific embodiments and implementations have been described herein, other embodiments and modifications will be apparent from the foregoing description. Accordingly, the features of the embodiments according to this disclosure are not limited to the foregoing embodiments, but are limited by the claims and their wider equivalents.

Claims

1. A display device, comprising: A display panel, including sub-pixels; a scan driver connected to the sub-pixels via scan lines; A data driver is connected to the sub-pixel via a data cable; A timing controller is configured to control the scan driver and the data driver, wherein the timing controller is configured to send pre-stored register values ​​to the processor, receive image data arranged in an order corresponding to the register values ​​from the processor, and control the data driver based on the image data.

2. The display device according to claim 1, wherein, The register value indicates one of the first logic level and the second logic level.

3. The display device according to claim 2, wherein, The sub-pixels form a pixel row, wherein at least one of the pixel rows includes a first sub-pixel and a second sub-pixel, and wherein the first sub-pixel is connected to a first scan line in the scan line, the second sub-pixel is connected to a second scan line in the scan line, and the register value has the first logic level.

4. The display device according to claim 2, wherein, The sub-pixels form pixel rows, and the pixel rows are connected to the corresponding scan lines, and the register value has the second logic level.

5. The display device according to claim 2, wherein, The subpixels form a first pixel column and a second pixel column arranged alternately with the first pixel column, wherein the first pixel column and the second pixel column are connected to the data driver via the data line, and wherein, based on the register value having the first logic level, a first image dataset corresponding to the first pixel column is configured to be received from the processor during a first time period, and a second image dataset corresponding to the second pixel column is configured to be received from the processor during a second time period after the first time period, and the first image dataset and the second image dataset are included in the image data.

6. The display device according to claim 5, wherein, The first image dataset and the second image dataset are configured to be received sequentially during a single frame period.

7. The display device according to claim 5, wherein, Each of the sub-pixels is configured to emit light of any one of a first color, a second color, and a third color, wherein in each of the first pixel columns, the sub-pixels emitting light of the first color and the sub-pixels emitting light of the second color are alternately arranged, and wherein in each of the second pixel columns, the sub-pixels emitting light of the third color are arranged.

8. The display device according to claim 7, wherein, The first image dataset includes first sub-pixel data corresponding to both the sub-pixel configured to emit light of the first color and the sub-pixel configured to emit light of the second color, and the second image dataset includes second sub-pixel data corresponding to the sub-pixel configured to emit light of the third color.

9. The display device according to claim 5, wherein, The data driver is configured to output a data voltage corresponding to the image data to the data line, wherein the first pixel column is connected to a first sub-data line, and wherein the second pixel column is connected to a second sub-data line, and the display device further includes a demultiplexer configured to selectively transmit the data voltage output through the data line to the first sub-data line and the second sub-data line.

10. The display device according to claim 9, wherein, The demultiplexer is configured to transmit a data voltage corresponding to the first image dataset to the first sub-data line and a data voltage corresponding to the second image dataset to the second sub-data line.

11. The display device according to claim 2, wherein, The subpixels form a pixel row, wherein the pixel row is connected to the scan driver via the scan line, wherein an image dataset corresponding to the pixel row is configured to be received from the processor based on the register value being at the second logic level, the image dataset being included in the image data, and wherein the image dataset includes subpixel data sequentially corresponding to the subpixels arranged in each of the pixel rows.

12. The display device according to claim 11, wherein, The image dataset is configured to be received during a single frame period.

13. The display device according to any one of claims 1 to 12, wherein, The timing controller includes a register configured to store the register value, wherein the register value is pre-stored based on the driving mode of the display panel.

14. An electronic device comprising: A display device includes sub-pixels; and a processor configured to control the display device, wherein the display device is configured to send pre-stored register values ​​to the processor, receive image data arranged in an order corresponding to the register values ​​from the processor, and drive the sub-pixels based on the image data.

15. The electronic device according to claim 14, wherein, The register value indicates one of the first logic level and the second logic level.

16. The electronic device according to claim 15, wherein, The display device further includes: a scan driver connected to the sub-pixels via scan lines, wherein the sub-pixels form pixel rows, wherein at least one of the pixel rows includes a first sub-pixel and a second sub-pixel, and wherein the first sub-pixel is connected to a first scan line in the scan lines, the second sub-pixel is connected to a second scan line in the scan lines, and the register value has the first logic level.

17. The electronic device according to claim 15, wherein, The display device further includes: a scan driver connected to the sub-pixels via scan lines, wherein the sub-pixels form pixel rows, and wherein the pixel rows are connected to corresponding scan lines, and the register value has the second logic level.

18. The electronic device according to claim 14, wherein, The display device further includes: a data driver connected to the sub-pixel via a data line, wherein the sub-pixel forms a first pixel column and a second pixel column alternately arranged with the first pixel column, wherein the first pixel column and the second pixel column are connected to the data driver via the data line, and wherein, based on the register value having a first logic level, a first image dataset corresponding to the first pixel column is configured to be received from the processor during a first time period, and a second image dataset corresponding to the second pixel column is configured to be received from the processor during a second time period after the first time period, and the first image dataset and the second image dataset are included in the image data.

19. The electronic device according to claim 18, wherein, The first image dataset and the second image dataset are configured to be received sequentially during a single frame period.

Images