A fully differential current domain echo cancellation analog front-end circuit and a working method thereof

Abstract

The application discloses a kind of full differential current domain echo cancellation analog front-end circuit and its working method.The circuit includes one end and chip pin connection resistance R50_to_AVDD, resistance R_hybrid and local sending current source LS, the other end of resistance R50_to_AVDD is connected with power supply positive pole VDD, the other end of resistance R_hybrid is respectively connected with echo cancellation current source LS_cancel, fixed pull-down current source Idc and the one end of capacitor AC_couple, the other end of capacitor AC_couple is respectively connected with recovery resistance Rdc and gain amplifier Gain, resistance R_hybrid and capacitor AC_couple are all connected with a signal switch in parallel.The application supports three kinds of working modes, can adapt to different encoding mode, different rate application demand, simplifies BOM management.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, specifically to a fully differential current domain echo cancellation analog front-end circuit and its operating method. Background Technology

[0002] With the continuous development of high-speed communication technology, ultra-high-speed full-duplex communication (such as >1GHz PAM signal transmission) places higher demands on analog front-end circuits. In application scenarios such as Ethernet, automotive Ethernet, and inter-chip communication, the transmitting end (TX) and the receiving end (RX) need to work simultaneously on the same transmission medium. Therefore, echo cancellation technology must be used to eliminate the interference of local transmitted signals on the receiving channel.

[0003] Traditional echo cancellation schemes mainly include the following:

[0004] 1. Transformer Hybrid: This method uses a transformer to achieve impedance matching and echo cancellation, but it is bulky and difficult to integrate into modern CMOS chips, and its frequency response characteristics are limited.

[0005] 2. Active Hybrid with DAC: This method uses a digital-to-analog converter (DAC) to generate echo cancellation signals. It requires a high-speed DAC and a precise calibration algorithm, resulting in high power consumption. Furthermore, the nonlinearity of the DAC can introduce distortion.

[0006] 3. Voltage domain hybrid circuit based on high-speed operational amplifier: The operational amplifier is used for signal subtraction and level conversion, but it is limited by the gain-bandwidth product (GBW) of the operational amplifier, making it difficult to support ultra-high-speed signal transmission of >1GHz.

[0007] 4. Line Driver Solution: This solution requires a separate driver chip to drive the transmission line, which increases system complexity, BOM cost, and power consumption.

[0008] The aforementioned existing technologies all have the following shortcomings: either they have limited bandwidth and cannot support ultra-high-speed PAM signals; or they require complex calibration algorithms and additional DAC / op-amp resources; or they cannot flexibly adapt to the signal requirements of different rates and encoding methods. Summary of the Invention

[0009] The purpose of this invention is to address the shortcomings of existing technologies by providing a fully differential current domain echo cancellation analog front-end circuit and its operating method.

[0010] To achieve the above objectives, this invention provides a fully differential current domain echo cancellation analog front-end circuit, including a resistor R50_to_AVDD, a resistor R_hybrid, and a local transmit current source LS, one end of which is connected to a chip pin. The other end of the resistor R50_to_AVDD is connected to the positive power supply VDD. The other end of the resistor R_hybrid is connected to one end of the echo cancellation current source LS_cancel, the fixed pull-down current source Idc, and the capacitor AC_couple, respectively. The other ends of the local transmit current source LS, the echo cancellation current source LS_cancel, and the fixed pull-down current source Idc are each grounded through a signal switch. The other end of the capacitor AC_couple is connected to the recovery resistor Rdc and the gain amplifier Gain, respectively. The other end of the recovery resistor Rdc is connected to the positive power supply Vdc. A signal switch is connected in parallel with both the resistor R_hybrid and the capacitor AC_couple.

[0011] Furthermore, both the resistor R50_to_AVDD and the recovery resistor Rdc are adjustable resistors.

[0012] Furthermore, the signal switch is a MOSFET.

[0013] In a second aspect, the present invention provides a method for operating the above-mentioned fully differential current domain echo cancellation analog front-end circuit, including three operating modes, namely operating mode one, operating mode two and operating mode three.

[0014] In the aforementioned operating mode, the signal switch connected to the fixed pull-down current source Idc remains in the off state; the superimposed signal of the received signal V_rx sent by the other device and the local transmitted signal V_tx at the chip pin is canceled by the echo cancellation current source LS_cancel at the node after passing through the resistor R_hybrid; after being filtered by the capacitor AC_couple and the recovery resistor Rdc, only the high-speed PAM signal V_rx sent by the other device remains.

[0015] In the second working mode, the signal switch controlling the parallel connection of the capacitor AC_couple remains closed; the superimposed signal of the received signal V_rx sent by the other device at the chip pin and the local transmitted signal V_tx, after passing through the resistor R_hybrid, is canceled by the echo cancellation current source LS_cancel at the node by current subtraction cancellation; the fixed pull-down current source completes the common-mode point conversion on the resistor R_hybrid.

[0016] In the third operating mode, the signal switch controlling the parallel connection of the resistor R_hybrid remains closed, and the signal switch connecting the echo cancellation current source LS_cancel and the fixed pull-down current source Idc remains open. The superimposed signal of the received signal V_rx sent by the other device at the chip pin and the local transmitted signal V_tx bypasses the resistor R_hybrid and directly passes through the high-pass filter composed of the capacitor AC_couple and the recovery resistor Rdc. The local transmitted signal V_tx achieves implicit cancellation by utilizing the frequency domain separation characteristics.

[0017] Furthermore, in the aforementioned working mode, data encoding techniques are used to avoid signal distortion and increased bit error rate caused by long 0s or long 1s in the data stream.

[0018] Furthermore, the data encoding techniques include Manchester encoding, 8b10b encoding, PAM-specific encoding, and scrambling codes.

[0019] Furthermore, the three operating modes are selected by hardware mode selection, automatically selected by detecting the characteristics of the input signal, or dynamically configured by the controller.

[0020] Beneficial effects: (1) Ultra-wide operating bandwidth: The open-loop architecture has no op-amp GBW limitation and can support ultra-high-speed PAM signals >1GHz;

[0021] (2) Low power consumption: No high-speed op-amp, line driver or independent hybrid DAC required;

[0022] (3) High integration: Fully differential minimal topology, easy to integrate with CMOS;

[0023] (4) Multi-mode adaptive: One chip supports three working modes, which can adapt to different encoding methods (PAM / NRZ) and different application requirements, simplifying BOM management;

[0024] (5) Excellent noise performance: Fully differential suppression of common-mode noise and even harmonics, and natural LPF suppression of high-frequency interference;

[0025] (6) Simplify the system BOM: Multi-mode design reduces external components and lowers system cost. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the fully differential current domain echo cancellation analog front-end circuit according to an embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram of the fully differential current domain echo cancellation analog front-end circuit in one of the operating modes of this invention.

[0028] Figure 3This is a schematic diagram of the fully differential current domain echo cancellation analog front-end circuit in operating mode two of this invention.

[0029] Figure 4 This is a schematic diagram of the fully differential current domain echo cancellation analog front-end circuit in operating mode three of this invention. Detailed Implementation

[0030] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. These embodiments are implemented based on the technical solutions of the present invention, and it should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0031] like Figure 1 As shown, this embodiment of the invention provides a fully differential current domain echo cancellation analog front-end circuit, including a chip pin (PAD interface). The chip pin is used to receive a differential signal from a transmission line (twisted pair), which is the superposition of the received signal V_rx sent by the other device and the local transmitted signal V_tx. One end of the chip pin is connected to one end of resistor R50_to_AVDD, resistor R_hybrid, and the local transmitted current source LS, respectively. The other end of resistor R50_to_AVDD is connected to the positive power supply VDD. The other end of resistor R_hybrid is connected to one end of the echo cancellation current source LS_cancel, the fixed pull-down current source Idc, and capacitor AC_couple, respectively. The other ends of the local transmitted current source LS, the echo cancellation current source LS_cancel, and the fixed pull-down current source Idc are respectively grounded through a signal switch. The signal switch connected to the local transmitted current source LS is controlled by the control signal Txdata, thereby controlling the local transmitted current source LS to generate the local transmitted signal V_tx and couple the local transmitted signal V_tx to the chip pin. The signal switch connected to the echo cancellation current source LS_cancel is controlled by the control signal -Txdata, thereby controlling the echo cancellation current source LS_cancel to generate an echo cancellation signal corresponding to the locally transmitted signal V_tx. The signal switch connected to the fixed pull-down current source Idc controls the fixed pull-down current source Idc to operate when closed. The other end of the capacitor AC_couple is connected to the recovery resistor Rdc and the gain amplifier Gain, respectively. The other end of the recovery resistor Rdc is connected to the positive power supply Vdc. The left input point of the gain amplifier Gain is the AFE input node. A signal switch is connected in parallel with both the resistor R_hybrid and the capacitor AC_couple. These two signal switches operate according to the control signals R_hybrid bypass and AC bypass, respectively, thereby controlling whether the resistor R_hybrid and the capacitor AC_couple are operating. The above signal switches are preferably MOSFETs.

[0032] The resistance value of the aforementioned resistor R_hybrid determines the accuracy of echo cancellation and the cutoff frequency of the LPF. A higher resistance value results in higher node impedance and higher echo cancellation accuracy, but reduces bandwidth. The specific resistance value is determined based on the transmission line impedance and application requirements.

[0033] The aforementioned resistor R50_to_AVDD not only provides DC bias for the PAD, but also, together with resistor R_hybrid, determines the DC operating point of the node. The specific resistance value is determined based on the transmission line impedance and application requirements; an adjustable resistor is preferred.

[0034] The aforementioned echo cancellation current source LS_cancel needs to be precisely matched with the local transmitted current to ensure the echo cancellation effect. Matching can be achieved using conventional techniques in this field.

[0035] The capacitance value of the aforementioned capacitor AC_couple determines the cutoff frequency of the high-pass filter. A larger capacitance value results in a lower cutoff frequency, allowing more low-frequency components to pass. The specific capacitance value is determined based on signal characteristics and application requirements.

[0036] The aforementioned recovery resistor Rdc not only provides DC bias for the AFE input node, but also, together with the capacitor AC_couple, determines the characteristics of the high-pass filter. The specific resistance value is adjusted according to application requirements, and an adjustable resistor is preferred.

[0037] Based on the above embodiments, those skilled in the art can easily understand that the present invention also provides a method for operating a fully differential current domain echo cancellation analog front-end circuit, including three operating modes, namely operating mode one, operating mode two and operating mode three.

[0038] Operating mode one is the conventional operating mode, which is the most basic implementation of this invention, and its circuit structure is as follows: Figure 2 As shown. This mode is suitable for cost-sensitive applications where data encoding can be used to maintain DC balance.

[0039] In the aforementioned operating mode, the signal switch controlling the fixed pull-down current source Idc remains in the off state, and the connection relationship of the simulated front-end circuit is as follows:

[0040] (1) The chip pin receives a differential signal from the transmission line (twisted pair), which is the superposition of the received signal V_rx sent by the other device and the local transmitted signal V_tx;

[0041] (2) PAD is connected to the positive terminal VDD of the power supply through resistor R50_to_AVDD to provide bias current;

[0042] (3) After passing through resistor R_hybrid, the signal enters the input node of capacitor AC_couple;

[0043] (4) The capacitor AC_couple input node is connected to the subsequent circuit through the capacitor AC_couple, and DC bias is provided through the recovery resistor Rdc.

[0044] (5) Control signal - Txdata controls the echo cancellation current source LS_cancel to generate an echo cancellation signal and injects it into the connection point between resistor R_hybrid and AFE input node, and uses KCL (Kirchhoff's Current Law) to achieve current subtraction.

[0045] After passing through resistor R_hybrid, the superimposed signals V_rx + V_tx are canceled out by the echo cancellation current source LS_cancel at the node. Since the current magnitude of LS_cancel precisely matches the local transmit current (achieved through current replication), the local transmit signal V_tx is completely canceled out, leaving only the signal V_rx transmitted by the other party. After filtering by capacitor AC_couple and recovery resistor Rdc, only the high-speed PAM signal transmitted by the other party remains, i.e., the effective received signal V_rx.

[0046] Due to the presence of AC coupling capacitors, when the input signal contains a DC component, the charging and discharging of the capacitors causes the DC operating point of the output signal to drift, resulting in baseline drift. This phenomenon is particularly pronounced when long 0s or long 1s appear in the data stream, leading to signal distortion and increased bit error rate.

[0047] Solution: This mode requires the use of data encoding techniques to avoid long 0s and long 1s, ensuring DC balance of the signal. Commonly used encoding schemes include:

[0048] (1) Manchester encoding: Each bit period is divided into two half-cycles. High-low level represents "1" and low-high level represents "0", which naturally ensures DC balance;

[0049] (2) 8b10b encoding: a commonly used DC balanced encoding method that encodes 8 bits of data into 10 bits of symbols, ensuring that the number of 0s and 1s is equal for a long time, and is suitable for high-speed serial communication;

[0050] (3) PAM-specific coding: For higher-order PAM modulation such as PAM-4, a special coding scheme is designed to maintain DC balance;

[0051] (4) Scrambling: Pseudo-random scrambling technology is used to break up long 0s and long 1s to achieve DC balance.

[0052] The resistor R_hybrid, together with the parasitic capacitance C_total of the AFE input node (including package parasitic capacitance and internal chip parasitic capacitance), forms a first-order low-pass filter (LPF), whose cutoff frequency f_c is approximately:

[0053] f_c = 1 / (2π × R × C)

[0054] Where R is the resistance value of resistor R_hybrid, and C is the capacitance value of parasitic capacitance C_total.

[0055] This LPF can effectively suppress high-frequency noise (such as EMI interference) on twisted-pair cables, preventing this noise from coupling into the RxAFE and causing a decrease in the ADC signal-to-noise ratio. This feature is particularly important for automotive Ethernet applications, as automotive unshielded twisted-pair (UTP) cables are susceptible to external electromagnetic interference.

[0056] Operating mode two employs a DC-coupled design, which is one of the core innovative modes of this invention. Its circuit structure is as follows: Figure 3 As shown. The most significant feature of this mode is the elimination of the AC coupling capacitor, fundamentally avoiding baseline drift problems. It supports all encoding methods, including various special PAM encoding schemes. In operating mode two, the signal switch controlling the parallel connection of the AC_couple capacitor remains closed, and the connection relationship of the analog front-end circuit is as follows:

[0057] (1) The chip pin receives a differential signal from the transmission line (twisted pair), which is the superposition of the received signal V_rx sent by the other device and the local transmitted signal V_tx;

[0058] (2) PAD is connected to the positive terminal VDD of the power supply through resistor R50_to_AVDD to provide bias current;

[0059] (3) After passing through resistor R_hybrid, the signal is directly connected to the AFE input node;

[0060] (4) The AFE input node is connected to a fixed pull-down current source, which provides a constant DC pull-down current;

[0061] (5) The recovery resistor Rdc can remain connected at this time. By turning off the output capability of the positive power supply Vdc, the recovery resistor Rdc is prevented from affecting the common mode point of the AFE input node. This is equivalent to disconnecting the recovery resistor Rdc.

[0062] (6) Control signal - Txdata controls the echo cancellation current source LS_cancel to generate an echo cancellation signal and injects it into the connection point between resistor R_hybrid and AFE input node, and uses KCL (Kirchhoff's Current Law) to achieve current subtraction.

[0063] Similar to working mode one, the echo cancellation current source LS_cancel subtracts the current from the locally transmitted signal at the node to achieve echo cancellation.

[0064] The difference lies in the fact that operating mode two uses a fixed pull-down current source to complete the common-mode conversion on R_hybrid, eliminating the need for AC coupling using a capacitor AC_coupler. The advantage of this design is:

[0065] (1) Eliminate baseline drift: Since there is no capacitor AC_couple, there is no capacitor charging and discharging process when the signal passes through, thus fundamentally eliminating the low-frequency baseline drift problem;

[0066] (2) Supports all encoding methods: No data encoding is required to maintain DC balance. It can support various special PAM encoding schemes, as well as other non-DC balance encoding methods;

[0067] (3) Minimize parasitic capacitance: The capacitor AC_couple is removed, thereby minimizing the total parasitic capacitance C_total of the AFE input node, improving the high-frequency response characteristics of the circuit, and making it suitable for higher frequency signal input.

[0068] Working mode two is particularly suitable for the following scenarios:

[0069] (1) Special PAM coding: A non-standard DC balanced PAM coding scheme is adopted;

[0070] (2) No data encoding required: Applications that are inconvenient or undesirable to use data encoding;

[0071] (3) Ultra-high speed signals: Extreme speed applications that require maximum bandwidth;

[0072] (4) Short transmission distance: scenarios with small signal attenuation.

[0073] Operating mode three utilizes frequency domain separation characteristics and is an optimized operating mode for specific application scenarios. Its circuit structure is as follows: Figure 4 As shown. Operating mode three is particularly suitable for high-speed communication scenarios using NRZ encoding, utilizing the difference in the spectrum between the NRZ signal sent by the other party and the locally transmitted signal V_tx to achieve echo cancellation. In operating mode three, the signal switch connected in parallel with the control resistor R_hybrid remains closed, while the signal switch connecting the echo cancellation current source LS_cancel and the fixed pull-down current source Idc remains open. The connection relationship of the simulated front-end circuit is as follows:

[0074] (1) The chip pin receives a differential signal from the transmission line (twisted pair), which is the superposition of the received signal V_rx sent by the other device and the local transmitted signal V_tx;

[0075] (2) PAD is connected to the positive terminal VDD of the power supply through resistor R50_to_AVDD to provide bias current;

[0076] (3) The signal bypasses the resistor R_hybrid and is directly connected to the capacitor AC_couple and the recovery resistor Rdc;

[0077] (4) The capacitor AC_couple and the recovery resistor Rdc together form a high-pass filter;

[0078] (5) The local transmitted signal V_tx is eliminated through other paths (implicit elimination is achieved by using frequency domain separation characteristics in this embodiment).

[0079] The main energy of the NRZ signal sent by the other party is in the mid-to-high frequency range. After passing through a high-pass filter composed of capacitor AC_couple and recovery resistor Rdc, the low-frequency local transmission signal V_tx can be filtered out, leaving only the high-frequency NRZ signal sent by the other party.

[0080] By adjusting the value of the recovery resistor Rdc, the cutoff frequency (high-pass point) of the AFE input high-pass filter can be adjusted, thereby optimizing its adaptability to NRZ signals of different rates.

[0081] Working mode three is particularly suitable for the following scenarios:

[0082] (1) NRZ encoded high-speed communication: suitable for high-speed SerDes and other applications using NRZ encoding;

[0083] (2) Significant spectrum separation: The spectrum of the high-speed NRZ signal sent by the other party is much higher than that of the local low-speed reverse control signal;

[0084] (3) Flexible configuration is required: the recovery resistor Rdc can be adjusted to adapt to different signal rates and application requirements.

[0085] The above three working modes can be switched in the following ways:

[0086] (1) Hardware mode selection: Different operating modes can be selected by configuring pins or registers;

[0087] (2) Adaptive switching: By detecting the rate, encoding method or spectral characteristics of the input signal, the most suitable working mode is automatically selected;

[0088] (3) Software configuration: Dynamic configuration is performed through controllers such as MCU or FPGA to achieve optimal performance.

[0089] The above description is merely a preferred embodiment of the present invention. It should be noted that for those skilled in the art, other parts not specifically described are existing technology or common knowledge. Several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A fully differential current-domain echo cancellation analog front-end circuit, characterized in that, This includes a resistor R50_to_AVDD, a resistor R_hybrid, and a local transmit current source LS, one end of which is connected to a chip pin. The other end of the resistor R50_to_AVDD is connected to the positive power supply VDD. The other end of the resistor R_hybrid is connected to one end of an echo cancellation current source LS_cancel, a fixed pull-down current source Idc, and a capacitor AC_couple. The other ends of the local transmit current source LS, the echo cancellation current source LS_cancel, and the fixed pull-down current source Idc are each grounded through a signal switch. The other end of the capacitor AC_couple is connected to a recovery resistor Rdc and a gain amplifier Gain. The other end of the recovery resistor Rdc is connected to the positive power supply Vdc. A signal switch is connected in parallel with both the resistor R_hybrid and the capacitor AC_couple.

2. The fully differential current domain echo cancellation analog front-end circuit according to claim 1, characterized in that, Both resistor R50_to_AVDD and recovery resistor Rdc are adjustable resistors.

3. The fully differential current domain echo cancellation analog front-end circuit according to claim 1, characterized in that, The signal switch is a MOSFET.

4. A method for operating the fully differential current domain echo cancellation analog front-end circuit as described in claim 1, characterized in that, It includes three working modes: Working Mode 1, Working Mode 2, and Working Mode 3. In the aforementioned operating mode, the signal switch connected to the fixed pull-down current source Idc remains in the off state; the superimposed signal of the received signal V_rx sent by the other device and the local transmitted signal V_tx at the chip pin is canceled by the echo cancellation current source LS_cancel at the node after passing through the resistor R_hybrid; after being filtered by the capacitor AC_couple and the recovery resistor Rdc, only the high-speed PAM signal V_rx sent by the other device remains. In the second working mode, the signal switch controlling the parallel connection of the capacitor AC_couple remains closed; the superimposed signal of the received signal V_rx sent by the other device at the chip pin and the local transmitted signal V_tx, after passing through the resistor R_hybrid, is canceled by the echo cancellation current source LS_cancel at the node by current subtraction cancellation; the fixed pull-down current source completes the common-mode point conversion on the resistor R_hybrid. In the third operating mode, the signal switch controlling the parallel connection of the resistor R_hybrid remains closed, and the signal switch connecting the echo cancellation current source LS_cancel and the fixed pull-down current source Idc remains open. The superimposed signal of the received signal V_rx sent by the other device at the chip pin and the local transmitted signal V_tx bypasses the resistor R_hybrid and directly passes through the high-pass filter composed of the capacitor AC_couple and the recovery resistor Rdc. The local transmitted signal V_tx achieves implicit cancellation by utilizing the frequency domain separation characteristics.

5. The operating method of a fully differential current domain echo cancellation analog front-end circuit according to claim 4, characterized in that, In the aforementioned working mode, data encoding technology is used to avoid signal distortion and increased bit error rate caused by long 0s or long 1s in the data stream.

6. The operating method of a fully differential current domain echo cancellation analog front-end circuit according to claim 5, characterized in that, The data encoding techniques include Manchester encoding, 8b10b encoding, PAM-specific encoding, and scrambling codes. The PAM-specific encoding refers to a special encoding scheme designed for high-order PAM modulation to maintain DC balance.

7. The operating method of a fully differential current domain echo cancellation analog front-end circuit according to claim 4, characterized in that, The three operating modes are selected by hardware mode selection, automatically selected by detecting the characteristics of the input signal, or dynamically configured by the controller.

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